The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all products and/or types are available in every country. Please check with an NEC Electronics
sales representative for availability and additional information.
MOS INTEGRATED CIRCUIT
µ
µµ
µ
PD23C64340, 23C64380
64M-BIT MASK-PROGRAMMABLE ROM
8M-WORD BY 8-BIT (BYTE MODE) / 4M-WORD BY 16-BIT (WORD MODE)
PAGE ACCESS MODE
Document No. M16335EJ3V1DS00 (3rd edition)
Date Published July 2004 NS CP(K)
Printed in Japan
DATA SHEET
The mark shows major revised points.
2002
Description
The
µ
PD23C64340 and
µ
PD23C64380 are 67,108,864 bits mask-programmable ROM. The word organization is
selectable (BYTE mode : 8,388,608 words by 8 bits, WORD mode : 4,194,304 words by 16 bits).
The active levels of OE (Output Enable Input) can be selected with mask-option.
The
µ
PD23C64340 and
µ
PD23C64380 are packed in 48-pin TAPE FBGA.
Features
• Pin compatible with NOR Flash Memory
• Word organization
8,388,608 words by 8 bits (BYTE mode)
4,194,304 words by 16 bits (WORD mode)
• Page access mode
BYTE mode : 8 byte random page access (
µ
PD23C64340)
16 byte random page access (
µ
PD23C64380)
WORD mode : 4 word random page access (
µ
PD23C64340)
8 word random page access (
µ
PD23C64380)
• Operating supply voltage : VCC = 2.7 V to 3.6 V
Operating supply Access time / Power supply current Standby current
voltage Page access time (Active mode) (CMOS level input)
VCC ns (MAX.) mA (MAX.)
µ
A (MAX.)
µ
PD23C64340
µ
PD23C64380
3.0 V ± 0.3 V 100 / 25 40 60 30
3.3 V ± 0.3 V 90 / 25 55 75
2
µ
µµ
µ
PD23C64340, 23C64380
Data Sheet M16335EJ3V1DS
Ordering Information
Part Number Package
µ
PD23C64340F9-xxx-BC3 48-pin TAPE FBGA (8 x 6)
µ
PD23C64380F9-xxx-BC3 48-pin TAPE FBGA (8 x 6)
(xxx : ROM code suffix No.)
Marking Image
Part Number Marking ( F )
µ
PD23C64340F9-xxx-BC3 B
µ
PD23C64380F9-xxx-BC3 C
J
R64 -xxx
INDEX MARK Lot No.
ROM code suffix No.
3
µ
µµ
µ
PD23C64340, 23C64380
Data Sheet M16335EJ3V1DS
Pin Configuration
/xxx indicates active low signal.
48-pin TAPE FBGA (8 x 6)
6
5
4
3
2
1
ABCDEFGHHGFEDCBA
Top View Bottom View
A B C D E F G H H G F E D C B A
6 A13 A12 A14 A15 A16 WORD, O15, GND 6 GND O15, WORD, A16 A15 A14 A12 A13
/BYTE A–1 A–1 /BYTE
5 A9 A8 A10 A11 O7 O14 O13 O6 5 O6 O13 O14 O7 A11 A10 A8 A9
4 NC NC A21 A19 O5 O12 VCC O4 4 O4 VCC O12 O5 A19 A21 NC NC
3 NC NC A18 A20 O2 O10 O11 O3 3 O3 O11 O10 O2 A20 A18 NC NC
2 A7 A17 A6 A5 O0 O8 O9 O1 2 O1 O9 O8 O0 A5 A6 A17 A7
1 A3 A4 A2 A1 A0 /CE /OE or GND 1 GND /OE or /CE A0 A1 A2 A4 A3
OE OE
A0 to A21 : Address inputs
O0 to O7, O8 to O14 : Data outputs
O15, A–1 : Data output 15 (WORD mode),
LSB Address input (BYTE mode)
WORD, /BYTE : Mode select
/CE : Chip Enable
/OE or OE : Output Enable
V
CC : Supply voltage
GND : Ground
NC
Note : No Connection
DC : Don’t Care
Note Some signals can be applied because this pin is not connected to the inside of the chip.
Remark Refer to Package Drawing for the index mark.
4
µ
µµ
µ
PD23C64340, 23C64380
Data Sheet M16335EJ3V1DS
Input / Output Pin Functions
Pin name Input / Output Function
WORD, /BYTE Input The pin for switching WORD mode and BYTE mode.
High level : WORD mode (4M-word by 16-bit)
Low level : BYTE mode (8M-word by 8-bit)
A0 to A21
(Address inputs)
Input Address input pins.
A0 to A21 are used differently in the WORD mode and the BYTE mode.
WORD mode (4M-word by 16-bit)
A0 to A21 are used as 22 bits address signals.
BYTE mode (8M-word by 8-bit)
A0 to A21 are used as the upper 22 bits of total 23 bits of address signal.
(The least significant bit (A−1) is combined to O15.)
O0 to O7, O8 to O14
(Data outputs)
Output Data output pins.
O0 to O7, O8 to O14 are used differently in the WORD mode and the BYTE mode.
WORD mode (4M-word by 16-bit)
The lower 15 bits of 16 bits data outputs to O0 to O14.
(The most significant bit (O15) combined to A−1.)
BYTE mode (8M-word by 8-bit)
8 bits data outputs to O0 to O7 and also O8 to O14 are high impedance.
O15, A−1
(Data output 15,
LSB Address input)
Output, Input O15, A−1 are used differently in the WORD mode and the BYTE mode.
WORD mode (4M-word by 16-bit)
The most significant output data bus (O15).
BYTE mode (8M-word by 8-bit)
The least significant address bus (A−1).
/CE
(Chip Enable)
Input Chip activating signal.
When the OE is active, output states are following.
High level : High-Z
Low level : Data out
/OE or OE or DC
(Output Enable, Don't care)
Input Output enable signal. The active level of OE is mask option. The active level of OE
can be selected from high active, low active and Don’t care at order.
VCC − Supply voltage
GND − Ground
NC − Not internally connected. (The signal can be connected.)
5
µ
µµ
µ
PD23C64340, 23C64380
Data Sheet M16335EJ3V1DS
Block Diagram
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
O15, A−1
WORD, /BYTE
/OE or OE or DC
/CE
Output Buffer
Y-Selector
Memory Cell Matrix
4,194,304 words by 16 bits /
8,388,608 words by 8 bits
Address Input Buffer
X-Decoder
Logic/InputInput Buffer
Y-Decoder
A19
O14
O13
O12
O11
O10
O9
O8
O0 O1 O2 O3 O4 O5 O6 O7
A20
A21
6
µ
µµ
µ
PD23C64340, 23C64380
Data Sheet M16335EJ3V1DS
Mask Option
The active levels of output enable pin (/OE or OE or DC) are mask programmable and optional, and can be selected
from among " 0 " " 1 " " x " shown in the table below.
Option /OE or OE or DC OE active level
0 /OE L
1 OE H
x DC Don’t care
Operation modes for each option are shown in the tables below.
Operation mode (Option : 0)
/CE /OE Mode Output state
L L Active Data out
H High-Z
H H or L Standby High-Z
Operation mode (Option : 1)
/CE OE Mode Output state
L L Active High-Z
H Data out
H H or L Standby High-Z
Operation mode (Option : x)
/CE DC Mode Output state
L H or L Active Data out
H H or L Standby High-Z
Remark L : Low level input
H : High level input
7
µ
µµ
µ
PD23C64340, 23C64380
Data Sheet M16335EJ3V1DS
Electrical Specifications
Absolute Maximum Ratings
Parameter Symbol Condition Rating Unit
Supply voltage VCC –0.3 to +4.6 V
Input voltage VI –0.3 to VCC+0.3 V
Output voltage VO –0.3 to VCC+0.3 V
Operating ambient temperature TA –10 to +70 °C
Storage temperature Tstg –65 to +150 °C
Caution Exposing the device to stress above those listed in Absolute Maximum Ratings could cause
permanent damage. The device is not meant to be operated under conditions outside the limits
described in the operational section of this specification. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability.
Capacitance (TA = 25 °C)
Parameter Symbol Test condition MIN. TYP. MAX. Unit
Input capacitance CI f = 1 MHz 10 pF
Output capacitance CO 12 pF
DC Characteristics (TA = –10 to +70 °C, VCC = 2.7 to 3.6 V)
Parameter Symbol Test conditions MIN. TYP. MAX. Unit
High level input voltage VIH 2.0 VCC + 0.3 V
Low level input voltage VIL VCC = 3.0 V ± 0.3 V –0.3 +0.5 V
VCC = 3.3 V ± 0.3 V –0.3 +0.8
High level output voltage VOH IOH = –100
µ
A 2.4 V
Low level output voltage VOL IOL = 2.1 mA 0.4 V
Input leakage current ILI VI = 0 V to VCC –10 +10
µ
A
Output leakage current ILO VO = 0 V to VCC, Chip deselected –10 +10
µ
A
Power supply current ICC1 /CE = VIL
µ
PD23C64340 VCC = 3.0 V ± 0.3 V 40 mA
(Active mode),
VCC = 3.3 V ± 0.3 V
55
IO = 0 mA
µ
PD23C64380 VCC = 3.0 V ± 0.3 V 60
VCC = 3.3 V ± 0.3 V
75
Standby current ICC3 /CE = VCC – 0.2 V (Standby mode) 30
µ
A
8
µ
µµ
µ
PD23C64340, 23C64380
Data Sheet M16335EJ3V1DS
AC Characteristics (TA = –10 to +70 °C, VCC = 2.7 to 3.6 V)
Parameter Symbol Test condition VCC = 3.0 V ± 0.3 V VCC = 3.3 V ± 0.3 V Unit
MIN. TYP. MAX. MIN. TYP. MAX.
Address access time tACC 100 90 ns
Page access time tPAC 25 25 ns
Address skew time tSKEW Note 10 10 ns
Chip enable access time tCE 100 90 ns
Output enable access time tOE 25 25 ns
Output hold time tOH 0 0 ns
Output disable time tDF 0 25 0 25 ns
WORD, /BYTE access time tWB 100 90 ns
Note tSKEW indicates the following three types of time depending on the condition.
1) When switching /CE from high level to low level, tSKEW is the time from the /CE low level input point until the
next address is determined.
2) When switching /CE from low level to high level, tSKEW is the time from the address change start point to the
/CE high level input point.
3) When /CE is fixed to low level, tSKEW is the time from the address change start point until the next address is
determined.
Since specs are defined for tSKEW only when /CE is active, tSKEW is not subject to limitations when /CE is switched
from high level to low level following address determination, or when the address is changed after /CE is switched
from low level to high level.
Remark tDF is the time from inactivation of Chip Enable input (/CE) or Output Enable input (/OE or OE) to
high impedance state output.
AC Test Conditions
Input waveform (Rise / Fall time ≤
≤≤
≤ 5 ns)
Test points1.4 V 1.4 V
Output waveform
Test points1.4 V 1.4 V
Output load
1TTL + 100 pF
9
µ
µµ
µ
PD23C64340, 23C64380
Data Sheet M16335EJ3V1DS
Cautions on power application
To ensure normal operation, always apply power using /CE following the procedure shown below.
1) Input a high level to /CE during and after power application.
2) Hold the high level input to /CE for 200 ns or longer (wait time).
3) Start normal operation after the wait time has elapsed.
Power Application Timing Chart 1 (When /CE is made high at power application)
Wait time
200 ns or longer
Normal operation
/CE (Input)
V
CC
Power Application Timing Chart 2 (When /CE is made high after power application)
Wait time
200 ns or longer
Normal operation
/CE (Input)
V
CC
Caution Other signals can be either high or low during the wait time.
10
µ
µµ
µ
PD23C64340, 23C64380
Data Sheet M16335EJ3V1DS
Read Cycle Timing Chart 1
t
ACC
t
OH
t
CE
t
OE
t
SKEW
t
SKEW
t
SKEW
t
OH
t
OH
t
DF Note2
t
DF Note2
t
ACC
t
ACC
Data out Data out Data out
(Input)
(Input)
(Input)
(Input)
A0 to A21,
A−1
Note1
O0 to O7,
O8 to O15
Note3
/CE
/OE or OE
High-ZHigh-Z
Notes 1. During WORD mode, A–1 is O15.
2. tDF is the time from inactivation of Chip Enable input (/CE) or Output Enable input (/OE or OE) to
high impedance state output.
3. During BYTE mode, O8 to O14 are high impedance and O15 is A–1.
11
µ
µµ
µ
PD23C64340, 23C64380
Data Sheet M16335EJ3V1DS
Read Cycle Timing Chart 2 (Page Access Mode)
(Input)
/CE (Input)
/OE or OE (Input)
tACC
Data Out
tCE
tOE
t
PAC
Note 5
tPAC Note 5
O0 to O7,
O8 to O15Note 4
(Input)
(Output) Data Out Data Out
High-Z High-Z
tOH tOH tOH
tDF Note 3
A2 to A21
A3 to A21
Upper addressNote 1
A–1Note 2, A0, A1
A–1Note 2, A0, A1, A2
Page addressNote 1
Notes 1. The address differs depending on the product as follows.
Part Number Upper address Page address
µ
PD23C64340 A2 to A21 A–1, A0, A1
µ
PD23C64380 A3 to A21 A–1, A0, A1, A2
2. During WORD mode, A–1 is O15.
3. t
DF is the time from inactivation of Chip Enable input (/CE) or Output Enable input (/OE or OE) to
high impedance state output.
4. During BYTE mode, O8 to O14 are high impedance and O15 is A–1.
5. The definition of page access time is as follows.
[
µ
µµ
µ
PD23C64340 ]
Page access time Upper address (A2 to A21) /CE input condition /OE or OE input condition
inputs condition
tPAC Before tACC – tPAC Before tCE – tPAC Before stabilizing of page
address (A–1, A0, A1)
[
µ
µµ
µ
PD23C64380 ]
Page access time Upper address (A3 to A21) /CE input condition /OE or OE input condition
inputs condition
tPAC Before tACC – tPAC Before tCE – tPAC Before stabilizing of page
address (A–1, A0, A1, A2)
12
µ
µµ
µ
PD23C64340, 23C64380
Data Sheet M16335EJ3V1DS
WORD, /BYTE Switch Timing Chart
Data Out
A–1 (Input)
WORD, /BYTE (Input)
Data Out Data Out
O0 to O7 (Output)
O8 to O15 (Output)
t
OH
t
ACC
t
OH
t
WB
Data Out Data Out
t
DF
High-Z
High-Z
High-Z
Remark Chip Enable (/CE) and Output Enable (/OE or OE) : Active.
13
µ
µµ
µ
PD23C64340, 23C64380
Data Sheet M16335EJ3V1DS
Package Drawing
ITEM MILLIMETERS
D
E
w
e
A
A1
A2
b
x
y
y1
ZD
ZE
6.0±0.1
8.0±0.1
0.80
0.08
0.1
0.2
1.00
1.20
0.2
0.27±0.05
0.97±0.10
0.45±0.05
0.70
SwB
y1 S
SwA
A
ZD ZE
A1
A2
S
ye
SxbAB
M
φφ
P48F9-80-BC3
48-PIN TAPE FBGA(8x6)
E
D
INDEX MARK INDEX MARK
B
S
A6
5
4
3
2
1
ABCDEFGH
14
µ
µµ
µ
PD23C64340, 23C64380
Data Sheet M16335EJ3V1DS
Recommended Soldering Conditions
Please consult with our sales offices for soldering conditions of the
µ
PD23C64340 and
µ
PD23C64380.
Types of Surface Mount Device
µ
PD23C64340F9-BC3 : 48-pin TAPE FBGA (8 x 6)
µ
PD23C64380F9-BC3 : 48-pin TAPE FBGA (8 x 6)
15
µ
µµ
µ
PD23C64340, 23C64380
Data Sheet M16335EJ3V1DS
Revision History
Edition/ Page Type of Location Description
Date This Previous revision (Previous edition → This edition)
edition edition
3rd edition/ Throughout Throughout Deletion Ordering Information
µ
PD23C64340GZ-xxx-MJH
Feb. 2004
µ
PD23C64380GZ-xxx-MJH
Package 48-pin PLASTIC TSOP (I)
(12 x 20) (Normal bent)
16
µ
µµ
µ
PD23C64340, 23C64380
Data Sheet M16335EJ3V1DS
[MEMO]
17
µ
µµ
µ
PD23C64340, 23C64380
Data Sheet M16335EJ3V1DS
[MEMO]
18
µ
µµ
µ
PD23C64340, 23C64380
Data Sheet M16335EJ3V1DS
[MEMO]
19
µ
µµ
µ
PD23C64340, 23C64380
Data Sheet M16335EJ3V1DS
1
2
3
4
VOLTAGE APPLICATION WAVEFORM AT INPUT PIN
Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the
CMOS device stays in the area between V
IL
(MAX) and V
IH
(MIN) due to noise, etc., the device may
malfunction. Take care to prevent chattering noise from entering the device when the input level is fixed,
and also in the transition period when the input level passes through the area between V
IL
(MAX) and
V
IH
(MIN).
HANDLING OF UNUSED INPUT PINS
Unconnected CMOS device inputs can be cause of malfunction. If an input pin is unconnected, it is
possible that an internal input level may be generated due to noise, etc., causing malfunction. CMOS
devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed
high or low by using pull-up or pull-down circuitry. Each unused pin should be connected to V
DD
or GND
via a resistor if there is a possibility that it will be an output pin. All handling related to unused pins must
be judged separately for each device and according to related specifications governing the device.
PRECAUTION AGAINST ESD
A strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as
much as possible, and quickly dissipate it when it has occurred. Environmental control must be
adequate. When it is dr y, a humidifier should be used. It is recommended to avoid using insulators that
easily build up static electricity. Semiconductor devices must be stored and transported in an anti-static
container, static shielding bag or conductive material. All test and measurement tools including work
benches and floors should be grounded. The operator should be grounded using a wrist strap.
Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for
PW boards with mounted semiconductor devices.
STATUS BEFORE INITIALIZATION
Power-on does not necessarily define the initial status of a MOS device. Immediately after the power
source is turned ON, devices with reset functions have not yet been initialized. Hence, power-on does
not guarantee output pin levels, I/O settings or contents of registers. A device is not initialized until the
reset signal is received. A reset operation must be executed immediately after power-on for devices
with reset functions.
NOTES FOR CMOS DEVICES
µ
µµ
µ
PD23C64340, 23C64380
These commodities, technology or software, must be exported in accordance
with the export administration regulations of the exporting country.
Diversion contrary to the law of that country is prohibited.
The information in this document is current as of July, 2004. The information is subject to change
without notice. For actual design-in, refer to the latest publications of NEC Electronics data sheets or
data books, etc., for the most up-to-date specifications of NEC Electronics products. Not all
products and/or types are available in every country. Please check with an NEC Electronics sales
representative for availability and additional information.
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written consent of NEC Electronics. NEC Electronics assumes no responsibility for any errors that may
appear in this document.
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The "Specific" quality grade applies only to NEC Electronics products developed based on a customer-
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not intended by NEC Electronics, they must contact an NEC Electronics sales representative in advance to
determine NEC Electronics' willingness to support a given application.
(Note)
•
•
•
•
•
•
M8E 02. 11-1
(1)
(2)
"NEC Electronics" as used in this statement means NEC Electronics Corporation and also includes its
majority-owned subsidiaries.
"NEC Electronics products" means any product developed or manufactured by or for NEC Electronics (as
defined above).
Computers, office equipment, communications equipment, test and measurement equipment, audio
and visual equipment, home electronic appliances, machine tools, personal electronic equipment
and industrial robots.
Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support).
Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems and medical equipment for life support, etc.
"Standard":
"Special":
"Specific":
