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Document # SRAM117 Rev OR
Revised October 2005
FEATURES
Full CMOS, 6T Cell
High Speed (Equal Access and Cycle Times)
– 15/20/25 ns (Commercial)
– 20/25/35 (Industrial)
Low Power Operation
Chip Clear Function
Output Enable and Dual Chip Enable Control
Functions
Single 5V±10% Power Supply
Common Data I/O
Fully TTL Compatible Inputs and Outputs
Standard Pinout (JEDEC Approved)
– 28-Pin Plastic DIP (300 mil)
P4C165
ULTRA HIGH SPEED 8K x 8
RESETTABLE STATIC CMOS RAM
DESCRIPTION
The P4C165 is a 65,536-bit ultra high-speed static RAM
organized as 8K x 8. The RAM features a reset control to
enable clearing all words to zero within two cycle times.
The CMOS memory requires no clocks or refreshing and
has equal access and cycle times. Inputs are fully TTL-
compatible. The RAM operates from a single 5V±10%
tolerance power supply.
FUNCTIONAL BLOCK DIAGRAM PIN CONFIGURATION
1519B
DIP (P5)
Access times as fast as 15 nanoseconds are available,
permitting greatly enhanced system operating speeds.
In full standby mode with CMOS inputs, power consump-
tion is only 5.5 mW for the P4C165.
The P4C165 is available in a 28-pin 300 mil DIP.
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P4C165
Page 2 of 9Document # SRAM117 Rev OR
MAXIMUM RATINGS(1)
Symbol Parameter Value Unit
VCC Power Supply Pin with –0.5 to +7 V
Respect to GND
Terminal Voltage with –0.5 to
VTERM Respect to GND VCC +0.5 V
(up to 7.0V)
TAOperating Temperature –55 to +125 °C
Symbol Parameter Value Unit
TBIAS Temperature Under –55 to +125 °C
Bias
TSTG Storage Temperature –65 to +150 °C
PTPower Dissipation 1.0 W
IOUT DC Output Current 50 mA
RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
ISB
Standby Power Supply Current
(TTL Input Levels)
CE ≥ VIH or
CE2 ≤VIL, VCC= Max Ind./Com’l.
f = Max., Outputs Open
___ 30
15
mA
mA
___
CE ≥ VHC or
CE2 ≤VLC, VCC= Max Ind./Com’l.
f = 0, Outputs Open
VIN ≤ VLC or VIN ≥ VHC
Standby Power Supply Current
(CMOS Input Levels)
ISB1
Grade(2) Ambient
Temperature GND VCC
0V
0V
5.0V ± 10%
5.0V ± 10%
Symbol
CIN
COUT
Parameter
Input Capacitance
Output Capacitance
Conditions
VIN = 0V
VOUT = 0V
5
7
Unit
pF
pF
CAPACITANCES(4)
VCC = 5.0V, TA = 25°C, f = 1.0MHz
n/a = Not Applicable
Symbol
DC ELECTRICAL CHARACTERISTICS
Over recommended operating temperature and supply voltage(2)
VIH
VIL
VHC
VLC
VCD
VOL
VOH
ILI
ILO
Parameter
Input High Voltage
Input Low Voltage
CMOS Input High Voltage
CMOS Input Low Voltage
Input Clamp Diode Voltage
Output Low Voltage
(TTL Load)
Output High Voltage
(TTL Load)
Input Leakage Current
Output Leakage Current
Test Conditions
VCC = Min., IIN = –18 mA
IOL = +8 mA, VCC = Min.
IOH = –4 mA, VCC = Min.
VCC = Max.
VIN = GND to VCC Ind./Com’l.
VCC = Max., CE = VIH,
VOUT = GND to VCC Ind./Com’l.
P4C165
Min
2.2
–0.5(3)
VCC –0.2
–0.5(3)
2.4
–5
–5
Max
VCC +0.5
0.8
VCC +0.5
0.2
–1.2
0.4
+5
+5
Unit
V
V
V
V
V
V
V
µA
µA
Notes:
1. Stresses greater than those listed under MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification
is not implied. Exposure to MAXIMUM rating conditions for extended
periods may affect reliability.
2. Extended temperature operation guaranteed with 400 linear feet per
minute of air flow.
3. Transient inputs with VIL and IIL not more negative than –3.0V and
–100mA, respectively, are permissible for pulse widths up to 20 ns.
4. This parameter is sampled and not 100% tested.
Typ.
Industrial
Commercial
–40°C to +85°C
0°C to +70°C
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P4C165
Page 3 of 9Document # SRAM117 Rev OR
ICC
Symbol Parameter Temperature Range
Dynamic Operating Current* Commercial
Industrial
–15 –20 –25 –35 Unit
mA
mA
*VCC = 5.5V. Tested with outputs open. f = Max. Switching inputs are 0V and 3V. CE1 = VIL, CE2 = VIH, OE = VIH
POWER DISSIPATION CHARACTERISTICS VS. SPEED
150155160
160 155 150 N/A
N/A
AC ELECTRICAL CHARACTERISTICS—READ CYCLE
(VCC = 5V ± 10%, All Temperature Ranges)(2)
Sym.
tRC
tAA
tAC
tOH
tLZ
tHZ
tOE
tOLZ
tOHZ
tPU
tPD
Parameter
Read Cycle Time
Address Access Time
Chip Enable Access Time
Output Hold from Address Change
Chip Enable to Output in Low Z
Chip Disable to Output in High Z
Output Enable Low to Low Z
Output Enable High to High Z
Chip Enable to Power Up Time
Chip Disable to Power Down Time
Output Enable Low to Data Valid
MaxMinMaxMinMaxMinMaxMin
-15 -20 -25 -35 Unit
15
3
2
2
0
15
15
8
9
9
15
20
3
2
2
0
20
20
8
10
9
20
25
3
2
2
0
25
25
10
13
12
20
35
3
2
2
0
35
35
15
18
15
20
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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P4C165
Page 4 of 9Document # SRAM117 Rev OR
READ CYCLE NO. 2 (ADDRESS CONTROLLED)(5,6)
READ CYCLE NO. 3 (CECE
CECE
CE1, CE2 CONTROLLED)(5,7,10)
READ CYCLE NO. 1 (OEOE
OEOE
OE CONTROLLED)(5)
Notes:
5. WE is HIGH for READ cycle.
6. CE1 is LOW, CE2 is HIGH and OE is LOW for READ cycle.
7. ADDRESS must be valid prior to, or coincident with CE1
transition
LOW and CE2 transition HIGH.
8. Transition is measured ± 200 mV from steady state voltage prior to
change, with loading as specified in Figure 1. This parameter is
sampled and not 100% tested.
9. READ Cycle Time is measured from the last valid address to the first
transitioning address.
10. Transitions caused by a chip enable control have similar delays
irrespective of whether CE1 or CE2 causes them.
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P4C165
Page 5 of 9Document # SRAM117 Rev OR
Notes:
11. CE1 and WE must be LOW, and CE2 HIGH for WRITE cycle.
12. OE is LOW for this WRITE cycle to show tWZ and tOW.
13. If CE1 goes HIGH, or CE2 goes LOW, simultaneously with WE HIGH,
the output remains in a high impedance state.
-20
AC CHARACTERISTICS—WRITE CYCLE
(VCC = 5V ± 10%, All Temperature Ranges)(2)
14. Write Cycle Time is measured from the last valid address to the first
transitioning address.
Sym.
tWC
tCW
tAS
tWP
tAH
tDW
tDH
Parameter
Write Cycle Time
Chip Enable Time to End of Write
Address Set-up Time
Write Pulse Width
Address Hold Time
Date Hold Time
Data Valid to End of Write
MaxMinMaxMinMaxMinMaxMin
-15 -25 -35 Unit
15
0
12
0
20
0
15
0
25
0
18
0
35
0
20
0
12
12
0
9
15
15
0
11
18
18
0
13
25
25
0
15
ns
ns
ns
ns
ns
ns
ns
ns
tAW Address Valid to End of Write
Write Enable to Output in High Z
tWZ 7 8 10 14 ns
Output Active from End of Write
tOW 3333ns
WRITE CYCLE NO. 1 (WEWE
WEWE
WE CONTROLLED)(11)
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P4C165
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TIMING WAVEFORM OF WRITE CYCLE NO. 2 (CECE
CECE
CE CONTROLLED)(11)
-20
AC CHARACTERISTICS—CLEAR CYCLE
(VCC = 5V ± 10%, All Temperature Ranges)(2)
Sym.
tCLCL
tCLPW
tCLIR
Parameter
CLEAR Cycle Time
CLEAR Pulse Width
CLEAR Low to Inputs Recognized
MaxMinMaxMinMaxMinMaxMin
-15 -25 -35 Unit
30
30
40
40
50
50
70
70
12
0
15
0
15
0
20
0
ns
ns
ns
ns
tCLIX CLEAR Low to Inputs Don't Care
TIMING WAVEFORM OF CLEARCLEAR
CLEARCLEAR
CLEAR CYCLE
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P4C165
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Mode CLEARCLEAR
CLEARCLEAR
CLEAR CECE
CECE
CE1CE2OEOE
OEOE
OE WEWE
WEWE
WE I/O Power
Reset L X X X X --- Active
Standby H H X X X High Z Standby
Standby H X L X X High Z Standby
Output
Disabled H L H H H High Z Active
Read H L H L H DOUT Active
Write H L H X L High Z Active
AC TEST CONDITIONS
Input Pulse Levels GND to 3.0V
Input Rise and
Fall Times 3ns
Input Timing
Reference Level 1.5V
Output Timing
Reference Level 1.5V
Output Load See Figures 1 and 2
TRUTH TABLE
Figure 1. Output Load Figure 2. Thevenin Equivalent
* including scope and test fixture.
Note:
Because of the ultra-high speed of the P4C165, care must be taken
when testing this device; an inadequate setup can cause a normal
functioning part to be rejected as faulty. Long high-inductance leads that
cause supply bounce must be avoided by bringing the VCC and ground
planes directly up to the contactor fingers. A 0.01 µF high frequency
capacitor is also required between VCC and ground. To avoid signal
reflections, proper termination must be used; for example, a 50Ω test
environment should be terminated into a 50Ω load with 1.73V (Thevenin
Voltage) at the comparator input, and a 116Ω resistor must be used in
series with DOUT to match 166Ω (Thevenin Resistance).
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P4C165
Page 8 of 9Document # SRAM117 Rev OR
SELECTION GUIDE
The P4C165 is available in the following temperature, speed and package options.
ORDERING INFORMATION
Pkg #
# Pins
Symbol Min Max
A-0.210
A1 -
b 0.014 0.023
b2 0.045 0.070
C 0.008 0.014
D 1.345 1.400
E1 0.270 0.300
E 0.300 0.380
e
eB - 0.430
L 0.115 0.150
0° 15°
0.100 BSC
P5
28 (300 mil)
PLASTIC DUAL IN-LINE PACKAGE
α
15 20 25 35
Commercial Plastic DIP -15PC -20PC -25PC -35PC
Industrial Plastic DIP -15PI -20PI -25PI -35PI
Speed
Temperature
Range Package
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P4C165
Page 9 of 9Document # SRAM117 Rev OR
REVISIONS
DOCUMENT NUMBER: SRAM117
DOCUMENT TITLE:P4C165 ULTRA HIGH SPEED 8K x 8 RESETTABLE STATIC CMOS RAM
REV. ISSUE
DATE
ORIG. OF
CHANGE DESCRIPTION OF CHANGE
OR Oct-05 JDB New Data Sheet
