General Description
The MAX5520/MAX5521 are single, 10-bit, ultra-low-
power, voltage-output, digital-to-analog converters
(DACs) offering Rail-to-Rail®buffered voltage outputs.
The DACs operate from a 1.8V to 5.5V supply and con-
sume less than 6µA, making them desirable for low-
power and low-voltage applications. A shutdown mode
reduces overall current, including the reference input
current, to just 0.18µA. The MAX5520/MAX5521 use a
3-wire serial interface that is compatible with SPI™,
QSPI™, and MICROWIRE™.
At power-up, the MAX5520/MAX5521 outputs are dri-
ven to zero scale, providing additional safety for appli-
cations that drive valves or for other transducers that
must be off during power-up. The zero-scale outputs
enable glitch-free power-up.
The MAX5520 accepts an external reference input. The
MAX5521 contains an internal reference and provides
an external reference output. Both devices have force-
sense-configured output buffers.
The MAX5520/MAX5521 are available in a 4mm x 4mm x
0.8mm, 12-pin, thin QFN package and are guaranteed
over the extended -40°C to +85°C temperature range.
For 12-bit compatible devices, refer to the MAX5530/
MAX5531 data sheet. For 8-bit compatible devices,
refer to the MAX5510/MAX5511 data sheet.
Applications
Portable Battery-Powered Devices
Instrumentation
Automatic Trimming and Calibration in Factory
or Field
Programmable Voltage and Current Sources
Industrial Process Control and Remote
Industrial Devices
Remote Data Conversion and Monitoring
Chemical Sensor Cell Bias for Gas Monitors
Programmable Liquid Crystal Display (LCD) Bias
Features
♦Single +1.8V to +5.5V Supply
♦Ultra-Low 6µA Supply Current
♦Shutdown Mode Reduces Supply Current to
0.18µA (max)
♦Small 4mm x 4mm x 0.8mm Thin QFN Package
♦Flexible Force-Sense-Configured Rail-to-Rail
Output Buffers
♦Internal Reference Sources 8mA of Current
(MAX5521)
♦Fast 16MHz 3-Wire SPI-/QSPI-/MICROWIRE-
Compatible Serial Interface
♦TTL- and CMOS-Compatible Digital Inputs with
Hysteresis
♦Glitch-Free Outputs During Power-Up
MAX5520/MAX5521
+1.8V to +5.5V, Ultra-Low-Power, 10-Bit,
Voltage-Output DACs
________________________________________________________________ Maxim Integrated Products 1
12
FB
11
N.C.
10
OUT
45
N.C.
6
N.C.
1
2SCLK
3
9
8
7DIN
GND
VDD
N.C.
MAX5520
MAX5521
CS
REFIN (MAX5520)
REFOUT(MAX5521)
THIN QFN
TOP VIEW
Pin Configuration
Ordering Information
Selector Guide
19-3065; Rev 0; 1/04
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
PART REFERENCE TOP MARK
MAX5520ETC External AACQ
MAX5521ETC Internal AACR
PART TEMP RANGE PIN-PACKAGE
MAX5520ETC -40°C to +85°C 12 Thin QFN-EP*
MAX5521ETC -40°C to +85°C 12 Thin QFN-EP*
Rail-to-Rail is a registered trademark of Nippon Motorola, Inc.
SPI and QSPI are trademarks of Motorola, Inc.
MICROWIRE is a trademark of National Semiconductor Corp
*EP = Exposed paddle (internally connected to GND).
MAX5520/MAX5521
+1.8V to +5.5V, Ultra-Low-Power, 10-Bit,
Voltage-Output DACs
2_______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
(VDD = +1.8V to +5.5V, OUT unloaded, TA= TMIN to TMAX, unless otherwise noted. Typical values are at TA= +25°C.)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
VDD to GND..............................................................-0.3V to +6V
OUT to GND ...............................................-0.3V to (VDD + 0.3V)
FB to GND ..................................................-0.3V to (VDD + 0.3V)
SCLK, DIN, CS to GND ..............................-0.3V to (VDD + 0.3V)
REFIN, REFOUT to GND ............................-0.3V to (VDD + 0.3V)
Continuous Power Dissipation (TA= +70°C)
Thin QFN (derate 16.9mW/°C above +70°C).............1349mW
Operating Temperature Range ...........................-40°C to +85°C
Storage Temperature Range .............................-65°C to +150°C
Junction Temperature..................................................... +150°C
Lead Temperature (soldering, 10s) .................................+300°C
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
STATIC ACCURACY (MAX5520 EXTERNAL REFERENCE)
Resolution N 10 Bits
VDD = 5V, VREF = 4.096V ±1±4
Integral Nonlinearity (Note 1) INL VDD = 1.8V, VREF = 1.024V ±1±4LSB
Guaranteed monotonic,
VDD = 5V, VREF = 4.096V
±0.2
±1
Differential Nonlinearity (Note 1) DNL Guaranteed monotonic,
VDD = 1.8V, VREF = 1.024V
±0.2
±1
LSB
VDD = 5V, VREF = 4.096V ±1±20
Offset Error (Note 2) VOS VDD = 1.8V, VREF = 1.024V ±1±20 mV
Offset-Error Temperature Drift ±2
VDD = 5V, VREF = 4.096V ±1±2
Gain Error (Note 3) GE VDD = 1.8V, VREF = 1.024V ±1±2LSB
Gain-Error Temperature
Coefficient ±4
Power-Supply Rejection Ratio PSRR 1.8V ≤ VDD ≤ 5.5V 85 dB
STATIC ACCURACY (MAX5521 INTERNAL REFERENCE)
Resolution N 10 Bits
VDD = 5V, VREF = 3.9V ±1±4
Integral Nonlinearity (Note 1) INL VDD = 1.8V, VREF = 1.2V ±1±4LSB
Guaranteed monotonic,
VDD = 5V, VREF = 3.9V
±0.2
±1
Differential Nonlinearity (Note 1) DNL Guaranteed monotonic,
VDD = 1.8V, VREF = 1.2V
±0.2
±1
LSB
VDD = 5V, VREF = 3.9V ±1±20
Offset Error (Note 2) VOS VDD = 1.8V, VREF = 1.2V ±1±20 mV
Offset-Error Temperature Drift ±2
VDD = 5V, VREF = 3.9V ±1±2
Gain Error (Note 3) GE VDD = 1.8V, VREF = 1.2V ±1±2LSB
Gain-Error Temperature
Coefficient ±4
MAX5520/MAX5521
+1.8V to +5.5V, Ultra-Low-Power, 10-Bit,
Voltage-Output DACs
_______________________________________________________________________________________ 3
ELECTRICAL CHARACTERISTICS (continued)
(VDD = +1.8V to +5.5V, OUT unloaded, TA= TMIN to TMAX, unless otherwise noted. Typical values are at TA= +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX
Power-Supply Rejection Ratio PSRR 1.8V ≤ VDD ≤ 5.5V 85 dB
REFERENCE INPUT (MAX5520)
Reference-Input Voltage Range VREFIN 0
VDD
V
Normal operation 4.1 MΩ
Reference-Input Impedance RREFIN In shutdown 2.5 GΩ
REFERENCE OUTPUT (MAX5521)
No external load, VDD = 1.8V
1.197 1.214 1.231
No external load, VDD = 2.5V
1.913 1.940 1.967
No external load, VDD = 3V
2.391 2.425 2.459
Initial Accuracy
VREFOUT
No external load, VDD = 5V
3.828 3.885 3.941
V
Output-Voltage Temperature
Coefficient
VTEMPCO
TA = -40°C to +85°C (Note 4) 12 30
Line Regulation VREFOUT < VDD - 200mV (Note 5) 0.3 2 µV/V
0 ≤ IREFOUT ≤ 1mA, sourcing, VDD = 1.8V,
VREF = 1.2V 0.3 2
0 ≤ IREFOUT ≤ 8mA, sourcing, VDD = 5V,
VREF = 3.9V 0.3 2
Load Regulation
-150µA ≤ IREFOUT ≤ 0, sinking 0.2
0.1Hz to 10Hz, VREFOUT = 3.9V
150
10Hz to 10kHz, VREFOUT = 3.9V
600
0.1Hz to 10Hz, VREFOUT = 1.2V 50
Output Noise Voltage
10Hz to 10kHz, VREFOUT = 1.2V
450
VDD = 5V 30
Short-Circuit Current (Note 6) VDD = 1.8V 14 mA
Capacitive Load Stability Range
(Note 7)
0 to 10
nF
Thermal Hysteresis (Note 8)
200
ppm
REFOUT unloaded, VDD = 5V 5.4
Reference Power-Up Time (from
Shutdown) REFOUT unloaded, VDD = 1.8V 4.4 ms
Long-Term Stability
200
ppm/
DAC OUTPUT (OUT)
Capacitive Driving Capability CL
1000
pF
VDD = 5V, VOUT set to full scale, OUT
shorted to GND, source current 65
VDD = 5V, VOUT set to 0V, OUT shorted to
VDD, sink current 65
VDD = 1.8V, VOUT set to full scale, OUT
shorted to GND, source current 14
Short-Circuit Current (Note 6)
VDD = 1.8V, VOUT set to 0V, OUT shorted to
VDD, sink current 14
mA
MAX5520/MAX5521
+1.8V to +5.5V, Ultra-Low-Power, 10-Bit,
Voltage-Output DACs
4_______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS (continued)
(VDD = +1.8V to +5.5V, OUT unloaded, TA= TMIN to TMAX, unless otherwise noted. Typical values are at TA= +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX
UNITS
VDD = 5V 3
Coming out of shutdown
(MAX5520)
VDD = 1.8V
3.8
DAC Power-Up Time Coming out of standby
(MAX5521)
VDD = 1.8V
to 5.5V 0.4
ms
Output Power-Up Glitch CL = 100pF 10 mV
FB_ Input Current 10 pA
DIGITAL INPUTS (SCLK, DIN, CS)
4.5V ≤ VDD ≤ 5.5V 2.4
2.7V < VDD ≤ 3.6V 2.0
Input High Voltage VIH
1.8V ≤ VDD ≤ 2.7V 0.7 x V
D D
V
4.5V ≤ VDD ≤ 5.5V 0.8
2.7V < VDD ≤ 3.6V 0.6Input Low Voltage VIL
1.8V≤ VDD ≤ 2.7V
0.3 x VDD
V
Input Leakage Current IIN (Note 9)
±0.05 ±0.5
µA
Input Capacitance CIN 10 pF
DYNAMIC PERFORMANCE
Voltage-Output Slew Rate SR Positive and negative (Note 10) 10
V/ms
Voltage-Output Settling Time 0.1 to 0.9 of full scale to within 0.5 LSB
(Note 10)
660
µs
VDD = 5V 80
0.1Hz to 10Hz
VDD = 1.8V
55
VDD = 5V
620
Output Noise Voltage
10Hz to 10kHz
VDD = 1.8V 476
µVP-P
POWER REQUIREMENTS
Supply Voltage Range VDD 1.8 5.5 V
VDD = 5V 2.6 4
VDD = 3V 2.6 4
MAX5520
VDD = 1.8V
3.6 5
VDD = 5V 5.3 7.0
VDD = 3V 4.8 7.0
Supply Current (Note 9) IDD
MAX5521
VDD = 1.8V
5.4 7.0
µA
VDD = 5V 3.3 4.5
VDD = 3V 2.8 4.0Standby Supply Current IDDSD (Note 9)
VDD = 1.8V
2.4 3.5
µA
Shutdown Supply Current IDDPD (Note 9)
0.05 0.25
µA
MAX5520/MAX5521
+1.8V to +5.5V, Ultra-Low-Power, 10-Bit,
Voltage-Output DACs
_______________________________________________________________________________________ 5
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX
UNITS
TIMING CHARACTERISTICS (VDD = 4.5V TO 5.5V)
Serial Clock Frequency fSCLK 0
16.7
MHz
DIN to SCLK Rise Setup Time tDS 15 ns
DIN to SCLK Rise Hold Time tDH 0ns
SCLK Pulse-Width High tCH 24 ns
SCLK Pulse-Width Low tCL 24 ns
CS Pulse-Width High tCSW 100 ns
SCLK Rise to CS Rise Hold Time
tCSH 0ns
CS Fall to SCLK Rise Setup Time
tCSS 20 ns
SCLK Fall to CS Fall Setup tCSO 0ns
CS Rise to SCK Rise Hold Time tCS1 20 ns
TIMING CHARACTERISTICS
(VDD = +4.5V to +5.5V, TA= TMIN to TMAX, unless otherwise noted. Typical values are at TA= +25°C.)
TIMING CHARACTERISTICS
(VDD = +1.8V to +5.5V, TA= TMIN to TMAX, unless otherwise noted. Typical values are at TA= +25°C.)
Note 1: Linearity is tested within codes 24 to 1020.
Note 2: Offset is tested at code 24.
Note 3: Gain is tested at code 1000. FB is connected to OUT.
Note 4: Guaranteed by design. Not production tested.
Note 5: VDD must be a minimum of 1.8V.
Note 6: Outputs can be shorted to VDD or GND indefinitely, provided that the package power dissipation is not exceeded.
Note 7: Optimal noise performance is at 2nF load capacitance.
Note 8: Thermal hysteresis is defined as the change in the initial +25°C output voltage after cycling the device from TMAX to TMIN.
Note 9: All digital inputs at VDD or GND.
Note 10: Load = 10kΩin parallel with 100pF, VDD = 5V, VREF = 4.096V (MAX5520) or VREF = 3.9V (MAX5521).
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
TIMING CHARACTERISTICS (VDD = 1.8V TO 5.5V)
Serial Clock Frequency fSCLK 010
MHz
DIN to SCLK Rise Setup Time tDS 24 ns
DIN to SCLK Rise Hold Time tDH 0ns
SCLK Pulse-Width High tCH 40 ns
SCLK Pulse-Width Low tCL 40 ns
CS Pulse-Width High tCSW
150
ns
SCLK Rise to CS Rise Hold Time
tCSH 0ns
CS Fall to SCLK Rise Setup Time
tCSS 30 ns
SCLK Fall to CS Fall Setup tCSO 0ns
CS Rise to SCK Rise Hold Time tCS1 30 ns
MAX5520/MAX5521
+1.8V to +5.5V, Ultra-Low-Power, 10-Bit,
Voltage-Output DACs
6_______________________________________________________________________________________
Typical Operating Characteristics
(VDD = 5.0V, VREF = 4.096V (MAX5520) or VREF = 3.9V (MAX5521), TA = +25°C, unless otherwise noted.)
SUPPLY CURRENT vs. SUPPLY VOLTAGE
(MAX5521)
MAX5520 toc01
SUPPLY VOLTAGE (V)
SUPPLY CURRENT (µA)
5.55.04.0 4.52.5 3.0 3.52.0
1
2
3
4
5
6
7
8
9
10
0
1.5 6.0
SUPPLY CURRENT vs. TEMPERATURE
(MAX5521)
MAX5520 toc02
TEMPERATURE (°C)
SUPPLY CURRENT (µA)
603510-15
1
2
3
4
5
6
7
8
9
10
0
-40 85
SHUTDOWN SUPPLY CURRENT
vs. TEMPERATURE (MAX5521)
MAX5520 toc03
TEMPERATURE (°C)
SHUTDOWN SUPPLY CURRENT (nA)
603510-15
1
10
100
1000
0.1
-40 85
STANDBY SUPPLY CURRENT
vs. TEMPERATURE (MAX5521)
MAX5520 toc04
TEMPERATURE (°C)
STANDBY SUPPLY CURRENT (µA)
603510-15
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
0
-40 85
VDD = 5V
VREF = 3.9V
VREF = 2.4V
VREF = 1.9V VREF = 1.2V
SUPPLY CURRENT
vs. CLOCK FREQUENCY
MAX5520 toc05
FREQUENCY (kHz)
SUPPLY CURRENT (µA)
1000010001001010.1
10
100
1000
1
0.01 100000
CS = LOGIC LOW
CODE = 0
VDD = 5V
VDD = 1.8V
SUPPLY CURRENT
vs. LOGIC INPUT VOLTAGE
MAX5520 toc06
LOGIC INPUT VOLTAGE (V)
SUPPLY CURRENT (mA)
4.54.03.0 3.51.0 1.5 2.0 2.50.5
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
0
0 5.0
ALL DIGITAL INPUTS
SHORTED TOGETHER
INL vs. INPUT CODE
(VDD = VREF = 1.8V)
MAX5520 toc07
DIGITAL INPUT CODE
INL (LSB)
1000800200 400 600
-1.0
-0.8
-0.6
-0.4
-0.2
0
0.2
0.4
-1.2
01200
INL vs. INPUT CODE
(VDD = VREF = 5V)
MAX5520 toc08
DIGITAL INPUT CODE
INL (LSB)
1000800200 400 600
-1.0
-0.8
-0.6
-0.4
-0.2
0
0.2
0.4
-1.2
01200
DNL vs. INPUT CODE
(VDD = VREF = 1.8V)
MAX5520 toc09
DIGITAL INPUT CODE
DNL (LSB)
1000800600400200
-0.02
-0.01
0
0.01
0.02
0.03
0.04
0.05
0.06
-0.03
01200
MAX5520/MAX5521
+1.8V to +5.5V, Ultra-Low-Power, 10-Bit,
Voltage-Output DACs
_______________________________________________________________________________________ 7
DNL vs. INPUT CODE
(VDD = VREF = 5V)
MAX5520 toc10
DIGITAL INPUT CODE
DNL (LSB)
1000800600400200
-0.02
-0.01
0
0.01
0.02
0.03
0.04
-0.03
01200
-1.0
-0.4
-0.6
-0.8
-0.2
0
0.2
0.4
0.6
0.8
1.0
-40 10-15 35 60 85
OFFSET VOLTAGE
vs. TEMPERATURE
MAX5520 toc11
TEMPERATURE (°C)
OFFSET VOLTAGE (mV)
VDD = 5V
VREF = 3.9V
-0.10
-0.04
-0.06
-0.08
-0.02
0
0.02
0.04
0.06
0.08
0.10
-40 10-15 35 60 85
GAIN-ERROR CHANGE
vs. TEMPERATURE
MAX5520 toc12
TEMPERATURE (°C)
GAIN-ERROR CHANGE (LSB)
VDD = 5V
VREF = 3.9V
DIGITAL FEEDTHROUGH RESPONSE
MAX5520 toc13
20µs/div
CS
5V/div
SCLK
5V/div
DIN
5V/div
OUT
50mV/div
ZERO SCALE
DAC OUTPUT LOAD REGULATION
vs. OUTPUT CURRENT
MAX5520 toc14
DAC OUTPUT CURRENT (µA)
DAC OUTPUT VOLTAGE (V)
8006004002000-200-400-600-800
0.6042
0.6044
0.6046
0.6048
0.6050
0.6040
-1000 1000
VDD = 1.8V
DAC CODE = MIDSCALE
VREF = 1.2V
DAC OUTPUT LOAD REGULATION
vs. OUTPUT CURRENT
MAX5520 toc15
DAC OUTPUT CURRENT (mA)
DAC OUTPUT VOLTAGE (V)
86-8 -6 -4 0 2-2 4
1.9405
1.9410
1.9415
1.9420
1.9425
1.9430
1.9435
1.9440
1.9400
-10 10
VDD = 5.0V
DAC CODE = MIDSCALE
VREF = 3.9V
DAC OUTPUT VOLTAGE
vs. OUTPUT SOURCE CURRENT
MAX5520 toc16
OUTPUT SOURCE CURRENT (mA)
OUTPUT VOLTAGE (V)
1010.100.01
1
2
3
4
5
0
0.001 100
VREF = VDD
CODE = MIDSCALE
VDD = 1.8V
VDD = 5V
VDD = 3V
DAC OUTPUT VOLTAGE
vs. OUTPUT SINK CURRENT
MAX5520 toc17
OUTPUT SINK CURRENT (mA)
DAC OUTPUT VOLTAGE (V)
1010.10.01
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
0
0.001 100
VREF = VDD
VDD = 5V
VDD = 3V
VDD = 1.8V
CODE = MIDSCALE
OUTPUT LARGE-SIGNAL STEP RESPONSE
(VDD = 1.8V, VREF = 1.2V)
MAX5520 toc18
100µs/div
VOUT
200mV/div
Typical Operating Characteristics (continued)
(VDD = 5.0V, VREF = 4.096V (MAX5520) or VREF = 3.9V (MAX5521), TA = +25°C, unless otherwise noted.)
MAX5520/MAX5521
+1.8V to +5.5V, Ultra-Low-Power, 10-Bit,
Voltage-Output DACs
8_______________________________________________________________________________________
OUTPUT LARGE-SIGNAL STEP RESPONSE
(VDD = 5V, VREF = 3.9V)
MAX5520 toc19
200µs/div
VOUT
500mV/div
OUTPUT MINIMUM SERIES RESISTANCE
vs. LOAD CAPACITANCE
MAX5520 toc20
CAPACITANCE (µF)
MINIMUM SERIES RESISTANCE (Ω)
1010.10.010.001
100
200
300
400
500
600
0
0.0001 100
FOR NO OVERSHOOT
POWER-UP OUTPUT VOLTAGE GLITCH
MAX5520 toc21
20ms/div
VOUT
10mV/div
VDD
2V/div
MAJOR CARRY OUTPUT VOLTAGE GLITCH
(CODE 7FFh TO 800h)
(VDD = 5V, VREF = 3.9V)
MAX5520 toc22
100µs/div
VOUT
AC-COUPLED
5mV/div
3.900
3.905
3.910
3.915
3.920
3.925
3.930
3.935
3.940
-40 -15 10 35 60 85
REFERENCE OUTPUT VOLTAGE
vs. TEMPERATURE
MAX5520 toc23
TEMPERATURE (°C)
REFERENCE OUTPUT VOLTAGE (V)
VDD = 5V
REFERENCE OUTPUT VOLTAGE
vs. REFERENCE OUTPUT CURRENT
MAX5520 toc24
REFERENCE OUTPUT CURRENT (µA)
REFERENCE OUTPUT VOLTAGE (V)
7500550035001500
1.215
1.216
1.217
1.218
1.219
1.220
1.214
-500
VDD = 1.8V
REFERENCE OUTPUT VOLTAGE
vs. REFERENCE OUTPUT CURRENT
MAX5520 toc25
REFERENCE OUTPUT CURRENT (µA)
REFERENCE OUTPUT VOLTAGE (V)
14,50012,0009500700045002000
3.89
3.90
3.91
3.92
3.88
-500
VDD = 5V
REFERENCE OUTPUT VOLTAGE
vs. SUPPLY VOLTAGE
MAX5520 toc26
SUPPLY VOLTAGE (V)
REFERENCE OUTPUT VOLTAGE (V)
5.55.04.0 4.52.5 3.0 3.52.0
1.21732
1.21734
1.21736
1.21738
1.21740
1.21742
1.21744
1.21746
1.21748
1.21750
1.21730
1.5 6.0
NO LOAD
Typical Operating Characteristics (continued)
(VDD = 5.0V, VREF = 4.096V (MAX5520) or VREF = 3.9V (MAX5521), TA = +25°C, unless otherwise noted.)
MAX5520/MAX5521
+1.8V to +5.5V, Ultra-Low-Power, 10-Bit,
Voltage-Output DACs
_______________________________________________________________________________________ 9
REFERENCE LINE-TRANSIENT RESPONSE
(VREF = 3.9V)
MAX5520 toc28
100µs/div
5.5V
VDD
4.5V
VREF
500mV/div
3.9V
REFERENCE LOAD TRANSIENT
(VDD = 1.8V)
MAX5520 toc29
200µs/div
REFOUT
SOURCE
CURRENT
0.5mA/div
VREFOUT
500mV/div
REFERENCE LOAD TRANSIENT
(VDD = 5V)
MAX5520 toc30
200µs/div
REFOUT
SOURCE
CURRENT
0.5mA/div
VREFOUT
500mV/div
3.9V
REFERENCE LOAD TRANSIENT
(VDD = 1.8V)
MAX5520 toc31
200µs/div
REFOUT
SINK
CURRENT
50µA/div
VREFOUT
500mV/div
REFERENCE LOAD TRANSIENT
(VDD = 5V)
MAX5520 toc32
200µs/div
REFOUT
SINK
CURRENT
100µA/div
VREFOUT
500mV/div
3.9V
REFERENCE LINE-TRANSIENT RESPONSE
(VREF = 1.2V)
MAX5520 toc27
100µs/div
2.8V
VDD
1.8V
VREF
500mV/div
Typical Operating Characteristics (continued)
(VDD = 5.0V, VREF = 4.096V (MAX5520) or VREF = 3.9V (MAX5521), TA = +25°C, unless otherwise noted.)
MAX5520/MAX5521
+1.8V to +5.5V, Ultra-Low-Power, 10-Bit,
Voltage-Output DACs
10 ______________________________________________________________________________________
Typical Operating Characteristics (continued)
(VDD = 5.0V, VREF = 4.096V (MAX5520) or VREF = 3.9V (MAX5521), TA = +25°C, unless otherwise noted.)
REFERENCE PSRR
vs. FREQUENCY
MAX5520 toc33
FREQUENCY (kHz)
POWER-SUPPLY REJECTION RATIO (dB)
100100.1 1
10
20
30
40
50
60
70
80
0
0.01 1000
VDD = 1.8V
REFERENCE PSRR
vs. FREQUENCY
MAX5520 toc34
FREQUENCY (kHz)
POWER-SUPPLY REJECTION RATIO (dB)
100100.1 1
10
20
30
40
50
60
70
80
0
0.01 1000
VDD = 5V
REFERENCE OUTPUT NOISE
(0.1Hz TO 10Hz) (VDD = 1.8V, VREF = 1.2V)
MAX5520 toc35
1s/div
100µV/div
REFERENCE OUTPUT NOISE
(0.1Hz TO 10Hz) (VDD = 5V, VREF = 3.9V)
MAX5520 toc36
1s/div
100µV/div
MAX5520/MAX5521
+1.8V to +5.5V, Ultra-Low-Power, 10-Bit,
Voltage-Output DACs
______________________________________________________________________________________ 11
10-BIT DAC
DAC
REGISTER
OUT
REFIN
GND
MAX5520
INPUT
REGISTER
POWER-
DOWN
CONTROL
CONTROL
LOGIC
AND
SHIFT
REGISTER FB
SCLK
VDD
DIN
CS
Pin Description
MAX5520 Functional Diagram
PIN
MAX5520
MAX5521
NAME FUNCTION
11CS Active-Low Digital-Input Chip Select
22SCLK Serial-Interface Clock
33DIN Serial-Interface Data Input
4—REFIN Reference Input
—4REFOUT Reference Output
5, 6, 7, 11
5, 6, 7, 11
N.C. No Connection. Leave N.C. inputs unconnected (floating) or connected to GND.
88V
DD Power Input. Connect VDD to a 1.8V to 5.5V power supply. Bypass VDD to GND with a
0.1µF capacitor.
99GND Ground
10 10 OUT Analog Voltage Output
12 12 FB Feedback Input
EP EP Exposed
Paddle Exposed Paddle. Connect EP to GND.
MAX5520/MAX5521
+1.8V to +5.5V, Ultra-Low-Power, 10-Bit,
Voltage-Output DACs
12 ______________________________________________________________________________________
Detailed Description
The MAX5520/MAX5521 single, 10-bit, ultra-low-power,
voltage-output DACs offer Rail-to-Rail buffered voltage
outputs. The DACs operate from a 1.8V to 5.5V supply
and require only 6µA (max) supply current. These
devices feature a shutdown mode that reduces overall
current, including the reference input current, to just
0.18µA. The MAX5521 includes an internal reference
that saves additional board space and can source up
to 8mA, making it functional as a system reference. The
16MHz, 3-wire serial interface is compatible with SPI,
QSPI, and MICROWIRE protocols. When VDD is
applied, all DAC outputs are driven to zero scale with
virtually no output glitch. The MAX5520/MAX5521 out-
put buffers are configured in force sense allowing users
to externally set voltage gains on the output (an output-
amplifier inverting input is available). These devices
come in a 4mm x 4mm thin QFN package.
Digital Interface
The MAX5520/MAX5521 use a 3-wire serial interface
compatible with SPI, QSPI, and MICROWIRE protocols
(Figures 1 and 2).
The MAX5520/MAX5521 include a single, 16-bit, input
shift register. Data loads into the shift register through
the serial interface. CS must remain low until all 16 bits
are clocked in. Data loads MSB first, D9–D0. The 16
bits consist of 4 control bits (C3–C0), 10 data bits
(D9–D0), and 2 sub-bits (see Table 1). D9–D0 are the
DAC data bits and S1 and S0 are the sub-bits. The
sub-bits must be set to zero for proper operation. The
control bits C3–C0 control the MAX5520/MAX5521, as
outlined in Table 2.
Each DAC channel includes two registers: an input reg-
ister and a DAC register. The input register holds input
data. The DAC register contains the data updated to
the DAC output.
The double-buffered register configuration allows any
of the following:
•Loading the input registers without updating the DAC
registers
•Updating the DAC registers from the input registers
•Updating all the input and DAC registers simultaneously
10-BIT DAC
2-BIT
PROGRAMMABLE
REFERENCE
DAC
REGISTER
OUT
REF
BUF
GND
MAX5521
REFOUT
INPUT
REGISTER
POWER-
DOWN
CONTROL
CONTROL
LOGIC
AND
SHIFT
REGISTER FB
SCLK
VDD
DIN
CS
MAX5521 Functional Diagram
MAX5520/MAX5521
+1.8V to +5.5V, Ultra-Low-Power, 10-Bit,
Voltage-Output DACs
______________________________________________________________________________________ 13
tCSW
tCSS
tCS0 tDH
tCL
tCS1
tCSH
tCH
tDS
SCLK
DIN
CS
C2 C1 S0
C3
16151413121110987654321SCLK
C3 C2 C1 C0 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 S1 S0DIN
CONTROL BITS DATA BITS SUB-BITS
COMMAND
EXECUTED
CS
Figure 1. Timing Diagram
Figure 2. Register Loading Diagram
CONTROL DATA BITS
MSB
LSB
C3
C2 C1 C0 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
S1
S0
Table 1. Serial Write Data Format
Sub-bits S1 and S0 must be set to zero for proper operation.
MAX5520/MAX5521
+1.8V to +5.5V, Ultra-Low-Power, 10-Bit,
Voltage-Output DACs
14 ______________________________________________________________________________________
CONTROL BITS INPUT DATA SUB-BITS
C3
C2 C1
C0 D9–D0 S1–S0 FUNCTION
0000XXXXXXXXXX 00 No operation; command is ignored.
0001 10-bit data 00 Load input register from shift register; DAC register
unchanged; DAC output unchanged.
0010 ——Command reserved; do not use.
0011 ——Command reserved; do not use.
0100 ——Command reserved; do not use.
0101 ——Command reserved; do not use.
0110 ——Command reserved; do not use.
0111 ——Command reserved; do not use.
1000 10-bit data 00
Load DAC register from input register; DAC output
updated; MAX5520 enters normal operation if in
shutdown; MAX5521 enters normal operation if in
standby or shutdown.
1001 10-bit data 00
Load input register and DAC register from shift register;
DAC output updated; MAX5520 enters normal operation
if in shutdown; MAX5521 enters normal operation if in
standby or shutdown.
1010 ——Command reserved; do not use.
1011 ——Command reserved; do not use.
1100 D9, D8,
XXXXXXXX 00
MAX5520 enters shutdown; MAX5521 enters standby*.
For the MAX5521, D9 and D8 configure the internal
reference voltage (Table 3).
1101 D9, D8,
XXXXXXXX 00
MAX5520/MAX5521 enter normal operation; DAC output
reflects existing contents of DAC register. For the
MAX5521, D9 and D8 configure the internal reference
voltage (Table 3).
1110 D9, D8,
XXXXXXXX 00
MAX5520/MAX5521 enter shutdown; DAC output set to
high impedance. For the MAX5521, D9 and D8 configure
the internal reference voltage (Table 3).
1111 10-bit data 00
Load input register and DAC register from shift register;
DAC output updated; MAX5520 enters normal operation
if in shutdown; MAX5521 enters normal operation if in
standby or shutdown.
Table 2. Serial-Interface Programming Commands
X = Don’t care.
*Standby mode can be entered from normal operation only. It is not possible to enter standby mode from shutdown.
MAX5520/MAX5521
+1.8V to +5.5V, Ultra-Low-Power, 10-Bit,
Voltage-Output DACs
______________________________________________________________________________________ 15
Power Modes
The MAX5520/MAX5521 feature two power modes to
conserve power during idle periods. In normal opera-
tion, the device is fully operational. In shutdown mode,
the device is completely powered down, including the
internal voltage reference in the MAX5521. The
MAX5521 also offers a standby mode where all circuitry
is powered down except the internal voltage reference.
Standby mode keeps the reference powered up while
the remaining circuitry is shut down, allowing it to be
used as a system reference. Standby mode also helps
reduce the wake-up delay by not requiring the refer-
ence to power up when returning to normal operation.
Shutdown Mode
The MAX5520/MAX5521 feature a software-program-
mable shutdown mode that reduces the typical supply
current and the reference input current to 0.18µA
(max). Writing an input control word with control bits
C[3:0] = 1110 places the device in shutdown mode
(Table 2). In shutdown, the MAX5520 reference input
and DAC output buffers go high impedance. Placing
the MAX5521 into shutdown turns off the internal refer-
ence, and the DAC output buffers go high impedance.
The serial interface remains active for all devices.
Table 2 shows several commands that bring the
MAX5520/MAX5521 back to normal operation. The
power-up time from shutdown is required before the
DAC outputs are valid.
Note: For the MAX5521, standby mode cannot be
entered directly from shutdown mode. The device must
be brought into normal operation before entering stand-
by mode.
Standby Mode (MAX5521 Only)
The MAX5521 features a software-programmable
standby mode that reduces the typical supply current
to 6µA. Standby mode powers down all circuitry except
the internal voltage reference. Place the device in
standby mode by writing an input control word with
control bits C[3:0] = 1100 (Table 2). The internal refer-
ence and serial interface remain active while the DAC
output buffers go high impedance. If the MAX5521 is
coming out of standby, the power-up time from standby
is required before the DAC outputs are valid.
For the MAX5521, standby mode cannot be entered
directly from shutdown mode. The device must be
brought into normal operation before entering standby
mode. To enter standby from shutdown, issue the com-
mand to return to normal operation, followed immedi-
ately by the command to go into standby.
Table 2 shows several commands that bring the
MAX5521 back to normal operation. When transition-
ing from standby mode to normal operation, only the
DAC power-up time is required before the DAC outputs
are valid.
Reference Input
The MAX5520 accepts a reference with a voltage range
extending from 0 to VDD. The output voltage (VOUT) is
represented by a digitally programmable voltage
source as:
VOUT = (VREF x N / 1024) x gain
where N is the numeric value of the DAC’s binary input
code (0 to 1023), VREF is the reference voltage and
gain is the externally set voltage gain for the MAX5520/
MAX5521.
In shutdown mode, the reference input enters a high-
impedance state with an input impedance of 2.5GΩ(typ).
Reference Output
The MAX5521 internal voltage reference is software
configurable to one of four voltages. Upon power-up,
the default reference voltage is 1.214V. Configure the
reference voltage using the D8 and D9 data bits (Table
3) when the control bits are as follows: C[3:0] = 1100,
1101, or 1110 (Table 2). VDD must be kept at a mini-
mum of 200mV above VREF for proper operation.
D9 D8 REFERENCE VOLTAGE (V)
00 1.214
01 1.940
10 2.425
11 3.885
Table 3. Reference Output Voltage
Programming
MAX5520/MAX5521
+1.8V to +5.5V, Ultra-Low-Power, 10-Bit,
Voltage-Output DACs
16 ______________________________________________________________________________________
Applications Information
1-Cell and 2-Cell Circuit
See Figure 3 for an illustration of how to power the
MAX5520/MAX5521 with either one lithium-ion battery
or two alkaline batteries. The low current consumption
of the devices makes the MAX5520/MAX5521 ideal for
battery-powered applications.
Programmable Current Source
See the circuit in Figure 4 for an illustration of how to
configure the MAX5520 as a programmable current
source for driving an LED. The MAX5520 drives a stan-
dard NPN transistor to program the current source. The
current source (ILED) is defined in the equation in
Figure 4.
Voltage Biasing a Current-Output
Transducer
See the circuit in Figure 5 for an illustration of how to con-
figure the MAX5520 to bias a current-output transducer.
In Figure 5, the output voltage of the MAX5520 is a func-
tion of the voltage drop across the transducer added to
the voltage drop across the feedback resistor R.
Self-Biased Two-Electrode
Potentiostat Application
See the circuit in Figure 6 for an illustration of how to
use the MAX5520 to bias a two-electrode potentiostat
on the input of an ADC.
Unipolar Output
Figure 7 shows the MAX5520 in a unipolar output con-
figuration with unity gain. Table 4 lists the unipolar out-
put codes.
Bipolar Output
The MAX5520 output can be configured for bipolar
operation, as shown in Figure 8. The output voltage is
given by the following equation:
VOUT = VREF x [(NA- 512) / 512]
where NArepresents the numeric value of the DAC’s
binary input code. Table 5 shows digital codes (offset
binary) and the corresponding output voltage for the
circuit in Figure 4.
Configurable Output Gain
The MAX5520/MAX5521 have a force-sense output,
which provides a connection directly to the inverting ter-
minal of the output op amp, yielding the most flexibility.
The advantage of the force-sense output is that specific
gains can be set externally for a given application. The
gain error for the MAX5520/MAX5521 is specified in a
unity-gain configuration (op-amp output and inverting ter-
minals connected), and additional gain error results from
external resistor tolerances. Another advantage of the
force-sense DAC is that it allows many useful circuits to
be created with only a few simple external components.
An example of a custom fixed gain using the force-sense
output of the MAX5520/MAX5521 is shown in Figure 9. In
this example R1 and R2 set the gain for VOUT.
VOUT = [(VREFIN x NA) / 1024] x [1 + (R2 / R1)]
where NArepresents the numeric value of the DAC
input code.
REFIN
MAX5520
MAX6006
(1µA, 1.25V
SHUNT
REFERENCE) GND
+1.25V
0.01µF
536kΩ
VDD
DAC VOUT
NDAC IS THE NUMERIC VALUE
OF THE DAC INPUT CODE.
VOUT (1.22mV / LSB)
1.8V ≤ VALKALINE ≤ 3.3V
2.2V ≤ VLITHIUM ≤ 3.3V
VOUT = VREFIN × NDAC
1024
0.1µF
Figure 3. Portable Application Using Two Alkaline Cells or One Lithium Coin Cell
MAX5520/MAX5521
+1.8V to +5.5V, Ultra-Low-Power, 10-Bit,
Voltage-Output DACs
______________________________________________________________________________________ 17
R
2N3904
NDAC IS THE NUMERIC VALUE OF THE DAC INPUT CODE.
ILED
REFIN
LED
MAX5520
V+
DAC
VOUT
ILED = VREFIN × NDAC
1024 × R
FB
Figure 4. Programmable Current Source Driving an LED
DAC
BAND
GAP
TO ADC
OUT
REFOUT
MAX5521
TO ADC
TO ADC
FB
WE
SENSOR
CE
IFRF
CL
REF
Figure 6. Self-Biased Two-Electrode Potentiostat Application
R
FB
NDAC IS THE NUMERIC VALUE
OF THE DAC INPUT CODE.
IT
REFIN
MAX5520
DAC VOUT
VOUT = VBIAS + (IT × R)
VOUT
VBIAS
TRANSDUCER
VBIAS = VREFIN × NDAC
1024
Figure 5. Transimpedance Configuration for a Voltage-Biased
Current-Output Transducer
NA IS THE DAC INPUT CODE
(0 TO 1023 DECIMAL).
REFIN
MAX5520
OUT
FB
VOUT = VREFIN × NA
1024
DAC
Figure 7. Unipolar Output Circuit
DAC CONTENTS
MSB LSB ANALOG OUTPUT
1111
1111 1100
+VREF (1023/21024)
1000
0000 0100
+VREF (513/1024)
1000
0000 0000
+ V
RE F
( 512/1024) = + V
RE F
/2
0111
1111 1100
+VREF (511/1024)
0000
0001 0100
+VREF (1/1024)
0000
0000 0000
0V
Table 4. Unipolar Code Table (Gain = +1)
DAC CONTENTS
MSB
LSB ANALOG OUTPUT
1111
1111 1100
+VREF (511/512)
1000
0000 0100
+VREF (1/512)
1000
0000 0000
0V
0111
1111 1100
-VREF (1/512)
0000
0000 0100
-VREF (511/512)
0000
0000 0000
-VREF (512/512) = -VREF
Table 5. Bipolar Code Table (Gain = +1)
MAX5520/MAX5521
+1.8V to +5.5V, Ultra-Low-Power, 10-Bit,
Voltage-Output DACs
18 ______________________________________________________________________________________
Power Supply and Bypassing
Considerations
Bypass the power supply with a 0.1µF capacitor to GND.
Minimize lengths to reduce lead inductance. If noise
becomes an issue, use shielding and/or ferrite beads to
increase isolation. For the thin QFN package, connect
the exposed paddle to ground.
Layout Considerations
Digital and AC transient signals coupling to GND can
create noise at the output. Use proper grounding tech-
niques, such as a multilayer board with a low-inductance
ground plane. Wire-wrapped boards and sockets are not
recommended. For optimum system performance, use
printed circuit (PC) boards. Good PC board ground lay-
out minimizes crosstalk between DAC outputs, reference
inputs, and digital inputs. Reduce crosstalk by keeping
analog lines away from digital lines.
Figure 8. Bipolar Output Circuit Figure 9. Separate Force-Sense Outputs Create Unity and
Greater-than-Unity DAC Gains Using the Same Reference
REFIN
MAX5520
OUT
VOUT
FB
V+
10kΩ10kΩ
V-
DAC
REFIN DAC
VOUT
OUT
MAX5520
FB
R2
R1
MAX5520/MAX5521
+1.8V to +5.5V, Ultra-Low-Power, 10-Bit,
Voltage-Output DACs
______________________________________________________________________________________ 19
Figure 10. Software-Configurable Output Gain
H
L
FB WNDAC IS THE NUMERIC VALUE OF THE DAC INPUT CODE.
NPOT IS THE NUMERIC VALUE OF THE POT INPUT CODE.
REFIN
MAX5520
MAX5401
SOT-POT
100kΩ
DAC VOUT
5PPM/°C
RATIOMETRIC
TEMPCO
1.8V ≤ VDD ≤ 5.5V
VOUT
VOUT = VREFIN × NDAC
1024
(
1 + 255 - NPOT
)
255
SCLK
DIN
CS2
CS1
Chip Information
TRANSISTOR COUNT: 10,688
PROCESS: BiCMOS
MAX5520/MAX5521
+1.8V to +5.5V, Ultra-Low-Power, 10-Bit,
Voltage-Output DACs
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
20 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
©2004 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information
go to www.maxim-ic.com/packages.)
24L QFN THIN.EPS
B
1
2
21-0139
PACKAGE OUTLINE
12,16,20,24L QFN THIN, 4x4x0.8 mm
B
2
2
21-0139
PACKAGE OUTLINE
12,16,20,24L QFN THIN, 4x4x0.8 mm