SLAS148 − SEPTEMBER 1996
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
D8-Bit Resolution
D2.7 V to 3.6 V VCC
DEasy Microprocessor Interface or
Standalone Operation
DOperates Ratiometrically or With VCC
Reference
DSingle Channel or Multiplexed Twin
Channels With Single-Ended or Differential
Input Options
DInput Range 0 V to VCC With VCC Reference
DInputs and Outputs Are Compatible With
TTL and MOS
DConversion Time of 32 µs at
f(CLK) = 250 kHz
DDesigned to Be Functionally Equivalent to
the National Semiconductor ADC0831 and
ADC0832 at 3 V Supply
DTotal Unadjusted Error . . . ±1 LSB
description
These devices are 8-bit successive-approximation analog-to-digital converters. The TLV0831 has single input
channels; the TLV0832 has multiplexed twin input channels. The serial output is configured to interface with
standard shift registers or microprocessors.
The TLV0832 multiplexer is software configured for single-ended or differential inputs. The differential analog
voltage input allows for common-mode rejection or of fset of the analog zero input voltage value. In addition, t h e
voltage reference input can be adjusted to allow encoding any smaller analog voltage span to the full 8 bits of
resolution.
The operation of the TLV0831 and TLV0832 devices is very similar to the more complex TLV0834 and TLV0838
devices. Ratiometric conversion can be attained by setting the REF input equal to the maximum analog input
signal value, which gives the highest possible conversion resolution. Typically, REF is set equal to VCC (done
internally on the TLV0832).
The T LV0831C and TLV0832C are characterized for operation from 0°C t o 70°C. The TLV0831I and TLV0832I
are characterized for operation from −40°C to 85°C.
AVAILABLE OPTIONS
PACKAGE
TASMALL OUTLINE
(D) PLASTIC DIP
(P)
0°C to 70°C TLV0831CD TLV0832CD TLV0831CP TLV0832CP
−40°C to 85°C TLV0831ID TLV0832ID TLV0831IP TLV0832IP
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications o
f
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
1
2
3
4
8
7
6
5
CS
IN+
IN−
GND
VCC
CLK
DO
REF
TLV0831 ...D OR P PACKAGE
(TOP VIEW)
1
2
3
4
8
7
6
5
CS
CH0
CH1
GND
VCC/REF
CLK
DO
DI
TLV0832 ...D OR P PACKAGE
(TOP VIEW)
!" # $%&" !# '%()$!" *!"&+
*%$"# $ " #'&$$!"# '& ",& "&# &-!# #"%&"#
#"!*!* .!!"/+ *%$" '$&##0 *&# " &$&##!)/ $)%*&
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Copyright 1996, Texas Instruments Incorporated
SLAS148 − SEPTEMBER 1996
2POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
functional block diagram
R
Start
Flip-Flop
S
CLK
CLK
Time
Delay
SR
CS
DO
CS
CS
D
CLK
R
EOC
9-Bit
Shift
Register
CS
R
CLK
First
LSB
Bit 1
Bits 0−7
First
One
Shot
SAR
Logic
and
Latch
R
EN
CS
Bits 0−7
REF Ladder
and
Decoder
EN
Comparator
EN
Analog
MUX
CH1/IN−
CH0/IN+
SGL/DIF
ODD/EVEN
Start
CLK
D
Shift Register
To Internal
Circuits
(TLV0832
only)
DI
CS
CLK
MSB
(TLV0831
only)
SLAS148 − SEPTEMBER 1996
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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
functional description
The T LV0831 and TLV0832 use a sample-data-comparator structure that converts differential analog inputs by
a successive-approximation routine. The input voltage to be converted is applied to an input terminal and is
compared to ground (single ended), or to an adjacent input (differential). The TLV0832 input terminals can be
assigned a positive (+) or negative (−) polarity. The TLV0831 contains only one differential input channel with
fixed polarity assignment; therefore it does not require addressing. The signal can be applied differentially,
between IN+ and IN−, to the TLV0831 or can be applied to IN+ with IN− grounded as a single ended input. When
the signal input applied to the assigned positive terminal is less than the signal on the negative terminal, the
converter output is all zeros.
Channel selection and input configuration are under software control using a serial-data link from the controlling
processor. A serial-communication format allows more functions to be included in a converter package with no
increase in size. In addition, it eliminates the transmission of low-level analog signals by locating the converter
at the analog sensor and communicating serially with the controlling processor. This process returns noise-free
digital data to the processor.
A conversion is initiated by setting CS low, which enables all logic circuits. CS must be held low for the complete
conversion process. A clock input is then received from the processor. An interval of one clock period is
automatically inserted to allow the selected multiplexed channel to settle. DO comes out of the high-impedance
state and provides a leading low for one clock period of multiplexer settling time. The SAR comparator compares
successive outputs from the resistive ladder with the incoming analog signal. The comparator output indicates
whether the analog input is greater than or less than the resistive-ladder output. As the conversion proceeds,
conversion data is simultaneously output from DO, with the most significant bit (MSB) first. After eight clock
periods, the conversion is complete. When CS goes high, all internal registers are cleared. At this time, the
output circuits go to the high-impedance state. If another conversion is desired, CS must make a high-to-low
transition followed by address information.
A TLV0832 input configuration is assigned during the multiplexer-addressing sequence. The multiplexer
address shifts into the converter through the data input (DI) line. The multiplexer address selects the analog
inputs to be enabled and determines whether the input is single ended or differential. When the input is
differential, the polarity of the channel input is assigned. In addition to selecting the differential mode, the polarity
may also be selected. Either channel of the channel pair may be designated as the negative or positive input.
On each low-to-high transition of the clock input, the data on DI is clocked into the multiplexer-address shift
register. The first logic high on the input is the start bit. A 2-bit assignment word follows the start bit on the
TLV0832. On each successive low-to-high transition of the clock input, the start bit and assignment word are
shifted through the shift register. When the start bit is shifted into the start location of the multiplexer register,
the input channel is selected and conversion starts. The TLV0832 DI terminal to the multiplexer shift register
is disabled for the duration of the conversion.
The TLV0832 outputs the least-significant-bit (LSB) first data after the MSB-first data stream. The DI and DO
terminals can be tied together and controlled by a bidirectional processor I/O bit received on a single wire. This
is possible because DI is only examined during the multiplexer-addressing interval and DO is still in the
high-impedance state.
SLAS148 − SEPTEMBER 1996
4POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
sequence of operation
Don’t Care
176201267
MSBLSB
LSB-First Data
EVENDIF
+Sign Bit
ODD
SGL
Start
Bit
1765 243
MSB
DI
DO
CS
tsu
CLK
21201918141312123456 1011
TLV0832
Hi-Z
0
LSB
tconv
MSB-First Data
MSB
Hi-Z
DO
MUX
Settling Time
CS
CLK
10987654321
tsu
tconv
TLV0831
Hi-Z
MSB-First Data
TLV0832 MUX-ADDRESS CONTROL LOGIC TABLE
MUX ADDRESS CHANNEL NUMBER
SGL/DIF ODD/EVEN CH0 CH1
L
H
L
H
L
L
H
H
+
−
+
−
+
+
MUX
Settling Time
H = high level, L = low level,
− or + = terminal polarity for the selected input channel
(TLV0832
only)
SLAS148 − SEPTEMBER 1996
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
absolute maximum ratings over recommended operating free-air temperature range (unless
otherwise noted)†
Supply voltage, VCC (see Note 1) 6.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, VI: Logic −0.3 V to VCC + 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Analog −0.3 V to VCC + 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input current, II ±5 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Total input current ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating free-air temperature range, TA: C suffix 0°C to 70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I suffix −40°C to 85°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, Tstg −65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: P package 260°C. . . . . . . . . . . . . . . . . . . . .
†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values, except differential voltages, are with respect to the network ground terminal.
recommended operating conditions
MIN NOM MAX UNIT
Supply voltage, VCC (see clock operating conditions) 2.7 3.3 3.6 V
High-level input voltage, VIH 2 V
Low-level input voltage, VIL 0.8 V
Clock frequency, f(CLK)
VCC = 2.7 V 250 kHz
Clock frequency, f(CLK) VCC = 3.3 V 10 600 kHz
Clock duty cycle (see Note 2) 40% 60%
Pulse duration, CS high, twH(CS) 220 ns
Setup time, CS low or TLV0832 data valid before CLK↑, tsu 350 ns
Hold time, TLV0832 data valid after CLK↑, th90 ns
Operating free-air temperature, TA
C suffix 0 70
°C
Operating free-air temperature, T
AI suffix −40 85 °
C
NOTE 2: The clock-duty-cycle range ensures proper operation at all clock frequencies. When a clock frequency is used outside the
recommended duty-cycle range, the minimum pulse duration (high or low) is 1 µs.
SLAS148 − SEPTEMBER 1996
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electrical characteristics over recommended range of operating free-air temperature, VCC = 3.3 V,
f(CLK) = 250 kHz (unless otherwise noted)
digital section
PARAMETER
TEST CONDITIONS†
C SUFFIX I SUFFIX
UNIT
PARAMETER
TEST CONDITIONS†
MIN TYP‡MAX MIN TYP‡MAX
UNIT
VOH
High-level output voltage
VCC = 3 V, IOH = −360 µA 2.8 2.4
V
VOH High-level output voltage VCC = 3 V, IOH = −10 µA2.9 2.8 V
VOL Low-level output voltage VCC = 3 V, IOL = 1.6 mA 0.34 0.4 V
IIH High-level input current VIH = 3.6 V 0.005 1 0.005 1 µA
IIL Low-level input current VIL = 0 −0.005 −1 −0.005 −1 µA
IOH High-level output
(source) current At VOH, DO= 0 V, TA = 25°C −6.5 −15 −6.5 −15 mA
IOL Low-level output (sink) current At VOL, DO= 0 V, TA = 25°C 8 −16 8 −16 mA
IOZ
High-impedance-state output
VO = 3.3 V, TA = 25°C 0.01 3 0.01 3
A
IOZ
High-impedance-state output
current (DO) VO = 0, TA = 25°C−0.01 −3 −0.01 −3 µA
CiInput capacitance 5 5 pF
CoOutput capacitance 5 5 pF
†All parameters are measured under open-loop conditions with zero common-mode input voltage.
‡All typical values are at VCC = 3.3 V, TA = 25°C.
analog and converter section
PARAMETER TEST CONDITIONS†MIN TYP‡MAX UNIT
VIC Common-mode input voltage See Note 3 −0.05
to
VCC+0.05 V
On channel VI = 3.3 V 1
II(stdby)
Standby input current (see Note 4)
Off channel VI = 0 −1
A
II(stdby
)
Standby input current (see Note 4) On channel VI = 0 −1 µA
Off channel VI = 3.3 V 1
ri(REF) Input resistance to REF 1.3 2.4 5.9 kΩ
†All parameters are measured under open-loop conditions with zero common-mode input voltage.
‡All typical values are at VCC = 3.3 V, TA = 25°C.
NOTES: 3. When ch a n nel IN− is more positive than channel IN+, the digital output code is 0000 0000. Connected to each analog input are two
on-chip diodes that conduct forward current for analog input voltages one diode drop above VCC. Care must be taken during testing
at low VCC levels (3 V) because high-level analog input voltage (3.6 V) can, especially at high temperatures, cause the input diode
to conduct and cause errors for analog inputs that are near full scale. As long as the analog voltage does not exceed the supply
voltage by m or e t h a n 5 0 m V, the output code is correct. To achieve an absolute 0- to 3.3-V input range requires a minimum VCC of
3.25 V for all variations of temperature and load.
4. Standby input currents go in or out of the on or of f channels when the A/D converter is not performing conversion and the clock is
in a high or low steady-state conditions.
total device
PARAMETER MIN TYP‡MAX UNIT
ICC Supply current
TLV0831 0.2 0.75
mA
I
CC
Supply current
TLV0832 1.5 2.5
mA
‡All typical values are at VCC = 3.3 V, TA = 25°C.
SLAS148 − SEPTEMBER 1996
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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
operating characteristics VCC = Vref = 3.3 V, f(CLK) = 250 kHz, tr = tf = 20 ns, TA = 25°C (unless
otherwise noted)
PARAMETER TEST CONDITIONS†MIN TYP MAX UNIT
Supply-voltage variation error VCC = 3 V to 3.6 V ±1/16 ±1/4 LSB
Total unadjusted error (see Note 5) Vref = 3.3 V,
TA = MIN to MAX ±1 LSB
Common-mode error Differential mode ±1/16 ±1/4 LSB
tpd
Propagation delay time,
output data after CLK↑
MSB-first data
CL = 100 pF
200 500
ns
tpd
output data after CLK↑
(see Note 6) LSB-first data CL = 100 pF 80 200 ns
tdis
Output disable time, DO after CS↑
CL = 10 pF, RL = 10 kΩ80 125
ns
tdis Output disable time, DO after CS↑CL = 100 pF, RL = 2 kΩ250 ns
tconv Conversion time (multiplexer-addressing
time not included) 8clock
periods
†All parameters are measured under open-loop conditions with zero common-mode input voltage. For conditions shown as MIN or MAX, use the
appropriate value specified under recommended operating conditions.
NOTES: 5. Total unadjusted error includes offset, full-scale, linearity, and multiplexer errors.
6. The MSB-first data is output directly from the comparator and, therefore, requires additional delay to allow for comparator response
time. LSB-first data applies only to TLV0832.
SLAS148 − SEPTEMBER 1996
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POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
PARAMETER MEASUREMENT INFORMATION
50%
tpd
50%
GND
VOL
VOH
VCC
CLK
DO
50%
tsu
thth
tsu
50%
V
CC
GND
GND
GND
0.4 V0.4 V
2 V
2 V
DI
0.4 V
CS
CLK
VCC
VCC
Figure 1. TLV0832 Data-Input Timing
Figure 2. Data-Output Timing
VOLTAGE W AVEFORMS
S2 open
S1 closed 10%
10%
90%
tr
VOLTAGE WAVEFORMS
S2 closed
S1 open
DO
Output
tr
S1
S2
LOAD CIRCUIT
(see Note A)
CL
From Output
Under Test
Test
Point
CS
CS
tdis
90%
10%
90%
50% 50%
VCC
GND
GND
GND
GND
VCC
VCC
VCC
V
CC
RL
DO
Output
tdis
NOTE A: CL includes probe and jig capacitance.
Figure 3. Output Disable Time Test Circuit and Voltage Waveforms
SLAS148 − SEPTEMBER 1996
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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
TYPICAL CHARACTERISTICS
V
ref
−
Reference Voltage − VV
ref
− Reference Voltage − V
VCC = 3.3 V
f(CLK) = 250 kHz
TA = 25°C
4321
0
0.25
0.5
0.75
1.0
1.25
0
1.5
101.00.10.01
VI+ = VI− = 0 V
0
2
4
6
8
10
12
14
16
UNADJUSTED OFFSET ERROR
vs
REFERENCE VOLTAGE
LINEARITY ERROR
vs
REFERENCE VOLTAGE
EO(unadj) − Unadjusted Offset Error − LSB
− Linearity Error − LSB
EL
Figure 4 Figure 5
f
(CLK)
− Clock Frequency − kHzT
A
− Free-Air Tempertature − °C
Vref = 3.3 V
f(CLK) = 250 kHz
1007550250−25
0.5
0.45
0.4
0.35
0.3
−50
0.25
LINEARITY ERROR
vs
FREE-AIR TEMPERATURE
LINEARITY ERROR
vs
CLOCK FREQUENCY
− Linearity Error − LSB
EL
− Linearity Error − LSB
EL
600500400300200100
2.0
1.8
1.2
1
0.8
0.2
0
0
85°C
25°C
−40°C
Vref = 3.3 V
VCC = 3.3 V
1.6
1.4
0.6
0.4
700 80
0
Figure 6 Figure 7
SLAS148 − SEPTEMBER 1996
10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
TYPICAL CHARACTERISTICS
f
(CLK)
− Clock Frequency − kHzT
A
− Free-Air Temperature — °C
f(CLK) = 250 kHz
CS = High
VCC = 3.6 V
VCC = 3 V
1007550250−25
0.3
0.2
−50
0.1
− Supply Current − mA
TLV0831
SUPPLY CURRENT
vs
FREE-AIR TEMPERATURE
TLV0831
SUPPLY CURRENT
vs
CLOCK FREQUENCY
CC
I
− Supply Current − mA
CC
I
VCC = 3.3 V
VCC = 3.3 V
TA = 25°C
5004003002001000
0
0.1
0.2
0.3
0.4
0.5
Figure 8 Figure 9
TA − Free-Air Temperature − °C
VCC = 3.3 V
IOL (DO = 0.4 V)
16
16.5
15.5
15
14.5
1007550250−25−50
14
− Output Current − mA
OUTPUT CURRENT
vs
FREE-AIR TEMPERATURE
IO
IOL (DO = 3.3 V)
−IOH (DO = 0 V)
−IOH (DO = 2.4 V)
Figure 10
SLAS148 − SEPTEMBER 1996
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
TYPICAL CHARACTERISTICS
Differential Nonlinearity − LSB
−1
Output Code
1
0.5
0
−0.5
0 32 64 96 128 160 192 224 256
Vref = 3.3 V
TA = 25°C
F(CLK) = 250 kHz
VDD = 3.3 V
Figure 11. Differential Nonlinearity With Output Code
Integral Nonlinearity − LSB
−1
Output Code
1
0.5
0
−0.5
0 32 64 96 128 160 192 224 256
Vref = 3.3 V
TA = 25°C
F(CLK) = 250 kHz
VDD = 3.3 V
Figure 12. Integral Nonlinearity With Output Code
Total Unadjusted Error − LSB
−1
Output Code
1
0.5
0
−0.5
0 32 64 96 128 160 192 224 256
Vref = 3.3 V
TA = 25°C
F(CLK) = 250 kHz
VDD = 3.3 V
Figure 13. Total Unadjusted Error With Output Code
PACKAGE OPTION ADDENDUM
www.ti.com 12-Nov-2010
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
TLV0831CD ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Request Free Samples
TLV0831CDG4 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Request Free Samples
TLV0831CDR ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Purchase Samples
TLV0831CDRG4 ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Purchase Samples
TLV0831CP ACTIVE PDIP P 8 50 Green (RoHS
& no Sb/Br) CU NIPDAU N / A for Pkg Type Request Free Samples
TLV0831CPE4 ACTIVE PDIP P 8 50 Green (RoHS
& no Sb/Br) CU NIPDAU N / A for Pkg Type Request Free Samples
TLV0831ID ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Request Free Samples
TLV0831IDG4 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Request Free Samples
TLV0831IDR ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Purchase Samples
TLV0831IDRG4 ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Purchase Samples
TLV0831IP ACTIVE PDIP P 8 50 Green (RoHS
& no Sb/Br) CU NIPDAU N / A for Pkg Type Request Free Samples
TLV0831IPE4 ACTIVE PDIP P 8 50 Green (RoHS
& no Sb/Br) CU NIPDAU N / A for Pkg Type Request Free Samples
TLV0832CD ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Request Free Samples
TLV0832CDG4 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Request Free Samples
TLV0832CDR ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Purchase Samples
TLV0832CDRG4 ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Purchase Samples
TLV0832CP ACTIVE PDIP P 8 50 Green (RoHS
& no Sb/Br) CU NIPDAU N / A for Pkg Type Request Free Samples
PACKAGE OPTION ADDENDUM
www.ti.com 12-Nov-2010
Addendum-Page 2
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
TLV0832CPE4 ACTIVE PDIP P 8 50 Green (RoHS
& no Sb/Br) CU NIPDAU N / A for Pkg Type Request Free Samples
TLV0832ID ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Request Free Samples
TLV0832IDG4 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Request Free Samples
TLV0832IDR ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Purchase Samples
TLV0832IDRG4 ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Purchase Samples
TLV0832IP ACTIVE PDIP P 8 50 Green (RoHS
& no Sb/Br) CU NIPDAU N / A for Pkg Type Request Free Samples
TLV0832IPE4 ACTIVE PDIP P 8 50 Green (RoHS
& no Sb/Br) CU NIPDAU N / A for Pkg Type Request Free Samples
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
PACKAGE OPTION ADDENDUM
www.ti.com 12-Nov-2010
Addendum-Page 3
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
TLV0831CDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
TLV0831IDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
TLV0832CDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
TLV0832IDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TLV0831CDR SOIC D 8 2500 367.0 367.0 35.0
TLV0831IDR SOIC D 8 2500 367.0 367.0 35.0
TLV0832CDR SOIC D 8 2500 367.0 367.0 35.0
TLV0832IDR SOIC D 8 2500 367.0 367.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
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