MGCL (il INTEGRATED CIRCUITS MEG (0 MC1600 Series (-30C to +85C) The requirement for digital systems with ever higher MECL. (El circuit design is similar to that used in the performance has increased the need for high-speed inte- popular MECL 10,000 family. In the MECL III line, as grated circuits. The industry has recognized that the only well as MECL 10,000, advanced processing techniques are economical way to obtain high operating system speed is employed and the capability for driving low-impedance through the use of emitter-coupled logic. Motorola offers terminated lines is provided. MECL III is recommended a state-of-the-art, emitter-coupled logic family with sub- for new designs. nanosecond propagation delays MECL III. GENERAL FEATURES @ Gate Switching Speeds of 1.0 ns typical Capability of Driving Terminated Lines with Impedance as Low as 50 Ohms @ Flip-Flop Toggle Rate Greater Than 500 MHz Operation with Unused Inputs Left Open @ Multilayer Metalization for economy mn a @ New Packages with Improved Electrical and Thermal Characteristics 1 Y @ Compatibility with MECL 10,000 Series Counting Speeds to above 1 GHz PLASTIC PRCKAGE CERAMIC PACKAGE CASE 646 CASE 632 wt P SUFFIX F SUFFIX F SUFFIX L SUFFIX CERAMIC PACKAGE PLASTIC PACKAGE CERAMIC PACKAGE CERAMIC PACKAGE CASE 650 CASE 648 CASE 607 CASE 620 FUNCTIONS AND CHARACTERISTICS (Vcc = 0, Veg = -5.2'V, Ta = 25C unless otherwise noted.) Power Dissipation Type @ Loading Factor # ereponm Lead Now Function -30 to +85C Each Output ns typ typipkg Case Voltage Controlled Oscillator Mc 1648 - *225 MHz typ 150 607,632,646 Dual A/D Comparator MC 1650 70 3.5 275 620,650 Dual A/D Comparator MC1651 70 3.0 2758 620,650 Binary Counter MC 1654 76 *325 MHz typ 760 22/ 620 Voitage-Controlled Multivibrator MC 1658 70 *150 MHz typ 425 620,648,650 Dual 4-Input OR/NOR Gate MC1660 70 1.1 120 620,650 Quad 2-Input NOR Gate MC1662 70 1.1 240 620,650 Quad 2-Input OR Gate MC 1664 70 11 246 626,656 Dual Clocked R-S Flip-Flop MC 1666 70 1.8 220 620,650 Dual Clocked Latch MC 1668 70 1.8 220 620,650 Master-Slave Type D Flip-Flop MC1670 70 *350 MHz typ 220 620,650 Triple 2-Input Exclusive OR Gate MC1672 70 1.3 220 620,850 Tripte 2-tnput Exciusive NOR Gate MC 1674 70 1.3 220 620,550 Bi-Quinary Counter MC1678 70 *350 MHz typ 750 24/ 620 Dual 4-5-Input OR/NOR Gate MC1688 70 0.8 125 650 UHF Prescaler Type D Flip-Flop MC 1690 70 *500 MHz min 200 620,550 Quad Line Receiver Mic 1692 7G tt 220 620,650 4-Bit Shift Register MC1694 70 *325 MHz typ 750 22/ 620 1 GHz Divide-By-Ten Counter MC1696 - *1 GHz min 650 650 L suffix denotes Dual In-Line Ceramic Package, F suffix denotes Ceramic Flat Package, P suffix denotes Dual In-Line Plastic Package. (i.e., MC16Q0L = Ceramic Dual In-Line Package, MC1GQ0F = Ceramic Flat Package, MC1600P = Plastic Qual In-Line Package). LL/J Requires Heat Sink 1ERC-LIC-214A2WCB or equivalent. *Toggle Frequency #DC Loading Factors are based on: 1. Full load output current, IL = -25 mAdc max 2. Maximum input current, big = 350 wAdc 2-5MIEGE 00 LOGIC DIAGRAMS Numbers at ends of terminals denote pin numbers for L package (Case 620 unless noted as Case 632) and P package (Case 646 unless noted as Case 648). case|_ Vv, Ve Numbers in parenthesis denote pin numbers for F package (Case 650 unless noted as Case 607). 650 4,5 12 -- GATES 4 See individual drawing for devices with other Cases, MC1660 Dual 4-Input OR/NOR Gate (a) 4A (9) 5 3 X 3 (7) (10) 6 Y_2 (6) any 72 (14) 10 (15) 14 14 (2) (16) 12 15 (3) (1) 13 X= AtBtC+O Y = AtB+C+D tod = 0.9 ns typ (51G-ohm Joad) 1.1 ns typ (50-ohm load) Pp = 120 mw typ/pkg (no load) MC1662 Quad 2-Input NOR Gate A 8 (9) 5 (10) oo 41) 7 (14) 10 (15) 11 (16) 12 | O- 2 (6) 3 (7) 14 (2) 15 (3) X= AtB tpg = 0.9 ns typ (510-ohm load) 1.1 ns typ (50-ohm load) Pp = 240 mW typ/pkg (no load) MC1664 Quad 2-input OR Gate (3) 44 x 1) 58 2 (6) 410) 6 aay 7 3) (14) 10 (5) 14 14 (2) (16) 12 (4) 13 15 (3) xX=AtB toa = 0.9 ns typ (610-ohm load) 1.1 ns typ (50-ohm load) PD = 240 mW typ/pkg (no load) MC1672 Triple 2-Input Exclusive OR Gate (8) 3 x (9) 6 > 2 6) (16) 13 40) <a) (2) ae 2) os (3) (11) 7- = 1.1ns typ (510-ohm toad) = 1.3 ns typ (50-ohm toad) Pp = 220 mW typ/pkg pd Mc1674 Triple 2-Input Exclusive NOR Gate (8) 3 x (9) 5 ) z (6) (16) 13 (10) 6 (14) 17 J 5 (11) 7 > 18 (3) X=ASBtACB tog = 1.1 styp (510-ohm load) = 1,3 ns type (50-ohm load) Pp = 220 mW typ/pkg MC 1688 Dual 4-5-input OR/NOR Gate (8) (9) 7) (10) (e) (11) (13) (14) (2) (15) {3) (16) (1) toa= 0.8 ns typ PD = 125 mW typ/pkg (No Load) 2-6QUAD 2-INPUT OR GATE MECL II! MC1600 series MC1664 POSITIVE LOGIC NEGATIVE LOGIC (9) 6) (9) 5 (10) (10) a! (41) (11) (14) 10 (14) 190 14 (2 14 ( (18) =. 2) (1) = (16) 12. 3 (16) 12 @) 13 169) (1) 13 X=A+B X=ACB Voec1 = Pin 1 (5) Vec2 = Pin 16 (4) Vee = Pin 8 (12) 15 ( Number in parenthesis denotes pin number for F package (Case 650). 2) 3) Number at end of terminals denotes pin number of L package (Case 620). Four 2-input OR or AND gating functions in a single package. An internal bias reference voltage insures that the threshold point remains in the center of the transition region over the temperature range -30 to +85C. Input pulidown resistors eliminate the need to tie unused inputs to VEE. tod = 0.9 ns typ {510-ohm load) = 4,1 ns typ (50-ohm load) Pp = 240 mW typ/pkg (No load) Full Load Current, [_ = -25 mAdc max Vec2 (14) (15) (12) CIRCUIT SCHEMATIC (11) (10) (4) (5) (8) (9) 7 6 16 1 4 5 2k 365 50k (16) (1) See General Information section for packaging. 4-386E-7 ELECTRICAL CHARACTERISTICS This MECL I/I circuit has been designed to meet the dc specifications shown in the test table, after thermal equitibrium has been established. Air flow greater than 500 linear fpm should be maintained while the circuit is either in a test socket or is mounted on a printed circuit board. Test procedures are shown for only one input and one output. The other inputs and outputs are tested in a similar manner. Outputs are tested with a 50-ohm resistor to -2.0 Vdc. See general information sec- tion for compiete thermai data. F SUFFIX CERAMIC PACKAGE 9 __) 6 CASE 650 10 7 11 14 2 15 16 3 TEST VOLTAGE VALUES 1 {Volts} @ Test Temperature Vit max VIL min VIHA min VILA max VEE -30C -0.875 -1,890 1,180 -1.515 5.2 +25C -0.810 -1.850 -1.095 ~1.485 5.2 +85C ~0.700 -1.830 ~1.025 -1.440 5.2 Pin MC1664F Test Limits TEST VOLTAGE APPLIED TO PINS LISTED BELOW: Under ~30C +25C +85C (Vcc) Characteristic Symbol Test Min Max Min Max Min Max Unit VIH max VIL min VIHA min VILA max VEE Gnd Power Supply Drain Current te 12 _ = - 56 _ = mAdc = _ ~ 12 45 Input Current lin * - - 350 - - uAdc * - = - 12 45 lin L * ~ = 05 = uAde = * ~ 12 45 Logic 1 Vou 6 -1.045 | -0:875 | -o.960 | -0.810 -0.890 | -0.700 Vde 8 - = 12 45 Output Voltage 6 -1.045 | -0.875 | -0.960 | -0.810 | -0.890 | -0.700 Vde 9 - - - 12 45 Logic 0 VoL 6 -1.890 | -1.650 [ -1850 [ -1.620 | -1830 | -1.575 Vde = 8 = = 12 45 Output Voltage 6 -1.890 | -1.650 | -1.850 | -1.620 | -1.830 | -1.575 Vde - 9 - - 12 45 Logic "1" VoHA 6 -1,065 - -0.980 - -0.910 = Vde ~ - 8 - 12 45 Threshold Voltage 6 1.065 = -0.980 - -0.910 = Vde - ~ 9 - 12 45 Logic O" VOLA 6 - -1.630 = ~1.600 = -1,555 Vde - = - 8 12 45 Threshold Voltage 6 = -1.630 = 1.600 = ~1.555 Vde = = = 9 12 4,5 Switching Times (50 {2 Load) Pulse In Pulse Out 3.2 +2.0V Propagation Delay terg+ 6 - 16 - 15 - 17 ns 8 6 - - 12 45 tg.g- 6 _ 1.8 = 17 - 19 ns 8 6 - = 12 45 Rise Time tee 6 = 2.2 - 24 ~ 2.3 ns 8 6 = = 12 45 Fall Time . tg- 6 - 2.2 _ 21 ~ 2.3 ns 8 6 - - 42 45 *Individually test each input applying Vj or Vi, to input under test. (panuluos) 7991 OWOr-r ELECTRICAL CHARACTERISTICS This MECL II! circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibrium has been established. The package should be housed in a suitable heat sink (!ERC- 14A2CB or equivalent) or a transverse air flow greater than 500 linear fpm should be maintained while the circuit is either in a test socket or is mounted on a printed circuit board. Test procedures are shown 4 ) 2 for only one input and one output. The 5 other inputs and outputs are tested in a 6 L SUFFIX similar manner, Outputs are tested with a ) CERAMIC PACKAGE 0-ohm resistor to -2.0 Vdc. See general 7 CASE 620 information section for complete thermal 10 ee data. 1 <> 15 13 TEST VOLTAGE VALUES {Volts} @ Test Temperature VIH max VEL min VIHA min VILA max VEE -30C -0.875 -1.890 -1.180 1.515 -5.2 +25C -0.810 -1.850 -1.095 -1.485 5.2 +85C | 9.700 -1.830 -1.025 1.440 5.2 Pin MC1G641. Test Limits TEST VOLTAGE APPLIED TO PINS LISTED BELOW: Under _=30C +25C +85C T cl isti Symbol Test Min Max Min Max Min Max Unit Vit max VIL min VIHA min VILA max VEE Gnd Power Supply Drain Current le 8 - - _ 56 - - mAdc - - - 8 4,16 \aput Current lin * - - - 350 = - wAdc * - - - 8 1,16 lin L " = = 05 - = uAde = . ~ = 8 1,16 Logic "1" Vou 2 -1,045 | -0875 | -0.960 | -0.810 | -0.890 | -0.700 Vde 4 - - = 8 1,16 Output Voltage 2 -1.045 | -0875 | -o960 | -0.8710 | -0.890 | -0.700 Vde 5 = - - 8 1,16 Logic 0 VOL 2 -1,890 | -1.650 | -1.850 | -1.620 | -1.830 | -1.575 Vde 4 = - 8 1,16 Output Voltage 2 -1.890 | -1.650 | -1.850 | -1.620 | -1.830 | -1.575 Vdc - 5 - - 8 1,16 Logic 1 VOHA 2 -1.065 - -0.980 - -0.910 _ Vde - 4 - 8 116 Threshold Voltage 2 -1,065 - -0.980 ~ -0.910 - Vde = - 5 8 116 Logic 0. VOLA 2 = ~1.630 -1.600 = ~1.565 Vde - - - 4 8 1,16 Threshold Voltage 2 - ~1,630 = ~1.600 = -1,565 Vde _ = 5 8 1,16 Switching Times (50 2 Load) Putse In Pulse Out 3.2 +2.0V Propagation Delay 14t2+ 2 - 1.6 - 15 - 17 ns 4 2 - - 8 1,16 t4-2- 2 - 18 - 1.7 _ 19 ns 4 2 - ~ 8 1,16 Rise Time t2+ 2 = 2.2 : 24 - 23 ns 4 2 8 1,16 Fall Time t2- 2 = 2.2 = 2.1 = 23 ns 4 2 = = 8 1,16 * Individually test each input applying V;44 or Vi, to input under test. (Psnunucs) POO LOINMC 1664 (continued) SWITCHING TIME TEST CIRCUIT AND WAVEFORMS @ 25C Vin to Channel A Vout to Channel B +1.14 V Input +0.31V Pulse Generstor Vout All input and output cables to the scope are equal lengths of 50-ohm coaxial cable. Input Pulse ty = t= 1.5 (40.2) ns Unused outputs connected to a 50-ohm resistor to ground. 4-41