2SK973(L), 2SK973(S)
Silicon N-Channel MOS FET
November 1996
Application
High speed power switching
Features
Low on-resistance
High speed switching
Low drive current
4 V gate drive device
Can be driven from 5 V source
Suitable for motor drive, DC-DC converter, power switch and solenoid drive
Outline
123
123
4
4
DPAK-1
1. Gate
2. Drain
3. Source
4. Drain
D
G
S
2SK973(L), 2SK973(S)
2
Absolute Maximum Ratings (Ta = 25°C)
Item Symbol Ratings Unit
Drain to source voltage VDSS 60 V
Gate to source voltage VGSS ±20 V
Drain current ID2A
Drain peak current ID(peak)*18A
Body to drain diode reverse drain current IDR 2A
Channel dissipation Pch*210 W
Channel temperature Tch 150 °C
Storage temperature Tstg –55 to +150 °C
Notes 1. PW 10 µs, duty cycle 1%
2. Value at TC = 25°C
2SK973(L), 2SK973(S)
3
Electrical Characteristics (Ta = 25°C)
Item Symbol Min Typ Max Unit Test conditions
Drain to source breakdown
voltage V(BR)DSS 60——V I
D
= 10 mA, VGS = 0
Gate to source breakdown
voltage V(BR)GSS ±20——V I
G
= ±100 µA, VDS = 0
Gate to source leak current IGSS ——±10 µAV
GS = ±16 V, VDS = 0
Zero gate voltage drain current IDSS 100 µAV
DS = 50 V, VGS = 0
Gate to source cutoff voltage VGS(off) 1.0 2.0 V ID = 1 mA, VDS = 10 V
Static drain to source on state
resistance RDS(on) 0.25 0.35 ID = 1 A, VGS = 10 V *1
0.40 0.50 ID = 1 A, VGS = 4 V *1
Forward transfer admittance |yfs| 1.2 2.0 S ID = 1 A, VDS = 10 V * 1
Input capacitance Ciss 240 pF VDS = 10 V, VGS = 0,
f = 1 MHz
Output capacitance Coss 115 pF
Reverse transfer capacitance Crss 35 pF
Turn-on delay time td(on) —4 —nsI
D
= 1 A, VGS = 10 V,
RL = 30
Rise time tr—15—ns
Turn-off delay time td(off) —80—ns
Fall time tf—40—ns
Body to drain diode forward
voltage VDF 1.0 V IF = 2 A, VGS = 0
Body to drain diode reverse
recovery time trr —70—nsI
F
= 2 A, VGS = 0,
diF/dt = 50 A/µs
Note 1. Pulse test
2SK973(L), 2SK973(S)
4
50 1000 Case Temperature TC (°C) 150
5
Channel Dissipation Pch (W)
10
15 Power vs. Temperature Derating Maximum Safe Operation Area
Drain Current ID (A)
0.3 1.0 3
1.0
3
10
10
30
50
Drain to Source Voltage VDS (V)
0.1 100
0.3
30
0.05
0.1
100 µs
1 ms
PW = 10 ms (1 Shot)
DC Operation (T
C
= 25°C)
Ta = 25°C
10 µs
Operation in this area is
limited by RDS (on)
Typical Output Characteristics
6
Drain to Source Voltage VDS (V)
842 10
Drain Current ID (A)
0
1
2
3
4
0
5
VGS = 2 V
Pulse Test
10 V
5 V
4 V
3 V
3.5 V
2.5 V
Typical Transfer Characteristics
3
Gate to Source Voltage VGS (V)
42105
1
2
3
4
5
0
Drain Current ID (A)
TC= 25°C
75°C
VDS = 10 V
Pulse Test
–25°C
Drain to Source Saturation Voltage
vs. Gate to Source Voltage
6
Gate to Source Voltage VGS (V)
842010
0.8
1.2
1.6
2.0
0
0.4
Drain to Source Saturation Voltage
VDS (on) (V)
Pulse Test
ID = 1 A
5 A
2 A
2
Drain Current ID (A)
51.00.5 20
0.2
0.5
1.0
2
5
0.2
0.1
0.05 10
Static Drain to Source on State
Resistance vs. Drain Current
Static Drain to Source on State Resistance
RDS (on) ()
VGS = 4 V
10 V
Pulse Test
80
Case Temperature TC (°C)
120400
0.2
0.4
0.6
0.8
1.0
–40
0160
Static Drain to Source on State
Resistance vs. Temperature
Static Drain to Source on State Resistance
RDS (on) ()
ID = 2 A
Pulse Test
VGS = 4 V
VGS = 10 V 5 A
1 A
1 A, 2 A
Forward Transfer Admittance
vs. Drain Current
10
5
2
1.0
0.5
0.2
0.1
0.05 0.1 0.2 0.5 1.0 5
Drain Current ID (A) 2
Forward Transfer Admittance yfs (S)
TC = 25°C
VDS = 10 V
Pulse Test –25°C
75°C
2SK973(L), 2SK973(S)
5
500
200
100
50
20
10
5
0.2 0.5 2 20
Reverse Drain Current IDR (A)
5
1.0 10
Body to Drain Diode Reverse
Recovery Time
Reverse Recovery Time trr (ns)
di/dt = 50 A/µs, Ta = 25°C
VGS = 0
Pulse Test
Typical Capacitance vs.
Drain to Source Voltage
1000
300
100
30
3
1
Capacitance C (pF)
01020 50
Drain to Source Voltage VDS (V)
30
10
40
VGS = 0
f = 1 MHz
Ciss
Coss
Crss
100
80
60
40
20
02 6
8
Gate Charge Qg (nc)
4
20
16
12
8
4
Dynamic Input Characteristics
Drain to Source Voltage VDS (V)
Gate to Source Voltage VGS (V)
10
VDS
VGS
VDD = 50 V
10 V
25 V
VDD = 50 V
25 V
10 V ID = 2 A
Switching Characteristics
100
50
20
10
2
1
0.05 0.1 0.5 5
Drain Current ID (A)
1.0
0.2 2
Switching Time t (ns)
5
td (off)
tf
tr
VGS = 10 V VDD = 30 V
PW = 2µs, duty < 1 %
td (on)
•
5
4
3
2
1
0 0.4 1.2 1.6 2.0
Source to Drain Voltage VSD (V)
0.8
Reverse Drain Current vs.
Source to Drain Voltage
Reverse Drain Current IDR (A)
VGS = 0, –5 V
Pulse Test
10 V
15 V
5 V
2SK973(L), 2SK973(S)
6
3
1.0
0.3
0.1
0.03
0.01
10 µ1 m 10 m 100 m
Pulse Width PW (s)
100 µ110
Normalized Transient Thermal Impedance vs. Pulse Width
Normalized Transient Thermal Impedance γS (t)
θch–c(t) = γS (t) · θch–c
θch–c = 12.5°C/W, TC = 25°C
PDM
PW D = PW
T
T
TC = 25°C
D = 1
0.5
0.05
1 Shot Pulse
0.2
0.1
0.02
0.01
Vin Monitor
Vout Monitor
RL
50
Vin = 10 V
D.U.T
.
VDD = 30 V
.
Switching Time Test Circuit
Vin 10 %
90 %
90 %
90 %
10 %
td (on) td (off)
trtf
Vout 10 %
Wavewforms
2SK973(L), 2SK973(S)
7
Notice
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part of this document without Hitachi’s permission.
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any other reasons during operation of the user’s unit according to this document.
4. Circuitry and other examples described herein are meant merely to indicate the characteristics and
performance of Hitachi’s semiconductor products. Hitachi assumes no responsibility for any
intellectual property claims or other problems that may result from applications based on the examples
described herein.
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party or Hitachi, Ltd.
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APPLICATIONS without the written consent of the appropriate officer of Hitachi’s sales company.
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