LTC1966
1
1966fb
Typical applicaTion
FeaTures DescripTion
Precision Micropower
∆∑ RMS-to-DC Converter
applicaTions
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and
No Latency DS is a trademark of Linear Technology Corporation. All other trademarks are the
property of their respective owners. Protected by U.S. Patents including 6359576, 6362677,
6516291 and 6651036.
n Simple to Use, Requires One Capacitor
n True RMS DC Conversion Using DS Technology
n High Accuracy:
0.1% Gain Accuracy from 50Hz to 1kHz
0.25% Total Error from 50Hz to 1kHz
n High Linearity:
0.02% Linearity Allows Simple System Calibration
n Low Supply Current:
155µA Typ, 170µA Max
n Ultralow Shutdown Current:
0.1µA
n Constant Bandwidth:
Independent of Input Voltage
800kHz –3dB, 6kHz ±1%
n Flexible Supplies:
2.7V to 5.5V Single Supply
Up to ±5.5V Dual Supply
n Flexible Inputs:
Differential or Single-Ended
Rail-to-Rail Common Mode Voltage Range
Up to 1VPEAK Differential Voltage
n Flexible Output:
Rail-to-Rail Output
Separate Output Reference Pin Allows Level Shifting
n Wide Temperature Range:
–55°C to 125°C
n Small Size:
Space Saving 8-Pin MSOP Package
The LTC
®
1966 is a true RMS-to-DC converter that utilizes
an innovative patented DS computational technique. The
internal delta sigma circuitry of the LTC1966 makes it sim-
pler to use, more accurate, lower power and dramatically
more flexible than conventional log antilog RMS-to-DC
converters.
The LTC1966 accepts single-ended or differential input
signals (for EMI/RFI rejection) and supports crest factors up
to 4. Common mode input range is rail-to-rail. Differential
input range is 1VPEAK, and offers unprecedented linearity.
Unlike previously available RMS-to-DC converters, the
superior linearity of the LTC1966 allows hassle free system
calibration at any input voltage.
The LTC1966 also has a rail-to-rail output with a separate
output reference pin providing flexible level shifting. The
LTC1966 operates on a single power supply from 2.7V to
5.5V or dual supplies up to ±5.5V. A low power shutdown
mode reduces supply current to 0.5µA.
The LTC1966 is insensitive to PC board soldering and
stresses, as well as operating temperature. The LTC1966
is packaged in the space saving MSOP package which is
ideal for portable applications.
n True RMS Digital Multimeters and Panel Meters
n True RMS AC + DC Measurements
Single Supply RMS-to-DC Converter
Quantum Leap in Linearity Performance
CAVE
1µF VOUT
+
–
1966 TA01
2.7V TO 5.5V
OUTPUT
DIFFERENTIAL
INPUT LTC1966
VDD
0.1µF
OPT. AC
COUPLING
VSS
EN GND
OUT RTN
IN1
IN2
VIN (mV ACRMS)
–1.0
LINEARITY ERROR (VOUT mV DC – VIN mV ACRMS)
–0.6
–0.2
0.2
–0.8
–0.4
0
100 200 300 400
1966 TA01b
500500 150 250 350 450
LTC1966, ∆∑
60Hz SINEWAVES
CONVENTIONAL
LOG/ANTILOG
LTC1966
2
1966fb
pin conFiguraTionabsoluTe MaxiMuM raTings
(Note 1)
1
2
3
4
GND
IN1
IN2
VSS
8
7
6
5
ENABLE
VDD
OUT RTN
VOUT
TOP VIEW
MS8 PACKAGE
8-LEAD PLASTIC MSOP
TJMAX = 150°C, θJA = 220°C/W
orDer inForMaTion
LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE
LTC1966CMS8#PBF LTC1966CMS8#TRPBF LTT G 8-Lead Plastic MSOP 0°C to 70°C
LTC1966IMS8#PBF LTC1966IMS8#TRPBF LTT H 8-Lead Plastic MSOP –40°C to 85°C
LTC1966HMS8#PBF LTC1966HMS8#TRPBF LTT G 8-Lead Plastic MSOP –40°C to 125°C
LTC1966MPMS8#PBF LTC1966MPMS8#TRPBF LTT G 8-Lead Plastic MSOP –55°C to 125°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
elecTrical characTerisTics
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
Conversion Accuracy
GERR Conversion Gain Error 50Hz to 1kHz Input (Notes 6, 7)
LTC1966C, LTC1966I
LTC1966H, LTC1966MP
l
l
±0.1
±0.3
±0.4
±0.7
%
%
%
VOOS Output Offset Voltage (Notes 6, 7)
LTC1966C, LTC1966I
LTC1966H, LTC1966MP
l
l
0.1
0.2
0.4
0.6
mV
mV
mV
LINERR Linearity Error 50mV to 350mV (Notes 7, 8) l0.02 0.15 %
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VDD = 5V, VSS = –5V, VOUTRTN = 0V, CAVE = 10µF, VIN = 200mVRMS,
VENABLE = 0.5V unless otherwise noted.
Supply Voltage
VDD to GND ............................................. – 0.3V to 7V
VDD to VSS ............................................ –0.3V to 12V
VSS to GND ............................................. –7V to 0.3V
Input Currents (Note 2) ...................................... ±10mA
Output Current (Note 3) ..................................... ± 10mA
ENABLE Voltage ....................... VSS – 0.3V to VSS + 12V
OUT RTN Voltage ............................... VSS – 0.3V to VDD
Operating Temperature Range (Note 4)
LTC1966C/LTC1966I ............................ –40°C to 85°C
LTC1966H .......................................... –40°C to 125°C
LTC1966MP ....................................... –55°C to 125°C
Specified Temperature Range (Note 5)
LTC1966C/LTC1966I ............................ –40°C to 85°C
LTC1966H .......................................... –40°C to 125°C
LTC1966MP ....................................... –55°C to 125°C
Maximum Junction Temperature ......................... 150°C
Storage Temperature Range ................. –65°C to 150°C
Lead Temperature (Soldering, 10 sec) .................. 300°C
LTC1966
3
1966fb
elecTrical characTerisTics
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VDD = 5V, VSS = –5V, VOUTRTN = 0V, CAVE = 10µF, VIN = 200mVRMS,
VENABLE = 0.5V unless otherwise noted.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
PSRR Power Supply Rejection (Note 9)
LTC1966C, LTC1966I
LTC1966H, LTC1966MP
l
l
0.02
0.15
0.20
0.3
%V
%V
%V
VIOS Input Offset Voltage (Notes 6, 7, 10)
l
0.02 0.8
1.0 mV
mV
Accuracy vs Crest Factor (CF)
CF = 4 60Hz Fundamental, 200mVRMS (Note 11) l–1 2 mV
CF = 5 60Hz Fundamental, 200mVRMS (Note 11) l–20 30 mV
Input Characteristics
IVR Input Voltage Range (Note 14) lVSS VDD V
ZIN Input Impedance Average, Differential (Note 12)
Average, Common Mode (Note 12)
8
100
MΩ
MΩ
CMRRI Input Common Mode Rejection (Note 13) l7 200 µV/V
VIMAX Maximum Input Swing Accuracy = 1% (Note 14) l1 1.05 V
VIMIN Minimum RMS Input l5 mV
PSRRI Power Supply Rejection VDD Supply (Note 9)
VSS Supply (Note 9)
l
l
250
120 600
300 µV/V
µV/V
Output Characteristics
OVR Output Voltage Range lVSS VDD V
ZOUT Output Impedance VENABLE = 0.5V (Note 12)
VENABLE = 4.5V
l75 85
30 95 kΩ
kΩ
CMRRO Output Common Mode Rejection (Note 13) l16 200 µV/V
VOMAX Maximum Differential Output Swing Accuracy = 2%, DC Input (Note 14)
l
1.0
0.9 1.05 V
V
PSRRO Power Supply Rejection VDD Supply (Note 9)
VSS Supply (Note 9)
l
l
250
50 1000
500 µV/V
µV/V
Frequency Response
f1P 1% Additional Error (Note 15) CAVE = 10µF 6 kHz
f10P 10% Additional Error (Note 15) CAVE = 10µF 20 kHz
f–3dB ±3dB Frequency (Note 15) 800 kHz
Power Supplies
VDD Positive Supply Voltage l2.7 5.5 V
VSS Negative Supply Voltage (Note 16) l–5.5 0 V
IDD Positive Supply Current IN1 = 20mV, IN2 = 0V
IN1 = 200mV, IN2 = 0V
l155
158 170 µA
µA
ISS Negative Supply Current IN1 = 20mV, IN2 = 0V l12 20 µA
Shutdown Characteristics
IDDS Supply Currents VENABLE = 4.5V l0.5 10 µA
ISSS Supply Currents VENABLE = 4.5V
LTC1966H, LTC1966MP
l
l
–1
–2 –0.1 µA
µA
IIH ENABLE Pin Current High VENABLE = 4.5V l–0.3 –0.05 µA
LTC1966
4
1966fb
elecTrical characTerisTics
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The inputs (IN1, IN2) are protected by shunt diodes to VSS and
VDD. If the inputs are driven beyond the rails, the current should be limited
to less than 10mA.
Note 3: The LTC1966 output (VOUT) is high impedance and can be
overdriven, either sinking or sourcing current, to the limits stated.
Note 4: The LTC1966C/LTC1966I are guaranteed functional over
the operating temperature range of –40°C to 85°C. The LTC1966H/
LTC1966MP are guaranteed functional over the operating temperature
range of –55°C to 125°C.
Note 5: The LTC1966C is guaranteed to meet specified performance from
0°C to 70°C. The LTC1966C is designed, characterized and expected to
meet specified performance from –40°C to 85°C but is not tested nor
QA sampled at these temperatures. The LTC1966I is guaranteed to meet
specified performance from –40°C to 85°C. The LTC1966H is guaranteed
to meet specified performance from –40°C to 125°C. The LTC1966MP is
guaranteed to meet specified performance from –55°C to 125°C.
Note 6: High speed automatic testing cannot be performed with
CAVE = 10µF. The LTC1966 is 100% tested with CAVE = 22nF. Correlation
tests have shown that the performance limits above can be guaranteed
with the additional testing being performed to guarantee proper operation
of all the internal circuitry.
Note 7: High speed automatic testing cannot be performed with 60Hz
inputs. The LTC1966 is 100% tested with DC and 10kHz input signals.
Measurements with DC inputs from 50mV to 350mV are used to calculate
the four parameters: GERR, VOOS, VIOS and linearity error. Correlation tests
have shown that the performance limits above can be guaranteed with the
additional testing being performed to guarantee proper operation of all
internal circuitry.
Note 8: The LTC1966 is inherently very linear. Unlike older log/antilog
circuits, its behavior is the same with DC and AC inputs, and DC inputs are
used for high speed testing.
Note 9: The power supply rejections of the LTC1966 are measured with DC
inputs from 50mV to 350mV. The change in accuracy from VDD = 2.7V to
VDD = 5.5V with VSS = 0V is divided by 2.8V. The change in accuracy from
VSS = 0V to VSS = –5.5V with VDD = 5.5V is divided by 5.5V.
Note 10: Previous generation RMS-to-DC converters required nonlinear
input stages as well as a nonlinear core. Some parts specify a DC reversal
error, combining the effects of input nonlinearity and input offset voltage.
The LTC1966 behavior is simpler to characterize and the input offset
voltage is the only significant source of DC reversal error.
Note 11: High speed automatic testing cannot be performed with 60Hz
inputs. The LTC1966 is 100% tested with DC stimulus. Correlation tests
have shown that the performance limits above can be guaranteed with the
additional testing being performed to verify proper operation of all internal
circuitry.
Note 12: The LTC1966 is a switched capacitor device and the input/
output impedance is an average impedance over many clock cycles. The
input impedance will not necessarily lead to an attenuation of the input
signal measured. Refer to the Applications Information section titled Input
Impedance for more information.
Note 13: The common mode rejection ratios of the LTC1966 are measured
with DC inputs from 50mV to 350mV. The input CMRR is defined as the
change in VIOS measured between input levels of VSS to VSS + 350mV and
input levels of VDD – 350mV to VDD divided by VDD – VSS – 350mV. The
output CMRR is defined as the change in VOOS measured with OUT RTN =
VSS and OUT RTN = VDD – 350mV divided by VDD – VSS – 350mV.
Note 14: Each input of the LTC1966 can withstand any voltage within
the supply range. These inputs are protected with ESD diodes, so going
beyond the supply voltages can damage the part if the absolute maximum
current ratings are exceeded. Likewise for the output pins. The LTC1966
input and output voltage swings are limited by internal clipping. The
maximum differential input of the LTC1966 (referred to as maximum input
swing) is 1V. This applies to either input polarity, so it can be thought of as
±1V. Because the differential input voltage gets processed by the LTC1966
with gain, it is subject to internal clipping. Exceeding the 1V maximum
can, depending on the input crest factor, impact the accuracy of the output
voltage, but does not damage the part. Fortunately, the LTC1966’s ∆∑
topology is relatively tolerant of momentary internal clipping. The input
clipping is tested with a crest factor of 2, while the output clipping is
tested with a DC input.
Note 15: The LTC1966 exploits oversampling and noise shaping to reduce
the quantization noise of internal 1-bit analog-to-digital conversions. At
higher input frequencies, increasingly large portions of this noise are
aliased down to DC. Because the noise is shifted in frequency, it becomes
a low frequency rumble and is only filtered at the expense of increasingly
long settling times. The LTC1966 is inherently wideband, but the output
accuracy is degraded by this aliased noise. These specifications apply with
CAVE = 10µF and constitute a 3-sigma variation of the output rumble.
Note 16: The LTC1966 can operate down to 2.7V single supply but cannot
operate at ±2.7V. This additional constraint on VSS can be expressed
mathematically as –3 • (VDD – 2.7V) ≤ VSS ≤ Ground.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
IIL ENABLE Pin Current Low VENABLE = 0.5V
LTC1966H, LTC1966MP
l
l
–2
–10 –1 –0.1 µA
µA
VTH ENABLE Threshold Voltage VDD = 5V, VSS = –5V
VDD = 5V, VSS = GND
VDD = 2.7V, VSS = GND
2.4
2.1
1.3
V
V
V
VHYS ENABLE Threshold Hysteresis 0.1 V
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VDD = 5V, VSS = –5V, VOUTRTN = 0V, CAVE = 10µF, VIN = 200mVRMS,
VENABLE = 0.5V unless otherwise noted.
LTC1966
5
1966fb
Typical perForMance characTerisTics
Gain and Offsets
vs Input Common Mode
INPUT COMMON MODE (V)
0
–0.5
GAIN ERROR (%)
OFFSET VOLTAGE (mV)
–0.4
–0.2
–0.1
0
0.5
0.2
1.0 2.0 2.5 5.04.5
1966 G02
–0.3
0.3
0.4
0.1
–0.5
–0.4
–0.2
–0.1
0
0.5
0.2
–0.3
0.3
0.4
0.1
0.5 1.5 3.0 3.5 4.0
VDD = 5V
VSS = GND VIOS
VOOS
GAIN ERROR
Gain and Offsets
vs Input Common Mode
INPUT COMMON MODE (V)
–5
–0.5
GAIN ERROR (%)
OFFSET VOLTAGE (mV)
–0.4
–0.2
–0.1
0
0.5
0.2
–3 –1 0 54
1966 G03
–0.3
0.3
0.4
0.1
–0.5
–0.4
–0.2
–0.1
0
0.5
0.2
–0.3
0.3
0.4
0.1
–4 –2 123
VDD = 5V
VSS = –5V
VIOS
VOOS
GAIN ERROR
Gain and Offsets
vs Output Common Mode
OUTPUT COMMON MODE (V)
0
–0.5
GAIN ERROR (%)
OFFSET VOLTAGE (mV)
–0.4
–0.2
–0.1
0
0.5
0.2
1.0 2.0 2.5 5.04.5
1966 G05
–0.3
0.3
0.4
0.1
–0.5
–0.4
–0.2
–0.1
0
0.5
0.2
–0.3
0.3
0.4
0.1
0.5 1.5 3.0 3.5 4.0
VDD = 5V
VSS = GND
VIOS
VOOS
GAIN ERROR
Gain and Offsets
vs Output Common Mode
OUTPUT COMMON MODE (V)
–5
–0.5
GAIN ERROR (%)
OFFSET VOLTAGE (mV)
–0.4
–0.2
–0.1
0
0.5
0.2
–3 –1 0 54
1966 G06
–0.3
0.3
0.4
0.1
–0.5
–0.4
–0.2
–0.1
0
0.5
0.2
–0.3
0.3
0.4
0.1
–4 –2 123
VDD = 5V
VSS = –5V
VIOS
VOOS
GAIN ERROR
Gain and Offsets
vs Input Common Mode
INPUT COMMON MODE (V)
0
–0.5
GAIN ERROR (%)
OFFSET VOLTAGE (mV)
–0.4
–0.2
–0.1
0
0.5
0.2
0.6 1.2 1.5 2.7
1966 G01
–0.3
0.3
0.4
0.1
–1.0
–0.8
–0.4
–0.2
1.0
0.4
–0.6
0.6
0.8
0.2
0
0.3 0.9 1.8 2.1 2.4
VDD = 2.7V
VSS = GND VIOS
VOOS
GAIN ERROR
Gain and Offsets
vs Output Common Mode
OUTPUT COMMON MODE (V)
0
–0.5
GAIN ERROR (%)
OFFSET VOLTAGE (mV)
–0.4
–0.2
–0.1
0
0.5
0.2
0.6 1.2 1.5 2.7
1966 G04
–0.3
0.3
0.4
0.1
–1.0
–0.8
–0.4
–0.2
1.0
0.4
–0.6
0.6
0.8
0.2
0
0.3 0.9 1.8 2.1 2.4
VDD = 2.7V
VSS = GND VIOS
VOOS
GAIN ERROR
Gain and Offsets vs Temperature
TEMPERATURE (°C)
–60
–0.5
GAIN ERROR (%)
OFFSET VOLTAGE (mV)
–0.4
–0.2
–0.1
0
0.5
0.2
–40 –20 0 140
1966 G08
–0.3
0.3
0.4
0.1
–0.5
–0.4
–0.2
–0.1
0
0.5
0.2
–0.3
0.3
0.4
0.1
40
20 60 80 100 120
VDD = 5V
VSS = GND
VIOS
VOOS
GAIN ERROR
Gain and Offsets vs Temperature
TEMPERATURE (°C)
–60
–0.5
GAIN ERROR (%)
OFFSET VOLTAGE (mV)
–0.4
–0.2
–0.1
0
0.5
0.2
–40 –20 0140
1966 G09
–0.3
0.3
0.4
0.1
–0.5
–0.4
–0.2
–0.1
0
0.5
0.2
–0.3
0.3
0.4
0.1
40 60
20 80 100 120
VDD = 5V
VSS = –5V
VIOS
VOOS
GAIN ERROR
Gain and Offsets vs Temperature
TEMPERATURE (°C)
–60
–0.5
GAIN ERROR (%)
OFFSET VOLTAGE (mV)
–0.4
–0.2
–0.1
0
0.5
0.2
–40
–20 0
140
1966 G07
–0.3
0.3
0.4
0.1
–1.0
–0.8
–0.4
–0.2
0
1.0
0.4
–0.6
0.6
0.8
0.2
40
20 60 80 100 120
VDD = 2.7V
VSS = GND
VIOS
VOOS
GAIN ERROR
LTC1966
6
1966fb
Typical perForMance characTerisTics
Gain and Offsets vs VSS Supply
VSS (V)
–6
–0.5
GAIN ERROR (%)
OFFSET VOLTAGE (mV)
–0.4
–0.2
–0.1
0
0.5
0.2
–5 –4 0
1966 G11
–0.3
0.3
0.4
0.1
–0.5
–0.4
–0.2
–0.1
0
0.5
0.2
–0.3
0.3
0.4
0.1
–2
–3 –1
VDD = 5V
VIOS
VOOS
GAIN ERROR
NOMINAL
SPECIFIED
CONDITIONS
VDD (V)
2.5
–0.5
GAIN ERROR (%)
OFFSET VOLTAGE (mV)
–0.4
–0.2
–0.1
0
0.5
0.2
3.0 3.5 5.5
1966 G10
–0.3
0.3
0.4
0.1
–1.0
–0.8
–0.4
–0.2
0
1
0.4
–0.6
0.6
0.8
0.2
4.5
4.0 5.0
VSS = GND
VIOS
VOOS
GAIN ERROR
AC Linearity
Performance vs Crest FactorGain and Offsets vs VDD Supply
VIN1 (VRMS)
0
–20
VOUT (mV DC) – VIN (mVRMS)
–15
–10
–5
0
5
10
0.5 1 1.5 2
1966 G24
2.5
1% ERROR AC INPUTS = 60Hz
SINEWAVES
VIN2 = GND
–1% ERROR
AC INPUT
VDD = 3V
AC INPUT
VDD = 5V
DC INPUT
VDD = 5V
Output Accuracy vs Signal
Amplitude
CREST FACTOR
1.0
199.8
OUTPUT VOLTAGE (mV DC)
200.0
200.2
200.4
200.6
2.0 3.0 4.0 5.0
1966 G15
200.8
201.0
1.5 2.5 3.5 4.5
20Hz 60Hz
100Hz
200mVRMS SCR WAVEFORMS
CAVE = 10µF
VDD = 5V
O.1%/DIV
Performance vs Large Crest Factors
CREST FACTOR
1
OUTPUT VOLTAGE (mV DC)
220
4
1966 G12
190
170
2 3 5
160
150
230
210
200
180
678
200mVRMS SCR WAVEFORMS
CAVE = 4.7µF
VDD = 5V
5%/DIV
20Hz
100Hz
60Hz
250Hz
FUNDAMENTAL
FREQUENCY
DC Linearity
VIN1 (mV)
–500
VOUTDC – |VINDC| (mV)
0.02
0.06
0.10
300
1966 G14
–0.02
–0.06
0
0.04
0.08
–0.04
–0.08
–0.10 –300 –100 100 500
EFFECT OF OFFSETS
MAY BE POSITIVE
OR NEGATIVE
CAVE = 1µF
VIN2 = GND
Quiescent Supply Currents
vs Supply Voltage
VDD SUPPLY VOLTAGE (V)
0
–25
SUPPLY CURRENT (µA)
0
50
75
100
4
200
1966 G16
25
2 6
3
1 5
125
150
175
VSS = GND
IDD
ISS
Shutdown Currents
vs ENABLE Voltage
ENABLE PIN VOLTAGE (V)
0
250
200
IDD
IEN
150
100
50
0
–50
–100
500
250
0
–250
–500
3 5
1966 G18
1 2 4 6
SUPPLY CURRENT (µA)
ENABLE PIN CURRENT (nA)
VDD = 5V
ISS
VIN1 (mV ACRMS)
0
VOUT (mV DC) – VIN (mV ACRMS)
0.20
0.15
0.10
0.05
0
–0.05
–0.10
–0.15
–0.20 400
1966 G13
100 200 300 50035050 150 250 450
60Hz SINEWAVES
CAVE = 1µF
VIN2 = GND
LTC1966
7
1966fb
Typical perForMance characTerisTics
Input Signal Bandwidth
INPUT SIGNAL FREQUENCY (Hz)
100 1K
OUTPUT DC VOLTAGE (mV)
10
1000
10K 100K 1M
1966 G19
1
100
0.1%
ERROR
1%
ERROR
10%
ERROR
–3dB
VIN1 (mV DC)
–20
VOUT (mV DC)
10
20
20
1966 G22
0
–10 –10 010
–15 –5 515
30
5
15
–5
25
VIN2 = GND
THREE REPRESENTITIVE UNITS
DC Transfer Function Near Zero
Quiescent Supply Currents
vs Temperature Input Signal Bandwidth
INPUT FREQUENCY (kHz)
1
190
OUTPUT DC VOLTAGE (mV)
192
194
196
198
10 100 1000
1966 G20
188
186
184
182
200
202
1%/DIV
CAVE = 2.2µF
Bandwidth to 100kHz
INPUT FREQUENCY (kHz)
0
195
OUTPUT DC VOLTAGE (mV)
196
198
199
200
202
10 50 70
1966 G21
197
201
40 90 100
20 30 60 80
0.5%/DIV
CAVE = 47µF
Common Mode Rejection Ratio
vs Frequency
FREQUENCY (Hz)
40
COMMON MODE REJECTION RATIO (dB)
50
70
80
100
110
10 1k 10k 1M
1966 G23
30
100 100k
90
60
20
VDD = 5V
VSS = –5V
±5V INPUT CONVERSION
TO DC OUTPUT
TEMPERATURE (°C)
–60
IDD (µA)
ISS (µA)
160
0 20
1966 G17
130
120
110
100
90 –40 –20 6040
170
150
140
15
20
25
30
35
40
0
10
5
80 100 120 140
VDD = 5V, VSS = –5V
VDD = 5V, VSS = –5V
VDD = 5V, VSS = GND
VDD = 5V, VSS = GND
VDD = 2.7V, VSS = GND
VDD = 2.7V, VSS = GND
LTC1966
8
1966fb
pin FuncTions
GND (Pin 1): Ground. A power return pin.
IN1 (Pin 2): Differential Input. DC coupled (polarity is
irrelevant).
IN2 (Pin 3): Differential Input. DC coupled (polarity is
irrelevant).
VSS (Pin 4): Negative Voltage Supply. GND to –5.5V.
VOUT (Pin 5): Output Voltage. This is high impedance.
The RMS averaging is accomplished with a single shunt
capacitor from this node to OUT RTN. The transfer func-
tion is given by:
V OUT RTN Average IN IN
OUT
––
()
=
()
21
2
OUT RTN (Pin 6): Output Return. The output voltage is
created relative to this pin. The VOUT and OUT RTN pins
are not balanced and this pin should be tied to a low
impedance, both AC and DC. Although it is typically tied
to GND, it can be tied to any arbitrary voltage, VSS < OUT
RTN < (VDD – Max Output). Best results are obtained when
OUT RTN = GND.
VDD (Pin 7): Positive Voltage Supply. 2.7V to 5.5V.
ENABLE (Pin 8): An Active Low Enable Input. LTC1966
is debiased if open circuited or driven to VDD. For normal
operation, pull to GND, a logic low or even VSS.
LTC1966
9
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applicaTions inForMaTion
START
NOT
SURE NO
NO
1966 TA02
DO YOU
NEED TRUE RMS-TO-DC
CONVERSION?
READ
RMS-TO-DC
CONVERSION
NO
NO
YES
YES
YES NO
NO
YES
YES
YES
DO YOU
HAVE ANY LTC1966s
YET?
DID
YOU ALREADY TRY OUT
THE LTC1966?
DID
YOUR CIRCUIT
WORK?
NOW DOES YOUR
RMS CIRCUIT WORK
WELL ENOUGH THAT YOU
ARE READY TO BUY
THE LTC1966?
DO YOU WANT TO
KNOW HOW TO USE THE
LTC1966 FIRST?
CONTACT LTC BY PHONE OR
AT www.linear.com AND
GET SOME NOW
READ THE TROUBLESHOOTING
GUIDE. IF NECESSARY, CALL
LTC FOR APPLICATIONS SUPPORT
CONTACT LTC
AND PLACE YOUR ORDER
READ THE DESIGN COOKBOOK
READ THE TROUBLESHOOTING
GUIDE AGAIN OR CALL LTC
FOR APPLICATIONS SUPPORT
FIND SOMEONE WHO DOES
AND GIVE THEM THIS
DATA SHEET
LTC1966
10
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applicaTions inForMaTion
The last two entries of Table 1 are chopped sine waves as
is commonly created with thyristors such as SCRs and
Triacs. Figure 2a shows a typical circuit and Figure 2b
shows the resulting load voltage, switch voltage and load
currents. The power delivered to the load depends on the
firing angle, as well as any parasitic losses such as switch
ON voltage drop. Real circuit waveforms will also typically
have significant ringing at the switching transition, depen-
dent on exact circuit parasitics. For the purposes of this
data sheet, SCR waveforms refers to the ideal chopped
sine wave, though the LTC1966 will do faithful RMS-to-DC
conversion with real SCR waveforms as well.
The case shown is for Θ = 90°, which corresponds to 50%
of available power being delivered to the load. As noted in
Table 1, when Θ = 114°, only 25% of the available power
is being delivered to the load and the power drops quickly
as Θ approaches 180°.
With an average rectification scheme and the typical
calibration to compensate for errors with sine waves, the
RMS level of an input sine wave is properly reported; it
is only with a nonsinusoidal waveform that errors occur.
Because of this calibration, and the output reading in
VRMS, the term true RMS got coined to denote the use of
an actual RMS-to-DC converter as opposed to a calibrated
average rectifier.
RMS-TO-DC CONVERSION
Definition of RMS
RMS amplitude is the consistent, fair and standard way to
measure and compare dynamic signals of all shapes and
sizes. Simply stated, the RMS amplitude is the heating
potential of a dynamic waveform. A 1VRMS AC waveform
will generate the same heat in a resistive load as will 1V DC.
Figure 1
Mathematically, RMS is the root of the mean of the square:
VV
RMS =2
Alternatives to RMS
Other ways to quantify dynamic waveforms include peak
detection and average rectification. In both cases, an aver-
age (DC) value results, but the value is only accurate at
the one chosen waveform type for which it is calibrated,
typically sine waves. The errors with average rectification
are shown in Table 1. Peak detection is worse in all cases
and is rarely used.
Table 1. Errors with Average Rectification vs True RMS
WAVEFORM VRMS
AVERAGE
RECTIFIED
(V) ERROR*
Square Wave 1.000 1.000 11%
Sine Wave 1.000 0.900 *Calibrate for 0% Error
Triangle Wave 1.000 0.866 –3.8%
SCR at 1/2 Power,
Θ = 90° 1.000 0.637 –29.3%
SCR at 1/4 Power,
Θ = 114° 1.000 0.536 –40.4%
Figure 2a
Figure 2b
+
–R1V DC
R
1966 F01
SAME
HEAT
1V ACRMS
R1V (AC + DC) RMS
CONTROL
VLOAD
AC
MAINS VLINE
VTHY
1966 F02a
+
+
–
+
–
–
ILOAD
VLINE
Θ
VLOAD
VTHY
ILOAD
1966 F02b
LTC1966
11
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applicaTions inForMaTion
How an RMS-to-DC Converter Works
Monolithic RMS-to-DC converters use an implicit com-
putation to calculate the RMS value of an input signal.
The fundamental building block is an analog multiply/
divide used as shown in Figure 3. Analysis of this topol-
ogy is easy and starts by identifying the inputs and the
output of the lowpass filter. The input to the LPF is the
calculation from the multiplier/divider; (VIN)2/VOUT. The
lowpass filter will take the average of this to create the
output, mathematically:
VV
V
V
V
Vso
V
V
Vand
VVor
VVRMS V
OUT IN
OUT
OUT
IN
OUT
OUT
IN
OUT
OUT IN
OUT IN IN
=
()
()
=
()
=
()
()
=
()
=
()
=
()
2
22
2
22
2
,
,
,
,
Because V is DC,
V
OUT
IN
How the LTC1966 RMS-to-DC Converter Works
The LTC1966 uses a completely new topology for RMS-
to-DC conversion, in which a ∆S modulator acts as the
divider, and a simple polarity switch is used as the multiplier
as shown in Figure 4.
Figure 3. RMS-to-DC Converter with Implicit Computation
Unlike the prior generation RMS-to-DC converters, the
LTC1966 computation does NOT use log/antilog circuits,
which have all the same problems, and more, of log/antilog
multipliers/dividers, i.e., linearity is poor, the bandwidth
changes with the signal amplitude and the gain drifts with
temperature.
Figure 4. Topology of LTC1966
The ∆S modulator has a single-bit output whose average
duty cycle (D) will be proportional to the ratio of the input
signal divided by the output. The ∆S is a 2nd order modula-
tor with excellent linearity. The single bit output is used to
selectively buffer or invert the input signal. Again, this is a
circuit with excellent linearity, because it operates at only
two points: ±1 gain; the average effective multiplication
over time will be on the straight line between these two
points. The combination of these two elements again creates
a lowpass filter input signal proportional to (VIN)2/VOUT,
which, as shown above, results in RMS-to-DC conversion.
The lowpass filter performs the averaging of the RMS
function and must be a lower corner frequency than the
lowest frequency of interest. For line frequency measure-
ments, this filter is simply too large to implement on-chip,
but the LTC1966 needs only one capacitor on the output
to implement the lowpass filter. The user can select this
capacitor depending on frequency range and settling time
requirements, as will be covered in the Design Cookbook
section to follow.
This topology is inherently more stable and linear than
log/antilog implementations primarily because all of the
signal processing occurs in circuits with high gain op amps
operating closed loop.
VIN VOUT
1966 F03
× ÷ LPF
V
V
IN
OUT
()
2
∆–∑
REF
VIN
VOUT
LPF
±1
DV
V
IN
OUT
α
LTC1966
12
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applicaTions inForMaTion
More detail of the LTC1966 inner workings is shown in
the Simplified Schematic towards the end of this data
sheet. Note that the internal scalings are such that the ∆S
output duty cycle is limited to 0% or 100% only when VIN
exceeds ± 4 • VOUT.
Linearity of an RMS-to-DC Converter
Linearity may seem like an odd property for a device that
implements a function that includes two very nonlinear
processes: squaring and square rooting.
However, an RMS-to-DC converter has a transfer function,
RMS volts in to DC volts out, that should ideally have a
1:1 transfer function. To the extent that the input to output
transfer function does not lie on a straight line, the part
is nonlinear.
A more complete look at linearity uses the simple model
shown in Figure 5. Here an ideal RMS core is corrupted by
both input circuitry and output circuitry that have imperfect
transfer functions. As noted, input offset is introduced in
the input circuitry, while output offset is introduced in the
output circuitry.
Any nonlinearity that occurs in the output circuity will cor-
rupt the RMS in to DC out transfer function. A nonlinearity
in the input circuitry will typically corrupt that transfer
function far less, simply because with an AC input, the
RMS-to-DC conversion will average the nonlinearity from
a whole range of input values together.
But the input nonlinearity will still cause problems in an
RMS-to-DC converter because it will corrupt the accuracy
as the input signal shape changes. Although an RMS-to-DC
converter will convert any input waveform to a DC output,
the accuracy is not necessarily as good for all waveforms
as it is with sine waves. A common way to describe dy-
namic signal wave shapes is crest factor. The crest factor
is the ratio of the peak value relative to the RMS value of
a waveform. A signal with a crest factor of 4, for instance,
has a peak that is four times its RMS value. Because this
peak has energy (proportional to voltage squared) that is
16 times (42) the energy of the RMS value, the peak is
necessarily present for at most 6.25% (1/16) of the time.
The LTC1966 performs very well with crest factors of 4
or less and will respond with reduced accuracy to signals
with higher crest factors. The high performance with crest
factors less than 4 is directly attributable to the high linear-
ity throughout the LTC1966.
The LTC1966 does not require an input rectifier, as is com-
mon with traditional log/antilog RMS-to-DC converters.
Thus, the LTC1966 has none of the nonlinearities that are
introduced by rectification.
The excellent linearity of the LTC1966 allows calibration to
be highly effective at reducing system errors. See System
Calibration section following the Design Cookbook.
Figure 5. Linearity Model of an RMS-to-DC Converter
INPUT CIRCUITRY
• VIOS
• INPUT NONLINEARITY
IDEAL
RMS-TO-DC
CONVERTER
OUTPUT CIRCUITRY
• VOOS
• OUTPUT NONLINEARITY
INPUT OUTPUT
1966 F05
LTC1966
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DESIGN COOKBOOK
The LTC1966 RMS-to-DC converter makes it easy to
implement a rather quirky function. For many applications
all that will be needed is a single capacitor for averaging,
appropriate selection of the I/O connections and power
supply bypassing. Of course, the LTC1966 also requires
power. A wide variety of power supply configurations are
shown in the Typical Applications section towards the end
of this data sheet.
Capacitor Value Selection
The RMS or root-mean-squared value of a signal, the root
of the mean of the square, cannot be computed without
some averaging to obtain the mean function. The LTC1966
true RMS-to-DC converter utilizes a single capacitor on
the output to do the low frequency averaging required for
RMS-to-DC conversion. To give an accurate measure of a
dynamic waveform, the averaging must take place over a
sufficiently long interval to average, rather than track, the
lowest frequency signals of interest. For a single averag-
ing capacitor, the accuracy at low frequencies is depicted
in Figure 6.
Figure 6 depicts the so-called DC error that results at a
given combination of input frequency and filter capacitor
values1. It is appropriate for most applications, in which
the output is fed to a circuit with an inherently band lim-
ited frequency response, such as a dual slope/integrating
A/D converter, a ∆S A/D converter or even a mechanical
analog meter.
Figure 6. DC Error vs Input Frequency
Figure 7. Output Ripple Exceeds DC Error
However, if the output is examined on an oscilloscope
with a very low frequency input, the incomplete averag-
ing will be seen, and this ripple will be larger than the
error depicted in Figure 6. Such an output is depicted in
Figure7. The ripple is at twice the frequency of the input
because of the computation of the square of the input.
The typical values shown, 5% peak ripple with 0.05% DC
error, occur with CAVE = 1µF and fINPUT = 10Hz.
If the application calls for the output of the LTC1966 to feed
a sampling or Nyquist A/D converter (or other circuitry that
will not average out this double frequency ripple) a larger
averaging capacitor can be used. This trade-off is depicted
in Figure 8. The peak ripple error can also be reduced by
additional lowpass filtering after the LTC1966, but the
simplest solution is to use a larger averaging capacitor.
1This frequency dependent error is in addition to the static errors that affect all readings and are
therefore easy to trim or calibrate out. The Error Analyses section to follow discusses the effect
of static error terms.
C = 4.7
µ
F
INPUT FREQUENCY (Hz)
1
–2.0
DC ERROR (%)
–1.6
–1.2
–0.8
–0.4
10 20 50 60 100
1966 F06
0
–1.8
–1.4
–1.0
–0.6
–0.2 C = 10µF
C = 2.2µF C = 1.0µF C = 0.47µF C = 0.22µF C = 0.1µF
TIME
OUTPUT
1966 F07
DC
ERROR
(0.05%)
IDEAL
OUTPUT
DC
AVERAGE
OF ACTUAL
OUTPUT
PEAK
RIPPLE
(5%)
ACTUAL OUTPUT
WITH RIPPLE
f = 2 × fINPUT
PEAK
ERROR =
DC ERROR +
PEAK RIPPLE
(5.05%)
LTC1966
14
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applicaTions inForMaTion
A 1µF capacitor is a good choice for many applications.
The peak error at 50Hz/60Hz will be <1% and the DC error
will be <0.1% with frequencies of 10Hz or more.
Note that both Figure 6 and Figure 8 assume AC-coupled
waveforms with a crest factor less than 2, such as sine
waves or triangle waves. For higher crest factors and/or
AC + DC waveforms, a larger CAVE will generally be required.
See Crest Factor and AC + DC Waveforms.
Capacitor Type Selection
The LTC1966 can operate with many types of capacitors.
The various types offer a wide array of sizes, tolerances,
parasitics, package styles and costs.
Ceramic chip capacitors offer low cost and small size,
but are not recommended for critical applications. The
value stability over voltage and temperature is poor with
many types of ceramic dielectrics. This will not cause an
RMS-to-DC accuracy problem except at low frequencies,
where it can aggravate the effects discussed in the pre-
vious section. If a ceramic capacitor is used, it may be
necessary to use a much higher nominal value in order
to assure the low frequency accuracy desired.
Another parasitic of ceramic capacitors is leakage, which is
again dependent on voltage and particularly temperature.
If the leakage is a constant current leak, the I • R drop of
the leak multiplied by the output impedance of the LTC1966
will create a constant offset of the output voltage. If the
leak is Ohmic, the resistor divider formed with the LTC1966
output impedance will cause a gain error. For <0.1%
gain accuracy degradation, the parallel impedance of the
capacitor leakage will need to be >1000 times the LTC1966
output impedance. Accuracy at this level can be hard to
achieve with a ceramic capacitor, particularly with a large
value of capacitance and at high temperature.
For critical applications, a film capacitor, such as metalized
polyester, will be a much better choice. Although more
expensive, and larger for a given value, the value stabil-
ity and low leakage make metal film capacitors a trouble
free choice.
With any type of capacitor, the self resonance of the capaci-
tor can be an issue with the switched capacitor LTC1966.
If the self resonant frequency of the averaging capacitor
is 1MHz or less, a second smaller capacitor should be
added in parallel to reduce the impedance seen by the
LTC1966 output stage at high frequencies. A capacitor 100
times smaller than the averaging capacitor will typically be
small enough to be a low cost ceramic with a high quality
dielectric such as X7R or NPO/COG.
Input Connections
The LTC1966 input is differential and DC coupled. The
LTC1966 responds to the RMS value of the differential
voltage between Pin 2 and Pin 3, including the DC por-
tion of that difference. However, there is no DC-coupled
path from the inputs to ground. Therefore, at least one of
the two inputs must be connected with a DC return path
to ground.
Both inputs must be connected to something. If either
input is left floating, a zero volt output will result.
Figure 8. Peak Error vs Input Frequency with One Cap Averaging
INPUT FREQUENCY (Hz)
1
–2.0
PEAK ERROR (%)
–1.6
–1.2
–0.8
–0.4
10 20 50 60 100
1966 F08
0
–1.8
–1.4
–1.0
–0.6
–0.2
C = 100µF
C = 47µF C = 22µF C = 10µF C = 4.7µF C = 2.2µF C = 1µF
LTC1966
15
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applicaTions inForMaTion
For single-ended DC-coupled applications, simply con-
nect one of the two inputs (they are interchangeable) to
the signal, and the other to ground. This will work well
for dual supply configurations, but for single supply
configurations it will only work well for unipolar input
signals. The LTC1966 input voltage range is from rail-
to-rail, and when the input is driven above VDD or below
VSS (ground for single supply operation) the gain and
offset errors will increase substantially after just a few
hundred millivolts of overdrive. Fortunately, most single
supply circuits measuring a DC-coupled RMS value will
include some reference voltage other than ground, and
the second LTC1966 input can be connected to that point.
For single-ended AC-coupled applications, Figure 9 shows
three alternate topologies. The first one, shown in Figure 9a
uses a coupling capacitor to one input while the other is
grounded. This will remove the DC voltage difference from
the input to the LTC1966, and it will therefore not be part
of the resulting output voltage. Again, this connection will
work well with dual supply configurations, but in single
supply configurations it will be necessary to raise the volt-
age on the grounded input to assure that the signal at the
active input stays within the range of VSS to VDD. If there
is already a suitable voltage reference available, connect
the second input to that point. If not, a midsupply voltage
can be created with two resistors as shown in Figure 9b.
Finally, if the input voltage is known to be between VSS
and VDD, it can be AC-coupled by using the configuration
shown in Figure 9c. Whereas the DC return path was
provided through Pin 3 in Figures 9a and 9b, in this case,
the return path is provided on Pin 2, through the input
signal voltages. The switched capacitor action between
the two input pins of the LTC1966 will cause the voltage
on the coupling capacitor connected to the second input
to follow the DC average of the input voltage.
For differential input applications, connect the two inputs
to the differential signal. If AC coupling is desired, one of
the two inputs can be connected through a series capacitor.
In all of these connections, to choose the input coupling
capacitor, CC, calculate the low frequency coupling time
constant desired, and divide by the LTC1966 differential
input impedance. Because the LTC1966 input impedance
is about 100 times its output impedance, this capacitor is
typically much smaller than the output averaging capaci-
tor. Its requirements are also much less stringent, and a
ceramic chip capacitor will usually suffice.
Output Connections
The LTC1966 output is differentially, but not symmetrically,
generated. That is to say, the RMS value that the LTC1966
computes will be generated on the output (Pin 5) relative
to the output return (Pin 6), but these two pins are not
interchangeable. For most applications, Pin 6 will be tied
to ground (Pin 1), and this will result in the best accuracy.
However, Pin 6 can be tied to any voltage between VSS
(Pin 4) and VDD (Pin 7) less the maximum output voltage
swing desired. This last restriction keeps VOUT itself (Pin 5)
within the range of VSS to VDD. If a reference level other
than ground is used, it should be a low impedance, both
AC and DC, for proper operation of the LTC1966.
Use of a voltage in the range of VDD – 1V to VDD – 1.3V can
lead to errors due to the switch dynamics as the NMOS
transistor is cut off. For this reason, it is recommended
that OUT RTN = 0V if VDD is ≤3V.
Figure 9. Single-Ended AC-Coupled Input Connection Alternatives
+
–
LTC1966
VDD VDD
VSS
VDD
VSS OR GND
(9a)
CC
IN1
VIN IN2
2
3
LTC1966
(9b)
CC
R1
100k R2
100k
IN1
VIN
VDD
IN2
2
3
LTC1966
(9c)
CC
IN1
VIN
1966 F09
VDC
IN2
2
3
LTC1966
16
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applicaTions inForMaTion
In any configuration, the averaging capacitor should be
connected between Pins 5 and 6. The LTC1966 RMS DC
output will be a positive voltage created at VOUT (Pin 5)
with respect to OUT RTN (Pin 6).
Power Supply Bypassing
The LTC1966 is a switched capacitor device, and large
transient power supply currents will be drawn as the
switching occurs. For reliable operation, standard power
supply bypassing must be included. For single supply
operation, a 0.01µF capacitor from VDD (Pin 7) to GND
(Pin1) located close to the device will suffice. For dual
supplies, add a second 0.01µF capacitor from VSS (Pin 4)
to GND (Pin 1), located close to the device. If there is a
good quality ground plane available, the capacitors can go
directly to that instead. Power supply bypass capacitors
can, of course, be inexpensive ceramic types.
The sampling clock of the LTC1966 operates at approxi-
mately 200kHz, and most operations repeat at a rate of
100kHz. If this internal clock becomes synchronized to a
multiple or submultiple of the input frequency, significant
conversion error could occur. This is particularly important
when frequencies exceeding 10kHz can be injected into
the LTC1966 via supply or ground bounce. To minimize
this possibility, capacitive bypassing is recommended on
both supplies with capacitors placed immediately adjacent
to the LTC1966. For best results, the bypass capacitors
should be separately routed from Pin 7 to Pin 1, and from
Pin 4 to Pin 1.
The LTC1966 needs at least 2.7V for its power supply,
more for dual supply configurations. The range of allow-
able negative supply voltages (VSS) vs positive supply
voltages (VDD) is shown in Figure 10. Mathematically, the
VSS constraint is:
–3 • (VDD – 2.7V) ≤ VSS ≤ GND
The LTC1966 has internal ESD absorption devices, which
are referenced to the VDD and VSS supplies. For effective
in-circuit ESD immunity, the VDD and VSS pins must be
connected to a low external impedance. This can be ac-
complished with low impedance power planes or simply
with the recommended 0.01µF decoupling to ground on
each supply.
Up and Running!
If you have followed along this far, you should have the
LTC1966 up and running by now! Don’t forget to enable
the device by grounding Pin 8, or driving it with a logic low.
Keep in mind that the LTC1966 output impedance is fairly
high, and that even the standard 10MΩ input impedance of
a digital multimeter (DMM) or a 10× scope probe will load
down the output enough to degrade its typical gain error
of 0.1%. In the end application circuit, either a buffer or
another component with an extremely high input impedance
(such as a dual slope integrating ADC) should be used.
For laboratory evaluation, it may suffice to use a bench
top DMM with the ability to disconnect the 10MΩ shunt.
If you are still having trouble, it may be helpful to skip
ahead a few pages and review the Troubleshooting Guide.
What About Response Time?
With a large value averaging capacitor, the LTC1966 can
easily perform RMS-to-DC conversion on low frequency
signals. It compares quite favorably in this regard to
prior generation products because nothing about the ∆S
circuitry is temperature sensitive. So the RMS result doesn’t
get distorted by signal driven thermal fluctuations like a
log/antilog circuit output does.
However, using large value capacitors results in a slow
response time. Figure 11 shows the rising and falling
step responses with a 1µF averaging capacitor. Although
they both appear at first glance to be standard exponential
Figure 10. VSS Limits vs VDD
VDD (V)
2.5
–6
VSS (V)
–5
–4
–3
–2
0
33.5 4 4.5
1966 F10
5 5.5
–1
LTC1966
OPERATES IN THIS RANGE
LTC1966
17
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applicaTions inForMaTion
2To convince oneself of this necessity, consider a pulse train of 50% duty cycle between 0mV
and 100mV. At very low frequencies, the LTC1966 will essentially track the input. But as the input
frequency is increased, the average result will converge to the RMS value of the input. If the rise
and fall characteristics were symmetrical, the output would converge to 50mV. In fact though, the
RMS value of a 100mV DC-coupled 50% duty cycle pulse train is 70.71mV, which the asymmetrical
rise and fall characteristics will converge to as the input frequency is increased.
decay type settling, they are not. This is due to the nonlinear
nature of an RMS-to-DC calculation. Also note the change
in the time scale between the two; the rising edge is more
than twice as fast to settle to a given accuracy. Again this
is a necessary consequence of RMS-to-DC calculation.2
Although shown with a step change between 0mV and
100mV, the same response shapes will occur with the
LTC1966 for ANY step size. This is in marked contrast
to prior generation log/antilog RMS-to-DC converters,
whose averaging time constants are dependent on the
signal level, resulting in excruciatingly long waits for the
output to go to zero.
The shape of the rising and falling edges will be dependent
on the total percent change in the step, but for less than
the 100% changes shown in Figure 11, the responses will
be less distorted and more like a standard exponential
decay. For example, when the input amplitude is changed
from 100mV to 110mV (+10%) and back (–10%), the step
responses are essentially the same as a standard expo-
nential rise and decay between those two levels. In such
cases, the time constant of the decay will be in between
that of the rising edge and falling edge cases of Figure 11.
Therefore, the worst case is the falling edge response as
it goes to zero, and it can be used as a design guide.
Figure12 shows the settling accuracy vs settling time for
a variety of averaging capacitor values. If the capacitor
value previously selected (based on error requirements)
gives an acceptable settling time, your design is done.
Figure 11a. LTC1966 Rising Edge with CAVE = 1µF Figure 11b. LTC1966 Falling Edge with CAVE = 1µF
Figure 12. LTC1966 Settling Time with One Cap Averaging
SETTLING TIME (SEC)
0.01
0.1
SETTLING ACCURACY (%)
1
10
1 100.1 100
1966 F12
C = 100µFC = 47µFC = 22µFC = 10µFC = 4.7µFC = 2.2µFC = 0.47µFC = 0.22µFC = 0.1µF C = 1µF
TIME (SEC)
0
0
LTC1966 OUTPUT (mV)
20
40
60
80
100
120
0.1 0.2 0.3 0.4
1966 F11a
0.5
CAVE = 1µF
TIME (SEC)
0
0
LTC1966 OUTPUT (mV)
20
40
60
80
100
120
0.2 0.4 0.6 0.8
1966 F11b
1
CAVE = 1µF
LTC1966
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But with 100µF, the settling time to even 10% is a full 38
seconds, which is a long time to wait. What can be done
about such a design? If the reason for choosing 100µF is
to keep the DC error with a 75mHz input less than 0.1%,
the answer is: not much. The settling time to 1% of 76
seconds is just 5.7 cycles of this extremely low frequency.
Averaging very low frequency signals takes a long time.
However, if the reason for choosing 100µF is to keep the
peak error with a 10Hz input less than 0.05%, there is
another way to achieve that result with a much improved
settling time.
Reducing Ripple with a Post Filter
The output ripple is always much larger than the DC er-
ror, so filtering out the ripple can reduce the peak error
substantially, without the large settling time penalty of
simply increasing the averaging capacitor.
Figure 13 shows a basic 2nd order post filter, for a net 3rd
order filtering of the LTC1966 RMS calculation. It uses the
85kΩ output impedance of the LTC1966 as the first resistor
of a 3rd order Sallen-Key active RC filter. This topology
features a buffered output, which can be desirable depend-
ing on the application. However, there are disadvantages
to this topology, the first of which is that the op amp input
voltage and current errors directly degrade the effective
LTC1966 VOOS. The table inset in Figure 13 shows these
errors for four of Linear Technology’s op amps.
A second disadvantage is that the op amp output has
to operate over the same range as the LTC1966 output,
including ground, which in single supply applications is
the negative supply. Although the LTC1966 output will
function fine just millivolts from the rail, most op amp
output stages (and even some input stages) will not.
There are at least two ways to address this. First of all,
the op amp can be operated split supply if a negative
supply is available. Just the op amp would need to do so;
the LTC1966 can remain single supply. A second way to
address this issue is to create a signal reference voltage a
half volt or so above ground. This is most attractive when
the circuitry that follows has a differential input, so that
the tolerance of the signal reference is not a concern. To
do this, tie all three ground symbols shown in Figure 13
to the signal reference, as well as to the differential return
for the circuitry that follows.
Figure 14 shows an alternative 2nd order post filter, for
a net 3rd order filtering of the LTC1966 RMS calculation.
It also uses the 85kΩ output impedance of the LTC1966
as the first resistor of a 3rd order active RC filter, but this
topology filters without buffering so that the op amp DC
error characteristics do not affect the output. Although the
output impedance of the LTC1966 is increased from 85kΩ
to 285kΩ, this is not an issue with an extremely high input
impedance load, such as a dual slope integrating ADC like
the ICL7106. And it allows a generic op amp to be used,
such as the SOT-23 one shown. Furthermore, it easily
works on a single supply rail by tying the noninverting
input of the op amp to a low noise reference as optionally
shown. This reference will not change the DC voltage at
the circuit output, although it does become the AC ground
for the filter, thus the (relatively) low noise requirement.
Figure 14. DC Accurate Post Filter
Figure 13. Buffered Post Filter
LTC1966 CAVE
1µF
5
6
R1
38.3k
–
+
R2
169k
RB
C2
0.1µF
C1
1µF
LT1880
1966 F13
OP AMP
LTC1966 VOOS
VIOS
IB/OS • R
TOTAL OFFSET
RB VALUE
ISQ
LT1494
±375µV
±73µV
±648µV
294k
1µA
LT1880
±150µV
±329µV
±679µV
SHORT
1.2mA
LT1077
±60µV
±329µV
±589µV
294k
48µA
LT 2050
±3µV
±27µV
±230µV
SHORT
750µA
±200µV
LTC1966 CAVE
1µF
5
6
OTHER
REF VOLTAGE,
SEE TEXT
R1
200k
–
+
R2
681k
C1
0.22µF
C2
0.22µF
LT1782
1066 F14
LTC1966
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Step Responses with a Post Filter
B
oth of the post filters, shown in Figures 13 and 14,
are optimized for additional filtering with clean step
responses. The 85kΩ output impedance of the LTC1966
working into a 1µF capacitor forms a 1st order LPF with
a –3dB frequency of ~1.8Hz. The two filters have 1µF at
the LTC1966 output for easy comparison with a 1µF only
case, and both have the same relative (Bessel-like) shape.
However, because of the topological differences of pole
placements between the various components within the
two filters, the net effective bandwidth for Figure 13 is
slightly higher (≈1.2 • 1.8 ≈ 2.1Hz) than with 1µF alone,
while the bandwidth for Figure 14 is somewhat lower
(≈0.7 • 1.8 ≈ 1.3Hz) than with 1µF alone. To adjust the
bandwidth of either of them, simply scale all the capacitors
by a common multiple, and leave the resistors unchanged.
The step responses of the LTC1966 with 1µF only and with
the two post filters are shown in Figure 15. This is the ris-
ing edge RMS output response to a 10Hz input starting
at t = 0. Although the falling edge response is the worst
case for settling, the rising edge illustrates the ripple that
these post filters are designed to address, so the rising
edge makes for a better intuitive comparison.
The initial rise of the LTC1966 will have enhanced slew rates
with DC and very low frequency inputs due to saturation
effects in the ∆S modulator. This is seen in Figure 15 in
two ways. First, the 1µF only output is seen to rise very
quickly in the first 40ms. The second way this effect shows
up is that the post filter outputs have a modest overshoot,
on the order of 3mV to 4mV, or 3% to 4%. This is only
an issue with input frequency bursts at 50Hz or less, and
even with the overshoot, the settling to a given level of
accuracy improves due to the initial speedup.
As predicted by Figure 6, the DC error with 1µF is well
under 1mV and is not noticeable at this scale. However, as
predicted by Figure 8, the peak error with the ripple from a
10Hz input is much larger, in this case about 5mV. As can
be clearly seen, the post filters reduce this ripple. Even
the wider bandwidth of Figure 13’s filter is seen to cut the
ripple down substantially (to <1mV) while the settling to
1% happens faster. With the narrower bandwidth of Figure
14’s filter, the step response is somewhat slower, but the
double frequency output ripple is just 180µV.
Figure 16 shows the step response of the same three cases
with a burst of 60Hz rather than 10Hz. With 60Hz, the ini-
tial portion of the step response is free of the boost seen
in Figure 15 and the two post filter responses have less
than 1% overshoot. The 1µF only case still has noticeable
120Hz ripple, but both filters have removed all detectable
ripple on this scale. This is to be expected; the first order
filter will reduce the ripple about 6:1 for a 6:1 change in
frequency, while the third order filters will reduce the
ripple about 63:1 or 216:1 for a 6:1 change in frequency.
Again, the two filter topologies have the same relative
shape, so the step response and ripple filtering trade-offs of
the two are the same, with the same performance of each
possible with the other by scaling it accordingly. Figures
17 and 18 show the peak error vs. frequency for a selec-
tion of capacitors for the two different filter topologies.
To keep the clean step response, scale all three capacitors
Figure 16. Step Responses with 60Hz Burst
Figure 15. Step Responses with 10Hz Burst
INPUT
BURST
200mV/
DIV
20mV/
DIV
0
0
1µF ONLY
FIGURE 13
FIGURE 14
STEP
RESPONSE
100ms/DIV 1966 F15
INPUT
BURST
200mV/
DIV
20mV/
DIV
0
0
1µF ONLY
FIGURE 13
FIGURE 14
STEP
RESPONSE
100ms/DIV 1966 F16
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within the filter. Scaling the buffered topology of Figure 13
is simple because the capacitors are in a 10:1:10 ratio.
Scaling the DC accurate topology of Figure 14 can be done
with standard value capacitors; one decade of scaling is
shown in Table 2.
Table 2. One Decade of Capacitor Scaling for Figure 14 with EIA
Standard Values
CAVE C1 = C2 =
1µF 0.22µF
1.5µF 0.33µF
2.2µF 0.47µF
3.3µF 0.68µF
4.7µF 1µF
6.8µF 1.5µF
Figures 19 and 20 show the settling time versus settling
accuracy for the buffered and DC accurate post filters,
respectively. The different curves represent different scal-
ings of the filters, as indicated by the CAVE value. These are
comparable to the curves in Figure 12 (single capacitor
case), with somewhat less settling time for the buffered
post filter, and somewhat more settling time for the DC
accurate post filter. These differences are due to the change
in overall bandwidth as mentioned earlier.
The other difference is the settling behavior of the filters
below the 1% level. Unlike the case of a 1st order filter,
any 3rd order filter can have overshoot and ringing. The
filter designs presented here have minimal overshoot
and ringing, but are somewhat sensitive to component
mismatches. Even the ±12% tolerance of the LTC1966
output impedance can be enough to cause some ringing.
The dashed lines indicate what can happen when ±5%
capacitors and ±1% resistors are used.
Figure 18. Peak Error vs Input Frequency with DC Accurate Post Filter
Figure 17. Peak Error vs Input Frequency with Buffered Post Filter
INPUT FREQUENCY (Hz)
1
–2.0
PEAK ERROR (%)
–1.6
–1.2
–0.8
–0.4
10 100
1966 F17
0
–1.8
–1.4
–1.0
–0.6
–0.2 C = 10µF
C = 4.7µF C = 2.2µF C = 1.0µF C = 0.47µF C = 0.22µF C = 0.1µF
INPUT FREQUENCY (Hz)
1
–2.0
PEAK ERROR (%)
–1.6
–1.2
–0.8
–0.4
10 100
1966 F18
0
–1.8
–1.4
–1.0
–0.6
–0.2 C = 10µF
C = 4.7µF C = 2.2µF C = 1.0µF C = 0.47µF C = 0.22µF C = 0.1µF
LTC1966
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Although the settling times for the post filtered configu-
rations shown on Figures 19 and 20 are not that much
different from those with a single capacitor, the point of
using a post filter is that the settling times are far better
for a given level peak error. The filters dramatically reduce
the low frequency averaging ripple with far less impact
on settling time.
Crest Factor and AC + DC Waveforms
In the preceding discussion, the waveform was assumed
to be AC-coupled, with a modest crest factor. Both as-
sumptions ease the requirements for the averaging
capacitor. With an AC-coupled sine wave, the calculation
engine squares the input, so the averaging filter that
follows is required to filter twice the input frequency,
making its job easier. But with a sinewave that includes
DC offset, the square of the input has frequency content
at the input frequency and the filter must average out
that lower frequency. So with AC + DC waveforms, the
required value for CAVE should be based on half of the
lowest input frequency, using the same design curves
presented in Figures 6, 8, 17 and 18.
Crest factor, which is the peak to RMS ratio of a dynamic
signal, also effects the required CAVE value. With a higher
crest factor, more of the energy in the signal is concen-
trated into a smaller portion of the waveform, and the
averaging has to ride out the long lull in signal activity.
For busy waveforms, such as a sum of sine waves, ECG
traces or SCR chopped sine waves, the required value for
CAVE should be based on the lowest fundamental input
frequency divided as such:
ff
CF
DESIGN INPUT MIN
=
()
•–
32
Figure 20. Settling Time with DC Accurate Post Filter
Figure 19. Settling Time with Buffered Post Filter
SETTLING TIME (SEC)
0.01
0.1
SETTLING ACCURACY (%)
1
10
10.1 10 100
1066 F14
C = 100µFC = 47µFC = 22µFC = 10µFC = 4.7µFC = 2.2µFC = 1.0µFC = 0.47µFC = 0.22µFC = 0.1µF
SETTLING TIME (SEC)
0.01
0.1
SETTLING ACCURACY (%)
1
10
10.1 10 100
1066 F20
C = 100µFC = 47µFC = 22µFC = 10µFC = 4.7µFC = 2.2µFC = 1.0µFC = 0.47µFC = 0.22µFC = 0.1µF
LTC1966
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using the same design curves presented in Figures 6, 8,
17 and 18. For the worst-case of square top pulse trains,
that are always either zero volts or the peak voltage, base
the selection on the lowest fundamental input frequency
divided by twice as much:
ff
CF
DESIGN INPUT MIN
=
()
•–
62
The effects of crest factor and DC offsets are cumulative.
So for example, a 10% duty cycle pulse train from 0VPEAK
to 1VPEAK (CF = √10 = 3.16) repeating at 16.67ms (60Hz)
input is effectively only 30Hz due to the DC asymmetry
and is effectively only:
fH
z
DESIGN
==
30
6316 2 378
•.–.
for the purposes of Figures 6, 8, 17 and 18.
Obviously, the effect of crest factor is somewhat simplified
above given the factor of 2 difference based on a subjec-
tive description of the waveform type. The results will vary
somewhat based on actual crest factor and waveform
dynamics and the type of filtering used. The above method
is conservative for some cases and about right for others.
The LTC1966 works well with signals whose crest factor is
4 or less. At higher crest factors, the internal ∆∑ modulator
will saturate, and results will vary depending on the exact
frequency, shape and (to a lesser extent) amplitude of the
input waveform. The output voltage could be higher or
lower than the actual RMS of the input signal.
The ∆∑ modulator may also saturate when signals with crest
factors less than 4 are used with insufficient averaging.
This will only occur when the output droops to less than
1/4 of the input voltage peak. For instance, a DC-coupled
pulse train with a crest factor of 4 has a duty cycle of
6.25% and a 1VPEAK input is 250mVRMS. If this input is
50Hz, repeating every 20ms, and CAVE = 1µF, the output
will droop during the inactive 93.75% of the waveform.
This droop is calculated as:
VVe
MIN RMS INACTIVE TIME
=
−
21– 2 • Z• C
OUT AVE
For the LTC1966, whose output impedance (ZOUT) is 85kΩ,
this droop works out to –5.22%, so the output would be
reduced to 237mV at the end of the inactive portion of the
input. When the input signal again climbs to 1VPEAK, the
peak/output ratio is 4.22.
With CAVE = 10µF, the droop is only –0.548% to 248.6mV
and the peak/output ratio is just 4.022, which the LTC1966
has enough margin to handle without error.
For crest factors less than 3.5, the selection of CAVE as
previously described should be sufficient to avoid this
droop and modulator saturation effect. But with crest
factors above 3.5, the droop should also be checked for
each design.
Error Analyses
Once the RMS-to-DC conversion circuit is working, it is
time to take a step back and do an analysis of the accuracy
of that conversion. The LTC1966 specifications include
three basic static error terms, VOOS, VIOS and GAIN. The
output offset is an error that simply adds to (or subtracts
from) the voltage at the output. The conversion gain of
the LTC1966 is nominally 1.000 VDCOUT/VRMSIN and the
gain error reflects the extent to which this conversion gain
is not perfectly unity. Both of these affect the results in a
fairly obvious way.
Input offset on the other hand, despite its conceptual
simplicity, effects the output in a nonobvious way. As
its name implies, it is a constant error voltage that adds
directly with the input. And it is the sum of the input and
VIOS that is RMS converted.
This means that the effect of VIOS is warped by the
nonlinear RMS conversion. With 0.2mV (typ) VIOS, and
a 200mVRMS AC input, the RMS calculation will add the
DC and AC terms in an RMS fashion and the effect is
negligible:
VOUT = √(200mV AC)2 + (0.2mV DC)2
= 200.0001mV
= 200mV + 1/2ppm
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But with 10× less AC input, the error caused by VIOS is
100× larger:
VOUT = √(20mV AC)2 + (0.2mV DC)2
= 20.001mV
= 20mV + 50ppm
This phenomena, although small, is one source of the
LTC1966’s residual nonlinearity.
On the other hand, if the input is DC-coupled, the input
offset voltage adds directly. With +200mV and a +0.2mV
VIOS, a 200.2mV output will result, an error of 0.1% or
1000ppm. With DC inputs, the error caused by VIOS can
be positive or negative depending if the two have the same
or opposing polarity.
The total conversion error with a sine wave input using the
typical values of the LTC1966 static errors is computed
as follows:
VOUT = (√(500mV AC)2 + (0.2mV DC)2) • 1.001 + 0.1mV
= 500.600mV
= 500mV + 0.120%
VOUT = (√(50mV AC)2 + (0.2mV DC)2) • 1.001 + 0.1mV
= 50.150mV
= 50mV + 0.301%
VOUT = (√(5mV AC)2 + (0.2mV DC)2) • 1.001 + 0.1mV
= 5.109mV
= 5mV + 2.18%
As can be seen, the gain term dominates with large inputs,
while the offset terms become significant with smaller
inputs. In fact, 5mV is the minimum RMS level needed to
keep the LTC1966 calculation core functioning normally,
so this represents the worst-case of usable input levels.
Using the worst-case values of the LTC1966 static errors,
the total conversion error is:
VOUT = (√(500mV AC)2 + (0.8mV DC)2) • 1.003 + 0.2mV
= 501.70mV
= 500mV + 0.340%
VOUT = (√(50mV AC)2 + (0.8mV DC)2) • 1.003 + 0.2mV
= 50.356mV
= 50mV + 0.713%
VOUT = (√(5mV AC)2 + (0.8mV DC)2) • 1.003 + 0.2mV
= 5.279mV
= 5mV + 5.57%
These static error terms are in addition to dynamic error
terms that depend on the input signal. See the Design
Cookbook for a discussion of the DC conversion error
with low frequency AC inputs. The LTC1966 bandwidth
limitations cause additional errors with high frequency
inputs. Another dynamic error is due to crest factor. The
LTC1966 performance versus crest factor is shown in the
Typical Performance Characteristics.
Monotonicity and Linearity
The LTC1966, like all implicit RMS-to-DC convertors
(Figure 3), has a division with the output in the denominator.
This works fine most of the time, but when the output is
zero or near zero this becomes problematic. The LTC1966
has multiple switched capacitor amplifier stages, and
depending on the different offsets and their polarity, the
DC transfer curve near zero input can take a few different
forms, as shown in the Typical Performance Characteristics
graph titled DC Transfer Function Near Zero.
Some units (about 1 of every 16) will even be well behaved
with a transfer function that is the upper half of a unit
rectangular hyperbola with a focal point on the y-axis of
a few millivolts.3 For AC inputs, these units will have a
monotonic transfer function all the way down to zero input.
The LTC1966 is trimmed for offsets as small as practical,
and the resulting behavior is the best statistical linearity
provided the zero region troubles are avoided.
It is possible, and even easy, to force the zero region to
be well behaved at the price of additional (though predict-
able) VOOS and some linearity error. For large enough input
signals, this linearity error may be negligible.
3In general, every LTC1966 will have a DC transfer function that is essentially a unit rectangular
hyperbola (the gain is not always exactly unity, but the gain error is small) with an X- and
Y- offset equal to VIOS and VOOS, respectively, until the inputs are small enough that the delta
sigma section gets confused. While some units will be the north half of a north south pair, other
units will have two upper halfs of the conjugate, east west, hyperbolas. The circuit of Figure 23
will assure a continuous transfer function.
LTC1966
24
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To do this, inject current into the output. As shown in
Figure 21, the charge pump output impedance is 170kΩ,
with the computational feedback cutting the closed loop
output impedance to the 85kΩ specification. By injecting
30nA of current into this 170Ω, with zero input, a 5mV offset
Figure 23 shows an analog implementation of this with
the offset and gain errors corrected; only the slight, but
necessary, degradation in nonlinearity remains. The cir-
cuit works by creating approximately 300mV of bias at
the junction of the 10MΩ resistors when the LTC1966’s
input/output are zero. The 10MΩ resistor to the LTC1966
output therefore feeds in 30nA. The loading of this resis-
tor causes a slight reduction in gain which is corrected,
as is the nominal 2.5mV offset, by the LT1494 op amp.
is created at the output feedback point, which is sufficient
to overcome the 5mV minimum signal level. With large
enough input signals, the computational feedback cuts
the output impedance to 85kΩ so the transfer function
asymptotes will have an output offset of 2.5mV, as shown
in Figure 22. This is the additional, predictable, VOOS that
is added, and should be subtracted from the RMS results,
either digitally, or by an analog means.
Figure 21. Behavioral Block Diagram of LTC1966
Figure 22a. DC Transfer Function with IINJECT = 30nA
Figure 22b. AC Transfer Function with IINJECT = 30nA
Figure 23. Monotonic AC Response with Offset
and Gain Corrected
1µF
1966 F23
5V
–5V
5V
85kΩ
10MΩ
10MΩ
LT1494
750k
VOUT
84.5k
100pF
OUT
LTC1966
VDD
VSS ENGND
OUTRTN
IN1
IN2 –
+
10MΩ
LT1494
5V
–5V
RMS TO DC
CONVERSION
CAVE
IINJECT DC
170kΩ
CHARGE
PUMP
LTC1966
OUTPUT
IN1
IN2
1966 F21
VIN (mV DC)
–20
0
VOUT (mV DC)
10
20
15
–15 –10 20
1966 F22a
5
0 5
–5 10 15
5mV MIN
IDEAL
ASYMPTOTES
SHIFTED +2.5mV
VIN (mV AC)
0
0
VOUT (mV DC)
10
20
15
520
1966 F22b
5
10 15
5mV MIN
IDEAL
ASYMPTOTES
SHIFTED +2.5mV
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The two 10MΩ resistors not connected to the supply can
be any value as long as they match and the feed voltage
is changed for 30nA injection. The op amp gain is only
1.00845, so the output is dominated by the LTC1966 RMS
results, which keeps errors low. With the values shown,
the resistors can be ±2% and only introduce ±170ppm of
gain error. The 84.5k resistor is the closest match in the
1% EIA values but if the 2% EIA value of 82k were used
instead, the gain would only be reduced by 248ppm.
This low error sensitivity is important because the LTC1966
output impedance is 85kΩ ±11.8%, which can create a
gain error of ±0.1%; enough to degrade the overall gain
accuracy somewhat. This gain variation term is increased
with lower value feed resistors, and decreased with higher
value feed resistors.
A bigger error caused by the variation of the LTC1966
output impedance is imperfect cancelation of the output
offset introduced by the injected current. The offset correc-
tion provided by the LT1494 will be based on a consistent
84.5kΩ times the injected current, while the LTC1966 output
impedance will vary enough that the output offset will have
a ±300µV range about the nominal 2.5mV. If this level of
output offset is not acceptable, either system calibration
or a potentiometer in the LT1494 feedback may be needed.
If the two 10MΩ feed resistors to the LT1494 have signifi-
cant mismatch, cancellation of the 2.5mV offset would be
further impacted, so it is probably worth paying an extra
penny or so for 1% resistors or even the better temperature
stability of thin film devices. The 300mV feed voltage is
not particularly critical because it is nominally cancelled,
but the offset errors due to these resistance mismatches
is scaled by that voltage.
Note that the input bias current of the op amp used in
Figure 23 is also nominally cancelled, but it will add or
subtract to the total current injected into the LTC1966
output. With the 1nA IBIAS of the LT1494 this is negligible.
While it is possible to eliminate the feed resistors by using
an op amp with a PNP input stage whose IBIAS is 30nA
or more, IBIAS is usually only specified for maximum and
this circuit needs a minimum of 30nA, therefore such an
approach may not always work.
Because the circuit of Figure 23 subtracts the offset cre-
ated by the injected current, the LT1494 output with zero
LTC1966 input will rest at +2.5mV, nominal before offsets,
rather then the 5mV seen in Figure 22.
Output Errors Versus Frequency
As mentioned in the Design Cookbook, the LTC1966 per-
forms very well with low frequency and very low frequency
inputs, provided a large enough averaging capacitor is used.
However, the LTC1966 will have additional dynamic errors as
the input frequency is increased. The LTC1966 is designed
for high accuracy RMS-to-DC conversion of signals into
the audible range. The input sampling amplifiers have a
–3dB frequency of 800kHz or so. However, the switched
capacitor circuitry samples the inputs at a modest 100kHz
nominal. The response versus frequency is depicted in the
Typical Performance Characteristics titled Input Signal
Bandwidth. Although there is a pattern to the response
versus frequency that repeats every sample frequency, the
errors are not overwhelming. This is because LTC1966 RMS
calculation is inherently wideband, operating properly with
minimal oversampling, or even undersampling, using sev-
eral proprietary techniques to exploit the fact that the RMS
value of an aliased signal is the same as the RMS value of
the original signal. However, a fundamental feature of the
∆S modulator is that sample estimation noise is shaped
such that minimal noise occurs with input frequencies
much less than the sampling frequency, but such noise
peaks when input frequency reaches half the sampling
frequency. Fortunately the LTC1966 output averaging filter
greatly reduces this error, but the RMS-to-DC topology
frequency shifts the noise to low (baseband) frequencies.
So with input frequencies above 5kHz to 10kHz, the output
will slowly wander around ±a few percent.
LTC1966
26
1966fb
applicaTions inForMaTion
Input Impedance
The LTC1966 true RMS-to-DC converter utilizes a 2.5pF
capacitor to sample the input at a nominal 100kHz sample
frequency. This accounts for the 8MΩ input impedance.
See Figure 24 for the equivalent analog input circuit. Note
however, that the 8MΩ input impedance does not directly
affect the input sampling accuracy. For instance, if a 100k
source resistance is used to drive the LTC1966, the sampling
action of the input stage will drag down the voltage seen
at the input pins with small spikes at every sample clock
edge as the sample capacitor is connected to be charged.
The time constant of this combination is small, 2.5pF •
100kΩ = 250ns, and during the 2.5µs period devoted to
sampling, ten time constants elapse. This allows each
sample to settle to within 46ppm and it is these samples
that are used to compute the RMS value.
This is a much higher accuracy than the LTC1966 conver-
sion limits, and far better than the accuracy computed via
the simplistic resistive divider model:
V V
R
R R
VM
M k
V
IN SOURCE IN
IN SOURCE
SOURCE
SOURCE
=+
=Ω
Ω + Ω
=
8
8 100
1 25– . %
Figure 24. LTC1966 Equivalent Analog Input Circuit
This resistive divider calculation does give the correct
model of what voltage is seen at the input terminals by a
parallel load averaged over a several clock cycles, which is
what a large shunt capacitor will do—average the current
spikes over several clock cycles.
When high source impedances are used, care must be taken
to minimize shunt capacitance at the LTC1966 input so as
not to increase the settling time. Shunt capacitance of just
2.5pF will double the input settling time constant and the
error in the above example grows from 46ppm to 0.67%
(6700ppm). A 13pF scope probe will increase the error
to almost 20%. As a consequence, it is important to not
try to filter the input with large input capacitances unless
driven by a low impedance. Keep time constant <<2.5µs.
When the LTC1966 is driven by op amp outputs, whose low
DC impedance can be compromised by sharp capacitive
load switching, a small series resistor may be added. A
10k resistor will easily settle with the 2.5pF input sampling
capacitor to within 1ppm.
These are important points to consider both during design
and debug. During lab debug, and even production testing,
a high value series resistor to any test point is advisable.
Output Impedance
The LTC1966 output impedance during operation is simi-
larly due to a switched capacitor action. In this case, 59pF
of on-chip capacitance operating at 100kHz translates into
170kΩ. The closed loop RMS-to-DC calculation cuts that
in half to the nominal 85kΩ specified.
In order to create a DC result, a large averaging capacitor
is required. Capacitive loading and time constants are not
an issue on the output.
IN1
VDD
VDD
VSS
VSS
RSW (TYP)
6k
CEQ
2.5pF
(TYP)
CEQ
2.5pF
(TYP)
IIN1
IN2
IIN2
1966 F24
RSW (TYP)
6k
IINVV
R
IINVV
R
RM
AVG
IN IN
EQ
AVG
IN IN
EQ
EQ
1
2
8
12
21
()
=−
()
=−
=
Ω
LTC1966
27
1966fb
applicaTions inForMaTion
However, resistive loading is an issue and the 10MΩ
impedance of a DMM or 10× scope probe will drag the
output down by –0.85% typ.
During shutdown, the switching action is halted and a
fixed 30k resistor shunts VOUT to OUT RTN so that CAVE
is discharged.
Guard Ringing the Output
The LTC1966’s combination of precision and high output
impedance can present challenges that make the use of
a guard ring around the output a good idea for many ap-
plications.
As mentioned above, a 10M resistive loading to ground
will drag down the gain far more than the specificed gain
tolerance. On a printed circuit board, contaminants from
solder flux residue to finger grime can create parasitic
resistances, which may be very high impedance, but can
have deleterious effects on the realized accuracy. As an
example, if the output (Pin 5) is routed near VSS (Pin 4)
in a ±5V application, a parasitic resistance of 1G (1,000M)
is enough to introduce a –425µV output offset error, more
than the specified limit of the LTC1966 itself.
Use of a guard ring, wherein the LTC1966 output node is
completely surrounded by a low impedance voltage, can
reduce leakage related errors substantially. The ground
ring can be tied to OUTRTN (Pin 6) and should encircle the
output (Pin 5), the averaging capacitor terminal, and the
destination terminal at the ADC, filter op amp, or whatever
else may be next.
Figure 24a shows a sample PCB layout for the circuit of
Figure 13, wherein the guard ring trace encloses R1, R2,
and the terminals of C1, C2, and the op amp input con-
nected to the high impedance LTC1966 Output. For the
circuit of figure 14, the guard ring should enclose R1 and
the terminals of C1 and C2, as well as the terminal at the
ultimate destination.
Figure 24b shows a sample PCB layout for the circuit of
Figure 23. The summing node of the LT1494 has the same
high impedance and high accuracy as the LTC1966 output,
so here the guard ring encircles both of them. Any leakage
between them is benign because the LT1494 forces them
to the same nominal voltage.
Figure 24a. PCB Layout of Figure 13 with Guard Ring
Figure 24b. PCB Layout of Figure 23 with Guard Ring
1966 F24a
LTC1966
MS8
LT1880
SO8
0.1µF
0.1µF
1µFCAVE
1966 F24b
LTC1966
MS8
LT1494
SO8
1µFCAVE
LTC1966
28
1966fb
applicaTions inForMaTion
Interfacing with an ADC
The LTC1966 output impedance and the RMS averaging
ripple need to be considered when using an analog-to-
digital converter (ADC) to digitize the LTC1966 RMS result.
The simplest configuration is to connect the LTC1966
directly to the input of a type 7106/7136 ADC as shown
in Figure 25a. These devices are designed specifically for
DVM/DPM use and include display drivers for a 3 1/2 digit
LCD segmented display. Using a dual slope conversion,
the input is sampled over a long integration window, which
results in rejection of line frequency ripple when integration
time is an integer number of line cycles. Finally, these parts
have an input impedance in the GΩ range, with specified
input leakage of 10pA to 20pA. Such a leakage, combined
with the LTC1966 output impedance, results in just 1µV
to 2µV of additional output offset voltage.
for are the input impedance, and any input sampling cur-
rents. The input sampling currents drawn by ∆∑ ADCs
often have large spikes of current with short durations
that can confuse some op amps, but with the large CAVE
needed by the LTC1966 these are not an issue.
The average current is important, as it can create LTC1966
errors; if it is constant it will create an offset, while aver-
age currents that change with the voltage level create gain
errors. Some converters run continuously, others only
sample upon demand, and this will change the results in
ways that need to be understood. The LTC1966 output
impedance has a loose tolerance relative to the usual re-
sistors and the same can be true for the input impedance
of ∆∑ ADC, resulting in gain errors from part-to-part. The
system calibration techniques described in the following
section should be used in applications that demand tight
tolerances.
One example of driving an oversampling ∆∑ ADC is shown
in Figure 25b. In this circuit, the LTC2420 is used with a
1V VREF. Since the LTC1966 output voltage range is about
1V, and the LTC2420 has a ±12.5% extended input range,
this configuration matches the two ranges with room to
spare. The LTC2420 has an input impedance of 16.6MΩ,
resulting in a gain error of –0.4% to –0.6%. In fact, the
LTC2420 DC input current is not zero at 0V, but rather at
one half its reference, so both an output offset and a gain
error will result. These errors will vary from part to part,
but with a specific LTC1966 and LTC2420 combination,
the errors will be fixed, varying less than ±0.05% over
temperature. So a system that has digital calibration can
be quite accurate despite the nominal gain and offset error.
With 20 bits of resolution, this part is more accurate than
the LTC1966, but the extra resolution is helpful because
it reduces nonlinearity at the LSB transitions as a digital
gain correction is made. Furthermore, its small size and
ease of use make it attractive.
Figure 25a. Interfacing to DVM/DPM ADC
Figure 25b. Interfacing to LTC2420
Another type of ADC that has inherent rejection of RMS
averaging ripple is an oversampling ∆∑. With most, but not
all, of these devices, it is possible to connect the LTC1966
output directly to the converter input. Issues to look out
CAVE
LTC1966
OUTPUT
OUT RTN
7106 TYPE
IN HI
IN LO
5
6
31
1966 F25a
30
CAVE
LTC1966
OUTPUT
OUT RTN
LTC2420
VIN SERIAL
DATA
DIGITALLY CORRECT
LOADING ERRORS
GND
SDO
SCK
CS
5
6
3
1966 F25b
4
VREF
2
1V
LTC1966
29
1966fb
As is shown in Figure 25b, where the LTC2420 is set to
continuously convert by grounding the CS pin. The gain
error will be less if CS is driven at a slower rate, however,
the rate should either be consistent or at a rate low enough
that the LTC1966 and its output capacitor have fully settled
by the beginning of each conversion, so that the loading
errors are consistent.
Note that in this circuit, the input current of the LTC2420
is being used to assure monotonicity. The LTC2420 ZIN of
16.6MΩ is effectively connected to half the reference volt-
age, so when the LTC1966 has zero signal, 500mV/16.6MΩ
= 30nA is provided.
Alternatively, a 5V VREF can be used, but in this case the
LTC1966 output span will only use 20% of the LTC2420’s
input voltage range. Furthermore, if the OUTRTN remains
grounded, the injected current with zero signal will be
150nA, resulting in 5× the offset error and nonlinearity
shown in Figure 22.
In both of the circuits of Figure 25, a guard ring only has to
encircle three terminals, the LTC1966 output, the top of the
averaging capacitor, and the ADC input. Figure 26 shows
the top copper patterns for example PCB layouts of each.
The low power consumption of the LTC1966 makes it well
suited for battery powered applications, and its slow output
(DC) makes it an ideal candidate for a micropower ADC.
applicaTions inForMaTion
Figure 26b. PCB Layout of Figure 25b with Guard Ring
Figure 26a. PCB Layout of Figure 25a with Guard Ring
Figure 10 in Application Note 75, for instance, details a
10-bit ADC with a 35ms conversion time that uses just
29µA of supply current. Such an ADC may also be of use
within a 4mA to 20mA loop.
Other types of ADCs sample the input signal once and
perform a conversion on that one sample. With these ADCs
(Nyquist ADCs), a post filter will be needed in most cases
to reduce the peak error with low input frequencies. The
DC accurate filter of Figure 14 is attractive from an error
standpoint, but it increases the impedance at the ADC
input. In most cases, the buffered post filter of Figure13
will be more appropriate for use with Nyquist analog-to-
digital converters.
SYSTEM CALIBRATION
The LTC1966 static accuracy can be improved with end
system calibration. Traditionally, calibration has been
done at the factory, or at a service depot only, typically
using manually adjusted potentiometers. Increasingly,
systems are being designed for electronic calibration
where the accuracy corrections are implemented in digital
code wherever possible, and with calibration DACs where
necessary. Additionally, many systems are now designed
for self calibration, in which the calibration occurs inside
the machine, automatically without user intervention.
LTC1966
MS8
1966 F26b
LTC2420
SO8
1µfCAVE
1966 F26a
1µfCAVE
LTC1966
MS8
ICL7106
MQFP
LTC1966
30
1966fb
Whatever calibration scheme is used, the linearity of the
LTC1966 will improve the calibrated accuracy over that
achievable with older log/antilog RMS-to-DC converters.
Additionally, calibration using DC reference voltages are
essentially as accurate with the LTC1966 as those using
AC reference voltages. Older log/antilog RMS-to-DC
converters required nonlinear input stages (rectifiers)
whose linearity would typically render DC based calibra-
tion unworkable.
The following are four suggested calibration methods.
Implementations of the suggested adjustments are de-
pendent on the system design, but in many cases, gain
and output offset can be corrected in the digital domain,
and will include the effect of all gains and offsets from the
LTC1966 output through the ADC. Input offset voltage, on
the other hand, will have to be corrected with adjustment
to the actual analog input to the LTC1966.
The methods below assume the unaltered linearity of the
LTC1966, i.e. without the monotonicity fix of Figure 21.
If this is present, the VOOS shift it introduces should be
taken out before using either method for which VOOS is
not calibrated. Also, the nonlinearity it introduces will
increase the 20mV readings discussed below by 0.78%
but increase the 200mV readings only 78ppm. There
are a variety of ways to deal with these errors, including
possibly ignoring them, but the specifics will depend on
system requirements. Designers are cautioned to avoid
the temptation to digitally take out the hyperbolic transfer
function introduced because if the offsets are not exactly
the nominals assumed, the system will end up right back
where it began with a potential discontinuity with zero
input, either from a divide by zero or from a square root
of a negative number in the calculations to undo the hy-
perobic transfer function. An adaptive algorithm would
most likely be necessary to safely take out more than half
of the introduced nonlinearity.
If a 5V reference is used in the connection of Figure 25b,
the VOOS and nonlinearity created would be even larger,
and will no doubt be more tempting to correct for. Design-
ers are likewise cautioned against correcting for all of the
nonlinearity.
AC-Only, 1 Point
The dominant error at full-scale will be caused by the
gain error, and by applying a full-scale sine wave input,
this error can be measured and corrected for. Unlike older
log/antilog RMS-to-DC converters, the correction should
be made for zero error at full scale to minimize errors
through
out the dynamic range.
The best frequency for the calibration signal is roughly ten
times the –0.1% DC error frequency. For 1µF, –0.1% DC
error occurs at 8Hz, so 80Hz is a good calibration frequency,
although anywhere from 60Hz to 100Hz should suffice.
The trade-off here is that on the one hand, the DC error
is input frequency dependent, so a calibration signal
frequency high enough to make the DC error negligible
should be used. On the other hand, as low a frequency as
can be used is best to avoid attenuation of the calibrated
AC signal, either from parasitic RC loading or insufficient
op amp gain. For instance, with a 1kHz calibration signal,
a 1MHz op amp will typically only have 60dB of open loop
gain, so it could attenuate the calibration signal a full 0.1%.
AC-Only, 2 Point
The next most significant error for AC-coupled applications
will be the effect of output offset voltage, noticeable at the
bottom end of the input scale. This too can be calibrated
out if two measurements are made, one with a full-scale
sine wave input and a second with a sine wave input (of
the same frequency) at 10% of full-scale. The trade-off in
selecting this second level is that it should be small enough
that the gain error effect becomes small compared to the
gain error effect at full-scale, while on the other hand,
not using so small an input that the input offset voltage
becomes an issue.
applicaTions inForMaTion
LTC1966
31
1966fb
The calculations of the error terms for a 200mV full-scale
case are:
Gain = Reading at 200mV – Reading at 20mV
180mV
Output Offset = Reading at 20mV
Gain –20mV
DC, 2 Point
DC based calibration is preferable in many cases because a
DC voltage of known, good accuracy is easier to generate
than such an AC calibration voltage. The only down side
is that the LTC1966 input offset voltage plays a role. It is
therefore suggested that a DC based calibration scheme
check at least two points: ±full-scale. Applying the –full-
scale input can be done by physically inverting the voltage
or by applying the same +full-scale input to the opposite
LTC1966 input.
For an otherwise AC-coupled application, only the gain
term may be worth correcting for, but for DC-coupled ap-
plications, the input offset voltage can also be calculated
and corrected for.
The calculations of the error terms for a 200mV full-scale
case are:
Gain = Reading at 200mV +Reading at – 200mV
400mV
Input Offset = Reading at – 200mV – Reading at 200mV
2•Gain
applicaTions inForMaTion
Note: Calculation of and correction for input offset voltage
are the only way in which the two LTC1966 inputs (IN1,
IN2) are distinguishable from each other. The calculation
above assumes the standard definition of offset; that a
positive offset is the case of a positive voltage error inside
the device that must be corrected by applying a like nega-
tive voltage outside. The offset is referred to whichever
pin is driven positive for the +full-scale reading.
DC, 3 Point
One more point is needed with a DC calibration scheme
to determine output offset voltage: +10% of full scale.
The calculation of the input offset is the same as for the
2-point calibration above, while the gain and output offset
are calculated for a 200mV full-scale case as:
Gain = Reading at 200mV – Reading at 20mV
180mV
Output Offset =
Reading at 200mV +Reading at – 200mV – 400mV •Gain
2
LTC1966
32
1966fb
TROUBLESHOOTING GUIDE
Top Ten LTC1966 Application Mistakes
1. Circuit won’t work–Dead On Arrival–no power drawn.
– Probably forgot to enable the LTC1966 by pulling
Pin8 low.
Solution: Tie Pin 8 to Pin 1.
2. Circuit won’t work, but draws power. Zero or
very little output, single-ended input application.
– Probably didn’t connect both input pins.
Solution: Tie both inputs to something. See Input
Connections in the Design Cookbook.
applicaTions inForMaTion
4. Gain is low by a few percent, along with other screwy
results.
– Probably tried to use output in a floating, differential
manner.
Solution: Tie Pin 6 to a low impedance. See Output
Connections in the Design Cookbook.
TYPE 7136
ADC
LTC1966
HI
31
30
5
6LO
VOUT
OUT RTN
1966 TS04
GROUND PIN 6
LTC1966
CONNECT PIN 3
IN1
2
3
NC IN2
1966 TS02
3. Screwy results, particularly with respect to linearity
or high crest factors; differential input application.
– Probably AC-coupled both input pins.
Solution: Make at least one input DC-coupled. See
Input Connections in the Design Cookbook.
LTC1966
IN1
2
3IN2
1966 TS03
DC CONNECT ONE INPUT
LTC1966
DC CONNECT ONE INPUT
IN1
2
3IN2
5. Offsets perceived to be out of specification because 0V
in ≠ 0V out.
– The offsets are not specified at 0V in. No RMS-to-DC
converter works well at 0 due to a divide-by-zero
calculation.
Solution: Measure VIOS/VOOS by extrapolating
readings > ±5mVDC.
6. Linearity perceived to be out of specification particularly
with small input signals.
– This could again be due to using 0V in as one of the
measurement points.
Solution: Check Linearity from 5mVRMS to 500mVRMS.
–
The input offset voltage can cause small AC
linearity errors at low input amplitudes as well. See
Error Analyses section.
Possible Solution: Include a trim for input offset.
LTC1966
33
1966fb
applicaTions inForMaTion
7. Output is noisy with >10kHz inputs.
– This is a fundamental characteristic of this topol-
ogy. The LTC1966 is designed to work very well
with inputs of 1kHz or less. It works okay as high
as 1MHz, but it is limited by aliased ∆S noise.
Solution: Bandwidth limit the input or digitally filter
the resulting output.
8. Large errors occur at crest factors approaching, but
less than 4.
– Insufficient averaging.
Solution: Increase CAVE. See Crest Factor and AC + DC
Waveforms section for discussion of output droop.
9. Screwy results, errors > spec limits, typically 1% to 5%.
– High impedance (85kΩ) and high accuracy (0.1%)
require clean boards! Flux residue, finger grime, etc.
all wreak havoc at this level.
Solution: Wash the board.
Helpful Hint: Sensitivity to leakages can be reduced
significantly through the use of guard traces.
LTC1966
KEEP BOARD CLEAN
10. Gain is low by ≅1% or more, no other problems.
– Probably due to circuit loading. With a DMM or
a 10× scope probe, ZIN = 10MΩ. The LTC1966
output is 85kΩ, resulting in –0.85% gain error.
Output impedance is higher with the DC accurate
post filter.
Solution: Remove the shunt loading or buffer the
output.
– Loading can also be caused by cheap averaging
capacitors.
Solution: Use a high quality metal film capacitor
for CAVE.
200mVRMS IN
–0.85%
DMM
DCV
LTC1966
10M
5
85k 6
VOUT
OUT RTN
1966 TS10
LOADING DRAGS DOWN GAIN
mV
LTC1966
34
1966fb
Typical applicaTions
±5V Supplies, Differential, DC-Coupled
RMS-to-DC Converter
VDD
5V
–5V
LTC1966
IN1 DC OUTPUT
CAVE
1µF
IN2
1966 TA03
VOUT
DC + AC
INPUTS
(1VPEAK
DIFFERENTIAL) OUT RTN
GND ENVSS
5V Single Supply, Differential, AC-Coupled
RMS-to-DC Converter
VDD
5V
LTC1966
IN1 DC OUTPUT
CAVE
1µF
CC
0.1µF
IN2
1966 TA05
VOUT
AC INPUTS
(1VPEAK
DIFFERENTIAL) OUT RTN
GND ENVSS
2.7V Single Supply, Single Ended, AC-Coupled
RMS-to-DC Converter with Shutdown
VDD
2.7V
2.7V/3V CMOS
LTC1966
IN1 DC OUTPUT
CAVE
1µF
CC
0.1µF
IN2
1966 TA04
VOUT
AC INPUT
(1VPEAK)
OUT RTN
GND
EN
VSS
OFF ON
±2.5V Supplies, Single Ended, DC-Coupled
RMS-to-DC Converter with Shutdown
VDD
2.5V
–2.5V –2.5V
–2.5V
LTC1966
IN1 DC OUTPUT
CAVE
1µF
0.1µF
X7R
IN2
1966 TA06
VOUT
DC + AC
INPUT
(1VPEAK)OUT RTN
GND
EN
VSS
OFF
2V
–2V
ON
Battery Powered Single-Ended AC-Coupled
RMS-to-DC Converter
VDD
AC INPUT
(1VPEAK)
LTC1966
IN1 DC
OUTPUT
CAVE
1µF
CC
0.1µF
0.1µF
X7R
IN2
1966 TA07
VOUT
OUT RTN
GND
GND
LT1175CS8-5
SHDN
VIN
OUT
9V
SENSE
ENVSS
LTC1966
35
1966fb
siMpliFieD scheMaTic
2nd ORDER ∆∑ MODULATOR
IN1
IN2
EN
VDD
–
+
–
+
OUTPUT
OUT RTN
30k
BLEED RESISTOR
FOR CAVE
CAVE
1966 SS
TO BIAS CONTROL
VSS
GND
C1
C2
Y1 Y2
C12
C11
CLOSED
DURING
SHUTDOWN
C9
C10
C5C3
C4
C6
C8
C7
A2A1
LTC1966
36
1966fb
package DescripTion
MS8 Package
8-Lead Plastic MSOP
(Reference LTC DWG # 05-08-1660 Rev F)
MSOP (MS8) 0307 REV F
0.53 ± 0.152
(.021 ± .006)
SEATING
PLANE
NOTE:
1. DIMENSIONS IN MILLIMETER/(INCH)
2. DRAWING NOT TO SCALE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
0.18
(.007)
0.254
(.010)
1.10
(.043)
MAX
0.22 – 0.38
(.009 – .015)
TYP
0.1016 ± 0.0508
(.004 ± .002)
0.86
(.034)
REF
0.65
(.0256)
BSC
0° – 6° TYP
DETAIL “A”
DETAIL “A”
GAUGE PLANE
1 2 34
4.90 ± 0.152
(.193 ± .006)
8765
3.00 ± 0.102
(.118 ± .004)
(NOTE 3)
3.00 ± 0.102
(.118 ± .004)
(NOTE 4)
0.52
(.0205)
REF
5.23
(.206)
MIN
3.20 – 3.45
(.126 – .136)
0.889 ± 0.127
(.035 ± .005)
RECOMMENDED SOLDER PAD LAYOUT
0.42 ± 0.038
(.0165 ± .0015)
TYP
0.65
(.0256)
BSC
LTC1966
37
1966fb
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
revision hisTory
REV DATE DESCRIPTION PAGE NUMBER
B 5/11 Revised entire data sheet to add H- and MP- grades 1 to 38
(Revision history begins at Rev B)
LTC1966
38
1966fb
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com
LINEAR TECHNOLOGY CORPORATION 2001
LT 0511 REV B • PRINTED IN USA
relaTeD parTs
Typical applicaTion
PART NUMBER DESCRIPTION COMMENTS
LT
®
1077 Micropower, Single Supply Precision Op Amp 48µA ISY, 60µV VOS(MAX), 450pA IOS(MAX)
LT1175-5 Negative, –5V Fixed, Micropower LDO Regulator 45µA IQ, Available in SO-8 or SOT-223
LT1494 1.5µA Max, Precision Rail-to-Rail I/O Op Amp 375µV VOS(MAX), 100pA IOS(MAX)
LT1782 General Purpose SOT-23 Rail-to-Rail Op Amp 40µA ISY, 800µV VOS(MAX), 2nA IOS(MAX)
LT1880 SOT-23 Rail-to-Rail Output Precision Op Amp 1.2mA ISY, 150µV VOS(MAX), 900pA IOS(MAX)
LTC1967 Precision, Extended Bandwidth RMS to DC Converter 330µA ISY, ∆∑ RMS Conversion to 4MHz
LTC1968 Precision, Wide Bandwidth RMS to DC Converter 2.3mA ISY, ∆∑ RMS Conversion to 15MHz
LTC2050 Zero Drift Op Amp in SOT-23 750µA ISY, 3µV VOS(MAX), 75pA IB(MAX)
LT2178/LT2178A 17µA Max, Single Supply Precision Dual Op Amp 14µA ISY, 120µV VOS(MAX), 350pA IOS(MAX)
LTC2402 2-Channel, 24-bit, Micropower, No Latency ∆S™ ADC 200µA ISY, 4ppm INL, 10ppm TUE
LTC2420 20-bit, Micropower, No Latency ∆S ADC in SO-8 200µA ISY, 8ppm INL, 16ppm TUE
LTC2422 2-Channel, 20-bit, Micropower, No Latency ∆S ADC Dual Channel Version of LTC2420
RMS Noise Measurement
70A Current Measurement Single Supply RMS Current Measurement
5V
LTC1966
IN1 VOUT
4mVDC/ARMS
CAVE
1µF
IN2
1966 TA09
VOUT
AC CURRENT
71.2A MAX
50Hz TO 400Hz OUT RTN
GND ENVSS
10Ω
T1: CR MAGNETICS CR8348-2500-N
www.crmagnetics.com
–5V
T1
V+
LTC1966
IN1
VOUT = 4mVDC/ARMS
CAVE
1µF
0.1µF
IN2
1966 TA08
VOUT
AC CURRENT
71.2A MAX
50Hz TO 400Hz OUT RTN
GND ENVSS
100k
100k
10Ω
T1: CR MAGNETICS CR8348-2500-N
www.crmagnetics.com
T1
VDD
5V
5V
–5V
–5V
LTC1966
IN1 CAVE
1µF
0.1µF
1.5µF
IN2
1966 TA10
VOUT
VOLTAGE
NOISE IN
OUT RTN
GND ENVSS
1mVDC
1µVRMS NOISE
VOUT =
–
+10k
100Ω
100Ω 100k
BW 1kHz TO 100kHz
INPUT SENSITIVITY = 1µVRMS TYP
1/2
LTC6203
