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LM101AJAN Operational Amplifiers
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1FEATURES DESCRIPTION
The LM101A is a general purpose operational
2 Offset Voltage 3 mV Maximum Over amplifier which features improved performance over
Temperature industry standards such as the LM709. Advanced
Input Current 100 nA Maximum Over processing techniques make possible an order of
Temperature magnitude reduction in input currents, and a redesign
of the biasing circuitry reduces the temperature drift
Offset Current 20 nA Maximum Over of input current. Improved specifications include:
Temperature Offset voltage 3 mV maximum over temperature
Ensured Drift Characteristics Input current 100 nA maximum over temperature
Offsets Ensured Over Entire Common Mode Offset current 20 nA maximum over temperature
and Supply Voltage Ranges Ensured drift characteristics
Slew Rate of 10 V/µS as a Summing Amplifier Offsets ensured over entire common mode and
supply voltage ranges
Slew rate of 10V/μs as a summing amplifier
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Copyright © 2006–2013, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
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This amplifier offers many features which make its In addition, the device provides better accuracy
application nearly foolproof: overload protection and lower noise in high impedance circuitry. The
on the input and output, no latch-up when the low input currents also make it particularly well
common mode range is exceeded, and freedom suited for long interval integrators or timers,
from oscillations and compensation with a single sample and hold circuits and low frequency
30 pF capacitor. It has advantages over internally waveform generators. Further, replacing circuits
compensated amplifiers in that the frequency where matched transistor pairs buffer the inputs of
compensation can be tailored to the particular conventional IC op amps, it can give lower offset
application. For example, in low frequency circuits voltage and a drift at a lower cost.
it can be overcompensated for increased stability
margin. Or the compensation can be optimized to
give more than a factor of ten improvement in high
frequency performance for most applications.
Schematic
Pin connections shown are for 8-pin packages
Connection Diagrams
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Pin 4 connected to case.
Figure 1. (Top View) Figure 2. (Top View)
TO-99 Package CDIP Package
See Package Number LMC See Package Number NAB0008A
Figure 3. (Top View) Figure 4. (Top View)
CDIP Package CLGA Package
See NS Package Number J See NS Package Number NAD0010A
Fast AC/DC Converter
Feedforward compensation can be used to make a fast full wave rectifier without a filter.
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
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Absolute Maximum Ratings(1)
Supply Voltage ±22V
Differential Input Voltage ±30V
Input Voltage(2) ±15V
Output Short Circuit Duration Continuous
Operating Ambient Temp. Range 55°C TA+125°C
TJMax 150°C
Power Dissipation at TA= LMC-Package Still Air) 750 mW
25°C(3) (500 LF / Min Air Flow) 1,200 mW
NAB0008A-Package (Still Air) 1,000 mW
(500 LF / Min Air Flow) 1,500 mW
J-Package (Still Air) 1,200mW
(500 LF / Min Air Flow) 2,000mW
NAD0010A-Package (Still Air) 500mW
(500 LF / Min Air Flow) 800mW
(Still Air) 165°C/W
LMC-Package (500 LF / Min Air Flow) 89°C/W
(Still Air) 128°C/W
NAB0008A-Package (500 LF / Min Air Flow) 75°C/W
θJA (Still Air) 98°C/W
J-Package (500 LF / Min Air Flow) 59°C/W
Thermal Resistance (Still Air) 233°C/W
NAD0010A-Package (500 LF / Min Air Flow) 155°C/W
LMC-Package 39°C/W
NAB0008A-Package 26°C/W
θJC (Typical) J-Package 24°C/W
NAD0010A-Package 26°C/W
Storage Temperature Range 65°C TA+150°C
Lead Temperature (Soldering, 10 sec.) 300°C
ESD Tolerance(4) 3000V
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating ratings indicate conditions for
which the device is intended to be functional, but do no ensure specific performance limits. For ensured specifications and test
conditions, see the Electrical Characteristics. The ensured specifications apply only for the test conditions listed. Some performance
characteristics may degrade when the device is not operated under the listed test conditions.
(2) For supply voltages less than ±15V, the absolute maximum input voltage is equal to the supply voltage.
(3) The maximum power dissipation must be derated at elevated temperatures and is dictated by TJmax (maximum junction temperature),
θJA (package junction to ambient thermal resistance), and TA(ambient temperature). The maximum allowable power dissipation at any
temperature is PDmax = (TJmax TA) / θJA or the number given in the Absolute Maximum Ratings, whichever is lower.
(4) Human body model, 100 pF discharged through 1.5 kΩ.
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Quality Conformance Inspection
Mil-Std-883, Method 5005 - Group A
Subgroup Description Temp (°C)
1 Static tests at 25
2 Static tests at 125
3 Static tests at -55
4 Dynamic tests at 25
5 Dynamic tests at 125
6 Dynamic tests at -55
7 Functional tests at 25
8A Functional tests at 125
8B Functional tests at -55
9 Switching tests at 25
10 Switching tests at 125
11 Switching tests at -55
LM101JAN Electrical Characteristics DC Parameters
The following conditions apply to all parameters, unless otherwise specified
VCC = ±20V, VCM = 0V, RS= 50
Symbol Parameters Conditions Sub-
Notes Min Max Unit groups
VIO Input Offset Voltage +VCC = 35V, -VCC = -5V, -2.0 +2.0 mV 1
VCM = -15V -3.0 +3.0 mV 2, 3
+VCC = 5V, -VCC = -35V, -2.0 +2.0 mV 1
VCM = +15V -3.0 +3.0 mV 2, 3
VCM = 0V -2.0 +2.0 mV 1
-3.0 +3.0 mV 2, 3
+VCC = 5V, -VCC = -5V, -2.0 +2.0 mV 1
VCM = 0V -3.0 +3.0 mV 2, 3
IIO Input Offset Current +VCC = 35V, -VCC = -5V, -10 +10 nA 1, 2
VCM = -15V, RS= 100K-20 +20 nA 3
+VCC = 5V, -VCC = -35V, -10 +10 nA 1, 2
VCM = +15V, RS= 100K-20 +20 nA 3
VCM = 0V, RS= 100K-10 +10 nA 1, 2
-20 +20 nA 3
+VCC = 5V, -VCC = -5V, -10 +10 nA 1, 2
VCM = 0V, RS= 100K-20 +20 nA 3
±IIB Input Bias Current +VCC = 35V, -VCC = -5V, -0.1 75 nA 1, 2
VCM = -15V, RS= 100K-0.1 100 nA 3
+VCC = 5V, -VCC = -35V, -0.1 75 nA 1, 2
VCM = +15V, RS= 100K-0.1 100 nA 3
VCM = 0V, RS= 100K-0.1 75 nA 1, 2
-0.1 100 nA 3
+VCC = 5V, -VCC = -5V, -0.1 75 nA 1, 2
VCM = 0V, RS= 100K-0.1 100 nA 3
+PSRR Power Supply Rejection Ratio +VCC = 10V, -VCC = -20V -50 +50 µV/V 1
-100 +100 µV/V 2, 3
-PSRR Power Supply Rejection Ratio +VCC = 20V, -VCC = -10V -50 +50 µV/V 1
-100 +100 µV/V 2, 3
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LM101JAN Electrical Characteristics DC Parameters (continued)
The following conditions apply to all parameters, unless otherwise specified
VCC = ±20V, VCM = 0V, RS= 50
Symbol Parameters Conditions Sub-
Notes Min Max Unit groups
CMRR Common Mode Rejection Ratio VCC = ±35V to ±5V, 80 dB 1, 2, 3
VCM = ±15V
+VIO Adj Adjustment for Input Offset 4.0 mV 1, 2, 3
Voltage
-VIO Adj Adjustment for Input Offset -4.0 mV 1, 2, 3
Voltage
+IOS Output Short Circuit Current +VCC = 15V, -VCC = -15V, -60 mA 1, 2, 3
t25mS, VCM = -15V
-IOS Output Short Circuit Current +VCC = 15V, -VCC = -15V, +60 mA 1, 2, 3
t25mS, VCM = +15V
ICC Power Supply Current +VCC = 15V, -VCC = -15V 3.0 mA 1
2.32 mA 2
3.5 mA 3
ΔVIO /ΔT Temperature Coefficient of Input -55°C TA+25°C See(1) -18 +18 µV/°C 2
Offset Voltage +25°C TA+125°C See(1) -15 +15 µV/°C 3
ΔIIO /ΔT Temperature Coefficient of Input -55°C TA+25°C See(2) -200 +200 pA/°C 2
Offset Current +25°C TA+125°C See(2) -100 +100 pA/°C 3
-AVS Large Signal (Open Loop) Voltage RL= 2K, VO= -15V See(3) 50 V/mV 4
Gain See(3) 25 V/mV 5, 6
RL= 10K, VO= -15V See(3) 50 V/mV 4
See(3) 25 V/mV 5, 6
+AVS Large Signal (Open Loop) Voltage RL= 2K, VO= +15V See(3) 50 V/mV 4
Gain See(3) 25 V/mV 5, 6
RL= 10K, VO= +15V See(3) 50 V/mV 4
See(3) 25 V/mV 5, 6
AVS Large Signal (Open Loop) Voltage VCC = ±5V, RL= 2K,See(3) 10 V/mV 4, 5, 6
Gain VO= ±2V
VCC = ±5V, RL= 10K,See(3) 10 V/mV 4, 5, 6
VO= ±2V
+VOP Output Voltage Swing RL= 10K, VCM = -20V +16 V 4, 5, 6
RL= 2K, VCM = -20V +15 V 4, 5, 6
-VOP Output Voltage Swing RL= 10K, VCM = 20V -16 V 4, 5, 6
RL= 2K, VCM = 20V -15 V 4, 5, 6
(1) Calculated parameter
(2) Calculated parameter
(3) Datalog reading of K = V/mV.
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LM101AJAN Electrical Characteristics AC Parameters
The following conditions apply to all parameters, unless otherwise specified
VCC = ±20V, VCM = 0V, RS= 50
Symbol Parameter Conditions Sub-
Notes Min Max Units groups
+SR Slew Rate AV= 1, VI= -5V to +5V 0.3 V/µS 7
-SR Slew Rate AV= 1, VI= +5V to -5V 0.3 V/µS 7
TRTR Rise Time AV= 1, VI= 50mV 800 nS 7
TROS Overshoot AV= 1, VI= 50mV 25 % 7
NIBB Noise Broadband BW = 10Hz to 5KHz, RS= 015 µVRMS 7
NIPC Noise Popcorn BW = 10Hz to 5KHz, 80 µVPK 7
RS= 100K
LM101AJAN Electrical Characteristics DC Parameters: Drift Values
The following conditions apply to all parameters, unless otherwise specified
VCC = ±20V, VCM = 0V, RS= 50
Delta calculations performed on JAN S devices at group B, Subgroup 5 only.
Symbol Parameter Conditions Sub-
Notes Min Max Units groups
VIO Input Offset Voltage VCM = 0V -0.5 0.5 mV 1
± IIB Input Bias Current VCM = 0V, RS= 100K-7.5 7.5 nA 1
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Typical Performance Characteristics LM101A
Input Voltage Range Output Swing
Figure 5. Figure 6.
Voltage Gain Supply Current
Figure 7. Figure 8.
Voltage Gain Maximum Power Dissipation
Figure 9. Figure 10.
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Typical Performance Characteristics LM101A (continued)
Input Current,
LM101A Input Noise Voltage
Figure 11. Figure 12.
Input Noise Current Common Mode Rejection
Figure 13. Figure 14.
Closed Loop Output
Power Supply Rejection Impedance
Figure 15. Figure 16.
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Typical Performance Characteristics for Various Compensation Circuits(1)
Single Pole Compensation Two Pole Compensation
CS= 30 pF
CS= 30 pF
C2 = 10 C1
Figure 17. Figure 18.
Open Loop Frequency
Feedforward Compensation Response
fo= 3 MHz Figure 19. Figure 20.
(1) Pin connections shown are for 8-pin packages.
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Typical Performance Characteristics for Various Compensation Circuits(1) (continued)
Open Loop Frequency Open Loop Frequency
Response Response
Figure 21. Figure 22.
Large Signal Frequency Large Signal Frequency
Response Response
Figure 23. Figure 24.
Large Signal Frequency Voltage Follower Pulse
Response Response
Figure 25. Figure 26.
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Typical Performance Characteristics for Various Compensation Circuits(1) (continued)
Voltage Follower Pulse
Response Inverter Pulse Response
Figure 27. Figure 28.
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TYPICAL APPLICATIONS(2)
Inverting Amplifier
Variable Capacitance Multiplier with Balancing Circuit
†May be zero or equal to parallel combination of R1 and R2 for
minimum offset.
Simulated Inductor Sine Wave Oscillator
LR1 R2 C1
RS= R2
RP= R1
fo= 10 kHz
Fast Inverting Amplifier
with High Input Impedance Integrator with Bias Current Compensation
*Adjust for zero integrator drift. Current drift typically 0.1 nA/°C over
55°C to +125°C temperature range.
(2) Pin connections shown are for 8-pin packages.
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Application Hints(2)
Protecting Against Gross
Fault Conditions
*Protects input
†Protects output
‡Protects output—not needed when R4 is used.
Compensating for Stray Input Capacitances
or Large Feedback Resistor
Isolating Large Capacitive Loads
Although the LM101A is designed for trouble free operation, experience has indicated that it is wise to observe
certain precautions given below to protect the devices from abnormal operating conditions. It might be pointed
out that the advice given here is applicable to practically any IC op amp, although the exact reason why may
differ with different devices.
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When driving either input from a low-impedance source, a limiting resistor should be placed in series with the
input lead to limit the peak instantaneous output current of the source to something less than 100 mA. This is
especially important when the inputs go outside a piece of equipment where they could accidentally be
connected to high voltage sources. Large capacitors on the input (greater than 0.1 μF) should be treated as a
low source impedance and isolated with a resistor. Low impedance sources do not cause a problem unless their
output voltage exceeds the supply voltage. However, the supplies go to zero when they are turned off, so the
isolation is usually needed.
The output circuitry is protected against damage from shorts to ground. However, when the amplifier output is
connected to a test point, it should be isolated by a limiting resistor, as test points frequently get shorted to bad
places. Further, when the amplifier drives a load external to the equipment, it is also advisable to use some sort
of limiting resistance to preclude mishaps.
Precautions should be taken to insure that the power supplies for the integrated circuit never become
reversed—even under transient conditions. With reverse voltages greater than 1V, the IC will conduct excessive
current, fusing internal aluminum interconnects. If there is a possibility of this happening, clamp diodes with a
high peak current rating should be installed on the supply lines. Reversal of the voltage between V+and Vwill
always cause a problem, although reversals with respect to ground may also give difficulties in many circuits.
The minimum values given for the frequency compensation capacitor are stable only for source resistances less
than 10 kΩ, stray capacitances on the summing junction less than 5 pF and capacitive loads smaller than 100
pF. If any of these conditions are not met, it becomes necessary to overcompensate the amplifier with a larger
compensation capacitor. Alternately, lead capacitors can be used in the feedback network to negate the effect of
stray capacitance and large feedback resistors or an RC network can be added to isolate capacitive loads.
Although the LM101A is relatively unaffected by supply bypassing, this cannot be ignored altogether. Generally it
is necessary to bypass the supplies to ground at least once on every circuit card, and more bypass points may
be required if more than five amplifiers are used. When feed-forward compensation is employed, however, it is
advisable to bypass the supply leads of each amplifier with low inductance capacitors because of the higher
frequencies involved.
Typical Applications(3)
Standard Compensation and
Offset Balancing Circuit
(3) Pin connections shown are for 8-pin packages.
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Fast Voltage Follower
Power Bandwidth: 15 kHz
Slew Rate: 1V/μs
Fast Summing Amplifier
Power Bandwidth: 250 kHz
Small Signal Bandwiidth: 3.5 MHz
Slew Rate: 10V/μs
Bilateral Current Source
R3 = R4 + R5
R1 = R2
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Fast AC/DC Converter
Feedforward compensation can be used to make a fast full wave rectifier without a filter.
Instrumentation Amplifier
R1 = R4; R2 = R3
*,† Matching determines CMRR. Voltage Comparator for Driving RTL Logic or High Current
Integrator with Bias Current Compensation Driver
*Adjust for zero integrator drift. Current drift typically 0.1 nA/°C over
0°C to +70°C temperature range.
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Low Frequency Square Wave Generator
Voltage Comparator for Driving
Low Drift Sample and Hold DTL or TTL Integrated Circuits
*Polycarbonate-dielectric capacitor
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REVISION HISTORY SECTION
Date Revision Section Originator Changes
Released
01/05/06 A New Release to corporate format L. Lytle 1 MDS datasheets converted into one Corp.
datasheet format. MJLM101A-X Rev 1A0
datasheet will be archived.
03/20/13 A All - Changed layout of National Data Sheet to TI
format
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PACKAGE OPTION ADDENDUM
www.ti.com 11-Apr-2013
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish MSL Peak Temp
(3)
Op Temp (°C) Top-Side Markings
(4)
Samples
JL101ABCA ACTIVE CDIP J 14 25 TBD Call TI Call TI -55 to 125 JL101ABCA
JM38510/10103BCA Q
JL101ABGA ACTIVE TO-99 LMC 8 20 TBD Call TI Call TI -55 to 125 JL101ABGA
JM38510/10103BGA Q
ACO
JM38510/10103BGA Q
>T
JL101ABPA ACTIVE CDIP NAB 8 40 TBD Call TI Call TI -55 to 125 JL101ABPA Q
JM38510/
10103BPA ACO
10103BPA >T
JM38510/10103BCA ACTIVE CDIP J 14 25 TBD Call TI Call TI -55 to 125 JL101ABCA
JM38510/10103BCA Q
JM38510/10103BGA ACTIVE TO-99 LMC 8 20 TBD Call TI Call TI -55 to 125 JL101ABGA
JM38510/10103BGA Q
ACO
JM38510/10103BGA Q
>T
JM38510/10103BPA ACTIVE CDIP NAB 8 40 TBD Call TI Call TI -55 to 125 JL101ABPA Q
JM38510/
10103BPA ACO
10103BPA >T
M38510/10103BCA ACTIVE CDIP J 14 25 TBD Call TI Call TI -55 to 125 JL101ABCA
JM38510/10103BCA Q
M38510/10103BGA ACTIVE TO-99 LMC 8 20 TBD Call TI Call TI -55 to 125 JL101ABGA
JM38510/10103BGA Q
ACO
JM38510/10103BGA Q
>T
M38510/10103BPA ACTIVE CDIP NAB 8 40 TBD Call TI Call TI -55 to 125 JL101ABPA Q
JM38510/
10103BPA ACO
10103BPA >T
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
PACKAGE OPTION ADDENDUM
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Addendum-Page 2
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
MECHANICAL DATA
NAB0008A
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J08A (Rev M)
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