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PCA9554A
SCPS127E –SEPTEMBER 2006–REVISED JUNE 2014
PCA9554A Remote 8-Bit I
2
C and SMBus I/O Expander With Interrupt Output and
Configuration Registers
1 Features 2 Description
This 8-bit I/O expander for the two-line bidirectional
1• I2C to Parallel Port Expander bus (I2C) is designed for 2.3-V to 5.5-V VCC
• Open-Drain Active-Low Interrupt Output operation. It provides general-purpose remote I/O
• Operating Power-Supply Voltage Range of 2.3 V expansion for most microcontroller families via the I2C
to 5.5 V interface [serial clock (SCL), serial data (SDA)].
• 5-V Tolerant I/Os The PCA9554A consists of one 8-bit Configuration
• 400-kHz Fast I2C Bus (input or output selection), Input, Output, and Polarity
Inversion (active high or active low) registers. At
• Three Hardware Address Pins Allow up to Eight power on, the I/Os are configured as inputs with a
Devices on the I2C/SMBus weak pullup to VCC. However, the system master can
• Input/Output Configuration Register enable the I/Os as either inputs or outputs by writing
• Polarity Inversion Register to the I/O configuration bits. The data for each input
or output is kept in the corresponding Input or Output
• Internal Power-On Reset register. The polarity of the Input Port register can be
• Power-Up With All Channels Configured as Inputs inverted with the Polarity Inversion register. All
• No Glitch on Power Up registers can be read by the system master.
• Latched Outputs With High-Current Drive The system master can reset the PCA9554A in the
Maximum Capability for Directly Driving LEDs event of a timeout or other improper operation by
• Latch-Up Performance Exceeds 100 mA Per utilizing the power-on reset feature, which puts the
registers in their default state and initializes the
JESD 78, Class II I2C/SMBus state machine.
• ESD Protection Exceeds JESD 22 The PCA9554A open-drain interrupt (INT) output is
– 2000-V Human-Body Model (A114-A) activated when any input state differs from its
– 200-V Machine Model (A115-A) corresponding Input Port register state and is used to
– 1000-V Charged-Device Model (C101) indicate to the system master that an input state has
changed.
Device Information(1)
PART NUMBER PACKAGE BODY SIZE (NOM)
SSOP (16) 6.20 mm × 5.30 mm
PCA9554A VQFN (16) 4.00 mm × 4.00 mm
QFN (16) 3.00 mm × 3.00 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
PCA9554A
SCPS127E –SEPTEMBER 2006–REVISED JUNE 2014
www.ti.com
Table of Contents
1 Features.................................................................. 18 Detailed Description............................................ 13
8.1 Functional Block Diagram....................................... 13
2 Description............................................................. 18.2 Device Functional Modes........................................ 14
3 Revision History..................................................... 28.3 Programming........................................................... 15
4 Description (Continued)........................................ 39 Application And Implementation........................ 21
5 Pin Configuration And Functions ........................ 39.1 Typical Application ................................................. 21
6 Specifications......................................................... 410 Power Supply Recommendations ..................... 23
6.1 Absolute Maximum Ratings ..................................... 410.1 Power-On Reset Errata......................................... 23
6.2 Handling Ratings....................................................... 411 Device and Documentation Support................. 23
6.3 Recommended Operating Conditions....................... 411.1 Trademarks........................................................... 23
6.4 Electrical Characteristics........................................... 511.2 Electrostatic Discharge Caution............................ 23
6.5 I2C Interface Timing Requirements........................... 611.3 Glossary................................................................ 23
6.6 Switching Characteristics.......................................... 612 Mechanical, Packaging, and Orderable
6.7 Typical Characteristics.............................................. 7Information ........................................................... 23
7 Parameter Measurement Information ................ 10
3 Revision History
Changes from Revision D (August 2008) to Revision E Page
• Added Interrupt Errata section. ............................................................................................................................................ 15
• Added Power-On Reset Errata section. .............................................................................................................................. 23
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DB, DBQ, DGV, DW,
OR PW PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
A0
A1
A2
P0
P1
P2
P3
GND
VCC
SDA
SCL
INT
P7
P6
P5
P4
RGV PACKAGE
(TOP VIEW)
16
6 8
2
10 P7
P5
VCC
4
3
1
75
12
11
9
131415
SDA
A0
A1
P6
INT
SCL
P3
GND
P4
A2
P0
P1
P2
RGT PACKAGE
(TOP VIEW)
16
6 8
210 P7
P5 VCC
4
3
1
75
12
11
9
131415
SDA
A0
A1
P6
INT
SCL
P3
GND
P4
A2
P0
P1
P2
PCA9554A
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SCPS127E –SEPTEMBER 2006–REVISED JUNE 2014
4 Description (Continued)
INT can be connected to the interrupt input of a microcontroller. By sending an interrupt signal on this line, the
remote I/O can inform the microcontroller if there is incoming data on its ports without having to communicate via
the I2C bus. Thus, the PCA9554A can remain a simple slave device.
The device's outputs (latched) have high-current drive capability for directly driving LEDs and low current
consumption.
Three hardware pins (A0, A1, and A2) are used to program and vary the fixed I2C address and allow up to eight
devices to share the same I2C bus or SMBus.
The PCA9554A is pin-to-pin and I2C address compatible with the PCF8574A. However, software changes are
required, due to the enhancements in the PCA9554A over the PCF8574A.
The PCA9554A and PCA9554 are identical except for their fixed I2C address. This allows for up to 16 of these
devices (8 of each) on the same I2C/SMBus.
5 Pin Configuration And Functions
Pin Functions
PIN
QSOP (DBQ)
SOIC (DW), DESCRIPTION
QFN (RGT AND
NAME SSOP (DB), RGV)
TSSOP (PW), AND
TVSOP (DGV)
A0 1 15 Address input. Connect directly to VCC or ground.
A1 2 16 Address input. Connect directly to VCC or ground.
A2 3 1 Address input. Connect directly to VCC or ground.
P0 4 2 P-port input/output. Push-pull design structure.
P1 5 3 P-port input/output. Push-pull design structure.
P2 6 4 P-port input/output. Push-pull design structure.
P3 7 5 P-port input/output. Push-pull design structure.
GND 8 6 Ground
P4 9 7 P-port input/output. Push-pull design structure.
P5 10 8 P-port input/output. Push-pull design structure.
P6 11 9 P-port input/output. Push-pull design structure.
P7 12 10 P-port input/output. Push-pull design structure.
INT 13 11 Interrupt output. Connect to VCC through a pullup resistor.
SCL 14 12 Serial clock bus. Connect to VCC through a pullup resistor.
SDA 15 13 Serial data bus. Connect to VCC through a pullup resistor.
VCC 16 14 Supply voltage
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6 Specifications
6.1 Absolute Maximum Ratings(1)
over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT
VCC Supply voltage range –0.5 6 V
VIInput voltage range(2) –0.5 6 V
VOOutput voltage range(2) –0.5 6 V
IIK Input clamp current VI< 0 –20 mA
IOK Output clamp current VO< 0 –20 mA
IIOK Input/output clamp current VO< 0 or VO> VCC ±20 mA
IOL Continuous output low current VO= 0 to VCC 50 mA
IOH Continuous output high current VO= 0 to VCC –50 mA
Continuous current through GND –250
ICC mA
Continuous current through VCC 160
DB package 82
DBQ package 90
DGV package 120
θJA Package thermal impedance(3) DW package 57 °C/W
PW package 108
RGT package TBD
RGV package 51
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
(3) The package thermal impedance is calculated in accordance with JESD 51-7.
6.2 Handling Ratings MIN MAX UNIT
Tstg Storage temperature range –65 150 °C
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all 0 2000
pins(1)
V(ESD) Electrostatic discharge V
Charged device model (CDM), per JEDEC specification 0 1000
JESD22-C101, all pins(2)
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions MIN MAX UNIT
VCC Supply voltage 2.3 5.5 V
0.7 ×
SCL, SDA 5.5
VCC
VIH High-level input voltage V
A2–A0, P7–P0 2 5.5
SCL, SDA –0.5 0.3 × VCC
VIL Low-level input voltage V
A2–A0, P7–P0 –0.5 0.8
IOH High-level output current P7–P0 –10 mA
IOL Low-level output current P7–P0 25 mA
TAOperating free-air temperature –40 85 °C
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SCPS127E –SEPTEMBER 2006–REVISED JUNE 2014
6.4 Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC MIN TYP(1) MAX UNIT
VIK Input diode clamp voltage II= –18 mA 2.3 V to 5.5 V –1.2 V
VPOR Power-on reset voltage VI= VCC or GND, IO= 0 VPOR 1.5 1.65 V
2.3 V 1.8
3 V 2.6
IOH = –8 mA 4.5 V 3.1
4.75 V 4.1
VOH P-port high-level output voltage(2) V
2.3 V 1.7
3 V 2.5
IOH = –10 mA 4.5 V 3
4.75 V 4
SDA VOL = 0.4 V 2.3 V to 5.5 V 3 8
2.3 V 8 10
3 V 8 14
VOL = 0.5 V 4.5 V 8 17
4.75 V 8 35
IOL P port(3) mA
2.3 V 10 13
3 V 10 19
VOL = 0.7 V 4.5 V 10 24
4.75 V 10 45
INT VOL = 0.4 V 2.3 V to 5.5 V 3 10
SCL, SDA ±1
IIVI= VCC or GND 2.3 V to 5.5 V μA
A2–A0 ±1
IIH P port VI= VCC 2.3 V to 5.5 V 1 μA
IIL P port VI= GND 2.3 V to 5.5 V –100 μA
5.5 V 104 175
VI= VCC, IO= 0, I/O = inputs, 3.6 V 50 90
fscl = 400 kHz, No load 2.7 V 20 65
Operating mode 5.5 V 60 150
VI= VCC, IO= 0, I/O = inputs, 3.6 V 15 40
fscl = 100 kHz, No load 2.7 V 8 20
ICC μA
5.5 V 450 700
VI= GND, IO= 0, I/O = inputs, 3.6 V 300 600
fscl = 0 kHz, No load 2.7 V 225 500
Standby mode 5.5 V 0.25 1
VI= VCC, IO= 0, I/O = inputs, 3.6 V 0.2 0.9
fscl = 0 kHz, No load 2.7 V 0.1 0.8
One input at VCC – 0.6 V, 2.3 V to 5.5 V 1.5
Other inputs at VCC or GND
Additional current in standby
ΔICC mA
mode Every LED I/O at VI= 4.3 V; 5.5 V 1
fscl = 0 kHz
CISCL VI= VCC or GND 2.3 V to 5.5 V 4 5 pF
SDA 5.5 6.5
Cio VIO = VCC or GND 2.3 V to 5.5 V pF
P port 8 9.5
(1) All typical values are at nominal supply voltage (2.5-V, 3.3-V, or 5-V VCC) and TA= 25°C.
(2) The total current sourced by all I/Os must be limited to 85 mA.
(3) Each I/O must be externally limited to a maximum of 25 mA, and the P port (P0 to P7) must be limited to a maximum current of 200 mA.
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6.5 I2C Interface Timing Requirements
over operating free-air temperature range (unless otherwise noted) (see Figure 14)
STANDARD MODE FAST MODE
I2C BUS I2C BUS UNIT
MIN MAX MIN MAX
fscl I2C clock frequency 0 100 0 400 kHz
tsch I2C clock high time 4 0.6 μs
tscl I2C clock low time 4.7 1.3 μs
tsp I2C spike time 50 50 ns
tsds I2C serial-data setup time 250 100 ns
tsdh I2C serial-data hold time 0 0 ns
ticr I2C input rise time 1000 20 + 0.1Cb(1) 300 ns
ticf I2C input fall time 300 20 + 0.1Cb(1) 300 ns
tocf I2C output fall time 10-pF to 400-pF bus 300 20 + 0.1Cb(1) 300 ns
tbuf I2C bus free time between Stop and Start 4.7 1.3 μs
tsts I2C Start or repeated Start condition setup 4.7 0.6 μs
tsth I2C Start or repeated Start condition hold 4 0.6 μs
tsps I2C Stop condition setup 4 0.6 μs
tvd(data) Valid data time SCL low to SDA output valid 300 50 ns
ACK signal from SCL low to
tvd(ack) Valid data time of ACK condition 0.3 3.45 0.1 0.9 μs
SDA (out) low
CbI2C bus capacitive load 400 400 ns
(1) Cb= Total capacitive load of one bus in pF
6.6 Switching Characteristics
over operating free-air temperature range (unless otherwise noted) (see Figure 15 and Figure 16)
STANDARD MODE FAST MODE
FROM TO I2C BUS I2C BUS
PARAMETER UNIT
(INPUT) (OUTPUT) MIN MAX MIN MAX
tiv Interrupt valid time P port INT 4 4 μs
tir Interrupt reset delay time SCL INT 4 4 μs
tpv Output data valid SCL P7–P0 200 200 ns
tps Input data setup time P port SCL 100 100 ns
tph Input data hold time P port SCL 1 1 μs
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0
25
50
75
100
125
150
175
200
225
250
275
300
-40 -15 10 35 60 85
TA– Free-Air Temperature – °C
VOL – Output Low Voltage – mV
VCC = 5 V, ISINK = 10 mA
VCC = 2.5 V, ISINK = 10 mA
VCC = 2.5 V, ISINK = 1 mA
VCC = 5 V, ISINK = 1 mA
0
5
10
15
20
25
30
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7
VOL – Output Low Voltage – V
ISINK – I/O Sink Current – mA
TA= –40°C
VCC = 2.5 V
TA= 25°C
TA= 85°C
0
10
20
30
40
50
60
70
2.3 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5
VCC – Supply Voltage – V
ICC – Supply Current – µA
fSCL = 400 kHz
I/Os unloaded
0
50
100
150
200
250
300
350
400
450
500
550
600
0 1 2 3 4 5 6 7 8
Number of I/Os Held Low
ICC – Supply Current – µA
TA= –40°C
VCC = 5 V
TA= 25°C
TA= 85°C
0
5
10
15
20
25
30
35
40
45
50
55
-40 -15 10 35 60 85
TA– Free-Air Temperature – °C
ICC – Supply Current – µA
VCC = 2.5 V
VCC = 3.3 V
VCC = 5 V
fSCL = 400 kHz
I/Os unloaded
0
5
10
15
20
25
30
35
-40 -15 10 35 60 85
TA– Free-Air Temperature – °C
ICC – Supply Current – nA
VCC = 2.5 V
VCC = 3.3 V
VCC = 5 V
SCL = VCC
PCA9554A
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SCPS127E –SEPTEMBER 2006–REVISED JUNE 2014
6.7 Typical Characteristics
Figure 1. Supply Current vs Temperature Figure 2. Quiescent Supply Current vs Temperature
Figure 4. Supply Current vs Number Of I/Os Held Low
Figure 3. Supply Current vs Supply Voltage
Figure 6. I/O Sink Current vs Output Low Voltage
Figure 5. I/O Output Low Voltage vs Temperature
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0
5
10
15
20
25
30
35
40
45
50
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7
(VCC – VOH) – Output High Voltage – V
ISOURCE – I/O Source Current – mA
TA= –40°C
VCC = 3.3 V
TA= 25°C
TA= 85°C
0
5
10
15
20
25
30
35
40
45
50
55
60
65
70
75
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7
(VCC – VOH) – Output High Voltage – V
ISOURCE – I/O Source Current – mA
TA= –40°C
VCC = 5 V
TA= 25°C
TA= 85°C
0
25
50
75
100
125
150
175
200
225
250
275
-40 -15 10 35 60 85
TA– Free-Air Temperature – °C
(VCC – VOH) – Output High Voltage – mV
VCC = 5 V, IOL = 10 mA
VCC = 2.5 V, IOL = 10 mA
VCC = 5 V, IOL = 1 mA
VCC = 2.5 V, IOL = 1 mA
0
5
10
15
20
25
30
35
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7
(VCC – VOH) – Output High Voltage – V
ISOURCE – I/O Source Current – mA
TA= –40°C
VCC = 2.5 V
TA= 25°C
TA= 85°C
0
5
10
15
20
25
30
35
40
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7
VOL – Output Low Voltage – V
ISINK – I/O Sink Current – mA
TA= –40°C
VCC = 3.3 V
TA= 25°C
TA= 85°C
0
5
10
15
20
25
30
35
40
45
50
55
60
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7
VOL – Output Low Voltage – V
ISINK – I/O Sink Current – mA
TA= –40°C
VCC = 5 V
TA= 25°C
TA= 85°C
PCA9554A
SCPS127E –SEPTEMBER 2006–REVISED JUNE 2014
www.ti.com
Typical Characteristics (continued)
Figure 7. I/O Sink Current vs Output Low Voltage Figure 8. I/O Sink Current vs Output Low Voltage
Figure 10. I/O Source Current vs Output High Voltage
Figure 9. I/O Output High Voltage vs Temperature
Figure 11. I/O Source Current vs Output High Voltage Figure 12. I/O Source Current vs Output High Voltage
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0
1
2
3
4
5
6
2.3 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5
VCC – Supply Voltage – V
VOH – Output High Voltage – V
IOH = –10 mA
IOH = –8 mA
TA= 25°C
PCA9554A
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SCPS127E –SEPTEMBER 2006–REVISED JUNE 2014
Typical Characteristics (continued)
Figure 13. Output High Voltage vs Supply Voltage
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RL = 1 kΩ
VCC
CL = 50 pF
(see Note A)
tbuf
ticr
tsth tsds
tsdh
ticf
ticr
tscl tsch
tsts
tPHL
tPLH
0.3 × VCC
Stop
Condition
tsps
Repeat
Start
Condition
Start or
Repeat
Start
Condition
SCL
SDA
Start
Condition
(S)
Address
Bit 7
(MSB)
Data
Bit 10
(LSB)
Stop
Condition
(P)
Three Bytes for Complete
Device Programming
SDA LOAD CONFIGURATION
VOLTAGE WAVEFORMS
ticf
Stop
Condition
(P)
tsp
DUT SDA
0.7 × VCC
0.3 × VCC
0.7 × VCC
R/W
Bit 0
(LSB)
ACK
(A)
Data
Bit 07
(MSB)
Address
Bit 1
Address
Bit 6
BYTE DESCRIPTION
1 I2C address
2, 3 P-port data
PCA9554A
SCPS127E –SEPTEMBER 2006–REVISED JUNE 2014
www.ti.com
7 Parameter Measurement Information
A. CLincludes probe and jig capacitance.
B. All inputs are supplied by generators having the following characteristics: PRR ≤10 MHz, ZO= 50 Ω, tr/tf≤30 ns.
C. All parameters and waveforms are not applicable to all devices.
Figure 14. I2C Interface Load Circuit And Voltage Waveforms
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Product Folder Links: PCA9554A
A
A
A
A
S 0 1 1 1 A1A2 A0 1 Data 1 1 PData 2
Start
Condition 8 Bits
(One Data Bytes)
From Port Data From PortSlave Address R/W
87654321
tir
tir
tsps
tiv
Address Data 1 Data 2
INT
Data
Into
Port
B
B
A
A
PnINT
R/W A
tir
0.7 × VCC
0.3 × VCC
0.7 × VCC
0.3 × VCC
0.7 × VCC
0.3 × VCC
0.7 × VCC
0.3 × VCC
INT SCL
View B−BView A−A
tiv
RL = 4.7 kΩ
VCC
CL = 100 pF
(see Note A)
INTERRUPT LOAD CONFIGURATION
DUT INT
ACK
From Slave ACK
From Slave
1.5 V
PCA9554A
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SCPS127E –SEPTEMBER 2006–REVISED JUNE 2014
Parameter Measurement Information (continued)
A. CLincludes probe and jig capacitance.
B. All inputs are supplied by generators having the following characteristics: PRR ≤10 MHz, ZO= 50 Ω, tr/tf≤30 ns.
C. All parameters and waveforms are not applicable to all devices.
Figure 15. Interrupt Load Circuit And Voltage Waveforms
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P0 A 0.7 × VCC
0.3 × VCC
SCL P7
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
tpv
(see Note B)
Slave
ACK
Unstable
Data
Last Stable Bit
SDA
Pn
Pn
WRITE MODE (R/W = 0)
P0 A 0.7 × VCC
0.3 × VCC
SCL P7
0.7 × VCC
0.3 × VCC
tps tph
READ MODE (R/W = 1)
P-PORT LOAD CONFIGURATION
DUT
CL = 50 pF
(see Note A)
Pn 2 × VCC
500 W
500 W
1.5 V
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Parameter Measurement Information (continued)
A. CLincludes probe and jig capacitance.
B. tpv is measured from 0.7 × VCC on SCL to 50% I/O pin output.
C. All inputs are supplied by generators having the following characteristics: PRR ≤10 MHz, ZO= 50 Ω, tr/tf≤30 ns.
D. The outputs are measured one at a time, with one transition per measurement.
E. All parameters and waveforms are not applicable to all devices.
Figure 16. P-Port Load Circuit And Voltage Waveforms
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14
I/O
Port
Shift
Register 8 Bits
LP Filter
Interrupt
Logic
Input
Filter
15
Power-On
Reset Read Pulse
Write Pulse
2
1
13
16
8
GND
VCC
SDA
SCL
A1
A0
INT
I2C Bus
Control
P7−P0
3
A2
PCA9554A
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SCPS127E –SEPTEMBER 2006–REVISED JUNE 2014
8 Detailed Description
8.1 Functional Block Diagram
A. Pin numbers shown are for the DB, DBQ, DGV, DW, or PW package.
B. All I/Os are set to inputs at reset.
Figure 17. Logic Diagram
Copyright © 2006–2014, Texas Instruments Incorporated Submit Documentation Feedback 13
Product Folder Links: PCA9554A
Data From
Shift Register
Data From
Shift Register
Write Configuration
Pulse
Write Pulse
Read Pulse
Write Polarity
Pulse
Data From
Shift Register
Output Port
Register
Configuration
Register
Input Port
Register
Polarity
Inversion
Register
Polarity
Register Data
Input Port
Register Data
GND
P0 to P7
VCC
Output Port
Register Data
Q1
Q2
D
CK
FF
Q
Q
D
CK
FF
Q
Q
D
CK
FF
Q
Q
D
CK
FF
Q
Q
INT
100 kW
PCA9554A
SCPS127E –SEPTEMBER 2006–REVISED JUNE 2014
www.ti.com
Functional Block Diagram (continued)
A. At power-on reset, all registers return to default values.
Figure 18. Simplified Schematic Of P0 To P7
8.2 Device Functional Modes
8.2.1 Power-On Reset
When power (from 0 V) is applied to VCC, an internal power-on reset holds the PCA9554A in a reset condition
until VCC has reached VPOR. At that point, the reset condition is released and the PCA9554A registers and
I2C/SMBus state machine will initialize to their default states. After that, VCC must be lowered to below 0.2 V and
then back up to the operating voltage for a power-reset cycle.
Refer to the Power-On Reset Errata section.
8.2.2 I/O Port
When an I/O is configured as an input, FETs Q1 and Q2 (in Figure 18) are off, which creates a high impedance
input with a weak pullup (100 kΩtyp) to VCC. The input voltage may be raised above VCC to a maximum of 5.5 V.
If the I/O is configured as an output, Q1 or Q2 is enabled, depending on the state of the output port register. In
this case, there are low impedance paths between the I/O pin and either VCC or GND. The external voltage
applied to this I/O pin should not exceed the recommended levels for proper operation.
8.2.3 Interrupt Output (INT)
An interrupt is generated by any rising or falling edge of the port inputs in the input mode. After time, tiv, the
signal INT is valid. Resetting the interrupt circuit is achieved when data on the port is changed to the original
setting, data is read from the port that generated the interrupt. Resetting occurs in the read mode at the
acknowledge (ACK) or not acknowledge (NACK) bit after the rising edge of the SCL signal.
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Device Functional Modes (continued)
Interrupts that occur during the ACK or NACK clock pulse can be lost (or be very short) due to the resetting of
the interrupt during this pulse. Each change of the I/Os after resetting is detected and is transmitted as INT.
Writing to another device does not affect the interrupt circuit, and a pin configured as an output cannot cause an
interrupt. Changing an I/O from an output to an input may cause a false interrupt to occur, if the state of the pin
does not match the contents of the Input Port register. Because each 8-pin port is read independently, the
interrupt caused by port 0 is not cleared by a read of port 1 or vice versa.
The INT output has an open-drain structure and requires pull-up resistor to VCC.
8.2.3.1 Interrupt Errata
Description
The INT will be improperly de-asserted if the following two conditions occur:
1. The last I2C command byte (register pointer) written to the device was 00h.
NOTE
This generally means the last operation with the device was a Read of the input
register. However, the command byte may have been written with 00h without ever
going on to read the input register. After reading from the device, if no other command
byte written, it will remain 00h.
2. Any other slave device on the I2C bus acknowledges an address byte with the R/W bit set high
System Impact
Can cause improper interrupt handling as the Master will see the interrupt as being cleared.
System Workaround
Minor software change: User must change command byte to something besides 00h after a Read operation to
the PCA9554A device or before reading from another slave device.
NOTE
Software change will be compatible with other versions (competition and TI redesigns) of
this device.
8.3 Programming
8.3.1 I2C Interface
The bidirectional I2C bus consists of the serial clock (SCL) and serial data (SDA) lines. Both lines must be
connected to a positive supply through a pullup resistor when connected to the output stages of a device. Data
transfer may be initiated only when the bus is not busy.
I2C communication with this device is initiated by a master sending a Start condition, a high-to-low transition on
the SDA input/output while the SCL input is high (see Figure 19). After the Start condition, the device address
byte is sent, most significant bit (MSB) first, including the data direction bit (R/W).
After receiving the valid address byte, this device responds with an acknowledge (ACK), a low on the SDA
input/output during the high of the ACK-related clock pulse. The address inputs (A0–A2) of the slave device must
not be changed between the Start and Stop conditions.
On the I2C bus, only one data bit is transferred during each clock pulse. The data on the SDA line must remain
stable during the high pulse of the clock period, as changes in the data line at this time are interpreted as control
commands (Start or Stop) (see Figure 20).
A Stop condition, a low-to-high transition on the SDA input/output while the SCL input is high, is sent by the
master (see Figure 19).
Copyright © 2006–2014, Texas Instruments Incorporated Submit Documentation Feedback 15
Product Folder Links: PCA9554A
Data Output
by Transmitter
SCL From
Master
Start
Condition
S
1 2 8 9
Data Output
by Receiver
Clock Pulse for
Acknowledgment
NACK
ACK
SDA
SCL
Data Line
Stable;
Data Valid
Change
of Data
Allowed
SDA
SCL
Start Condition
S
Stop Condition
P
PCA9554A
SCPS127E –SEPTEMBER 2006–REVISED JUNE 2014
www.ti.com
Programming (continued)
Any number of data bytes can be transferred from the transmitter to receiver between the Start and Stop
conditions. Each byte of eight bits is followed by one ACK bit. The transmitter must release the SDA line before
the receiver can send an ACK bit. The device that acknowledges must pull down the SDA line during the ACK
clock pulse so that the SDA line is stable low during the high pulse of the ACK-related clock period (see
Figure 21). When a slave receiver is addressed, it must generate an ACK after each byte is received. Similarly,
the master must generate an ACK after each byte that it receives from the slave transmitter. Setup and hold
times must be met to ensure proper operation.
A master receiver will signal an end of data to the slave transmitter by not generating an acknowledge (NACK)
after the last byte has been clocked out of the slave. This is done by the master receiver by holding the SDA line
high. In this event, the transmitter must release the data line to enable the master to generate a Stop condition.
Figure 19. Definition Of Start And Stop Conditions
Figure 20. Bit Transfer
Figure 21. Acknowledgment On The I2C Bus
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Product Folder Links: PCA9554A
0 0 0 0 B1 B000
0 1 1 1A1A2 A0
Slave Address
R/W
Fixed Hardware
Selectable
PCA9554A
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SCPS127E –SEPTEMBER 2006–REVISED JUNE 2014
Programming (continued)
8.3.2 Register Map
Table 1. Interface Definition
BIT
BYTE 7 (MSB) 6 5 4 3 2 1 0 (LSB)
I2C slave address L H H H A2 A1 A0 R/W
Px I/O data bus P7 P6 P5 P4 P3 P2 P1 P0
8.3.2.1 Device Address
Figure 22 shows the address byte for the PCA9554A.
Figure 22. Pca9554a Address
Table 2. Address Reference
INPUTS I2C BUS SLAVE ADDRESS
A2 A1 A0
L L L 56 (decimal), 38 (hexadecimal)
L L H 57 (decimal), 39 (hexadecimal)
L H L 58 (decimal), 3A (hexadecimal)
L H H 59 (decimal), 3B (hexadecimal)
H L L 60 (decimal), 3C (hexadecimal)
H L H 61 (decimal), 3D (hexadecimal)
H H L 62 (decimal), 3E (hexadecimal)
H H H 63 (decimal), 3F (hexadecimal)
The last bit of the slave address defines the operation (read or write) to be performed. When it is high (1), a read
is selected. A low (0) selects a write operation.
8.3.2.2 Control Register And Command Byte
Following the successful acknowledgment of the address byte, the bus master sends a command byte that is
stored in the control register in the PCA9554A. Two bits of this command byte state the operation (read or write)
and the internal register (input, output, polarity inversion or configuration) that will be affected. This register can
be written or read through the I2C bus. The command byte is sent only during a write transmission.
Once a command byte has been sent, the register that was addressed continues to be accessed by reads until a
new command byte has been sent.
Figure 23. Control Register Bits
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Table 3. Command Byte
CONTROL REGISTER BITS COMMAND BYTE POWER-UP
REGISTER PROTOCOL
(HEX) DEFAULT
B1 B0
0 0 0x00 Input Port Read byte XXXX XXXX
0 1 0x01 Output Port Read/write byte 1111 1111
1 0 0x02 Polarity Inversion Read/write byte 0000 0000
1 1 0x03 Configuration Read/write byte 1111 1111
8.3.2.3 Register Descriptions
The Input Port register (register 0) reflects the incoming logic levels of the pins, regardless of whether the pin is
defined as an input or an output by the Configuration register. It only acts on read operation. Writes to these
registers have no effect. The default value, X, is determined by the externally applied logic level.
Before a read operation, a write transmission is sent with the command byte to let the I2C device know that the
Input Port register will be accessed next.
Table 4. Register 0 (Input Port Register)
BIT I7 I6 I5 I4 I3 I2 I1 I0
DEFAULT XXXXXXXX
The Output Port register (register 1) shows the outgoing logic levels of the pins defined as outputs by the
Configuration register. Bit values in this register have no effect on pins defined as inputs. In turn, reads from this
register reflect the value that is in the flip-flop controlling the output selection, not the actual pin value.
Table 5. Register 1 (Output Port Register)
BIT O7 O6 O5 O4 O3 O2 O1 O0
DEFAULT 11111111
The Polarity Inversion register (register 2) allows polarity inversion of pins defined as inputs by the Configuration
register. If a bit in this register is set (written with 1), the corresponding port pin polarity is inverted. If a bit in this
register is cleared (written with a 0), the corresponding port pin original polarity is retained.
Table 6. Register 2 (Polarity Inversion Register)
BIT N7 N6 N5 N4 N3 N2 N1 N0
DEFAULT 00000000
The Configuration register (register 3) configures the directions of the I/O pins. If a bit in this register is set to 1,
the corresponding port pin is enabled as an input with high impedance output driver. If a bit in this register is
cleared to 0, the corresponding port pin is enabled as an output.
Table 7. Register 3 (Configuration Register)
BIT C7 C6 C5 C4 C3 C2 C1 C0
DEFAULT 11111111
8.3.2.4 Bus Transactions
Data is exchanged between the master and PCA9554A through write and read commands.
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SCL
SDA
Data to
Register
Start Condition R/W ACK From Slave ACK From Slave ACK From Slave
1 98765432
Data1/0A20 1S 11 A1 A0 0 A 1000000 A A P
Data to RegisterCommand ByteSlave Address
SCL
Start Condition
Data 1 Valid
SDA
Write to Port
Data Out
From Port
R/W ACK From Slave ACK From Slave ACK From Slave
1 98765432
Data 1
1A20 1S 11 A1 A0 0 A 0000000 A A P
tpv
Data to PortCommand ByteSlave Address
PCA9554A
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SCPS127E –SEPTEMBER 2006–REVISED JUNE 2014
8.3.2.4.1 Writes
Data is transmitted to the PCA9554A by sending the device address and setting the least-significant bit to a logic
0 (see Figure 22 for device address). The command byte is sent after the address and determines which register
receives the data that follows the command byte (see Figure 24 and Figure 25). There is no limitation on the
number of data bytes sent in one write transmission.
Figure 24. Write To Output Port Register
<br/>
Figure 25. Write To Configuration Or Polarity Inversion Registers
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Product Folder Links: PCA9554A
SCL
SDA
INT
Start
Condition
R/W
Read From
Port
Data Into
Port
Stop
Condition
ACK From
Master
NACK From
Master
ACK From
Slave
Data From Port
Slave Address Data From Port
1 98765432
A2
01S 11 A1 A0 1AData 1 Data 4
A NA P
Data 2 Data 3 Data 4
tiv
tph tps
tir
Data 5
A20 1S 11 A1 A0 0 A A
Data From Register
Slave Address
Slave Address
R/W
ACK From
Slave
Command Byte
ACK From
Slave
S A20 1 11 A1 A0
R/W
1 A Data A
ACK From
Master
Data
Data From Register NACK From
Master
NA P
Last Byte
ACK From
Slave
PCA9554A
SCPS127E –SEPTEMBER 2006–REVISED JUNE 2014
www.ti.com
8.3.2.4.2 Reads
The bus master first must send the PCA9554A address with the least significant bit (LSB) set to a logic 0 (see
Figure 22 for device address). The command byte is sent after the address and determines which register is
accessed. After a restart, the device address is sent again, but this time the LSB is set to a logic 1. Data from the
register defined by the command byte then is sent by the PCA9554A (see Figure 26 and Figure 27). After a
restart, the value of the register defined by the command byte matches the register being accessed when the
restart occurred. Data is clocked into the register on the rising edge of the ACK clock pulse. There is no limitation
on the number of data bytes received in one read transmission, but when the final byte is received, the bus
master must not acknowledge the data.
Figure 26. Read From Register
<br/>
A. This figure assumes the command byte has previously been programmed with 00h.
B. Transfer of data can be stopped at any moment by a Stop condition.
C. This figure eliminates the command byte transfer, a restart, and slave address call between the initial slave address
call and actual data transfer from the P port. See Figure 26 for these details.
Figure 27. Read From Input Port Register
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Product Folder Links: PCA9554A
A2
A1
SDA
SCL
INT
GND
P6
P0
P1
P2
P3
P4
P5
P7
INT
GND
VCC
VCC
(5 V) VCC 10 kW10 kW10 kW2 kW
Master
Controller
PCA9554A
INT
RESET
Subsystem 2
(e.g., Counter)
Subsystem 3
(e.g., Alarm System)
ALARM
Controlled Device
(e.g., CBT Device)
ENABLE
A
B
VCC
Subsystem 1
(e.g., Temperature Sensor)
SDA
SCL
A0
PCA9554A
www.ti.com
SCPS127E –SEPTEMBER 2006–REVISED JUNE 2014
9 Application And Implementation
9.1 Typical Application
Figure 28 shows an application in which the PCA9554A can be used.
A. Device address is configured as 0111000 for this example.
B. P0, P2, and P3 are configured as outputs.
C. P1, P4, and P5 are configured as inputs.
D. P6 and P7 are not used and have internal 100-kΩpullup resistors to protect them from floating.
Figure 28. Typical Application
Copyright © 2006–2014, Texas Instruments Incorporated Submit Documentation Feedback 21
Product Folder Links: PCA9554A
LED
3.3 V 5 V
LEDx
VCC
LED
LEDx
VCC
100 kW
VCC
PCA9554A
SCPS127E –SEPTEMBER 2006–REVISED JUNE 2014
www.ti.com
Typical Application (continued)
9.1.1 Detailed Design Procedure
9.1.1.1 Minimizing ICC When I/Os Control Leds
When the I/Os are used to control LEDs, they are normally connected to VCC through a resistor as shown in
Figure 28. Because the LED acts as a diode, when the LED is off, the I/O VIN is about 1.2 V less than VCC. The
supply current, ICC, increases as VIN becomes lower than VCC and is specified as ΔICC in Electrical
Characteristics.
For battery-powered applications, it is essential that the voltage of I/O pins is greater than or equal to VCC when
the LED is off to minimize current consumption. Figure 29 shows a high-value resistor in parallel with the LED.
Figure 30 shows VCC less than the LED supply voltage by at least 1.2 V. Both of these methods maintain the I/O
VIN at or above VCC and prevents additional supply-current consumption when the LED is off.
Figure 29. High-Value Resistor In Parallel With The Led
Figure 30. Device Supplied By A Lower Voltage
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SCPS127E –SEPTEMBER 2006–REVISED JUNE 2014
10 Power Supply Recommendations
10.1 Power-On Reset Errata
A power-on reset condition can be missed if the VCC ramps are outside specification listed below.
System Impact
If ramp conditions are outside timing allowances above, POR condition can be missed, causing the device to lock
up.
11 Device and Documentation Support
11.1 Trademarks
All trademarks are the property of their respective owners.
11.2 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.3 Glossary
SLYZ022 —TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2006–2014, Texas Instruments Incorporated Submit Documentation Feedback 23
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PACKAGE OPTION ADDENDUM
www.ti.com 24-Aug-2018
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
PCA9554ADB ACTIVE SSOP DB 16 80 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 PD554A
PCA9554ADBQR NRND SSOP DBQ 16 TBD Call TI Call TI -40 to 85
PCA9554ADBR ACTIVE SSOP DB 16 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 PD554A
PCA9554ADGV NRND TVSOP DGV 16 TBD Call TI Call TI -40 to 85
PCA9554ADGVR ACTIVE TVSOP DGV 16 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 PD554A
PCA9554ADW ACTIVE SOIC DW 16 40 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 PCA9554A
PCA9554ADWR ACTIVE SOIC DW 16 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 PCA9554A
PCA9554APW NRND TSSOP PW 16 90 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 PD554A
PCA9554APWR NRND TSSOP PW 16 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 PD554A
PCA9554APWRG4 NRND TSSOP PW 16 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 PD554A
PCA9554ARGTR ACTIVE VQFN RGT 16 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 ZVH
PCA9554ARGVR ACTIVE VQFN RGV 16 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 PD554A
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
PACKAGE OPTION ADDENDUM
www.ti.com 24-Aug-2018
Addendum-Page 2
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
PCA9554ADBR SSOP DB 16 2000 330.0 16.4 8.2 6.6 2.5 12.0 16.0 Q1
PCA9554ADGVR TVSOP DGV 16 2000 330.0 12.4 6.8 4.0 1.6 8.0 12.0 Q1
PCA9554ADWR SOIC DW 16 2000 330.0 16.4 10.75 10.7 2.7 12.0 16.0 Q1
PCA9554APWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
PCA9554ARGTR VQFN RGT 16 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2
PCA9554ARGVR VQFN RGV 16 2500 330.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2
PACKAGE MATERIALS INFORMATION
www.ti.com 11-Aug-2017
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
PCA9554ADBR SSOP DB 16 2000 367.0 367.0 38.0
PCA9554ADGVR TVSOP DGV 16 2000 367.0 367.0 35.0
PCA9554ADWR SOIC DW 16 2000 367.0 367.0 38.0
PCA9554APWR TSSOP PW 16 2000 367.0 367.0 35.0
PCA9554ARGTR VQFN RGT 16 3000 367.0 367.0 35.0
PCA9554ARGVR VQFN RGV 16 2500 367.0 367.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 11-Aug-2017
Pack Materials-Page 2
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE
4040065 /E 12/01
28 PINS SHOWN
Gage Plane
8,20
7,40
0,55
0,95
0,25
38
12,90
12,30
28
10,50
24
8,50
Seating Plane
9,907,90
30
10,50
9,90
0,38
5,60
5,00
15
0,22
14
A
28
1
2016
6,50
6,50
14
0,05 MIN
5,905,90
DIM
A MAX
A MIN
PINS **
2,00 MAX
6,90
7,50
0,65 M
0,15
0°–ā8°
0,10
0,09
0,25
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150
GENERIC PACKAGE VIEW
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
DW 16 SOIC - 2.65 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
4040000-2/H
www.ti.com
PACKAGE OUTLINE
C
TYP
10.63
9.97
2.65 MAX
14X 1.27
16X 0.51
0.31
2X
8.89
TYP
0.33
0.10
0 - 8 0.3
0.1
(1.4)
0.25
GAGE PLANE
1.27
0.40
A
NOTE 3
10.5
10.1
BNOTE 4
7.6
7.4
4220721/A 07/2016
SOIC - 2.65 mm max heightDW0016A
SOIC
NOTES:
1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm, per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm, per side.
5. Reference JEDEC registration MS-013.
116
0.25 C A B
9
8
PIN 1 ID
AREA
SEATING PLANE
0.1 C
SEE DETAIL A
DETAIL A
TYPICAL
SCALE 1.500
www.ti.com
EXAMPLE BOARD LAYOUT
0.07 MAX
ALL AROUND 0.07 MIN
ALL AROUND
(9.3)
14X (1.27)
R0.05 TYP
16X (2)
16X (0.6)
4220721/A 07/2016
SOIC - 2.65 mm max heightDW0016A
SOIC
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
METAL SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
OPENING
SOLDER MASK METAL
SOLDER MASK
DEFINED
LAND PATTERN EXAMPLE
SCALE:7X
SYMM
1
89
16
SEE
DETAILS
SYMM
www.ti.com
EXAMPLE STENCIL DESIGN
R0.05 TYP
16X (2)
16X (0.6)
14X (1.27)
(9.3)
4220721/A 07/2016
SOIC - 2.65 mm max heightDW0016A
SOIC
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:7X
SYMM
SYMM
1
89
16
www.ti.com
PACKAGE OUTLINE
C
16X 0.30
0.18
1.45 0.1
16X 0.5
0.3
1 MAX
(0.2) TYP
0.05
0.00
12X 0.5
4X
1.5
A3.1
2.9 B
3.1
2.9
VQFN - 1 mm max heightRGT0016A
PLASTIC QUAD FLATPACK - NO LEAD
4219032/A 02/2017
PIN 1 INDEX AREA
0.08
SEATING PLANE
1
49
12
58
16 13
(OPTIONAL)
PIN 1 ID 0.1 C A B
0.05
EXPOSED
THERMAL PAD
SYMM
SYMM
17
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
4. Reference JEDEC registration MO-220
SCALE 3.600
www.ti.com
EXAMPLE BOARD LAYOUT
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
16X (0.24)
16X (0.6)
( 0.2) TYP
VIA
12X (0.5)
(2.8)
(2.8)
(0.475)
TYP
( 1.45)
(R0.05)
ALL PAD CORNERS (0.475) TYP
VQFN - 1 mm max heightRGT0016A
PLASTIC QUAD FLATPACK - NO LEAD
4219032/A 02/2017
SYMM
1
4
58
9
12
13
16
SYMM
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:20X
17
NOTES: (continued)
5. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
6. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
DEFINED
EXPOSED METAL
METAL
SOLDER MASK
OPENING
SOLDER MASK DETAILS
NON SOLDER MASK
DEFINED
(PREFERRED)
EXPOSED METAL
www.ti.com
EXAMPLE STENCIL DESIGN
16X (0.6)
16X (0.24)
12X (0.5)
(2.8)
(2.8)
( 1.34)
(R0.05) TYP
VQFN - 1 mm max heightRGT0016A
PLASTIC QUAD FLATPACK - NO LEAD
4219032/A 02/2017
NOTES: (continued)
7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
SYMM
ALL AROUND
METAL
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 17:
86% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:25X
SYMM
1
4
58
9
12
13
16
17
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