SLOS051E - OCTOBER 1987 - REVISED AUGUST 2008 D Trimmed Offset Voltage: D D D D, JG, P OR PW PACKAGE (TOP VIEW) 8 2 7 3 6 4 5 D D D D DISTRIBUTION OF TLC27M7 INPUT OFFSET VOLTAGE FK PACKAGE (TOP VIEW) VCC 2OUT 2IN - 2IN + NC 1IN - NC 1IN + NC 4 3 2 1 20 19 18 5 17 6 16 7 15 8 14 9 10 11 12 13 IIIIIIIIIII IIIIIIIIIII 30 NC 1OUT NC VDD NC 1 D NC 2OUT NC 2IN - NC 25 340 Units Tested From 2 Wafer Lots VDD = 5 V TA = 25C P Package 20 15 10 5 NC GND NC 2IN + NC 1OUT 1IN - 1IN + GND D f = 1 kHz Low Power . . . Typically 2.1 mW at 25C, VDD = 5 V Output Voltage Range Includes Negative Rail High Input impedance . . . 1012 Typ ESD-Protection Circuitry Small-Outline Package Option Also Available in Tape and Reel Designed-In Latch-Up Immunity Percentage of Units - % D D Low Noise . . . Typically 32 nV/Hz at TLC27M7 . . . 500 V Max at 25C, VDD = 5 V Input Offset Voltage Drift . . . Typically 0.1 V/Month, Including the First 30 Days Wide Range of Supply Voltages Over Specified Temperature Ranges: 0C to 70C . . . 3 V to 16 V -40C to 85C . . . 4 V to 16 V -55C to 125C . . . 4 V to 16 V Single-Supply Operation Common-Mode Input Voltage Range Extends Below the Negative Rail (C-Suffix, I-Suffix Types) 0 -800 NC - No internal connection -400 0 400 800 VIO - Input Offset Voltage - V AVAILABLE OPTIONS PACKAGE TA VIOmax AT 25C 500 V 0C to 70C -40C to 85C -55C to 125C SMALL OUTLINE (D) CHIP CARRIER (FK) CERAMIC DIP (JG) PLASTIC DIP (P) TSSOP (PW) TLC27M7CD -- -- TLC27M7CP -- 2 mV TLC27M2BCD -- -- TLC27M2BCP -- 5 mV TLC27M2ACD -- -- TLC27M2ACP -- 10 mV TLC27M2CD -- -- TLC27M2CP TLC27M2CPW 500 V TLC27M7ID -- -- TLC27M7IP -- 2 mV TLC27M2BID -- -- TLC27M2BIP -- 5 mV TLC27M2AID -- -- TLC27M2AIP 10 mV TLC27M2ID -- -- TLC27M2IP TLC27M2IPW 500 V TLC27M7MD TLC27M7MFK TLC27M7MJG TLC27M7MP -- 10 mV TLC27M2MD TLC27M2MFK TLC27M2MJG TLC27M2MP -- -- The D and PW package are available taped and reeled. Add R suffix to the device type (e.g.,TLC27M7CDR). For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. LinCMOS is a trademark of Texas Instruments. All other trademarks are the property of their respective owners. Copyright 1987 - 2008, Texas Instruments Incorporated !"# $% $ ! ! & ' $$ ( )% $ ! * $ #) #$ * ## !% POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 1 SLOS051E - OCTOBER 1987 - REVISED AUGUST 2008 description The TLC27M2 and TLC27M7 dual operational amplifiers combine a wide range of input offset voltage grades with low offset voltage drift, high input impedance, low noise, and speeds approaching that of general-purpose bipolar devices.These devices use Texas Instruments silicon-gate LinCMOS technology, which provides offset voltage stability far exceeding the stability available with conventional metal-gate processes. The extremely high input impedance, low bias currents, and high slew rates make these cost-effective devices ideal for applications which have previously been reserved for general-purpose bipolar products, but with only a fraction of the power consumption. Four offset voltage grades are available (C-suffix and I-suffix types), ranging from the low-cost TLC27M2 (10 mV) to the high-precision TLC27M7 (500 V). These advantages, in combination with good common-mode rejection and supply voltage rejection, make these devices a good choice for new state-of-the-art designs as well as for upgrading existing designs. In general, many features associated with bipolar technology are available on LinCMOS operational amplifiers, without the power penalties of bipolar technology. General applications such as transducer interfacing, analog calculations, amplifier blocks, active filters, and signal buffering are easily designed with the TLC27M2 and TLC27M7. The devices also exhibit low voltage single-supply operation, making them ideally suited for remote and inaccessible battery-powered applications. The common-mode input voltage range includes the negative rail. A wide range of packaging options is available, including small-outline and chip-carrier versions for high-density system applications. The device inputs and outputs are designed to withstand -100-mA surge currents without sustaining latch-up. The TLC27M2 and TLC27M7 incorporate internal ESD-protection circuits that prevent functional failures at voltages up to 2000 V as tested under MIL-STD-883C, Method 3015.2; however, care should be exercised in handling these devices as exposure to ESD may result in the degradation of the device parametric performance. The C-suffix devices are characterized for operation from 0C to 70C. The I-suffix devices are characterized for operation from - 40C to 85C. The M-suffix devices are characterized for operation over the full military temperature range of -55C to 125C. 2 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 SLOS051E - OCTOBER 1987 - REVISED AUGUST 2008 equivalent schematic (each amplifier) VDD P3 P4 R6 R1 R2 IN - N5 P5 P1 P6 P2 IN + C1 R5 OUT N3 N1 R3 N2 D1 N4 R4 D2 N6 R7 N7 GND POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 3 SLOS051E - OCTOBER 1987 - REVISED AUGUST 2008 absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage, VDD (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 V Differential input voltage, VID (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V DD Input voltage range, VI (any input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.3 V to VDD Input current, II . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 mA Output current, IO (each output) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 mA Total current into VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 mA Total current out of GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 mA Duration of short-circuit current at (or below) 25C (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Unlimited Continuous total dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table Operating free-air temperature, TA: C suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0C to 70C I suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40C to 85C M suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55C to 125C Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65C to 150C Case temperature for 60 seconds: FK package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: D or P package . . . . . . . . . . . . . . . . . 260C Lead temperature 1,6 mm (1/16 inch) from case for 60 seconds: JG package . . . . . . . . . . . . . . . . . . . . 300C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. All voltage values, except differential voltages, are with respect to network ground. 2. Differential voltages are at IN+ with respect to IN -. 3. The output may be shorted to either supply. Temperature and/or supply voltages must be limited to ensure that the maximum dissipation rating is not exceeded (see application section). DISSIPATION RATING TABLE PACKAGE TA 25C POWER RATING DERATING FACTOR ABOVE TA = 25C TA = 70C POWER RATING TA = 85C POWER RATING TA = 125C POWER RATING D 725 mW 5.8 mW/C 464 mW 377 mW FK 1375 mW 11.0 mW/C 880 mW 715 mW 275 mW JG 1050 mW 8.4 mW/C 672 mW 546 mW 210 mW P 1000 mW 8.0 mW/C 640 mW 520 mW recommended operating conditions Supply voltage, VDD Common-mode input voltage, VIC VDD = 5 V VDD = 10 V Operating free-air temperature, TA 4 POST OFFICE BOX 655303 C SUFFIX I SUFFIX M SUFFIX MIN MIN MAX MIN MAX MAX 3 16 4 16 4 16 -0.2 3.5 -0.2 3.5 0 3.5 -0.2 8.5 -0.2 8.5 0 8.5 0 70 -40 85 -55 125 * DALLAS, TEXAS 75265 UNIT V V C SLOS051E - OCTOBER 1987 - REVISED AUGUST 2008 electrical characteristics at specified free-air temperature, VDD = 5 V (unless otherwise noted) PARAMETER TEST CONDITIONS TA TLC27M2C TLC27M2AC TLC27M2BC TLC27M7C MIN VIO TLC27M2C VO = 1.4 V, RS = 50 , VIC = 0, RI = 100 k TLC27M2AC VO = 1.4 V, RS = 50 , VIC = 0, RI = 100 k Input offset voltage TLC27M2BC VO = 1.4 V, RS = 50 , VIC = 0, RI = 100 k TLC27M7C VO = 1.4 V, RS = 50 , VIC = 0, RI = 100 k 25C UNIT TYP MAX 1.1 10 Full range 12 25C 0.9 5 220 2000 Full range 6.5 25C Full range 3000 25C 185 Full range 500 Average temperature coefficient of input offset voltage IIO Input offset current (see Note 4) VO = 2.5 V, VIC = 2.5 V 25C 0.6 60 IIB Input bias current (see Note 4) VO = 2.5 V, VIC = 2.5 V 70C 40 600 VICR VOH VOL AVD CMRR kSVR IDD High-level output voltage Low-level output voltage Large-signal differential voltage amplification Common-mode rejection ratio VID = 100 mV, RL = 100 k VID = - 100 mV, VO = 0.25 V to 2 V, IOL = 0 RL = 100 k VIC = VICRmin Supply-voltage rejection ratio (VDD /VIO) VDD = 5 V to 10 V, Supply current (two amplifiers) VO = 2.5 V, No load VO = 1.4 V VIC = 2.5 V, V V 1500 VIO 25C to 70C 1.7 25C 0.1 60 70C 7 300 25C -0.2 to 4 Full range -0.2 to 3.5 25C 3.2 3.9 0C 3 3.9 70C 3 4 Common-mode input voltage range (see Note 5) mV V/C -0.3 to 4.2 pA pA V V V 25C 0 50 0C 0 50 70C 0 50 25C 25 170 0C 15 200 70C 15 140 25C 65 91 0C 60 91 70C 60 92 25C 70 93 0C 60 92 70C 60 94 mV V/mV dB dB 25C 210 560 0C 250 640 70C 170 440 A Full range is 0C to 70C. NOTES: 4. The typical values of input bias current and input offset current below 5 pA were determined mathematically. 5. This range also applies to each input individually. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 5 SLOS051E - OCTOBER 1987 - REVISED AUGUST 2008 electrical characteristics at specified free-air temperature, VDD = 10 V (unless otherwise noted) PARAMETER TEST CONDITIONS TA TLC27M2C TLC27M2AC TLC27M2BC TLC27M7C MIN VIO TLC27M2C VO = 1.4 V, RS = 50 , VIC = 0, RL = 100 k TLC27M2AC VO = 1.4 V, RS = 50 , VIC = 0, RL = 100 k Input offset voltage TLC27M2BC VO = 1.4 V, RS = 50 , VIC = 0, RL = 100 k TLC27M7C VO = 1.4 V, RS = 50 , VIC = 0, RL = 100 k 25C UNIT TYP MAX 1.1 10 Full range 12 25C 0.9 5 224 2000 Full range 6.5 25C Full range 3000 25C 190 Full range 800 Average temperature coefficient of input offset voltage IIO Input offset current (see Note 4) VO = 5 V, VIC = 5 V 25C 0.7 60 IIB Input bias current (see Note 4) VO = 5 V, VIC = 5 V 70C 50 600 VICR VOH VOL AVD CMRR kSVR IDD High-level output voltage Low-level output voltage Large-signal differential voltage amplification Common-mode rejection ratio VID = 100 mV, RL = 100 k VID = -100 mV, IOL = 0 VO = 1 V to 6 V, RL = 100 k VIC = VICRmin Supply-voltage rejection ratio (VDD /VIO) VDD = 5 V to 10 V, Supply current (two amplifiers) VO = 5 V, No load VO = 1.4 V VIC = 5 V, 25C to 70C 2.1 25C 0.1 60 70C 7 300 25C -0.2 to 9 Full range -0.2 to 8.5 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 V/C -0.3 to 9.2 pA pA V V 25C 8 8.7 0C 7.8 8.7 70C 7.8 8.7 V 25C 0 50 0C 0 50 70C 0 50 25C 25 275 0C 15 320 70C 15 230 25C 65 94 0C 60 94 70C 60 94 25C 70 93 0C 60 92 70C 60 94 mV V/mV dB dB 25C 285 600 0C 345 800 70C 220 560 Full range is 0C to 70C. NOTES: 4. The typical values of input bias current and input offset current below 5 pA were determined mathematically. 5. This range also applies to each input individually. 6 V V 1900 VIO Common-mode input voltage range (see Note 5) mV A SLOS051E - OCTOBER 1987 - REVISED AUGUST 2008 electrical characteristics at specified free-air temperature, VDD = 5 V (unless otherwise noted) PARAMETER TEST CONDITIONS TA TLC27M2I TLC27M2AI TLC27M2BI TLC27M7I MIN VIO TLC27M2I VO = 1.4 V, RS = 50 , VIC = 0, RL = 100 k TLC27M2AI VO = 1.4 V, RS = 50 , VIC = 0, RL = 100 k Input offset voltage TLC27M2BI VO = 1.4 V, RS = 50 , VIC = 0, RL = 100 k TLC27M7I VO = 1.4 V, RS = 50 , VIC = 0, RL = 100 k 25C UNIT TYP MAX 1.1 10 Full range 13 25C 0.9 5 220 2000 Full range 7 25C Full range 3500 25C 185 Full range 500 Average temperature coefficient of input offset voltage 25C to 85C 1.7 IIO Input offset current (see Note 4) VO = 2.5 V, VIC = 2.5 V 25C 0.1 60 85C 24 1000 25C 0.6 60 IIB Input bias current (see Note 4) VO = 2.5 V, VIC = 2.5 V 85C 200 2000 VICR Common-mode input voltage range (see Note 5) Full range VOH VOL AVD CMRR kSVR IDD High-level output voltage Low-level output voltage Large-signal differential voltage amplification Common-mode rejection ratio VID = 100 mV, RL = 100 k VID = -100 mV, IOL = 0 VO = 0.25 V to 2 V, RL = 100 k VIC = VICRmin Supply-voltage rejection ratio (VDD /VIO) VDD = 5 V to 10 V, Supply current (two amplifiers) VO = 2.5 V, No load VO = 1.4 V VIC = 2.5 V, V V 2000 VIO 25C mV -0.2 to 4 V/C -0.3 to 4.2 pA pA V -0.2 to 3.5 V 25C 3.2 3.9 -40C 3 3.9 85C 3 4 V 25C 0 50 -40C 0 50 85C 0 50 25C 25 170 -40C 15 270 85C 15 130 25C 65 91 -40C 60 90 85C 60 90 25C 70 93 -40C 60 91 85C 60 94 mV V/mV dB dB 25C 210 560 -40C 315 800 85C 160 400 A Full range is - 40C to 85C. NOTES: 4. The typical values of input bias current and input offset current below 5 pA were determined mathematically. 5. This range also applies to each input individually. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 7 SLOS051E - OCTOBER 1987 - REVISED AUGUST 2008 electrical characteristics at specified free-air temperature, VDD = 10 V (unless otherwise noted) PARAMETER TEST CONDITIONS TA TLC27M2I TLC27M2AI TLC27M2BI TLC27M7I MIN VIO TLC27M2I VO = 1.4 V, RS = 50 , VIC = 0, RL = 100 k TLC27M2AI VO = 1.4 V, RS = 50 , VIC = 0, RL = 100 k Input offset voltage TLC27M2BI VO = 1.4 V, RS = 50 , VIC = 0, RL = 100 k TLC27M7I VO = 1.4 V, RS = 50 , VIC = 0, RL = 100 k VIO Average temperature coefficient of input offset voltage IIO Input offset current (see Note 4) VO = 5 V, VIC = 5 V IIB Input bias current (see Note 4) VO = 5 V, VIC = 5 V 25C VOL AVD CMRR kSVR Low-level output voltage Large-signal differential voltage amplification Common-mode rejection ratio VID = 100 mV, RL = 100 k VID = - 100 mV, VO = 1 V to 6 V, IOL = 0 RL = 100 k VIC = VICRmin Supply-voltage rejection ratio (VDD /VIO) VDD = 5 V to 10 V, Supply current VO = 5 V, No load VO = 1.4 V 10 0.9 5 224 2000 Full range Full range 3500 25C 190 Full range 800 25C to 85C 2.1 V/C 25C 0.1 60 85C 26 1000 25C 0.7 85C 220 -0.2 to 9 -0.3 to 9.2 -0.2 to 8.5 V 25C 8 8.7 -40C 7.8 8.7 85C 7.8 8.7 V 25C 0 50 -40C 0 50 85C 0 50 25C 25 275 -40C 15 390 85C 15 220 25C 65 94 -40C 60 93 85C 60 94 25C 70 93 -40C 60 91 85C 60 94 dB dB 600 900 85C 205 Full range is - 40C to 85C. NOTES: 4. The typical values of input bias current and input offset current below 5 pA were determined mathematically. 5. This range also applies to each input individually. 520 * DALLAS, TEXAS 75265 mV V/mV 450 POST OFFICE BOX 655303 pA V 285 8 pA 60 200 0 25C VIC = 5 V, V V 2900 -40C IDD mV 7 25C Common-mode input voltage range (see Note 5) High-level output voltage MAX 1.1 13 25C Full range VOH TYP Full range 25C VICR UNIT A SLOS051E - OCTOBER 1987 - REVISED AUGUST 2008 electrical characteristics at specified free-air temperature, VDD = 5 V (unless otherwise noted) PARAMETER TEST CONDITIONS TA TLC27M2M TLC27M7M MIN VIO TLC27M2M VO = 1.4 V, RS = 50 , VIC = 0, RL = 100 k TLC27M7M VO = 1.4 V, RS = 50 , VIC = 0, RL = 100 k Input offset voltage VIO Average temperature coefficient of input offset voltage IIO Input offset current (see Note 4) VO = 2.5 V, VIC = 2.5 V IIB Input bias current (see Note 4) VO = 2.5 V, VIC = 2.5 V 25C VOL AVD CMRR kSVR IDD Low-level output voltage Large-signal differential voltage amplification Common-mode rejection ratio VID = 100 mV, RL = 100 k VID = - 100 mV, IOL = 0 VO = 0.25 V to 2 V, RL = 100 k VIC = VICRmin Supply-voltage rejection ratio (VDD /VIO) VDD = 5 V to 10 V, Supply current (two amplifiers) VO = 2.5 V, No load VO = 1.4 V VIC = 2.5 V, 10 185 500 Full range mV 3750 25C to 125C 1.7 25C 0.1 60 pA 125C 1.4 15 nA 25C 0.6 60 pA 125C 9 35 nA Common-mode input voltage range (see Note 5) High-level output voltage 1.1 12 25C Full range VOH MAX Full range 25C VICR UNIT TYP 0 to 4 V/C -0.3 to 4.2 V 0 to 3.5 V 25C 3.2 3.9 -55C 3 3.9 125C 3 4 V 25C 0 50 -55C 0 50 125C 0 50 25C 25 170 -55C 15 290 125C 15 120 25C 65 91 -55C 60 89 125C 60 91 25C 70 93 -55C 60 91 125C 60 94 mV V/mV dB dB 25C 210 560 -55C 340 880 125C 140 360 A Full range is - 55C to 125C. NOTES: 4. The typical values of input bias current and input offset current below 5 pA were determined mathematically. 5. This range also applies to each input individually. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 9 SLOS051E - OCTOBER 1987 - REVISED AUGUST 2008 electrical characteristics at specified free-air temperature, VDD = 10 V (unless otherwise noted) PARAMETER TEST CONDITIONS TA TLC27M2M TLC27M7M MIN TLC27M2M VIO Input offset voltage TLC27M7M VO = 1.4 V, RS = 50 , VIC = 0, RL = 100 k VO = 1.4 V, RS = 50 , VIC = 0, RL = 100 k 25C UNIT TYP MAX 1.1 10 190 800 Full range 12 25C Full range 4300 VIO Average temperature coefficient of input offset voltage 25C to 125C 2.1 25C 0.1 60 IIO Input offset current (see Note 4) VO = 5 V, VIC = 5 V 125C 1.8 15 25C 0.7 60 IIB Input bias current (see Note 4) VO = 5 V, VIC = 5 V 125C 10 35 25C VICR Common-mode input voltage range (see Note 5) Full range VOH VOL High-level output voltage Low-level output voltage VID = 100 mV, RL = 100 k VID = - 100 mV, IOL = 0 0 to 9 CMRR kSVR IDD Large-signal differential voltage amplification Common-mode rejection ratio VO = 1 V to 6 V, RL = 100 k VIC = VICRmin Supply-voltage rejection ratio (VDD /VIO) VDD = 5 V to 10 V, Supply current (two amplifiers) VO = 5 V, No load VO = 1.4 V VIC = 5 V, -0.3 to 9.2 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 pA pA V V 25C 8 8.7 -55C 7.8 8.6 125C 7.8 8.8 V 25C 0 50 -55C 0 50 0 50 25C 25 275 -55C 15 420 125C 15 190 25C 65 94 -55C 60 93 125C 60 93 25C 70 93 -55C 60 91 125C 60 94 mV V/mV dB dB 25C 285 600 -55C 490 1000 125C 180 480 Full range is - 55C to 125C. NOTES: 4. The typical values of input bias current and input offset current below 5 pA were determined mathematically. 5. This range also applies to each input individually. 10 V/C 0 to 8.5 125C AVD mV A SLOS051E - OCTOBER 1987 - REVISED AUGUST 2008 operating characteristics at specified free-air temperature, VDD = 5 V PARAMETER TEST CONDITIONS TA TLC27M2C TLC27M2AC TLC27M2BC TLC27M7C MIN VI(PP) = 1 V SR Slew rate at unity gain RL = 100 k, k , CL = 20 pF, See Figure 1 VI(PP) = 2.5 V Vn BOM B1 m Equivalent input noise voltage f = 1 kHz, See Figure 2 RS = 20 , Maximum output-swing bandwidth VO = VOH, RL = 100 k, CL = 20 pF, See Figure 1 Unity-gain bandwidth Phase margin VI = 10 mV, See Figure 3 VI = 10 mV, CL = 20 pF, CL = 20 pF, f = B1, See Figure 3 TYP 25C 0.43 0C 0.46 70C 0.36 25C 0.40 0C 0.43 70C 0.34 25C 32 25C 55 0C 60 70C 50 25C 525 0C 600 70C 400 25C 40 0C 41 70C 39 UNIT MAX V/ V/ss nV/Hz kHz kHz operating characteristics at specified free-air temperature, VDD = 10 V PARAMETER TEST CONDITIONS TA TLC27M2C TLC27M2AC TLC27M2BC TLC27M7C MIN VI(PP) = 1 V SR Slew rate at unity gain k , RL = 100 k, CL = 20 pF, See Figure 1 VI(PP) = 5.5 V Vn Equivalent input noise voltage f = 1 kHz, See Figure 2 RS = 20 , BOM Maximum output-swing bandwidth VO = VOH, RL = 100 k, CL = 20 pF, See Figure 1 B1 m Unity-gain bandwidth Phase margin VI = 10 mV, See Figure 3 VI = 10 mV, CL = 20 pF, POST OFFICE BOX 655303 CL = 20 pF, f = B1, See Figure 3 * DALLAS, TEXAS 75265 TYP 25C 0.62 0C 0.67 70C 0.51 25C 0.56 0C 0.61 70C 0.46 25C 32 25C 35 0C 40 70C 30 25C 635 0C 710 70C 510 25C 43 0C 44 70C 42 UNIT MAX V/ s V/s nV/Hz kHz kHz 11 SLOS051E - OCTOBER 1987 - REVISED AUGUST 2008 operating characteristics at specified free-air temperature, VDD = 5 V PARAMETER TEST CONDITIONS TA TLC27M2I TLC27M2AI TLC27M2BI TLC27M7I MIN VI(PP) = 1 V SR Slew rate at unity gain RL = 100 k, k , CL = 20 pF, See Figure 1 VI(PP) = 2.5 V Vn BOM B1 m Equivalent input noise voltage f = 1 kHz, See Figure 2 RS = 20 , Maximum output-swing bandwidth VO = VOH, RL = 100 k, CL = 20 pF, See Figure 1 VI = 10 mV, See Figure 3 CL = 20 pF, Unity-gain bandwidth Phase margin VI = 10 mV, CL = 20 pF, f = B1, See Figure 3 TYP 25C 0.43 -40C 0.51 85C 0.35 25C 0.40 -40C 0.48 85C 0.32 25C 32 25C 55 -40C 75 85C 45 25C 525 -40C 770 85C 370 25C 40 -40C 43 85C 38 UNIT MAX V/ V/ss nV/Hz kHz kHz operating characteristics at specified free-air temperature, VDD = 10 V PARAMETER TEST CONDITIONS TA TLC27M2I TLC27M2AI TLC27M2BI TLC27M7I MIN VI(PP) = 1 V SR Slew rate at unity gain k , RL = 100 k, CL = 20 pF, See Figure 1 VI(PP) = 5.5 V Vn Equivalent input noise voltage f = 1 kHz, See Figure 2 RS = 20 , BOM Maximum output-swing bandwidth VO = VOH, RL = 100 k, CL = 20 pF, See Figure 1 B1 m 12 Unity-gain bandwidth Phase margin VI = 10 mV, See Figure 3 VI = 10 mV, CL = 20 pF, POST OFFICE BOX 655303 CL = 20 pF, f = B1, See Figure 3 * DALLAS, TEXAS 75265 TYP 25C 0.62 -40C 0.77 85C 0.47 25C 0.56 -40C 0.70 85C 0.44 25C 32 25C 35 -40C 45 85C 25 25C 635 -40C 880 85C 480 25C 43 -40C 46 85C 41 UNIT MAX V/ s V/s nV/Hz kHz kHz SLOS051E - OCTOBER 1987 - REVISED AUGUST 2008 operating characteristics at specified free-air temperature, VDD = 5 V PARAMETER TEST CONDITIONS TA TLC27M2M TLC27M7M MIN VI(PP) = 1 V SR Slew rate at unity gain k , RL = 100 k, CL = 20 pF, See Figure 1 VI(PP) = 2.5 V Vn BOM B1 m Equivalent input noise voltage f = 1 kHz, See Figure 2 RS = 20 , Maximum output-swing bandwidth VO = VOH, RL = 100 k, CL = 20 pF, See Figure 1 VI = 10 mV, See Figure 3 CL = 20 pF, Unity-gain bandwidth Phase margin VI = 10 mV, CL = 20 pF, f = B1, See Figure 3 TYP 25C 0.43 -55C 0.54 125C 0.29 25C 0.40 -55C 0.49 125C 0.28 25C 32 25C 55 -55C 80 125C 40 25C 525 -55C 850 125C 330 25C 40 -55C 44 125C 36 UNIT MAX V/ s V/s nV/Hz kHz kHz operating characteristics at specified free-air temperature, VDD = 10 V PARAMETER TEST CONDITIONS TA TLC27M2M TLC27M7M MIN VI(PP) = 1 V SR Slew rate at unity gain RL = 100 k, k , CL = 20 pF, See Figure 1 VI(PP) = 5.5 V Vn BOM B1 m Equivalent input noise voltage f = 1 kHz, See Figure 2 RS = 20 , Maximum output-swing bandwidth VO = VOH, RL = 100 k, CL = 20 pF, See Figure 1 VI = 10 mV, See Figure 3 CL = 20 pF, Unity gain bandwidth Phase margin VI = 10 mV, CL = 20 pF, POST OFFICE BOX 655303 f = B1, See Figure 3 * DALLAS, TEXAS 75265 TYP 25C 0.62 -55C 0.81 125C 0.38 25C 0.56 -55C 0.73 125C 0.35 25C 32 25C 35 -55C 50 125C 20 25C 635 -55C 960 125C 440 25C 43 -55C 47 125C 39 UNIT MAX V/ s V/s nV/Hz kHz kHz 13 SLOS051E - OCTOBER 1987 - REVISED AUGUST 2008 PARAMETER MEASUREMENT INFORMATION single-supply versus split-supply test circuits Because the TLC27M2 and TLC27M7 are optimized for single-supply operation, circuit configurations used for the various tests often present some inconvenience since the input signal, in many cases, must be offset from ground. This inconvenience can be avoided by testing the device with split supplies and the output load tied to the negative rail. A comparison of single-supply versus split-supply test circuits is shown below. The use of either circuit gives the same result. VDD + VDD - - VO VO + CL VI RL + VI CL RL VDD - (a) SINGLE SUPPLY (b) SPLIT SUPPLY Figure 1. Unity-Gain Amplifier 2 k VO VO + + 20 VDD + - 1/2 VDD VDD - 20 2 k 20 20 VDD - (a) SINGLE SUPPLY (b) SPLIT SUPPLY Figure 2. Noise-Test Circuit 10 k 100 VI VO - VO + + 1/2 VDD VDD + - VDD 100 VI 10 k CL CL VDD - (a) SINGLE SUPPLY (b) SPLIT SUPPLY Figure 3. Gain-of-100 Inverting Amplifier 14 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 SLOS051E - OCTOBER 1987 - REVISED AUGUST 2008 PARAMETER MEASUREMENT INFORMATION input bias current Because of the high input impedance of the TLC27M2 and TLC27M7 operational amplifiers, attempts to measure the input bias current can result in erroneous readings. The bias current at normal room ambient temperature is typically less than 1 pA, a value that is easily exceeded by leakages on the test socket. Two suggestions are offered to avoid erroneous measurements: 1. Isolate the device from other potential leakage sources. Use a grounded shield around and between the device inputs (see Figure 4). Leakages that would otherwise flow to the inputs are shunted away. 2. Compensate for the leakage of the test socket by actually performing an input bias current test (using a picoammeter) with no device in the test socket. The actual input bias current can then be calculated by subtracting the open-socket leakage readings from the readings obtained with a device in the test socket. One word of caution--many automatic testers as well as some bench-top operational amplifier testers use the servo-loop technique with a resistor in series with the device input to measure the input bias current (the voltage drop across the series resistor is measured and the bias current is calculated). This method requires that a device be inserted into the test socket to obtain a correct reading; therefore, an open-socket reading is not feasible using this method. 8 5 8 5 V = VIC 1 4 Figure 4. Isolation Metal Around Device Inputs (JG and P packages) low-level output voltage To obtain low-supply-voltage operation, some compromise was necessary in the input stage. This compromise results in the device low-level output being dependent on both the common-mode input voltage level as well as the differential input voltage level. When attempting to correlate low-level output readings with those quoted in the electrical specifications, these two conditions should be observed. If conditions other than these are to be used, please refer to Figures 14 through 19 in the Typical Characteristics of this data sheet. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 15 SLOS051E - OCTOBER 1987 - REVISED AUGUST 2008 PARAMETER MEASUREMENT INFORMATION input offset voltage temperature coefficient Erroneous readings often result from attempts to measure temperature coefficient of input offset voltage. This parameter is actually a calculation using input offset voltage measurements obtained at two different temperatures. When one (or both) of the temperatures is below freezing, moisture can collect on both the device and the test socket. This moisture results in leakage and contact resistance, which can cause erroneous input offset voltage readings. The isolation techniques previously mentioned have no effect on the leakage, since the moisture also covers the isolation metal itself, thereby rendering it useless. It is suggested that these measurements be performed at temperatures above freezing to minimize error. full-power response Full-power response, the frequency above which the operational amplifier slew rate limits the output voltage swing, is often specified two ways: full-linear response and full-peak response. The full-linear response is generally measured by monitoring the distortion level of the output while increasing the frequency of a sinusoidal input signal until the maximum frequency is found above which the output contains significant distortion. The full-peak response is defined as the maximum output frequency, without regard to distortion, above which full peak-to-peak output swing cannot be maintained. Because there is no industry-wide accepted value for significant distortion, the full-peak response is specified in this data sheet and is measured using the circuit of Figure 1. The initial setup involves the use of a sinusoidal input to determine the maximum peak-to-peak output of the device (the amplitude of the sinusoidal wave is increased until clipping occurs). The sinusoidal wave is then replaced with a square wave of the same amplitude. The frequency is then increased until the maximum peak-to-peak output can no longer be maintained (Figure 5). A square wave is used to allow a more accurate determination of the point at which the maximum peak-to-peak output is reached. (a) f = 1 kHz (b) BOM > f > 1 kHz (c) f = BOM (d) f > BOM Figure 5. Full-Power-Response Output Signal test time Inadequate test time is a frequent problem, especially when testing CMOS devices in a high-volume, short-test-time environment. Internal capacitances are inherently higher in CMOS than in bipolar and BiFET devices and require longer test times than their bipolar and BiFET counterparts. The problem becomes more pronounced with reduced supply levels and lower temperatures. 16 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 SLOS051E - OCTOBER 1987 - REVISED AUGUST 2008 TYPICAL CHARACTERISTICS Table of Graphs FIGURE VIO VIO Input offset voltage Distribution 6, 7 Temperature coefficient Distribution 8, 9 VOH High-level output voltage vs High-level output current vs Supply voltage vs Free-air temperature 10, 11 12 13 VOL Low-level output voltage vs Common-mode input voltage vs Differential input voltage vs Free-air temperature vs Low-level output current 14, 15 16 17 18, 19 AVD Differential voltage amplification vs Supply voltage vs Free-air temperature vs Frequency 20 21 32, 33 Input bias and input offset current vs Free-air temperature 22 Common-mode input voltage vs Supply voltage 23 IDD Supply current vs Supply voltage vs Free-air temperature 24 25 SR Slew rate vs Supply voltage vs Free-air temperature 26 27 Normalized slew rate vs Free-air temperature 28 Maximum peak-to-peak output voltage vs Frequency 29 B1 Unity-gain bandwidth vs Free-air temperature vs Supply voltage 30 31 m Phase margin vs Supply voltage vs Free-air temperature vs Capacitive loads 34 35 36 Vn Equivalent input noise voltage vs Frequency 37 Phase shift vs Frequency 32, 33 IIB / IIO VIC VO(PP) POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 17 SLOS051E - OCTOBER 1987 - REVISED AUGUST 2008 TYPICAL CHARACTERISTICS DISTRIBUTION OF TLC27M2 INPUT OFFSET VOLTAGE DISTRIBUTION OF TLC27M2 INPUT OFFSET VOLTAGE IIIIIIIIIIII IIIIIIIIIIII 60 50 Percentage of Units - % 50 Percentage of Units - % 60 612 Amplifiers Tested From 4 Wafer Lots VDD = 5 V TA = 25C P Package 40 30 20 10 IIIIIIIIIII IIIIIIIIIII 612 Amplifiers Tested From 4 Wafer Lots VDD = 10 V TA = 25C P Package 40 30 20 10 0 0 -5 -4 -3 -2 -1 0 1 2 3 VIO - Input Offset Voltage - mV 4 5 -5 -4 Figure 6 IIIIIIIIIIII IIIIIIIIIIII 50 Percentage of Units - % Percentage of Units - % 60 224 Amplifiers Tested From 6 Wafer Lots VDD = 5 V TA = 25C to 125C P Package Outliers: (1) 33.0 V/C 30 20 10 40 IIIIIIIIIIII IIIIIIIIIIII 224 Amplifiers Tested From 6 Wafer Lots VDD = 10 V TA = 25C to 125C P Package Outliers: (1) 34.6 V/C 30 20 10 0 -10 -8 -6 -4 -2 0 2 4 6 8 VIO - Temperature Coefficient - V/C 10 0 -10 -8 -6 -4 -2 0 2 4 6 8 VIO - Temperature Coefficient - V/C Figure 8 18 5 DISTRIBUTION OF TLC27M2 AND TLC27M7 INPUT OFFSET VOLTAGE TEMPERATURE COEFFICIENT 60 40 4 Figure 7 DISTRIBUTION OF TLC27M2 AND TLC27M7 INPUT OFFSET VOLTAGE TEMPERATURE COEFFICIENT 50 -3 -2 -1 0 1 2 3 VIO - Input Offset Voltage - mV Figure 9 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 10 SLOS051E - OCTOBER 1987 - REVISED AUGUST 2008 TYPICAL CHARACTERISTICS HIGH-LEVEL OUTPUT VOLTAGE vs HIGH-LEVEL OUTPUT CURRENT HIGH-LEVEL OUTPUT VOLTAGE vs HIGH-LEVEL OUTPUT CURRENT 5 VOH - High-Level Output Voltage - V VOH VOH - High-Level Output Voltage - V VOH 4 IIII IIIIIIII IIII VDD = 5 V 3 VDD = 4 V AA AA AA AAAAA AAAAA IIIIII IIIIII 16 VID = 100 mV TA = 25C VDD = 3 V 2 AA AA AA 1 0 0 -2 -4 -6 -8 IOH - High-Level Output Current - mA -10 14 VDD = 16 V 12 10 IIII IIII 8 VDD = 10 V 6 4 2 0 0 -10 -20 -30 -40 IOH - High-Level Output Current - mA Figure 10 Figure 11 HIGH-LEVEL OUTPUT VOLTAGE vs FREE-AIR TEMPERATURE HIGH-LEVEL OUTPUT VOLTAGE vs SUPPLY VOLTAGE AAAA AAAA AAAA VDD - 1.6 VID = 100 mV RL = 100 k TA = 25C 14 12 VOH - High-Level Output Voltage - V VOH VOH - High-Level Output Voltage - V VOH 16 10 AA AA AA 8 6 2 0 2 4 6 8 10 12 VDD - Supply Voltage - V 14 16 IIII VDD - 1.7 VDD = 5 V VDD - 1.8 VDD - 1.9 VDD - 2 IOH = - 5 mA VID = 100 mA IIII IIII VDD = 10 V VDD - 2.1 AA AA AA 4 0 VID= 100 mV TA = 25C VDD - 2.2 VDD - 2.3 VDD - 2.4 -75 -50 Figure 12 -25 0 25 50 75 100 TA - Free-Air Temperature - C 125 Figure 13 Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 19 SLOS051E - OCTOBER 1987 - REVISED AUGUST 2008 TYPICAL CHARACTERISTICS LOW-LEVEL OUTPUT VOLTAGE vs COMMON-MODE INPUT VOLTAGE LOW-LEVEL OUTPUT VOLTAGE vs COMMON-MODE INPUT VOLTAGE AA AA 500 VDD = 5 V IOL = 5 mA TA = 25C 650 VOL VOL - Low-Level Output Voltage - mV VOL VOL - Low-Level Output Voltage - mV 700 600 550 VID = - 100 mV 500 450 450 400 VID = - 100 mV VID = - 1 V 350 VID = - 2.5 V AA AA 400 VID = - 1 V 350 300 250 300 0 VDD = 10 V IOL = 5 mA TA = 25C 1 2 3 VIC - Common-Mode Input Voltage - V 4 0 1 3 5 7 7 2 4 6 8 VIC - Common-Mode Input Voltage - V Figure 14 Figure 15 LOW-LEVEL OUTPUT VOLTAGE vs FREE-AIR TEMPERATURE LOW-LEVEL OUTPUT VOLTAGE vs DIFFERENTIAL INPUT VOLTAGE 900 IOL = 5 mA VIC = |VID/2| TA = 25C 700 VOL VOL - Low-Level Output Voltage - mV VOL VOL - Low-Level Output Voltage - mV 800 AA AA AA 600 500 VDD = 5 V 400 300 VDD = 10 V 200 100 800 700 IOL = 5 mA VID = - 1 V VIC = 0.5 V VDD = 5 V 600 500 400 VDD = 10 V AA AA AA 300 200 100 0 0 -1 -2 -3 -4 -5 -6 -7 -8 -9 -10 VID - Differential Input Voltage - V 0 -75 -50 Figure 16 -25 0 25 50 75 100 TA - Free-Air Temperature - C Figure 17 Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices. 20 10 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 125 SLOS051E - OCTOBER 1987 - REVISED AUGUST 2008 TYPICAL CHARACTERISTICS LOW-LEVEL OUTPUT VOLTAGE vs LOW-LEVEL OUTPUT CURRENT LOW-LEVEL OUTPUT VOLTAGE vs LOW-LEVEL OUTPUT CURRENT AAAAA AAAAA AAAAA AAAAA 3 1 VOL - Low-Level Output Voltage - V VOL 0.9 AA AA AA 0.8 VOL - Low-Level Output Voltage - V VOL VID = - 1 V VIC = 0.5 V TA = 25C VDD = 5 V 0.7 0.6 VDD = 4 V VDD = 3 V 0.5 0.4 0.2 0.1 0 0 1 2 3 4 5 6 7 IOL - Low-Level Output Current - mA VDD = 10 V 1.5 1 0.5 0 0 8 5 10 15 20 25 IOL - Low-Level Output Current - mA Figure 18 LARGE-SIGNAL DIFFERENTIAL VOLTAGE AMPLIFICATION vs FREE-AIR TEMPERATURE TA = - 55C 400 0C 350 25C 300 70C 250 85C 200 125C 150 100 50 AA AA AA 0 0 2 4 6 8 10 12 VDD - Supply Voltage - V 14 RL = 100 k 450 -40C AVD AVD - Large-Signal Differential Voltage Amplification - V/mV AVD AVD - Large-Signal Differential Voltage Amplification - V/mV AA AA AA IIII IIII IIII IIII 500 500 RL = 100 k 30 Figure 19 LARGE-SIGNAL DIFFERENTIAL VOLTAGE AMPLIFICATION vs SUPPLY VOLTAGE 450 IIII IIII VDD = 16 V IIII IIII 2 AA AA AA 0.3 VID = - 1 V VIC = 0.5 V TA = 25C 2.5 16 400 350 VDD = 10 V 300 250 IIII IIII 200 150 VDD = 5 V 100 50 0 -75 -50 Figure 20 -25 0 25 50 75 100 TA - Free-Air Temperature - C 125 Figure 21 Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 21 SLOS051E - OCTOBER 1987 - REVISED AUGUST 2008 TYPICAL CHARACTERISTICS COMMON-MODE INPUT VOLTAGE POSITIVE LIMIT vs SUPPLY VOLTAGE 16 10000 TA = 25C VDD = 10 V VIC = 5 V See Note A II II 1000 IIB 100 VIC - Common-Mode Input Voltage - V VIC IIB I IO - input Bias and Offset Currents - pA I IB and IIO INPUT BIAS CURRENT AND INPUT OFFSET CURRENT vs FREE-AIR TEMPERATURE II II IIO 10 12 10 8 AA AA AA 1 0.1 14 6 4 2 0 0 25 45 65 85 105 125 TA - Free-Air Temperature - C NOTE A: The typical values of input bias current and input offset current below 5 pA were determined mathematically. 2 Figure 22 14 SUPPLY CURRENT vs FREE-AIR TEMPERATURE 500 800 600 -40C 500 0C 400 AA AA 25C 300 70C 200 100 4 6 8 10 12 VDD - Supply Voltage - V 14 IIII IIII IIIII IIIII 350 300 VDD = 10 V 250 AA AA AA 0 2 400 200 VDD = 5 V 150 100 125C 0 VO = VDD/2 No Load 450 TA = - 55C A IIDD DD - Supply Current - A VO = VDD/2 No Load 700 16 50 0 -75 -50 Figure 24 -25 0 25 50 75 100 TA - Free-Air Temperature - C Figure 25 Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices. 22 16 Figure 23 SUPPLY CURRENT vs SUPPLY VOLTAGE A IIDD DD - Supply Current - A 4 6 8 10 12 VDD - Supply Voltage - V POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 125 SLOS051E - OCTOBER 1987 - REVISED AUGUST 2008 TYPICAL CHARACTERISTICS SLEW RATE vs SUPPLY VOLTAGE 0.9 IIIII 0.6 0.5 0.4 0.3 2 4 6 8 10 12 VDD - Supply Voltage - V 14 0.5 AAAAA AAAAAAAAAA AAAAA VDD = 5 V VI(PP) = 1 V 0.2 - 75 - 50 16 MAXIMUM PEAK-TO-PEAK OUTPUT VOLTAGE vs FREQUENCY VO(PP) - Maximum Peak-to-Peak Output Voltage - V 1.4 Normalized Slew Rate 1.2 1.1 AV = 1 VI(PP) = 1 V RL = 100 k CL = 20 pF VDD = 5 V 1 0.9 0.8 0.7 0.6 0.5 -75 -50 125 Figure 27 NORMALIZED SLEW RATE vs FREE-AIR TEMPERATURE VDD = 10 V VDD = 5 V VI(PP) = 2.5 V - 25 0 25 50 75 100 TA - Free-Air Temperature - C Figure 26 1.3 IIIII AAAAA AAAAA IIIII VDD = 10 V VI(PP) = 1 V 0.6 0.3 AV = 1 RL = 100 k CL = 20 pF See Figure 1 VDD = 10 V VI(PP) = 5.5 V 0.7 0.4 0 AAAAA AAAAA 0.8 SR - Slew Rate - V/ s SR - Slew Rate - V/ s 0.9 AV = 1 VIPP = 1 V RL = 100 k CL = 20 pF TA = 25C See Figure 1 0.8 0.7 SLEW RATE vs FREE-AIR TEMPERATURE -25 0 25 50 75 100 TA - Free-Air Temperature - C 125 10 IIII IIII 9 VDD = 10 V 8 7 6 TA = 125C TA = 25C TA = - 55C IIII IIII IIIII IIIII 5 VDD = 5 V 4 3 RL = 100 k See Figure 1 2 1 0 1 Figure 28 10 100 f - Frequency - kHz 1000 Figure 29 Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 23 SLOS051E - OCTOBER 1987 - REVISED AUGUST 2008 TYPICAL CHARACTERISTICS UNITY-GAIN BANDWIDTH vs FREE-AIR TEMPERATURE AAAAA AAAAA AAAAA AAAAA 900 800 VDD = 5 V VI = 10 mV CL = 20 pF See Figure 3 800 700 750 B1 B1 - Unity-Gain Bandwidth - kHz B1 B1 - Unity-Gain Bandwidth - kHz UNITY-GAIN BANDWIDTH vs SUPPLY VOLTAGE 600 500 400 700 AAAAA AAAAA AAAAA AAAAA VI = 10 mV CL = 20 pF TA = 25C See Figure 3 650 600 550 500 450 300 -75 -50 -25 0 25 50 75 100 TA - Free-Air Temperature - C 400 125 0 2 4 6 8 10 12 VDD - Supply Voltage - V Figure 30 14 Figure 31 LARGE-SCALE DIFFERENTIAL VOLTAGE AMPLIFICATION AND PHASE SHIFT vs FREQUENCY 10 7 AVD AVD - Large-Signal Differential Voltage Amplification AA AA 10 5 III III 10 4 0 30 AVD 10 3 60 10 2 90 Phase Shift VDD = 5 V RL = 100 k TA = 25C 10 6 Phase Shift 10 120 1 150 0.1 0 10 100 1k 10 k f - Frequency - Hz 100 k 180 1M Figure 32 Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices. 24 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 16 SLOS051E - OCTOBER 1987 - REVISED AUGUST 2008 TYPICAL CHARACTERISTICS LARGE-SCALE DIFFERENTIAL VOLTAGE AMPLIFICATION AND PHASE SHIFT vs FREQUENCY 10 7 VDD = 10 V RL = 100 k TA = 25C AA AA AA 10 5 0 III III 10 4 30 AVD 10 3 60 10 2 90 Phase Shift AVD AVD - Large-Signal Differential Voltage Amplification 10 6 Phase Shift 10 120 1 150 0.1 0 10 100 1k 10 k f - Frequency - Hz 180 1M 100 k Figure 33 PHASE MARGIN vs FREE-AIR TEMPERATURE PHASE MARGIN vs SUPPLY VOLTAGE 45 50 VI = 10 mV CL = 20 pF TA = 25C See Figure 3 43 m m - Phase Margin m m - Phase Margin 48 VDD = 5 V VI = 10 mV CL = 20 pF See Figure 3 46 44 AA AA 41 AA AA 42 39 37 40 38 0 2 4 6 8 10 12 VDD - Supply Voltage - V 14 16 35 -75 -50 -25 0 25 50 75 100 TA - Free-Air Temperature - C Figure 34 125 Figure 35 Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 25 SLOS051E - OCTOBER 1987 - REVISED AUGUST 2008 TYPICAL CHARACTERISTICS PHASE MARGIN vs CAPACITIVE LOAD 44 VDD = 5 V VI = 10 mV TA = 25C See Figure 3 42 m m - Phase Margin 40 AA AA 38 36 34 32 30 28 0 10 20 30 40 50 60 70 80 CL - Capacitive Load - pF 90 100 Figure 36 nV/ Hz Vn V n- Equivalent Input Noise Voltage - nV/Hz AA AA AA EQUIVALENT INPUT NOISE VOLTAGE vs FREQUENCY 300 VDD = 5 V RS = 20 TA = 25C See Figure 2 250 200 150 100 50 0 1 10 100 f -Frequency - Hz Figure 37 26 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 1000 SLOS051E - OCTOBER 1987 - REVISED AUGUST 2008 APPLICATION INFORMATION single-supply operation While the TLC27M2 and TLC27M7 perform well using dual power supplies (also called balanced or split supplies), the design is optimized for single-supply operation. This design includes an input common-mode voltage range that encompasses ground, as well as an output voltage range that pulls down to ground. The supply voltage range extends down to 3 V (C-suffix types), thus allowing operation with supply levels commonly available for TTL and HCMOS; however, for maximum dynamic range, 16-V single-supply operation is recommended. Many single-supply applications require that a voltage be applied to one input to establish a reference level that is above ground. A resistive voltage divider is usually sufficient to establish this reference level (see Figure 38). The low input bias current of the TLC27M2 and TLC27M7 permits the use of very large resistive values to implement the voltage divider, thus minimizing power consumption. The TLC27M2 and TLC27M7 work well in conjunction with digital logic; however, when powering both linear devices and digital logic from the same power supply, the following precautions are recommended: 1. Power the linear devices from separate bypassed supply lines (see Figure 39); otherwise, the linear device supply rails can fluctuate due to voltage drops caused by high switching currents in the digital logic. 2. Use proper bypass techniques to reduce the probability of noise-induced errors. Single capacitive decoupling is often adequate; however, high-frequency applications may require RC decoupling. VDD R4 R1 VI V R2 - VO V REF O + + V R3 DD R1 ) R3 VREF - VI R4 R2 ) V REF + VREF R3 C 0.01F Figure 38. Inverting Amplifier With Voltage Reference - Output Logic Logic Logic Power Supply + (a) COMMON SUPPLY RAILS - + Output Logic Logic Logic Power Supply (b) SEPARATE BYPASSED SUPPLY RAILS (preferred) Figure 39. Common Versus Separate Supply Rails POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 27 SLOS051E - OCTOBER 1987 - REVISED AUGUST 2008 APPLICATION INFORMATION input characteristics The TLC27M2 and TLC27M7 are specified with a minimum and a maximum input voltage that, if exceeded at either input, could cause the device to malfunction. Exceeding this specified range is a common problem, especially in single-supply operation. Note that the lower range limit includes the negative rail, while the upper range limit is specified at VDD -1 V at TA = 25C and at VDD -1.5 V at all other temperatures. The use of the polysilicon-gate process and the careful input circuit design gives the TLC27M2 and TLC27M7 very good input offset voltage drift characteristics relative to conventional metal-gate processes. Offset voltage drift in CMOS devices is highly influenced by threshold voltage shifts caused by polarization of the phosphorus dopant implanted in the oxide. Placing the phosphorus dopant in a conductor (such as a polysilicon gate) alleviates the polarization problem, thus reducing threshold voltage shifts by more than an order of magnitude. The offset voltage drift with time has been calculated to be typically 0.1 V/month, including the first month of operation. Because of the extremely high input impedance and resulting low bias current requirements, the TLC27M2 and TLC27M7 are well suited for low-level signal processing; however, leakage currents on printed-circuit boards and sockets can easily exceed bias current requirements and cause a degradation in device performance. It is good practice to include guard rings around inputs (similar to those of Figure 4 in the Parameter Measurement Information section). These guards should be driven from a low-impedance source at the same voltage level as the common-mode input (see Figure 40). The inputs of any unused amplifiers should be tied to ground to avoid possible oscillation. noise performance The noise specifications in operational amplifier circuits are greatly dependent on the current in the first-stage differential amplifier. The low input bias current requirements of the TLC27M2 and TLC27M7 result in a very low noise current, which is insignificant in most applications. This feature makes the devices especially favorable over bipolar devices when using values of circuit impedance greater than 50 k, since bipolar devices exhibit greater noise currents. VO + + VI + VI - - VO - VI VO (c) UNITY-GAIN AMPLIFIER (a) NONINVERTING AMPLIFIER (b) INVERTING AMPLIFIER Figure 40. Guard-Ring Schemes output characteristics The output stage of the TLC27M2 and TLC27M7 is designed to sink and source relatively high amounts of current (see typical characteristics). If the output is subjected to a short-circuit condition, this high current capability can cause device damage under certain conditions. Output current capability increases with supply voltage. All operating characteristics of the TLC27M2 and TLC27M7 were measured using a 20-pF load. The devices drive higher capacitive loads; however, as output load capacitance increases, the resulting response pole occurs at lower frequencies, thereby causing ringing, peaking, or even oscillation (see Figure 41). In many cases, adding a small amount of resistance in series with the load capacitance alleviates the problem. 28 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 SLOS051E - OCTOBER 1987 - REVISED AUGUST 2008 APPLICATION INFORMATION (a) CL = 20 pF, RL = NO LOAD (b) CL = 170 pF, RL = NO LOAD 2.5 V - VO + VI CL TA = 25C f = 1 kHz VI(PP) = 1 V -2.5 V (c) CL = 190 pF, RL = NO LOAD (d) TEST CIRCUIT Figure 41. Effect of Capacitive Loads and Test Circuit output characteristics (continued) Although the TLC27M2 and TLC27M7 possess excellent high-level output voltage and current capability, methods for boosting this capability are available, if needed. The simplest method involves the use of a pullup resistor (RP) connected from the output to the positive supply rail (see Figure 42). There are two disadvantages to the use of this circuit. First, the NMOS pulldown transistor N4 (see equivalent schematic) must sink a comparatively large amount of current. In this circuit, N4 behaves like a linear resistor with an on-resistance between approximately 60 and 180 , depending on how hard the operational amplifier input is driven. With very low values of RP, a voltage offset from 0 V at the output occurs. Second, pullup resistor RP acts as a drain load to N4 and the gain of the operational amplifier is reduced at output voltage levels where N5 is not supplying the output current. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 29 SLOS051E - OCTOBER 1987 - REVISED AUGUST 2008 APPLICATION INFORMATION output characteristics (continued) VDD VI + RP IP VO - C IP R2 IL R1 RL - P + V I F DD ) I VO *V L O ) I + R P IP = Pullup current required by the operational amplifier (typically 500 A) Figure 42. Resistive Pullup to Increase VOH Figure 43. Compensation for Input Capacitance feedback Operational amplifier circuits nearly always employ feedback, and since feedback is the first prerequisite for oscillation, some caution is appropriate. Most oscillation problems result from driving capacitive loads (discussed previously) and ignoring stray input capacitance. A small-value capacitor connected in parallel with the feedback resistor is an effective remedy (see Figure 43). The value of this capacitor is optimized empirically. electrostatic-discharge protection The TLC27M2 and TLC27M7 incorporate an internal electrostatic-discharge (ESD) protection circuit that prevents functional failures at voltages up to 2000 V as tested under MIL-STD-883C, Method 3015.2. Care should be exercised, however, when handling these devices as exposure to ESD may result in the degradation of the device parametric performance. The protection circuit also causes the input bias currents to be temperature dependent and have the characteristics of a reverse-biased diode. latch-up Because CMOS devices are susceptible to latch-up due to their inherent parasitic thyristors, the TLC27M2 and TLC27M7 inputs and outputs were designed to withstand -100-mA surge currents without sustaining latch-up; however, techniques should be used to reduce the chance of latch-up whenever possible. Internal protection diodes should not, by design, be forward biased. Applied input and output voltage should not exceed the supply voltage by more than 300 mV. Care should be exercised when using capacitive coupling on pulse generators. Supply transients should be shunted by the use of decoupling capacitors (0.1 F typical) located across the supply rails as close to the device as possible. The current path established if latch-up occurs is usually between the positive supply rail and ground and can be triggered by surges on the supply lines and/or voltages on either the output or inputs that exceed the supply voltage. Once latch-up occurs, the current flow is limited only by the impedance of the power supply and the forward resistance of the parasitic thyristor and usually results in the destruction of the device. The chance of latch-up occurring increases with increasing temperature and supply voltages. 30 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 SLOS051E - OCTOBER 1987 - REVISED AUGUST 2008 APPLICATION INFORMATION 1N4148 470 k 100 k 5V 1/2 TLC27M2 5V - 47 k 100 k VI VO + IS 1/2 TLC27M7 + - 2N3821 R2 68 k 100 k 1 F R1 68 k C2 2.2 nF C1 2.2 nF R NOTES: VO(PP) 2 V f O + NOTES: VI = 0 V to 3 V V I + I S R 1 2p R1R2C1C2 Figure 45. Precision Low-Current Sink Figure 44. Wien Oscillator 5V Gain Control 1 M (see Note A) 1 F - + 100 k + + 10 k - + - 1/2 TLC27M2 1 k - 0.1 F 100 k 0.1 F 100 k NOTE A: Low to medium impedance dynamic mike Figure 46. Microphone Preamplifier POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 31 SLOS051E - OCTOBER 1987 - REVISED AUGUST 2008 APPLICATION INFORMATION 10 M VDD - 1 k - 1/2 TLC27M2 VO 1/2 TLC27M2 VREF + 15 nF + 100 k 150 pF NOTES: VDD = 4 V to 15 V Vref = 0 V to VDD - 2 V Figure 47. Photo-Diode Amplifier With Ambient Light Rejection 1 M VDD 33 pF - VO + 1/2 TLC27M2 1N4148 100 k 100 k NOTES: VDD = 8 V to 16 V VO = 5 V, 10 mA Figure 48. 5-V Low-Power Voltage Regulator 32 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 SLOS051E - OCTOBER 1987 - REVISED AUGUST 2008 APPLICATION INFORMATION 5V 0.1 F VI 1 M 0.22 F + VO - 1/2 TLC27M2 1 M 100 k 100 k 10 k 0.1 F Figure 49. Single-Rail AC Amplifiers POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 33 PACKAGE OPTION ADDENDUM www.ti.com 27-Apr-2012 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp TLC27M2ACD ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC27M2ACDG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC27M2ACDR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC27M2ACDRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC27M2ACP ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type TLC27M2ACPE4 ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type TLC27M2AID ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC27M2AIDG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC27M2AIDR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC27M2AIDRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC27M2AIP ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type TLC27M2AIPE4 ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type TLC27M2BCD ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC27M2BCDG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC27M2BCDR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC27M2BCDRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC27M2BCP ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type TLC27M2BCPE4 ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type TLC27M2BID ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) Addendum-Page 1 CU NIPDAU Level-1-260C-UNLIM (3) Samples (Requires Login) PACKAGE OPTION ADDENDUM www.ti.com Orderable Device 27-Apr-2012 Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC27M2BIDR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC27M2BIDRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC27M2BIP ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type TLC27M2BIPE4 ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type TLC27M2CD ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC27M2CDG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC27M2CDR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC27M2CDRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC27M2CP ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type TLC27M2CPE4 ACTIVE PDIP P 8 TLC27M2CPSLE OBSOLETE SO PS 8 TLC27M2CPSR ACTIVE SO PS 8 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC27M2CPSRG4 ACTIVE SO PS 8 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC27M2CPW ACTIVE TSSOP PW 8 150 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC27M2CPWG4 ACTIVE TSSOP PW 8 150 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC27M2CPWLE OBSOLETE TSSOP PW 8 TLC27M2CPWR ACTIVE TSSOP PW 8 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC27M2CPWRG4 ACTIVE TSSOP PW 8 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC27M2ID ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TBD Addendum-Page 2 Call TI Call TI Samples (Requires Login) TLC27M2BIDG4 TBD (3) Call TI Call TI PACKAGE OPTION ADDENDUM www.ti.com Orderable Device 27-Apr-2012 Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC27M2IDR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC27M2IDRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC27M2IP ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type TLC27M2IPE4 ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type TLC27M2IPW ACTIVE TSSOP PW 8 150 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC27M2IPWG4 ACTIVE TSSOP PW 8 150 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC27M2IPWR ACTIVE TSSOP PW 8 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC27M2IPWRG4 ACTIVE TSSOP PW 8 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC27M2MD ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC27M2MDG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC27M2MFKB OBSOLETE LCCC FK 20 TBD Call TI Call TI TLC27M2MJG OBSOLETE CDIP JG 8 TBD Call TI Call TI TLC27M2MJGB OBSOLETE CDIP JG 8 Call TI Call TI TLC27M7CD ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC27M7CDG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC27M7CDR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC27M7CDRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC27M7CP ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type TLC27M7CPE4 ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type TLC27M7CPSR ACTIVE SO PS 8 2000 Green (RoHS & no Sb/Br) Addendum-Page 3 Samples (Requires Login) TLC27M2IDG4 TBD (3) CU NIPDAU Level-1-260C-UNLIM PACKAGE OPTION ADDENDUM www.ti.com Orderable Device 27-Apr-2012 Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp (3) Samples (Requires Login) TLC27M7CPSRG4 ACTIVE SO PS 8 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC27M7ID ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC27M7IDG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC27M7IDR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC27M7IDRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC27M7IP ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type TLC27M7IPE4 ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type TLC27M7MFKB OBSOLETE LCCC FK 20 TBD Call TI Call TI TLC27M7MJG OBSOLETE CDIP JG 8 TBD Call TI Call TI TLC27M7MJGB OBSOLETE CDIP JG 8 TBD Call TI Call TI TLC27M7MUB OBSOLETE CFP U 10 TBD Call TI Call TI (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Addendum-Page 4 PACKAGE OPTION ADDENDUM www.ti.com 27-Apr-2012 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 5 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant TLC27M2ACDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 TLC27M2AIDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 TLC27M2BCDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 TLC27M2BIDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 TLC27M2CDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 TLC27M2CPSR SO PS 8 2000 330.0 16.4 8.2 6.6 2.5 12.0 16.0 Q1 TLC27M2CPWR TSSOP PW 8 2000 330.0 12.4 7.0 3.6 1.6 8.0 12.0 Q1 TLC27M2IDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 TLC27M2IPWR TSSOP PW 8 2000 330.0 12.4 7.0 3.6 1.6 8.0 12.0 Q1 TLC27M7CDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 TLC27M7CPSR SO PS 8 2000 330.0 16.4 8.2 6.6 2.5 12.0 16.0 Q1 TLC27M7IDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TLC27M2ACDR SOIC D 8 2500 340.5 338.1 20.6 TLC27M2AIDR SOIC D 8 2500 340.5 338.1 20.6 TLC27M2BCDR SOIC D 8 2500 340.5 338.1 20.6 TLC27M2BIDR SOIC D 8 2500 340.5 338.1 20.6 TLC27M2CDR SOIC D 8 2500 340.5 338.1 20.6 TLC27M2CPSR SO PS 8 2000 367.0 367.0 38.0 TLC27M2CPWR TSSOP PW 8 2000 367.0 367.0 35.0 TLC27M2IDR SOIC D 8 2500 340.5 338.1 20.6 TLC27M2IPWR TSSOP PW 8 2000 367.0 367.0 35.0 TLC27M7CDR SOIC D 8 2500 340.5 338.1 20.6 TLC27M7CPSR SO PS 8 2000 367.0 367.0 38.0 TLC27M7IDR SOIC D 8 2500 340.5 338.1 20.6 Pack Materials-Page 2 MECHANICAL DATA MCER001A - JANUARY 1995 - REVISED JANUARY 1997 JG (R-GDIP-T8) CERAMIC DUAL-IN-LINE 0.400 (10,16) 0.355 (9,00) 8 5 0.280 (7,11) 0.245 (6,22) 1 0.063 (1,60) 0.015 (0,38) 4 0.065 (1,65) 0.045 (1,14) 0.310 (7,87) 0.290 (7,37) 0.020 (0,51) MIN 0.200 (5,08) MAX Seating Plane 0.130 (3,30) MIN 0.023 (0,58) 0.015 (0,38) 0-15 0.100 (2,54) 0.014 (0,36) 0.008 (0,20) 4040107/C 08/96 NOTES: A. B. C. D. E. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. This package can be hermetically sealed with a ceramic lid using glass frit. Index point is provided on cap for terminal identification. Falls within MIL STD 1835 GDIP1-T8 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All semiconductor products (also referred to herein as "components") are sold subject to TI's terms and conditions of sale supplied at the time of order acknowledgment. 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