   
    
SLOS051E − O C TOBER 1987 − REVISED AUGUST 2008
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DTrimmed Offset Voltage:
TLC27M7 . . . 500 µV Max at 25°C,
VDD = 5 V
DInput Offset Voltage Drift ...Typically
0.1 µV/Month, Including the First 30 Days
DWide Range of Supply Voltages Over
Specified Temperature Ranges:
0°C to 70°C...3 V to 16 V
−40°C to 85°C...4 V to 16 V
−55°C to 125°C...4 V to 16 V
DSingle-Supply Operation
DCommon-Mode Input Voltage Range
Extends Below the Negative Rail (C-Suffix,
I-Suffix Types)
DLow Noise ...Typically 32 nV/√Hz at
f = 1 kHz
DLow Power ...Typically 2.1 mW at 25°C,
VDD = 5 V
DOutput Voltage Range Includes Negative
Rail
DHigh Input impedance ...10
12 Ω Typ
DESD-Protection Circuitry
DSmall-Outline Package Option Also
Available in Tape and Reel
DDesigned-In Latch-Up Immunity
1
2
3
4
8
7
6
5
1OUT
1IN −
1IN +
GND
VCC
2OUT
2IN −
2IN +
D, JG, P OR PW PACKAGE
(TOP VIEW)
3 2 1 20 19
910111213
4
5
6
7
8
18
17
16
15
14
NC
2OUT
NC
2IN −
NC
NC
1IN −
NC
1IN +
NC
FK PACKAGE
(TOP VIEW)
NC
1OUT
NC
NC NC
NC
GND
NC
NC − No internal connection
DD
V
2IN +
−800
Percentage of Units − %
V
IO
− Input Offset Voltage − µV
30
800
0−400 0 400
5
10
15
20
25 TA = 25°C
P Package
DISTRIBUTION OF TLC27M7
INPUT OFFSET VOLTAGE
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
340 Units Tested From 2 Wafer Lots
VDD = 5 V
AVAILABLE OPTIONS
VIOmax
PACKAGE
TA
V
IO
max
AT 25°CSMALL OUTLINE
(D) CHIP CARRIER
(FK) CERAMIC DIP
(JG) PLASTIC DIP
(P) TSSOP
(PW)
500 µV TLC27M7CD — — TLC27M7CP —
0°C to 70°C
2 mV TLC27M2BCD — — TLC27M2BCP —
0°C to 70°C5 mV TLC27M2ACD — — TLC27M2ACP —
10 mV TLC27M2CD — — TLC27M2CP TLC27M2CPW
500 µV TLC27M7ID — — TLC27M7IP —
−40°C to 85°C
2 mV TLC27M2BID — — TLC27M2BIP —
−40°C to 85°C5 mV TLC27M2AID — — TLC27M2AIP —
10 mV TLC27M2ID — — TLC27M2IP TLC27M2IPW
−55°C to 125°C
500 µV TLC27M7MD TLC27M7MFK TLC27M7MJG TLC27M7MP —
−55
°
C to 125
°
C
10 mV TLC27M2MD TLC27M2MFK TLC27M2MJG TLC27M2MP —
The D and PW package are available taped and reeled. Add R suffix to the device type (e.g.,TLC27M7CDR). For the most current package and
ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com.
Copyright 1987 − 2008, Texas Instruments Incorporated
       !"# $%
$   ! ! &   ' 
$$ ()% $ !* $  #) #$
*  ## !%
LinCMOS is a trademark of Texas Instruments. All other trademarks are the property of their respective owners.
   
    
SLOS051E − O C TOBER 1987 − REVISED AUGUST 2008
2POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
description
The TLC27M2 and TLC27M7 dual operational amplifiers combine a wide range of input offset voltage grades
with low of fset voltage drift, high input impedance, low noise, and speeds approaching that of general-purpose
bipolar devices.These devices use Texas Instruments silicon-gate LinCMOStechnology, which provides offset
voltage stability far exceeding the stability available with conventional metal-gate processes.
The extremely high input impedance, low bias currents, and high slew rates make these cost-effective devices
ideal for applications which have previously been reserved for general-purpose bipolar products, but with only
a fraction of the power consumption. Four offset voltage grades are available (C-suffix and I-suffix types),
ranging from the low-cost TLC27M2 (10 mV) to the high-precision TLC27M7 (500 µV). These advantages, in
combination with good common-mode rejection and supply voltage rejection, make these devices a good
choice for new state-of-the-art designs as well as for upgrading existing designs.
In general, many features associated with bipolar technology are available on LinCMOS operational amplifiers,
without the power penalties of bipolar technology. General applications such as transducer interfacing, analog
calculations, amplifier blocks, active filters, and signal buffering are easily designed with the TLC27M2 and
TLC27M7. The devices also exhibit low voltage single-supply operation, making them ideally suited for remote
and inaccessible battery-powered applications. The common-mode input voltage range includes the negative
rail.
A wide range of packaging options is available, including small-outline and chip-carrier versions for high-density
system applications.
The device inputs and outputs are designed to withstand −100-mA surge currents without sustaining latch-up.
The TLC27M2 and TLC27M7 incorporate internal ESD-protection circuits that prevent functional failures at
voltages up to 2000 V as tested under MIL-STD-883C, Method 3015.2; however, care should be exercised in
handling th e s e d e v i c e s a s exposure to ESD may result in the degradation of th e device parametric performance.
The C-suffix devices are characterized for operation from 0°C to 70°C. The I-suffix devices are characterized
for operation from −40°C to 85°C. The M-suffix devices are characterized for operation over the full military
temperature range of −55°C to 125°C.
   
    
SLOS051E − O C TOBER 1987 − REVISED AUGUST 2008
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
equivalent schematic (each amplifier)
VDD
P4P3
R6
N5R2
P2
R1
P1
IN −
IN +
N1
R3 D1 R4 D2
N2
GND
N3
R5 C1
N4 R7
N6 N7
OUT
P6P5
   
    
SLOS051E − O C TOBER 1987 − REVISED AUGUST 2008
4POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage, VDD (see Note 1) 18 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Differential input voltage, VID (see Note 2) ±VDD
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, VI (any input) − 0.3 V to VDD
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input current, II ±5 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output current, IO (each output) ±30 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Total current into VDD 45 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Total current out of GND 45 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Duration of short-circuit current at (or below) 25°C (see Note 3) Unlimited. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous total dissipation See Dissipation Rating Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating free-air temperature, TA: C suffix 0°C to 70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I suffix −40°C to 85°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
M suffix −55°C to 125°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range −65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Case temperature for 60 seconds: FK package 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: D or P package 260°C. . . . . . . . . . . . . . . . .
Lead temperature 1,6 mm (1/16 inch) from case for 60 seconds: JG package 300°C. . . . . . . . . . . . . . . . . . . .
†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values, except differential voltages, are with respect to network ground.
2. Differential voltages are at IN+ with respect to IN−.
3. The output may be shorted to either supply. Temperature and/or supply voltages must be limited to ensure that the maximum
dissipation rating is not exceeded (see application section).
DISSIPATION RATING TABLE
PACKAGE TA ≤ 25°C
POWER RATING DERATING FACTOR
ABOVE TA = 25°CTA = 70°C
POWER RATING TA = 85°C
POWER RATING TA = 125°C
POWER RATING
D725 mW 5.8 mW/°C464 mW 377 mW
FK 1375 mW 11.0 mW/°C 880 mW 715 mW 275 mW
JG 1050 mW 8.4 mW/°C 672 mW 546 mW 210 mW
P1000 mW 8.0 mW/°C640 mW 520 mW
recommended operating conditions
C SUFFIX I SUFFIX M SUFFIX
UNIT
MIN MAX MIN MAX MIN MAX
UNIT
Supply voltage, VDD 3 16 4 16 4 16 V
Common-mode input voltage, VIC
VDD = 5 V −0.2 3.5 −0.2 3.5 0 3.5
V
Common-mode input voltage, VIC VDD = 10 V −0.2 8.5 −0.2 8.5 0 8.5 V
Operating free-air temperature, TA0 70 −40 85 −55 125 °C
   
    
SLOS051E − O C TOBER 1987 − REVISED AUGUST 2008
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics at specified free-air temperature, VDD = 5 V (unless otherwise noted)
PARAMETER TEST CONDITIONS TA†
TLC27M2C
TLC27M2AC
TLC27M2BC
TLC27M7C UNIT
A
MIN TYP MAX
TLC27M2C
VIC = 0,
25°C 1.1 10
TLC27M2C
RS = 50 Ω,
VIC = 0,
RI = 100 kΩFull range 12
mV
TLC27M2AC
VIC = 0,
25°C 0.9 5 mV
VIO
Input offset voltage
TLC27M2AC
RS = 50 Ω,
VIC = 0,
RI = 100 kΩFull range 6.5
VIO Input offset voltage
TLC27M2BC
VIC = 0,
25°C 220 2000
TLC27M2BC
RS = 50 Ω,
VIC = 0,
RI = 100 kΩFull range 3000
V
TLC27M7C
VIC = 0,
25°C 185 500 µV
TLC27M7C
RS = 50 Ω,
VIC = 0,
RI = 100 kΩFull range 1500
αVIO Average temperature coefficient of input
offset voltage 25°C to
70°C1.7 µV/°C
IIO
Input offset current (see Note 4)
VIC = 2.5 V
25°C 0.1 60
pA
IIO Input offset current (see Note 4) VO = 2.5 V, VIC = 2.5 V 70°C7 300 pA
IIB
Input bias current (see Note 4)
VIC = 2.5 V
25°C 0.6 60
pA
IIB Input bias current (see Note 4) VO = 2.5 V, VIC = 2.5 V 70°C40 600 pA
VICR
Common-mode input voltage range
25°C−0.2
to
4
−0.3
to
4.2 V
VICR
Common-mode input voltage range
(see Note 5) Full range −0.2
to
3.5 V
25°C 3.2 3.9
V
OH
High-level output voltage V
= 100 mV, R
L
= 100 kΩ0°C3 3.9 V
VOH
High-level output voltage
RL = 100 kΩ
70°C 3 4
V
25°C 0 50
V
OL
Low-level output voltage V
= −100 mV, I
OL
= 0 0°C0 50 mV
VOL
Low-level output voltage
IOL = 0
70°C 0 50
mV
Large-signal differential voltage
25°C 25 170
A
VD
Large-signal differential voltage
amplification
V
= 0.25 V to 2 V
R
L
= 100 kΩ0°C15 200 V/mV
AVD
amplification
RL = 100 kΩ
70°C 15 140
V/mV
25°C 65 91
CMRR Common-mode rejection ratio V
IC
= V
ICR
min 0°C 60 91 dB
CMRR
Common-mode rejection ratio
VIC = VICRmin
70°C 60 92
dB
Supply-voltage rejection ratio
25°C 70 93
k
SVR
Supply-voltage rejection ratio
(∆VDD/∆VIO)
V
= 5 V to 10 V, V
O
= 1.4 V 0°C60 92 dB
kSVR
(∆VDD/∆VIO)
VO = 1.4 V
70°C 60 94
dB
VIC = 2.5 V,
25°C 210 560
I
DD
Supply current (two amplifiers) VO = 2.5 V,
VIC = 2.5 V, 0°C250 640 µA
IDD
Supply current (two amplifiers)
70°C 170 440
µA
†Full range is 0°C to 70°C.
NOTES: 4. The typical values of input bias current and input offset current below 5 pA were determined mathematically.
5. This range also applies to each input individually.
   
    
SLOS051E − O C TOBER 1987 − REVISED AUGUST 2008
6POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics at specified free-air temperature, VDD = 10 V (unless otherwise noted)
PARAMETER TEST CONDITIONS TA†
TLC27M2C
TLC27M2AC
TLC27M2BC
TLC27M7C UNIT
MIN TYP MAX
TLC27M2C
VIC = 0,
25°C 1.1 10
TLC27M2C
RS = 50 Ω,
VIC = 0,
RL = 100 kΩFull range 12
mV
TLC27M2AC
VIC = 0,
25°C 0.9 5 mV
VIO
Input offset voltage
TLC27M2AC
RS = 50 Ω,
VIC = 0,
RL = 100 kΩFull range 6.5
VIO Input offset voltage
TLC27M2BC
VIC = 0,
25°C 224 2000
TLC27M2BC
RS = 50 Ω,
VIC = 0,
RL = 100 kΩFull range 3000
V
TLC27M7C
VIC = 0,
25°C 190 800 µV
TLC27M7C
RS = 50 Ω,
VIC = 0,
RL = 100 kΩFull range 1900
αVIO Average temperature coefficient of input
offset voltage 25°C to
70°C2.1 µV/°C
IIO
Input offset current (see Note 4)
VIC = 5 V
25°C 0.1 60
pA
IIO Input offset current (see Note 4) VO = 5 V, VIC = 5 V 70°C7 300 pA
IIB
Input bias current (see Note 4)
VIC = 5 V
25°C 0.7 60
pA
IIB Input bias current (see Note 4) VO = 5 V, VIC = 5 V 70°C50 600 pA
VICR
Common-mode input voltage range
25°C−0.2
to
9
−0.3
to
9.2 V
VICR
Common-mode input voltage range
(see Note 5) Full range −0.2
to
8.5 V
25°C 8 8.7
V
OH
High-level output voltage V
= 100 mV, R
L
= 100 kΩ0°C7.8 8.7 V
VOH
High-level output voltage
RL = 100 kΩ
70°C 7.8 8.7
V
25°C 0 50
V
OL
Low-level output voltage V
= −100 mV, I
OL
= 0 0°C0 50 mV
VOL
Low-level output voltage
IOL = 0
70°C 0 50
mV
Large-signal differential voltage
25°C 25 275
A
VD
Large-signal differential voltage
amplification
V
= 1 V to 6 V, R
L
= 100 kΩ0°C15 320 V/mV
AVD
amplification
RL = 100 kΩ
70°C 15 230
V/mV
25°C 65 94
CMRR Common-mode rejection ratio V
IC
= V
ICR
min 0°C 60 94 dB
CMRR
Common-mode rejection ratio
VIC = VICRmin
70°C 60 94
dB
Supply-voltage rejection ratio
25°C 70 93
k
SVR
Supply-voltage rejection ratio
(∆VDD/∆VIO)
V
= 5 V to 10 V, V
O
= 1.4 V 0°C60 92 dB
kSVR
(∆VDD/∆VIO)
VO = 1.4 V
70°C 60 94
dB
VIC = 5 V,
25°C 285 600
I
DD
Supply current (two amplifiers) VO = 5 V,
VIC = 5 V, 0°C345 800 µA
IDD
Supply current (two amplifiers)
70°C 220 560
µA
†Full range is 0°C to 70°C.
NOTES: 4. The typical values of input bias current and input offset current below 5 pA were determined mathematically.
5. This range also applies to each input individually.
   
    
SLOS051E − O C TOBER 1987 − REVISED AUGUST 2008
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics at specified free-air temperature, VDD = 5 V (unless otherwise noted)
PARAMETER TEST CONDITIONS TA†
TLC27M2I
TLC27M2AI
TLC27M2BI
TLC27M7I UNIT
MIN TYP MAX
TLC27M2I
VIC = 0,
25°C 1.1 10
TLC27M2I
RS = 50 Ω,
VIC = 0,
RL = 100 kΩFull range 13
mV
TLC27M2AI
VIC = 0,
25°C 0.9 5 mV
VIO
Input offset voltage
TLC27M2AI
RS = 50 Ω,
VIC = 0,
RL = 100 kΩFull range 7
VIO Input offset voltage
TLC27M2BI
VIC = 0,
25°C 220 2000
TLC27M2BI
RS = 50 Ω,
VIC = 0,
RL = 100 kΩFull range 3500
V
TLC27M7I
VIC = 0,
25°C 185 500 µV
TLC27M7I
RS = 50 Ω,
VIC = 0,
RL = 100 kΩFull range 2000
αVIO Average temperature coefficient of input
offset voltage 25°C to
85°C1.7 µV/°C
IIO
Input offset current (see Note 4)
VIC = 2.5 V
25°C 0.1 60
pA
IIO Input offset current (see Note 4) VO = 2.5 V, VIC = 2.5 V 85°C24 1000 pA
IIB
Input bias current (see Note 4)
VIC = 2.5 V
25°C 0.6 60
pA
IIB Input bias current (see Note 4) VO = 2.5 V, VIC = 2.5 V 85°C200 2000 pA
VICR
Common-mode input voltage range
25°C−0.2
to
4
−0.3
to
4.2 V
VICR
Common-mode input voltage range
(see Note 5) Full range −0.2
to
3.5 V
25°C 3.2 3.9
V
OH
High-level output voltage V
= 100 mV, R
L
= 100 kΩ−40°C3 3.9 V
VOH
High-level output voltage
RL = 100 kΩ
85°C 3 4
V
25°C 0 50
V
OL
Low-level output voltage V
= −100 mV, I
OL
= 0 −40°C0 50 mV
VOL
Low-level output voltage
IOL = 0
85°C 0 50
mV
Large-signal differential voltage
25°C 25 170
A
VD
Large-signal differential voltage
amplification
V
= 0.25 V to 2 V
R
L
= 100 kΩ−40°C15 270 V/mV
AVD
amplification
RL = 100 kΩ
85°C 15 130
V/mV
25°C 65 91
CMRR Common-mode rejection ratio V
IC
= V
ICR
min −40°C 60 90 dB
CMRR
Common-mode rejection ratio
VIC = VICRmin
85°C 60 90
dB
Supply-voltage rejection ratio
25°C 70 93
k
SVR
Supply-voltage rejection ratio
(∆VDD/∆VIO)
V
= 5 V to 10 V, V
O
= 1.4 V −40°C60 91 dB
kSVR
(∆VDD/∆VIO)
VO = 1.4 V
85°C 60 94
dB
VIC = 2.5 V,
25°C 210 560
I
DD
Supply current (two amplifiers) VO = 2.5 V,
VIC = 2.5 V, −40°C315 800 µA
IDD
Supply current (two amplifiers)
85°C 160 400
µA
†Full range is −40°C to 85°C.
NOTES: 4. The typical values of input bias current and input offset current below 5 pA were determined mathematically.
5. This range also applies to each input individually.
   
    
SLOS051E − O C TOBER 1987 − REVISED AUGUST 2008
8POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics at specified free-air temperature, VDD = 10 V (unless otherwise noted)
PARAMETER TEST CONDITIONS TA†
TLC27M2I
TLC27M2AI
TLC27M2BI
TLC27M7I UNIT
MIN TYP MAX
TLC27M2I
VIC = 0,
25°C 1.1 10
TLC27M2I
RS = 50 Ω,
VIC = 0,
RL = 100 kΩFull range 13
mV
TLC27M2AI
VIC = 0,
25°C 0.9 5 mV
VIO
Input offset voltage
TLC27M2AI
RS = 50 Ω,
VIC = 0,
RL = 100 kΩFull range 7
VIO Input offset voltage
TLC27M2BI
VIC = 0,
25°C 224 2000
TLC27M2BI
RS = 50 Ω,
VIC = 0,
RL = 100 kΩFull range 3500
V
TLC27M7I
VIC = 0,
25°C 190 800 µV
TLC27M7I
RS = 50 Ω,
VIC = 0,
RL = 100 kΩFull range 2900
αVIO Average temperature coefficient of input
offset voltage 25°C to
85°C2.1 µV/°C
IIO
Input offset current (see Note 4)
VIC = 5 V
25°C 0.1 60
pA
IIO Input offset current (see Note 4) VO = 5 V, VIC = 5 V 85°C26 1000 pA
25°C 0.7 60
IIB Input bias current (see Note 4) VO = 5 V, VIC = 5 V 85°C220 200
0pA
VICR
Common-mode input voltage range
25°C−0.2
to
9
−0.3
to
9.2 V
VICR
Common-mode input voltage range
(see Note 5) Full range −0.2
to
8.5 V
25°C 8 8.7
V
OH
High-level output voltage V
= 100 mV, R
L
= 100 kΩ−40°C7.8 8.7 V
VOH
High-level output voltage
RL = 100 kΩ
85°C 7.8 8.7
V
25°C 0 50
V
OL
Low-level output voltage V
= −100 mV, I
OL
= 0 −40°C0 50 mV
VOL
Low-level output voltage
IOL = 0
85°C 0 50
mV
Large-signal differential voltage
25°C 25 275
A
VD
Large-signal differential voltage
amplification
V
= 1 V to 6 V, R
L
= 100 kΩ−40°C15 390 V/mV
AVD
amplification
RL = 100 kΩ
85°C 15 220
V/mV
25°C 65 94
CMRR Common-mode rejection ratio V
IC
= V
ICR
min −40°C 60 93 dB
CMRR
Common-mode rejection ratio
VIC = VICRmin
85°C 60 94
dB
Supply-voltage rejection ratio
25°C 70 93
k
SVR
Supply-voltage rejection ratio
(∆VDD/∆VIO)
V
= 5 V to 10 V, V
O
= 1.4 V −40°C60 91 dB
kSVR
(∆VDD/∆VIO)
VO = 1.4 V
85°C 60 94
dB
VIC = 5 V,
25°C 285 600
I
DD
Supply current VO = 5 V,
VIC = 5 V, −40°C450 900 µA
IDD
Supply current
85°C 205 520
µA
†Full range is −40°C to 85°C.
NOTES: 4. The typical values of input bias current and input offset current below 5 pA were determined mathematically.
5. This range also applies to each input individually.
   
    
SLOS051E − O C TOBER 1987 − REVISED AUGUST 2008
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics at specified free-air temperature, VDD = 5 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
†TLC27M2M
TLC27M7M
UNIT
PARAMETER
TEST CONDITIONS
TA†
MIN TYP MAX
UNIT
TLC27M2M
VIC = 0,
25°C 1.1 10
VIO
Input offset voltage
TLC27M2M
RS = 50 Ω,
VIC = 0,
RL = 100 kΩFull range 12
mV
VIO Input offset voltage
TLC27M7M
VIC = 0,
25°C 185 500 mV
TLC27M7M
RS = 50 Ω,
VIC = 0,
RL = 100 kΩFull range 3750
αVIO Average temperature coefficient of input
offset voltage 25°C to
125°C1.7 µV/°C
IIO
Input offset current (see Note 4)
VIC = 2.5 V
25°C 0.1 60 pA
IIO Input offset current (see Note 4) VO = 2.5 V, VIC = 2.5 V 125°C1.4 15 nA
IIB
Input bias current (see Note 4)
VIC = 2.5 V
25°C 0.6 60 pA
IIB Input bias current (see Note 4) VO = 2.5 V, VIC = 2.5 V 125°C9 35 nA
VICR
Common-mode input voltage range
25°C0
to
4
−0.3
to
4.2 V
VICR
Common-mode input voltage range
(see Note 5) Full range 0
to
3.5 V
25°C 3.2 3.9
V
OH
High-level output voltage V
= 100 mV, R
L
= 100 kΩ−55°C3 3.9 V
VOH
High-level output voltage
RL = 100 kΩ
125°C 3 4
V
25°C 0 50
V
OL
Low-level output voltage V
= −100 mV, I
OL
= 0 −55°C0 50 mV
VOL
Low-level output voltage
IOL = 0
125°C 0 50
mV
Large-signal differential voltage
25°C 25 170
A
VD
Large-signal differential voltage
amplification
V
= 0.25 V to 2 V
R
L
= 100 kΩ−55°C15 290 V/mV
AVD
amplification
RL = 100 kΩ
125°C 15 120
V/mV
25°C 65 91
CMRR Common-mode rejection ratio V
IC
= V
ICR
min −55°C 60 89 dB
CMRR
Common-mode rejection ratio
VIC = VICRmin
125°C 60 91
dB
Supply-voltage rejection ratio
25°C 70 93
k
SVR
Supply-voltage rejection ratio
(∆VDD/∆VIO)
V
= 5 V to 10 V, V
O
= 1.4 V −55°C60 91 dB
kSVR
(∆VDD/∆VIO)
VO = 1.4 V
125°C 60 94
dB
VIC = 2.5 V,
25°C 210 560
I
DD
Supply current (two amplifiers) VO = 2.5 V,
VIC = 2.5 V, −55°C340 880 µA
IDD
Supply current (two amplifiers)
125°C 140 360
µA
†Full range is −55°C to 125°C.
NOTES: 4. The typical values of input bias current and input offset current below 5 pA were determined mathematically.
5. This range also applies to each input individually.
   
    
SLOS051E − O C TOBER 1987 − REVISED AUGUST 2008
10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics at specified free-air temperature, VDD = 10 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
†TLC27M2M
TLC27M7M
UNIT
PARAMETER
TEST CONDITIONS
TA†
MIN TYP MAX
UNIT
TLC27M2M
VIC = 0,
25°C 1.1 10
VIO
Input offset voltage
TLC27M2M
RS = 50 Ω,
VIC = 0,
RL = 100 kΩFull range 12
mV
VIO Input offset voltage
TLC27M7M
VIC = 0,
25°C 190 800 mV
TLC27M7M
RS = 50 Ω,
VIC = 0,
RL = 100 kΩFull range 4300
αVIO Average temperature coefficient of input
offset voltage 25°C to
125°C2.1 µV/°C
IIO
Input offset current (see Note 4)
VIC = 5 V
25°C 0.1 60
pA
IIO Input offset current (see Note 4) VO = 5 V, VIC = 5 V 125°C1.8 15 pA
IIB
Input bias current (see Note 4)
VIC = 5 V
25°C 0.7 60
pA
IIB Input bias current (see Note 4) VO = 5 V, VIC = 5 V 125°C10 35 pA
VICR
Common-mode input voltage range
25°C0
to
9
−0.3
to
9.2 V
VICR
Common-mode input voltage range
(see Note 5) Full range 0
to
8.5 V
25°C 8 8.7
V
OH
High-level output voltage V
= 100 mV, R
L
= 100 kΩ−55°C7.8 8.6 V
VOH
High-level output voltage
RL = 100 kΩ
125°C 7.8 8.8
V
25°C 0 50
V
OL
Low-level output voltage V
= −100 mV, I
OL
= 0 −55°C0 50 mV
VOL
Low-level output voltage
IOL = 0
125°C 0 50
mV
Large-signal differential voltage
25°C 25 275
A
VD
Large-signal differential voltage
amplification
V
= 1 V to 6 V, R
L
= 100 kΩ−55°C15 420 V/mV
AVD
amplification
RL = 100 kΩ
125°C 15 190
V/mV
25°C 65 94
CMRR Common-mode rejection ratio V
IC
= V
ICR
min −55°C 60 93 dB
CMRR
Common-mode rejection ratio
VIC = VICRmin
125°C 60 93
dB
Supply-voltage rejection ratio
25°C 70 93
k
SVR
Supply-voltage rejection ratio
(∆VDD/∆VIO)
V
= 5 V to 10 V, V
O
= 1.4 V −55°C60 91 dB
kSVR
(∆VDD/∆VIO)
VO = 1.4 V
125°C 60 94
dB
VIC = 5 V,
25°C 285 600
I
DD
Supply current (two amplifiers) VO = 5 V,
VIC = 5 V, −55°C490 1000 µA
IDD
Supply current (two amplifiers)
125°C 180 480
µA
†Full range is −55°C to 125°C.
NOTES: 4. The typical values of input bias current and input offset current below 5 pA were determined mathematically.
5. This range also applies to each input individually.
   
    
SLOS051E − O C TOBER 1987 − REVISED AUGUST 2008
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
operating characteristics at specified free-air temperature, VDD = 5 V
PARAMETER TEST CONDITIONS TA
TLC27M2C
TLC27M2AC
TLC27M2BC
TLC27M7C UNIT
MIN TYP MAX
25°C 0.43
R = 100 k ,
V
I(PP)
= 1 V 0°C 0.46
SR
Slew rate at unity gain
RL = 100 kΩ,
CL = 20 pF,
VI(PP) = 1 V
70°C 0.36
V/ s
SR Slew rate at unity gain
L
C
L
= 20 pF,
See Figure 1
25°C 0.40 V/µs
See Figure 1
V
I(PP)
= 2.5 V 0°C 0.43
VI(PP) = 2.5 V
70°C 0.34
VnEquivalent input noise voltage f = 1 kHz,
See Figure 2 RS = 20 Ω,25°C 32 nV/√Hz
VO = VOH,
CL = 20 pF,
25°C 55
B
OM
Maximum output-swing bandwidth VO = VOH,
RL = 100 kΩ,
CL = 20 pF,
See Figure 1
0°C 60 kHz
BOM
Maximum output-swing bandwidth
RL = 100 kΩ,
See Figure 1
70°C 50
VI = 10 mV,
CL = 20 pF,
25°C 525
B
1
Unity-gain bandwidth VI = 10 mV,
See Figure 3
CL = 20 pF, 0°C600 kHz
B1
Unity-gain bandwidth
See Figure 3
70°C 400
VI = 10 mV,
f = B1,
25°C 40°
φ
m
Phase margin VI = 10 mV,
CL = 20 pF,
f = B1,
See Figure 3
0°C 41°
φm
Phase margin
CL = 20 pF,
See Figure 3
70°C 39°
operating characteristics at specified free-air temperature, VDD = 10 V
PARAMETER TEST CONDITIONS TA
TLC27M2C
TLC27M2AC
TLC27M2BC
TLC27M7C UNIT
MIN TYP MAX
25°C 0.62
R = 100 k ,
V
I(PP)
= 1 V 0°C 0.67
SR
Slew rate at unity gain
RL = 100 kΩ,
CL = 20 pF,
VI(PP) = 1 V
70°C 0.51
V/ s
SR Slew rate at unity gain
L
C
L
= 20 pF,
See Figure 1
25°C 0.56 V/µs
See Figure 1
V
I(PP)
= 5.5 V 0°C 0.61
VI(PP) = 5.5 V
70°C 0.46
VnEquivalent input noise voltage f = 1 kHz,
See Figure 2 RS = 20 Ω,25°C 32 nV/√Hz
VO = VOH,
CL = 20 pF,
25°C 35
B
OM
Maximum output-swing bandwidth VO = VOH,
RL = 100 kΩ,
CL = 20 pF,
See Figure 1
0°C 40 kHz
BOM
Maximum output-swing bandwidth
RL = 100 kΩ,
See Figure 1
70°C 30
kHz
VI = 10 mV,
CL = 20 pF,
25°C 635
B
1
Unity-gain bandwidth VI = 10 mV,
See Figure 3
CL = 20 pF, 0°C710 kHz
B1
Unity-gain bandwidth
See Figure 3
70°C 510
kHz
VI = 10 mV,
f = B1,
25°C 43°
φ
m
Phase margin VI = 10 mV,
CL = 20 pF,
f = B1,
See Figure 3
0°C 44°
φm
Phase margin
CL = 20 pF,
See Figure 3
70°C 42°
   
    
SLOS051E − O C TOBER 1987 − REVISED AUGUST 2008
12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
operating characteristics at specified free-air temperature, VDD = 5 V
PARAMETER TEST CONDITIONS TA
TLC27M2I
TLC27M2AI
TLC27M2BI
TLC27M7I UNIT
MIN TYP MAX
25°C 0.43
R = 100 k ,
V
I(PP)
= 1 V −40°C 0.51
SR
Slew rate at unity gain
RL = 100 kΩ,
CL = 20 pF,
VI(PP) = 1 V
85°C 0.35
V/ s
SR Slew rate at unity gain
L
C
L
= 20 pF,
See Figure 1
25°C 0.40 V/µs
See Figure 1
V
I(PP)
= 2.5 V −40°C 0.48
VI(PP) = 2.5 V
85°C 0.32
VnEquivalent input noise voltage f = 1 kHz,
See Figure 2 RS = 20 Ω,25°C 32 nV/√Hz
VO = VOH,
CL = 20 pF,
25°C 55
B
OM
Maximum output-swing bandwidth VO = VOH,
RL = 100 kΩ,
CL = 20 pF,
See Figure 1
−40°C 75 kHz
BOM
Maximum output-swing bandwidth
RL = 100 kΩ,
See Figure 1
85°C 45
kHz
VI = 10 mV,
CL = 20 pF,
25°C 525
B
1
Unity-gain bandwidth VI = 10 mV,
See Figure 3
CL = 20 pF, −40°C770 kHz
B1
Unity-gain bandwidth
See Figure 3
85°C 370
kHz
VI = 10 mV,
f = B1,
25°C 40°
φ
m
Phase margin VI = 10 mV,
CL = 20 pF,
f = B1,
See Figure 3
−40°C 43°
φm
Phase margin
CL = 20 pF,
See Figure 3
85°C 38°
operating characteristics at specified free-air temperature, VDD = 10 V
PARAMETER TEST CONDITIONS TA
TLC27M2I
TLC27M2AI
TLC27M2BI
TLC27M7I UNIT
MIN TYP MAX
25°C 0.62
R = 100 k ,
V
I(PP)
= 1 V −40°C 0.77
SR
Slew rate at unity gain
RL = 100 kΩ,
CL = 20 pF,
VI(PP) = 1 V
85°C 0.47
V/ s
SR Slew rate at unity gain
L
C
L
= 20 pF,
See Figure 1
25°C 0.56 V/µs
See Figure 1
V
I(PP)
= 5.5 V −40°C 0.70
VI(PP) = 5.5 V
85°C 0.44
VnEquivalent input noise voltage f = 1 kHz,
See Figure 2 RS = 20 Ω,25°C 32 nV/√Hz
VO = VOH,
CL = 20 pF,
25°C 35
B
OM
Maximum output-swing bandwidth VO = VOH,
RL = 100 kΩ,
CL = 20 pF,
See Figure 1
−40°C 45 kHz
BOM
Maximum output-swing bandwidth
RL = 100 kΩ,
See Figure 1
85°C 25
kHz
VI = 10 mV,
CL = 20 pF,
25°C 635
B
1
Unity-gain bandwidth VI = 10 mV,
See Figure 3
CL = 20 pF, −40°C880 kHz
B1
Unity-gain bandwidth
See Figure 3
85°C 480
kHz
VI = 10 mV,
f = B1,
25°C 43°
φ
m
Phase margin VI = 10 mV,
CL = 20 pF,
f = B1,
See Figure 3
−40°C 46°
φm
Phase margin
CL = 20 pF,
See Figure 3
85°C 41°
   
    
SLOS051E − O C TOBER 1987 − REVISED AUGUST 2008
13
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
operating characteristics at specified free-air temperature, VDD = 5 V
PARAMETER TEST CONDITIONS T
A
TLC27M2M
TLC27M7M
UNIT
PARAMETER
TEST CONDITIONS
TA
MIN TYP MAX
UNIT
25°C 0.43
R = 100 k ,
V
I(PP)
= 1 V −55°C 0.54
SR
Slew rate at unity gain
RL = 100 kΩ
,
CL = 20 pF,
VI(PP) = 1 V
125°C 0.29
V/ s
SR Slew rate at unity gain
L
C
L
= 20 pF,
See Figure 1
25°C 0.40 V/µs
See Figure 1
V
I(PP)
= 2.5 V −55°C 0.49
VI(PP) = 2.5 V
125°C 0.28
VnEquivalent input noise voltage f = 1 kHz,
See Figure 2 RS = 20 Ω,25°C 32 nV/√Hz
VO = VOH,
CL = 20 pF,
25°C 55
B
OM
Maximum output-swing bandwidth VO = VOH,
RL = 100 kΩ,
CL = 20 pF,
See Figure 1
−55°C 80 kHz
BOM
Maximum output-swing bandwidth
RL = 100 kΩ,
See Figure 1
125°C 40
kHz
VI = 10 mV,
CL = 20 pF,
25°C 525
B
1
Unity-gain bandwidth VI = 10 mV,
See Figure 3
CL = 20 pF, −55°C850 kHz
B1
Unity-gain bandwidth
See Figure 3
125°C 330
kHz
VI = 10 mV,
f = B1,
25°C 40°
φ
m
Phase margin VI = 10 mV,
CL = 20 pF,
f = B1,
See Figure 3
−55°C 44°
φm
Phase margin
CL = 20 pF,
See Figure 3
125°C 36°
operating characteristics at specified free-air temperature, VDD = 10 V
PARAMETER TEST CONDITIONS T
A
TLC27M2M
TLC27M7M
UNIT
PARAMETER
TEST CONDITIONS
TA
MIN TYP MAX
UNIT
25°C 0.62
R = 100 k ,
V
I(PP)
= 1 V −55°C 0.81
SR
Slew rate at unity gain
RL = 100 kΩ
,
CL = 20 pF,
VI(PP) = 1 V
125°C 0.38
V/ s
SR Slew rate at unity gain
L
C
L
= 20 pF,
See Figure 1
25°C 0.56 V/µs
See Figure 1
V
I(PP)
= 5.5 V −55°C 0.73
VI(PP) = 5.5 V
125°C 0.35
VnEquivalent input noise voltage f = 1 kHz,
See Figure 2 RS = 20 Ω,25°C 32 nV/√Hz
VO = VOH,
CL = 20 pF,
25°C 35
B
OM
Maximum output-swing bandwidth VO = VOH,
RL = 100 kΩ,
CL = 20 pF,
See Figure 1
−55°C 50 kHz
BOM
Maximum output-swing bandwidth
RL = 100 kΩ,
See Figure 1
125°C 20
kHz
VI = 10 mV,
CL = 20 pF,
25°C 635
B
1
Unity gain bandwidth VI = 10 mV,
See Figure 3
CL = 20 pF, −55°C960 kHz
B1
Unity gain bandwidth
See Figure 3
125°C 440
kHz
VI = 10 mV,
f = B1,
25°C 43°
φ
m
Phase margin VI = 10 mV,
CL = 20 pF,
f = B1,
See Figure 3
−55°C 47°
φm
Phase margin
CL = 20 pF,
See Figure 3
125°C 39°
   
    
SLOS051E − O C TOBER 1987 − REVISED AUGUST 2008
14 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
single-supply versus split-supply test circuits
Because the TLC27M2 and TLC27M7 are optimized for single-supply operation, circuit configurations used for
the various tests often present some inconvenience since the input signal, in many cases, must be offset from
ground. This inconvenience can be avoided by testing the device with split supplies and the output load tied to
the negative rail. A comparison of single-supply versus split-supply test circuits is shown below . The use of either
circuit gives the same result.
−
+
VDD
CLRL
VO
VIVI
VO
RL
CL
−
+
VDD+
VDD−
(a) SINGLE SUPPLY (b) SPLIT SUPPLY
Figure 1. Unity-Gain Amplifier
1/2 VDD
VDD
−
+
VDD+
−
+
20 Ω
VO
2 kΩ
20 Ω
VDD−
20 Ω20 Ω
2 kΩ
VO
(b) SPLIT SUPPLY(a) SINGLE SUPPLY
Figure 2. Noise-Test Circuit
VDD
−
+
10 kΩ
VO
100 Ω
CL
1/2 VDD
VIVI
CL
100 Ω
VO
10 kΩ
−
+
VDD+
VDD−
(a) SINGLE SUPPLY (b) SPLIT SUPPLY
Figure 3. Gain-of-100 Inverting Amplifier
   
    
SLOS051E − O C TOBER 1987 − REVISED AUGUST 2008
15
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PARAMETER MEASUREMENT INFORMATION
input bias current
Because of the high input impedance of the TLC27M2 and TLC27M7 operational amplifiers, attempts to
measure the input bias current can result in erroneous readings. The bias current at normal room ambient
temperature is typically less than 1 pA, a value that is easily exceeded by leakages on the test socket. Two
suggestions are offered to avoid erroneous measurements:
1. Isolate the device from other potential leakage sources. Use a grounded shield around and between the
device inputs (see Figure 4). Leakages that would otherwise flow to the inputs are shunted away.
2. Compensate for the leakage of the test socket by actually performing an input bias current test (using
a picoammeter) with no device in the test socket. The actual input bias current can then be calculated
by subtracting the open-socket leakage readings from the readings obtained with a device in the test
socket.
One word of caution—many automatic testers as well as some bench-top operational amplifier testers
use the servo-loop technique with a resistor in series with the device input to measure the input bias
current (the voltage drop across the series resistor is measured and the bias current is calculated). This
method requires that a device be inserted into the test socket to obtain a correct reading; therefore, an
open-socket reading is not feasible using this method.
V = VIC
41
5
8
85
Figure 4. Isolation Metal Around Device Inputs (JG and P packages)
low-level output voltage
To obtain low-supply-voltage operation, some compromise was necessary in the input stage. This compromise
results in the device low-level output being dependent on both the common-mode input voltage level as well
as the differential input voltage level. When attempting to correlate low-level output readings with those quoted
in the electrical specifications, these two conditions should be observed. If conditions other than these are to
be used, please refer to Figures 14 through 19 in the Typical Characteristics of this data sheet.
   
    
SLOS051E − O C TOBER 1987 − REVISED AUGUST 2008
16 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
input offset voltage temperature coefficient
Erroneous readings often result from attempts to measure temperature coefficient of input offset voltage. This
parameter is actually a calculation using input offset voltage measurements obtained at two different
temperatures. When one (or both) of the temperatures is below freezing, moisture can collect on both the device
and the test socket. This moisture results in leakage and contact resistance, which can cause erroneous input
offset voltage readings. The isolation techniques previously mentioned have no effect on the leakage, since
the moisture also covers the isolation metal itself, thereby rendering it useless. It is suggested that these
measurements be performed at temperatures above freezing to minimize error.
full-power response
Full-power response, the frequency above which the operational amplifier slew rate limits the output voltage
swing, is often specified two ways: full-linear response and full-peak response. The full-linear response is
generally measured by monitoring the distortion level of the output while increasing the frequency of a sinusoidal
input signal until the maximum frequency is found above which the output contains significant distortion. The
full-peak response is defined as the maximum output frequency, without regard to distortion, above which full
peak-to-peak output swing cannot be maintained.
Because there is no industry-wide accepted value for significant distortion, the full-peak response is specified
in this data sheet and is measured using the circuit of Figure 1. The initial setup involves the use of a sinusoidal
input to determine the maximum peak-to-peak output of the device (the amplitude of the sinusoidal wave is
increased until clipping occurs). The sinusoidal wave is then replaced with a square wave of the same
amplitude. The frequency is then increased until the maximum peak-to-peak output can no longer be maintained
(Figure 5). A square wave is used to allow a more accurate determination of the point at which the maximum
peak-to-peak output is reached.
(a) f = 1 kHz (b) BOM > f > 1 kHz (c) f = BOM (d) f > BOM
Figure 5. Full-Power-Response Output Signal
test time
Inadequate test time is a frequent problem, especially when testing CMOS devices in a high-volume,
short-test-time environment. Internal capacitances are inherently higher in CMOS than in bipolar and BiFET
devices and require longer test times than their bipolar and BiFET counterparts. The problem becomes more
pronounced with reduced supply levels and lower temperatures.
   
    
SLOS051E − O C TOBER 1987 − REVISED AUGUST 2008
17
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TYPICAL CHARACTERISTICS
Table of Graphs
FIGURE
VIO Input offset voltage Distribution 6, 7
αVIO Temperature coefficient Distribution 8, 9
vs High-level output current
10, 11
VOH
High-level output voltage
vs High-level output current
vs Supply voltage
10, 11
12
VOH
High-level output voltage
vs Supply voltage
vs Free-air temperature
12
13
vs Common-mode input voltage
14, 15
VOL
Low-level output voltage
vs Common-mode input voltage
vs Differential input voltage
14, 15
16
VOL Low-level output voltage
vs Differential input voltage
vs Free-air temperature
16
17
vs Free-air temperature
vs Low-level output current
17
18, 19
vs Supply voltage
20
AVD
Differential voltage amplification
vs Supply voltage
vs Free-air temperature
20
21
AVD
Differential voltage amplification
vs Free-air temperature
vs Frequency
21
32, 33
IIB/IIO Input bias and input offset current vs Free-air temperature 22
VIC Common-mode input voltage vs Supply voltage 23
IDD
Supply current
vs Supply voltage
24
IDD Supply current
vs Supply voltage
vs Free-air temperature
24
25
SR
Slew rate
vs Supply voltage
26
SR Slew rate
vs Supply voltage
vs Free-air temperature
26
27
Normalized slew rate vs Free-air temperature 28
VO(PP) Maximum peak-to-peak output voltage vs Frequency 29
B1
Unity-gain bandwidth
vs Free-air temperature
30
B1Unity-gain bandwidth
vs Free-air temperature
vs Supply voltage
30
31
vs Supply voltage
34
φ
m
Phase margin
vs Supply voltage
vs Free-air temperature
34
35
φm
Phase margin
vs Free-air temperature
vs Capacitive loads
35
36
VnEquivalent input noise voltage vs Frequency 37
φPhase shift vs Frequency 32, 33
   
    
SLOS051E − O C TOBER 1987 − REVISED AUGUST 2008
18 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 6
−5
Percentage of Units − %
VIO − Input Offset Voltage − mV
60
5
0−4 −3 −2 −1 0 1 2 3 4
10
20
30
40
50
DISTRIBUTION OF TLC27M2
INPUT OFFSET VOLTAGE
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
612 Amplifiers Tested From 4 Wafer Lots
VDD = 5 V
TA = 25°C
P Package
Figure 7
50
40
30
20
10
43210−1−2−3−4
05
60
VIO − Input Offset Voltage − mV
Percentage of Units − %
−5
DISTRIBUTION OF TLC27M2
INPUT OFFSET VOLTAGE
P Package
TA = 25°C
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
612 Amplifiers Tested From 4 Wafer Lots
VDD = 10 V
Figure 8
−10
Percentage of Units − %
αVIO − Temperature Coefficient − µV/°C
60
10
0−8 −6 −4 −2 0 2 4 6 8
10
20
30
40
50
DISTRIBUTION OF TLC27M2 AND TLC27M7
INPUT OFFSET VOLTAGE
TEMPERATURE COEFFICIENT
Outliers:
(1) 33.0 µV/°C
TA = 25°C to 125°C
P Package
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
224 Amplifiers Tested From 6 Wafer Lots
VDD = 5 V
Figure 9
50
40
30
20
10
86420−2−4−6−8
010
60
αVIO − Temperature Coefficient − µV/°C
Percentage of Units − %
−10
DISTRIBUTION OF TLC27M2 AND TLC27M7
INPUT OFFSET VOLTAGE
TEMPERATURE COEFFICIENT
Outliers:
(1) 34.6 µV/°C
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
224 Amplifiers Tested From 6 Wafer Lots
VDD = 10 V
TA = 25°C to 125°C
P Package
   
    
SLOS051E − O C TOBER 1987 − REVISED AUGUST 2008
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TYPICAL CHARACTERISTICS†
Figure 10
0
0
VOH − High-Level Output Voltage − V
IOH − High-Level Output Current − mA −10
5
−2 −4 −6 −8
1
2
3
4TA = 25°C
VID = 100 mV
VDD = 3 V
HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
ÁÁ
ÁÁ
ÁÁ
VOH
ÎÎÎÎ
ÎÎÎÎ
VDD = 5 V
ÎÎÎÎ
ÎÎÎÎ
VDD = 4 V
Figure 11
0
0
IOH − High-Level Output Current − mA −40
16
−10 −20 −30
2
4
6
8
10
12
14
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
VDD = 16 V
HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
VOH − High-Level Output Voltage − V
ÁÁ
ÁÁ
ÁÁ
VOH
ÁÁÁÁÁ
ÁÁÁÁÁ
VID= 100 mV
TA = 25°C
ÎÎÎÎ
ÎÎÎÎ
VDD = 10 V
Figure 12
0VDD − Supply Voltage − V 162 4 6 8 10 12 14
14
12
10
8
6
4
2
16
0
HIGH-LEVEL OUTPUT VOLTAGE
vs
SUPPLY VOLTAGE
VOH − High-Level Output Voltage − V
ÁÁ
ÁÁ
ÁÁ
VOH
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
VID = 100 mV
RL = 100 kΩ
TA = 25°C
Figure 13
VDD −1.7
VDD −1.8
VDD −1.9
VDD −2
VDD −2.1
VDD −2.2
VDD −2.3
1007550250−25−50
VDD −1.6
12
5
TA − Free-Air Temperature − °C
VDD −2.4
−75
IOH = −5 mA
VID = 100 mA
ÎÎÎÎ
VDD = 5 V
ÎÎÎÎ
ÎÎÎÎ
VDD = 10 V
HIGH-LEVEL OUTPUT VOLTAGE
vs
FREE-AIR TEMPERATURE
VOH − High-Level Output Voltage − V
ÁÁ
ÁÁ
ÁÁ
VOH
†Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
   
    
SLOS051E − O C TOBER 1987 − REVISED AUGUST 2008
20 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS†
Figure 14
0
300
VOL − Low-Level Output Voltage − mV
VIC − Common-Mode Input Voltage − V 4
700
123
400
500
600 TA = 25°C
IOL = 5 mA
VDD = 5 V
VID = −100 mV
VID = −1 V
LOW-LEVEL OUTPUT VOLTAGE
vs
COMMON-MODE INPUT VOLTAGE
650
550
450
350
ÁÁ
ÁÁ
VOL
Figure 15
250 0VIC − Common-Mode Input Voltage − V
300
350
400
450
500
24 6810
VDD = 10 V
IOL = 5 mA
TA = 25°C
VID = −1 V
VID = −2.5 V
VID = −100 mV
LOW-LEVEL OUTPUT VOLTAGE
vs
COMMON-MODE INPUT VOLTAGE
1357 7
VOL − Low-Level Output Voltage − mV
ÁÁ
ÁÁ
VOL
Figure 16
0VID − Differential Input Voltage − V −10−2 −4 −6 −8
800
700
600
500
400
300
200
100
0
IOL = 5 mA
VIC = |VID/2|
TA = 25°C
VDD = 5 V
LOW-LEVEL OUTPUT VOLTAGE
vs
DIFFERENTIAL INPUT VOLTAGE
−1 −3 −5 −7 −9
VOL − Low-Level Output Voltage − mV
ÁÁ
ÁÁ
ÁÁ
VOL
VDD = 10 V
Figure 17
LOW-LEVEL OUTPUT VOLTAGE
vs
FREE-AIR TEMPERATURE
−75
0
TA − Free-Air Temperature − °C125
900
−50 −25 0 25 50 75 100
100
200
300
400
500
600
700
800 VIC = 0.5 V
VID = −1 V
IOL = 5 mA
VDD = 5 V
VDD = 10 V
VOL − Low-Level Output Voltage − mV
ÁÁ
ÁÁ
ÁÁ
VOL
†Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
   
    
SLOS051E − O C TOBER 1987 − REVISED AUGUST 2008
21
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS†
Figure 18
0
VOL − Low-Level Output Voltage − V
IOL − Low-Level Output Current − mA
1
8
0123 4 5 6 7
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
VDD = 3 V
VDD = 5 V
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
ÁÁ
ÁÁ
ÁÁ
VOL
VDD = 4 V
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
VID = −1 V
VIC = 0.5 V
TA = 25°C
Figure 19
0IOL − Low-Level Output Current − mA
3
30
05 10 15 20 25
0.5
1
1.5
2
2.5 TA = 25°C
VIC = 0.5 V
VID = −1 V
ÎÎÎÎ
ÎÎÎÎ
VDD = 16 V
ÎÎÎÎ
ÎÎÎÎ
VDD = 10 V
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
VOL − Low-Level Output Voltage − V
ÁÁ
ÁÁ
ÁÁ
VOL
Figure 20
0
500
16
02 4 6 8 10 12 14
50
100
150
200
250
300
350
400
450 RL = 100 kΩTA = −55°C
−40°C
0°C
25°C
70°C
85°C
125°C
LARGE-SIGNAL
DIFFERENTIAL VOLTAGE AMPLIFICATION
vs
SUPPLY VOLTAGE
VDD − Supply Voltage − V
AVD − Large-Signal Differential
ÁÁ
ÁÁ
ÁÁ
AVD
Voltage Amplification − V/mV
Figure 21
450
400
350
300
250
200
150
100
50
1007550250−25−50
012
5
500
TA − Free-Air Temperature − °C
−75
ÎÎÎÎ
ÎÎÎÎ
VDD = 10 V
ÎÎÎÎ
ÎÎÎÎ
RL = 100 kΩ
LARGE-SIGNAL
DIFFERENTIAL VOLTAGE AMPLIFICATION
vs
FREE-AIR TEMPERATURE
ÎÎÎÎ
ÎÎÎÎ
VDD = 5 V
AVD − Large-Signal Differential
ÁÁ
ÁÁ
ÁÁ
AVD
Voltage Amplification − V/mV
†Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
   
    
SLOS051E − O C TOBER 1987 − REVISED AUGUST 2008
22 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS†
Figure 22
0.1 125
10000
45 65 85 105
1
10
100
1000
25
IIB and IIO − input Bias and Offset Currents − pA
TA − Free-Air Temperature − °C
VDD = 10 V
VIC = 5 V
See Note A
INPUT BIAS CURRENT AND INPUT OFFSET
CURRENT
vs
FREE-AIR TEMPERATURE
ÎÎ
ÎÎ
IIO
ÎÎ
ÎÎ
IIB
IB
IIIO
NOTE A: The typical values of input bias current and input offset
current below 5 pA were determined mathematically. Figure 23
0
VIC − Common-Mode Input Voltage − V
VDD − Supply Voltage − V
16
16
0246 8 10 12 14
2
4
6
8
10
12
14 TA = 25°C
COMMON-MODE
INPUT VOLTAGE POSITIVE LIMIT
vs
SUPPLY VOLTAGE
ÁÁ
ÁÁ
ÁÁ
VIC
Figure 24
300
IDD − Supply Current − A
VDD − Supply Voltage − V
VO = VDD/2
No Load TA = −55°C
0°C
25°C
70°C
125°C
0
800
16
02 4 6 8 10 12 14
100
200
400
500
600
700
−40°C
SUPPLY CURRENT
vs
SUPPLY VOLTAGE
ÁÁ
ÁÁ
DD
IAµ
Figure 25
No Load
VO = VDD/2
−75 TA − Free-Air Temperature − °C
500
125
0−50 −25 0 25 50 75 100
50
100
150
200
250
300
350
400
450
SUPPLY CURRENT
vs
FREE-AIR TEMPERATURE
IDD − Supply Current − A
ÁÁ
ÁÁ
ÁÁ
DD
IAµ
ÎÎÎÎ
ÎÎÎÎ
VDD = 10 V
ÎÎÎÎÎ
ÎÎÎÎÎ
VDD = 5 V
†Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
   
    
SLOS051E − O C TOBER 1987 − REVISED AUGUST 2008
23
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS†
Figure 26
0VDD − Supply Voltage − V
0.9
16
0.3 246 8 10 12 14
0.4
0.5
0.6
0.7
0.8 CL = 20 pF
RL = 100 kΩ
VIPP = 1 V
AV = 1
ÎÎÎÎÎ
See Figure 1
TA = 25°C
SLEW RATE
vs
SUPPLY VOLTAGE
sµ
SR − Slew Rate − V/
Figure 27
− 75 TA − Free-Air Temperature − °C
0.9
125
0.2 − 50 − 25 0 25 50 75 100
0.3
0.4
0.5
0.6
0.7
0.8 RL = 100 kΩ
AV = 1
See Figure 1
CL = 20 pF
SLEW RATE
vs
FREE-AIR TEMPERATURE
sµ
SR − Slew Rate − V/
ÁÁÁÁÁ
ÁÁÁÁÁ
VI(PP) = 5.5 V
VDD = 10 V
ÁÁÁÁÁ
ÁÁÁÁÁ
ÎÎÎÎÎ
ÎÎÎÎÎ
VDD = 10 V
VI(PP) = 1 V
ÁÁÁÁÁ
ÁÁÁÁÁ
VDD = 5 V
VI(PP) = 1 V
ÁÁÁÁÁ
ÁÁÁÁÁ
VDD = 5 V
VI(PP) = 2.5 V
Figure 28
−75
Normalized Slew Rate
TA − Free-Air Temperature − °C
1.4
125
0.5 −50 −25 0 25 50 75 100
0.6
0.7
0.8
0.9
1
1.1
1.2
1.3 AV = 1
VI(PP) = 1 V
RL = 100 kΩ
CL = 20 pF
VDD = 10 V
VDD = 5 V
NORMALIZED SLEW RATE
vs
FREE-AIR TEMPERATURE
Figure 29
1f − Frequency − kHz
10
1000
0
1
2
3
4
5
6
7
8
9
10 100
TA = −55°C
TA = 25°C
TA = 125°C
ÎÎÎÎÎ
ÎÎÎÎÎ
See Figure 1
MAXIMUM PEAK-TO-PEAK OUTPUT
VOLTAGE
vs
FREQUENCY
RL = 100 kΩ
ÎÎÎÎ
ÎÎÎÎ
VDD = 5 V
ÎÎÎÎ
ÎÎÎÎ
VDD = 10 V
− Maximum Peak-to-Peak Output Voltage − VVO(PP)
†Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
   
    
SLOS051E − O C TOBER 1987 − REVISED AUGUST 2008
24 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS†
Figure 30
−75
B1 − Unity-Gain Bandwidth − kHz
TA − Free-Air Temperature − C
900
125
300 −50 −25 0 25 50 75 100
400
500
600
700
800
UNITY-GAIN BANDWIDTH
vs
FREE-AIR TEMPERATURE
B1
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
VDD = 5 V
VI = 10 mV
CL = 20 pF
See Figure 3
Figure 31
0VDD − Supply Voltage − V
800
16
400 2 4 6 8 10 12 14
450
500
550
600
650
700
750
UNITY-GAIN BANDWIDTH
vs
SUPPLY VOLTAGE
B1 − Unity-Gain Bandwidth − kHz
B1
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
See Figure 3
TA = 25°C
CL = 20 pF
VI = 10 mV
LARGE-SCALE DIFFERENTIAL VOLTAGE
AMPLIFICATION AND PHASE SHIFT
vs
FREQUENCY
0f − Frequency − Hz 1 M
0.1 10 100 1 k 10 k 100 k
1
10
10 2
10 3
10 4
10 5
10 6
150°
120°
90°
60°
30°
0°
180°
Phase Shift
TA = 25°C
RL = 100 kΩ
VDD = 5 V
Phase Shift
10 7
ÎÎÎ
ÎÎÎ
AVD
AVD − Large-Signal Differential
ÁÁ
ÁÁ
AVD Voltage Amplification
Figure 32
†Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
   
    
SLOS051E − O C TOBER 1987 − REVISED AUGUST 2008
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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS†
100 k10 k1 k10010 1 M0
Phase Shift
VDD = 10 V
RL = 100 kΩ
TA = 25°C
Phase Shift
180°
0°
30°
60°
90°
120°
150°
10 6
10 5
10 4
10 3
10 2
10
1
0.1
f − Frequency − Hz
10 7
LARGE-SCALE DIFFERENTIAL VOLTAGE
AMPLIFICATION AND PHASE SHIFT
vs
FREQUENCY
ÎÎÎ
ÎÎÎ
AVD
AVD − Large-Signal Differential
ÁÁ
ÁÁ
ÁÁ
AVD Voltage Amplification
Figure 33
Figure 34
0
38°
m − Phase Margin
VDD − Supply Voltage − V 16
50°
2 4 6 8 10 12 14
40°
42°
44°
46°
48°
See Figure 3
TA = 25°C
CL = 20 pF
VI = 10 mV
PHASE MARGIN
vs
SUPPLY VOLTAGE
ÁÁ
ÁÁ
m
φ
Figure 35
−75
35°
TA − Free-Air Temperature − C 125
45°
−50 −25 0 25 50 75 100
37°
39°
41°
43°
VDD = 5 V
VI = 10 mV
CL = 20 pF
See Figure 3
PHASE MARGIN
vs
FREE-AIR TEMPERATURE
m − Phase Margin
ÁÁ
ÁÁ
m
φ
†Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
   
    
SLOS051E − O C TOBER 1987 − REVISED AUGUST 2008
26 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 36
0
28°
CL − Capacitive Load − pF 100
44°
20 40 60 80
30°
32°
34°
36°
38°
40°
42°VDD = 5 V
VI = 10 mV
TA = 25°C
See Figure 3
PHASE MARGIN
vs
CAPACITIVE LOAD
9070503010
m − Phase Margin
ÁÁ
ÁÁ
m
φ
Figure 37
1
0
Vn − Equivalent Input Noise Voltage − nV/Hz
f −Frequency − Hz 1000
300
50
100
150
200
250
10 100
See Figure 2
TA = 25°C
RS = 20 Ω
VDD = 5 V
EQUIVALENT INPUT NOISE VOLTAGE
vs
FREQUENCY
Vn
ÁÁ
ÁÁ
ÁÁ
nV/ Hz
   
    
SLOS051E − O C TOBER 1987 − REVISED AUGUST 2008
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APPLICATION INFORMATION
single-supply operation
While the TLC27M2 and TLC27M7 perform well using dual power supplies (also called balanced or split
supplies), the design is optimized for single-supply operation. This design includes an input common-mode
voltage range that encompasses ground, as well as an output voltage range that pulls down to ground. The
supply voltage range extends down to 3 V (C-suf fix types), thus allowing operation with supply levels commonly
available for TTL and HCMOS; however, for maximum dynamic range, 16-V single-supply operation is
recommended.
Many single-supply applications require that a voltage be applied to one input to establish a reference level that
is above ground. A resistive voltage divider is usually sufficient to establish this reference level (see Figure 38).
The low input bias current of the TLC27M2 and TLC27M7 permits the use of very large resistive values to
implement the voltage divider, thus minimizing power consumption.
The TLC27M2 and TLC27M7 work well in conjunction with digital logic; however, when powering both linear
devices and digital logic from the same power supply, the following precautions are recommended:
1. Power the linear devices from separate bypassed supply lines (see Figure 39); otherwise, the linear
device supply rails can fluctuate due to voltage drops caused by high switching currents in the digital
logic.
2. Use proper bypass techniques to reduce the probability of noise-induced errors. Single capacitive
decoupling is often adequate; however, high-frequency applications may require RC decoupling.
R4
VO
VDD
R2
R1
VI
VREF R3 C
0.01µF
−
+
VREF +VDD R3
R1 )R3
VO+ǒVREF–VIǓR4
R2 )VREF
Figure 38. Inverting Amplifier With Voltage Reference
−
+
−
+
(a) COMMON SUPPLY RAILS
Logic
Power
Supply
Logic Logic
Logic Logic Logic
(b) SEPARATE BYPASSED SUPPLY RAILS (preferred)
Power
Supply
Output
Output
Figure 39. Common Versus Separate Supply Rails
   
    
SLOS051E − O C TOBER 1987 − REVISED AUGUST 2008
28 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
input characteristics
The TLC27M2 and TLC27M7 are specified with a minimum and a maximum input voltage that, if exceeded at
either input, could cause the device to malfunction. Exceeding this specified range is a common problem,
especially in single-supply operation. Note that the lower range limit includes the negative rail, while the upper
range limit is specified at VDD −1 V at TA = 25°C and at VDD −1.5 V at all other temperatures.
The use of the polysilicon-gate process and the careful input circuit design gives the TLC27M2 and TLC27M7
very go o d i n put of fset voltage drift characteristics relative to conventional metal-gate processes. Offset voltage
drift in CMOS devices is highly influenced by threshold voltage shifts caused by polarization of the phosphorus
dopant implanted in the oxide. Placing the phosphorus dopant in a conductor (such as a polysilicon gate)
alleviates the polarization problem, thus reducing threshold voltage shifts by more than an order of magnitude.
The offset voltage drift with time has been calculated to be typically 0.1 µV/month, including the first month of
operation.
Because of the extremely high input impedance and resulting low bias current requirements, the TLC27M2 and
TLC27M7 are well suited for low-level signal processing; however, leakage currents on printed-circuit boards
and sockets can easily exceed bias current requirements and cause a degradation in device performance. It
is good practice to include guard rings around inputs (similar to those of Figure 4 in the Parameter Measurement
Information section). These guards should be driven from a low-impedance source at the same voltage level
as the common-mode input (see Figure 40).
The inputs of any unused amplifiers should be tied to ground to avoid possible oscillation.
noise performance
The noise specifications in operational amplifier circuits are greatly dependent on the current in the first-stage
differential amplifier. The low input bias current requirements of the TLC27M2 and TLC27M7 result in a very
low noise current, which is insignificant in most applications. This feature makes the devices especially
favorable over bipolar devices when using values of circuit impedance greater than 50 kΩ, since bipolar devices
exhibit greater noise currents.
VI
(a) NONINVERTING AMPLIFIER (c) UNITY-GAIN AMPLIFIER
−
+
(b) INVERTING AMPLIFIER
VI
−
+
−
+
VIVOVOVO
Figure 40. Guard-Ring Schemes
output characteristics
The output stage of the TLC27M2 and TLC27M7 is designed to sink and source relatively high amounts of
current (see typical characteristics). If the output is subjected to a short-circuit condition, this high current
capability can cause device damage under certain conditions. Output current capability increases with supply
voltage.
All operating characteristics of the TLC27M2 and TLC27M7 were measured using a 20-pF load. The devices
drive higher capacitive loads; however, as output load capacitance increases, the resulting response pole
occurs at lower frequencies, thereby causing ringing, peaking, or even oscillation (see Figure 41). In many
cases, adding a small amount of resistance in series with the load capacitance alleviates the problem.
   
    
SLOS051E − O C TOBER 1987 − REVISED AUGUST 2008
29
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
−
+
2.5 V
VO
CL
−2.5 V
VI
(a) CL = 20 pF, RL = NO LOAD (b) CL = 170 pF, RL = NO LOAD
(c) CL = 190 pF, RL = NO LOAD (d) TEST CIRCUIT
TA = 25°C
f = 1 kHz
VI(PP) = 1 V
Figure 41. Effect of Capacitive Loads and Test Circuit
output characteristics (continued)
Although the TLC27M2 and TLC27M7 possess excellent high-level output voltage and current capability,
methods for boosting this capability are available, if needed. The simplest method involves the use of a pullup
resistor ( R P) connected from the output to the positive supply rail (see Figure 42). There are two disadvantages
to the use of this circuit. First, the NMOS pulldown transistor N4 (see equivalent schematic) must sink a
comparatively large amount of current. In this circuit, N4 behaves like a linear resistor with an on-resistance
between approximately 60 Ω and 180 Ω, depending on how hard the operational amplifier input is driven. With
very low values of RP, a voltage offset from 0 V at the output occurs. Second, pullup resistor RP acts a s a drain
load to N 4 and the gain of the operational amplifier is reduced at output voltage levels where N5 is not supplying
the output current.
   
    
SLOS051E − O C TOBER 1987 − REVISED AUGUST 2008
30 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
output characteristics (continued)
Figure 42. Resistive Pullup to Increase VOH
−
+
VI
VDD
RP
VO
R2
R1 RL
IP
IP
IL
RP+VDD *VO
IF)IL)IP
IP = Pullup current required by the op-
erational amplifier (typically 500 µA)
VO
−
+
C
Figure 43. Compensation for Input Capacitance
feedback
Operational amplifier circuits nearly always employ feedback, and since feedback is the first prerequisite for
oscillation, some caution is appropriate. Most oscillation problems result from driving capacitive loads
(discussed previously) and ignoring stray input capacitance. A small-value capacitor connected in parallel with
the feedback resistor is an effective remedy (see Figure 43). The value of this capacitor is optimized empirically.
electrostatic-discharge protection
The TLC27M2 and TLC27M7 incorporate an internal electrostatic-discharge (ESD) protection circuit that
prevents functional failures at voltages up to 2000 V as tested under MIL-STD-883C, Method 3015.2. Care
should be exercised, however, when handling these devices as exposure to ESD may result in the degradation
of the device parametric performance. The protection circuit also causes the input bias currents to be
temperature dependent and have the characteristics of a reverse-biased diode.
latch-up
Because CMOS devices are susceptible to latch-up due to their inherent parasitic thyristors, the TLC27M2 and
TLC27M7 inputs and outputs were designed to withstand −100-mA surge currents without sustaining latch-up;
however, techniques should be used to reduce the chance of latch-up whenever possible. Internal protection
diodes should not, by design, be forward biased. Applied input and output voltage should not exceed the supply
voltage by more than 300 mV. Care should be exercised when using capacitive coupling on pulse generators.
Supply transients should be shunted by the use of decoupling capacitors (0.1 µF typical) located across the
supply rails as close to the device as possible.
The current path established if latch-up occurs is usually between the positive supply rail and ground and can
be triggered by surges on the supply lines and/or voltages on either the output or inputs that exceed the supply
voltage. Once latch-up occurs, the current flow is limited only by the impedance of the power supply and the
forward resistance of the parasitic thyristor and usually results in the destruction of the device. The chance of
latch-up occurring increases with increasing temperature and supply voltages.
   
    
SLOS051E − O C TOBER 1987 − REVISED AUGUST 2008
31
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
−
+
R2
68 kΩ
2.2 nF
C2
VO
1N4148
470 kΩ
100 kΩ
C1
2.2 nF
68 kΩ
R1
47 kΩ
100 kΩ
1 µF
100 kΩ
5 V
1/2
TLC27M2
NOTES: VO(PP) ≈ 2 V
fO+1
2pR1R2C1C2
Ǹ
Figure 44. Wien Oscillator Figure 45. Precision Low-Current Sink
VI
R
5 V IS
2N3821
−
+1/2
TLC27M7
NOTES: VI = 0 V to 3 V
IS+VI
R
(see Note A)
−
+
100 kΩ
+−
100 kΩ
100 kΩ
Gain Control
1 MΩ
1 kΩ
10 kΩ
5 V
1µ F
− +
− +
0.1 µF
1/2
TLC27M2 0.1 µF
NOTE A: Low to medium impedance dynamic mike
Figure 46. Microphone Preamplifier
   
    
SLOS051E − O C TOBER 1987 − REVISED AUGUST 2008
32 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
−
+
10 MΩ
VO
VREF
150 pF
100 kΩ
15 nF
VDD
−
+
1 kΩ1/2
TLC27M2
TLC27M2
1/2
NOTES: VDD = 4 V to 15 V
Vref = 0 V to VDD − 2 V
Figure 47. Photo-Diode Amplifier With Ambient Light Rejection
−
+
VDD
VO
1/2
TLC27M2
1 MΩ
33 pF
100 kΩ
1N4148
100 kΩ
NOTES: VDD = 8 V to 16 V
VO = 5 V, 10 mA
Figure 48. 5-V Low-Power Voltage Regulator
   
    
SLOS051E − O C TOBER 1987 − REVISED AUGUST 2008
33
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
−
+
10 kΩ
TLC27M2
1/2 VO
100 kΩ
100 kΩ
0.1 µF
1 MΩ
0.22 µF
1 MΩ
VI
0.1 µ F
5 V
Figure 49. Single-Rail AC Amplifiers
PACKAGE OPTION ADDENDUM
www.ti.com 27-Apr-2012
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
TLC27M2ACD ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC27M2ACDG4 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC27M2ACDR ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC27M2ACDRG4 ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC27M2ACP ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
TLC27M2ACPE4 ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
TLC27M2AID ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC27M2AIDG4 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC27M2AIDR ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC27M2AIDRG4 ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC27M2AIP ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
TLC27M2AIPE4 ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
TLC27M2BCD ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC27M2BCDG4 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC27M2BCDR ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC27M2BCDRG4 ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC27M2BCP ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
TLC27M2BCPE4 ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
TLC27M2BID ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PACKAGE OPTION ADDENDUM
www.ti.com 27-Apr-2012
Addendum-Page 2
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
TLC27M2BIDG4 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC27M2BIDR ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC27M2BIDRG4 ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC27M2BIP ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
TLC27M2BIPE4 ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
TLC27M2CD ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC27M2CDG4 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC27M2CDR ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC27M2CDRG4 ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC27M2CP ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
TLC27M2CPE4 ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
TLC27M2CPSLE OBSOLETE SO PS 8 TBD Call TI Call TI
TLC27M2CPSR ACTIVE SO PS 8 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC27M2CPSRG4 ACTIVE SO PS 8 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC27M2CPW ACTIVE TSSOP PW 8 150 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC27M2CPWG4 ACTIVE TSSOP PW 8 150 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC27M2CPWLE OBSOLETE TSSOP PW 8 TBD Call TI Call TI
TLC27M2CPWR ACTIVE TSSOP PW 8 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC27M2CPWRG4 ACTIVE TSSOP PW 8 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC27M2ID ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PACKAGE OPTION ADDENDUM
www.ti.com 27-Apr-2012
Addendum-Page 3
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
TLC27M2IDG4 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC27M2IDR ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC27M2IDRG4 ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC27M2IP ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
TLC27M2IPE4 ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
TLC27M2IPW ACTIVE TSSOP PW 8 150 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC27M2IPWG4 ACTIVE TSSOP PW 8 150 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC27M2IPWR ACTIVE TSSOP PW 8 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC27M2IPWRG4 ACTIVE TSSOP PW 8 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC27M2MD ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC27M2MDG4 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC27M2MFKB OBSOLETE LCCC FK 20 TBD Call TI Call TI
TLC27M2MJG OBSOLETE CDIP JG 8 TBD Call TI Call TI
TLC27M2MJGB OBSOLETE CDIP JG 8 TBD Call TI Call TI
TLC27M7CD ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC27M7CDG4 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC27M7CDR ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC27M7CDRG4 ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC27M7CP ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
TLC27M7CPE4 ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
TLC27M7CPSR ACTIVE SO PS 8 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PACKAGE OPTION ADDENDUM
www.ti.com 27-Apr-2012
Addendum-Page 4
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
TLC27M7CPSRG4 ACTIVE SO PS 8 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC27M7ID ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC27M7IDG4 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC27M7IDR ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC27M7IDRG4 ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC27M7IP ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
TLC27M7IPE4 ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
TLC27M7MFKB OBSOLETE LCCC FK 20 TBD Call TI Call TI
TLC27M7MJG OBSOLETE CDIP JG 8 TBD Call TI Call TI
TLC27M7MJGB OBSOLETE CDIP JG 8 TBD Call TI Call TI
TLC27M7MUB OBSOLETE CFP U 10 TBD Call TI Call TI
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
PACKAGE OPTION ADDENDUM
www.ti.com 27-Apr-2012
Addendum-Page 5
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
TLC27M2ACDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
TLC27M2AIDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
TLC27M2BCDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
TLC27M2BIDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
TLC27M2CDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
TLC27M2CPSR SO PS 8 2000 330.0 16.4 8.2 6.6 2.5 12.0 16.0 Q1
TLC27M2CPWR TSSOP PW 8 2000 330.0 12.4 7.0 3.6 1.6 8.0 12.0 Q1
TLC27M2IDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
TLC27M2IPWR TSSOP PW 8 2000 330.0 12.4 7.0 3.6 1.6 8.0 12.0 Q1
TLC27M7CDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
TLC27M7CPSR SO PS 8 2000 330.0 16.4 8.2 6.6 2.5 12.0 16.0 Q1
TLC27M7IDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TLC27M2ACDR SOIC D 8 2500 340.5 338.1 20.6
TLC27M2AIDR SOIC D 8 2500 340.5 338.1 20.6
TLC27M2BCDR SOIC D 8 2500 340.5 338.1 20.6
TLC27M2BIDR SOIC D 8 2500 340.5 338.1 20.6
TLC27M2CDR SOIC D 8 2500 340.5 338.1 20.6
TLC27M2CPSR SO PS 8 2000 367.0 367.0 38.0
TLC27M2CPWR TSSOP PW 8 2000 367.0 367.0 35.0
TLC27M2IDR SOIC D 8 2500 340.5 338.1 20.6
TLC27M2IPWR TSSOP PW 8 2000 367.0 367.0 35.0
TLC27M7CDR SOIC D 8 2500 340.5 338.1 20.6
TLC27M7CPSR SO PS 8 2000 367.0 367.0 38.0
TLC27M7IDR SOIC D 8 2500 340.5 338.1 20.6
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
MECHANICAL DATA
MCER001A – JANUARY 1995 – REVISED JANUAR Y 1997
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
JG (R-GDIP-T8) CERAMIC DUAL-IN-LINE
0.310 (7,87)
0.290 (7,37)
0.014 (0,36)
0.008 (0,20)
Seating Plane
4040107/C 08/96
5
4
0.065 (1,65)
0.045 (1,14)
8
1
0.020 (0,51) MIN
0.400 (10,16)
0.355 (9,00)
0.015 (0,38)
0.023 (0,58)
0.063 (1,60)
0.015 (0,38)
0.200 (5,08) MAX
0.130 (3,30) MIN
0.245 (6,22)
0.280 (7,11)
0.100 (2,54)
0°–15°
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a ceramic lid using glass frit.
D. Index point is provided on cap for terminal identification.
E. Falls within MIL STD 1835 GDIP1-T8
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