SIP11203DLP-T1-E3 - Vishay [Siliconix]

Vishay Siliconix

SiP11203, SiP11204

Document Number: 73868

S11-0975–Rev. C, 16-May-11

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Synchronous Rectifier Driver with Power Up/Down Control,

Output OVP, Error Amplifier and Precision Reference

FEATURES

• High Current synchronous rectifier drivers

- 2.2 A source and 4 A sink

• Driver switching synchronized with primary

controller

• Full output control during power-up and power-

down

• 5.5 V to 13 V operating voltage range

• 1.225 V on board bandgap voltage reference

• Can be powered from the pulse transformer

supplying synchronous rectifier timing signals

• On-chip ground-sensing error amplifier

• Programmable rising edge delay

• Output over-voltage protection (OVP)

- SiP11203 turns synchronous rectifiers on

- SiP11204 turns synchronous rectifiers off

• Secondary-side companion chip for the Si9122

Half-Bridge Controller IC

APPLICATIONS

• High efficiency DC-DC Converter Modules and

Bricks

• Telecom and Server Power Supplies

• High Efficiency Intermediate Bus Converters (IBC)

• Half-bridge, full-bridge, or push-pull primary DC-DC

topologies

• Center-tapped or current-doubler secondary

configurations

DESCRIPTION

The SiP11203/SiP11204 provide the secondary side

error amplifier, reference voltage and synchronous

rectifier drivers for isolated converter topologies. Both

ICs are capable of being powered via conventional

bias supplies (output inductor winding or power

transformer winding), or from a pulse transformer

supplying the gate timing signals, and both parts

generate a regulated supply for powering the error

amplifier and control circuitry.

During power-up the SiP11203/SiP11204 ensure that

the synchronous rectifiers are held off until the supply

voltages are adequate to guarantee effective

operation of the driver circuits. During the soft-start

interval, a gradual ramp-up of the synchronous

rectifier conduction time is provided. Both ICs also

allow control of the discharge rate of the synchronous

rectifier driver outputs during power-down.

The SiP11203 and SiP11204 are available in a

Pb-free MLP44-16 package and are rated to handle

the industrial ambient temperature range of - 40 to 85 °C.

TYPICAL APPLICATION CIRCUIT

OUT B

OUT A

Vin

IN A

IN B

OVPin

EA+

VL Cpd Rdel Rpd

GND

Vref

EA-

EAout

PGND

Half Brid

SiP11203

SiP11204

GND

OUT

GND

PWM

Controlle r

Optoisolator

Pulse

Transformer

ZF1

ZF2

SRH

SRL

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Document Number: 73868

S11-0975–Rev. C, 16-May-11

Vishay Siliconix

SiP11203, SiP11204

This document is subject to change without notice.

THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

Notes:

a. Device mounted with all leads soldered to printed circuit board.

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation

of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum

rating conditions for extended periods may affect device reliability.

ABSOLUTE MAXIMUM RATINGS

Parameter Limit Unit

VIN, INA, INB15 V

VREF

, Linear Inputs - 0.3 to VL + 0.3

Storage Temperature - 65 to + 160

°C

Junction Temperature - 40 to + 125

Package Thermal Impedance (RJA)16 Pin 44MLP 47 °C/W

Package Power Dissipation (package)a745 mW

RECOMMENDED OPERATING RANGE

Parameter Limit Unit

VIN 5.5 to 13 V

CVIN 1

µF

CVL 1

CREF 0.1

Linear Inputs (EA+, EA-, OVPIN)0 to VL

Error Amplifier Output Voltage 0 to 3.5 V

Logic Inputs (INA, INB)0 to 13

Reference voltage output current 10 µA

RPD > 15 k

CPD 1 to 10 nF

SPECIFICATIONS

Parameter Symbol

Test Conditions

Unless Otherwise Specified

5.5 V  VIN  13 V

TA = - 40 °C to 85 °C

Limits

Unit Min.a Typ.bMax.a

Power Supply

VL Output Voltage VLOutput disabled (Note e) 4.75 5.0 5.25 V

VL Temperature Coefficient TC1 (Note c) 160 µV/°C

VL Line Regulation VL_LNR IL = 0 mA 38

VL Load Regulation VL_LDR IL = 0 mA to 3.3 mA, VIN = 5.5 V 1.2 10

VL Supply PSRR VL_PSRR fTEST =100 Hz, (Note c) 70 dB

Supply Current IIN

= 5.5 V, C

LOAD(A)

= C

LOAD(B)

= 6 nF (Note c, d)

= 7.5 V, C

LOAD(A)

= C

LOAD(B)

= 6 nF (Note c, d)

15.5

Quiescent Current IQDevice switching disabled (Note e) 3.5 4.5

Start-up Current Capability ISTARTUP Current sourced from VIN to VL, VL = 0 V 35 45 55

Reference Voltages

VREF Voltage VREF

IREF2 = 0 mA, TA = 25 °C 1.212 1.225 1.238 V

IREF2 = 0 mA 1.188 1.225 1.262

VREF Temperature Coefficient TC2 (Note c) 160 µV/°C

VREF Load Regulation VREF_LDR

= 5.5 V, I

REF

= 0 to 10

µA 1.5 2.5 mV

VREF PSRR VREF_PSRR fTEST = 100 Hz, (Note c) 60 dB

Internal Buffered Reference Voltage VREFINT

= 5.5, measured at R

2.320 2.5 2.570 V

Document Number: 73868

S11-0975–Rev. C, 16-May-11

www.vishay.com

Vishay Siliconix

SiP11203, SiP11204

This document is subject to change without notice.

THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

Parameter Symbol

Test Conditions

Unless Otherwise Specified

5.5 V  VIN  13 V

TA = - 40 °C to 85 °C

Limits

Unit Min.a Typ.bMax.a

Logic Inputs - IN A and IN B

Input High VIH Rising 4.0 2.5 V

Input Low VIL Falling 2.1 1.0

Input Resistance RIN VIN = 13 V, 13 V at INA and/or INB 3.0 3.8 4.5 k

Input Frequency Range (INA and

INB) fIN (Note c) 100 500 kHz

Error Amplifier - DC Electrical Characteristics

Voltage Gain AV20 log (VOUT/VOS) for VOUT = 0.5 V to 3.0 V 65 70 dB

Common Mode Rejection Ratio CMRR Input CMR = 0 V to 3.5 V 60 65

Input Offset Voltage VOS VCM = 1.225 V, RLOAD = 10 k to VCM ± 3 ± 15 mV

VOS Temperature Coefficient TC3 (Note c) 30 µV/°C

Input Bias Current IBIAS VCM = 1.225 V 210

Input Offset Current IOS (IEA+) - (IEA-), (Note c) ± 0.3

Output Voltage VOL Output sinking 0.8 mA 225 400 mV

VOH Output sourcing 0.8 mA 3.0 3.45 V

Output Current IOH

Sourcing, EA

OUT

= 1.0 V, EA+ overdrive = 500 mV

3.5 4.7 mA

IOL

Sinking, EA

OUT

= 2.5 V, EA+ overdrive = 500 mV

0.8 1.3

Error Amplifier - AC Electrical Characteristics

Gain-Bandwidth Product BW(Note c) 1 MHz

Slew Rate SR+ Rising, RLOAD = 2 k II 1 nf to Ground 0.75 V/µs

SR- Falling, RLOAD = 2 k II 1 nf to Ground 1

MOSFET Drivers

Driver Impedance

RD(SOURCE) VIN = 5.5 V, IOUT = 100 mA, TJ = 25 °C 2.3 3.7



RD(SINK) 1.5 2.4

RD(SOURCE) VIN = 7.5 V, IOUT = 100 mA, TJ = 25 °C 2.1 3.4

RD(SINK) 1.4 2.2

Peak Drive Current

IPK(SOURCE) VIN = 5.5 V, TJ = 25 °C (Note c) 1.2

IPK(SINK) 2.4

IPK(SOURCE) VIN = 7.5 V, TJ = 25 °C (Note c) 2.2

IPK(SINK) 4.0

Rise Time tr

10 % to 90 %, VIN = 5.5 V, CLOAD = 6 nF, (Note c) 45

10 % to 90 %, VIN = 7.5 V, CLOAD = 6 nF, (Note c) 42

Fall Time tf

90 % to 10 %, VIN = 5.5 V, CLOAD = 6 nF, (Note c) 35

90 % to 10 %, VIN = 7.5 V, CLOAD = 6 nF, (Note c) 32

IN to OUT Propagation Delay

tpdr

INA/INB rising to OUTA/OUTB rising, 50 % to 50 %

VIN = 5.5 V, RDEL connected to VL, CLOAD = 0 nF 20 32 55

tpdf

INA/INB falling to OUTA/OUTB falling, 50 % to 50 %

VIN = 5.5 V, RDEL connected to VL, CLOAD = 0 nF 20 34 55

Additional Rising Edge OUT A/B

Delay vs. RDEL

tDELAY

RDEL connected to VL0

RDEL = 25 k to GND, CLOAD = 0 nF (Note d) 28 38 48

Power-down Detection Timeout tPDDET

IN A and IN B low to OUT A/OUT B low

RPD = 25 k, CPD = 1 nF (Note c) 25 µs

Power-up Output Hold-off Current IHOFF

No forcing voltage on VIN or VL, both VIN and VL

bypassed by 1 µF to GND, INA or INB = 5 V, other

input = 0 V, force 1 V at active output (A or B) 350 530 mA

SPECIFICATIONS

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Document Number: 73868

S11-0975–Rev. C, 16-May-11

Vishay Siliconix

SiP11203, SiP11204

This document is subject to change without notice.

THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

Notes:

a. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum and over - 40 °C to 85 °C.

b. Typical values are specified for 25 °C operation, and are for design reference only.

c. Not 100 % tested in production. This information is provided for reference only.

d. IN A or IN B switching at 250 kHz, RDEL = 25 k to ground.

e. IN A = step 5 to 0 V and IN B = 5 V or vice versa, RDEL = 25 k to ground, error amplifier configured as voltage follower with EA+ connected

to VREF.

PIN CONFIGURATION

Parameter Symbol

Test Conditions

Unless Otherwise Specified

5.5 V  VIN  13 V

TA = - 40 °C to 85 °C

Limits

Unit Min.a Typ.bMax.a

Under Voltage Lockout Section

UVLO Threshold (Rising) UVLORVIN Rising until output transitions on 4.3 4.45 4.6

VUVLO Threshold (Falling) UVLOFVIN Falling until output transitions off 2.9 3.05 3.2

UVLO Hysteresis VHYS(UVLO) UVLOR - UVLOF

, IL = 0 mA 1.25 1.40 1.55

Output Overvoltage Protection

Force Outputs On Threshold OVPR

Rising voltage on OVPIN to force OUTA and OUTB

high 1.40 1.47 1.55

Resume Normal Operation Threshold OVPF

Falling voltage on OVPIN to allow OUTA and OUTB

to go low 1.06 1.13 1.20

Hysteresis VHYS(OVP) OVPR - OVPF 0.30 0.35 0.40

Housekeeping Supply Section

IC logic enable CUVLORVIN Rising until current at VIN > 1 mA 3.35 3.55 3.70

IC logic disable CUVLOFVIN Falling until current at VIN < 0.25 mA 2.90 3.05 3.20

Hysteresis VHYS(CUVLO

)CUVLOR - CUVLOF 0.35 0.50 0.65

SPECIFICATIONS

Top ViewBottom View

MLP44-16

OUTB R

REF

OVP

EA-

EA+

OUT

OUTA GNDR V

DEL L

INB

PGND

INA

OUTBR

REF

INB

INA

PGND

OVP

EA-

EA+

OUT

OUTAGNDRV

DELL

13141516

5678

12 1

13 14 15 16

5678

ORDERING INFORMATION

Part Number Marking Ambient Temperature Range

SiP11203DLP-T1-E3 11203 - 40 ° to 85 °C

SiP11204DLP-T1-E3 11204

Document Number: 73868

S11-0975–Rev. C, 16-May-11

www.vishay.com

Vishay Siliconix

SiP11203, SiP11204

This document is subject to change without notice.

THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

FUNCTIONAL BLOCK DIAGRAM

PIN DESCRIPTION

Pin Number Name Function

1 INB Logic input for output driver B

2VIN Input supply voltage

3 PGND Power ground

4 INA Logic input for output driver A

5 OUTA Driver output A

6 GND Analog ground (connect GND to the exposed pad of the IC package)

7RDEL Sets output rising edge delay

8VL5 V supply voltage for internal circuitry

9EAOUT Error amplifier output

10 EA- Error amplifier inverting input

11 EA+ Error amplifier non inverting input

12 OVPIN Input pin for over voltage detection

13 VREF 1.225 V reference voltage for converter output voltage regulating setting

14 CPD Capacitor value sets power down detection time in conjunction with RPD

15 RPD Resistor value sets currents for power down detection timer and for power down discharge of outputs

16 OUTB Driver output B

Figure 1.

5 V

Pre-regulator

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Document Number: 73868

S11-0975–Rev. C, 16-May-11

Vishay Siliconix

SiP11203, SiP11204

This document is subject to change without notice.

THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

DETAILED OPERATION

SUPPLY VOLTAGE (VIN)

The SiP11203/SiP11204 are designed to operate at an

input voltage (VIN) between 5.5 V and 13 V. The

synchronous rectifier drivers (OUTA and OUTB) are

powered directly from VIN, to facilitate setting the gate

drive voltage for the rectifier MOSFETs. Due to the

high peak currents available from the SiP11203/

SiP11204 outputs, careful attention must be paid to the

bypassing of VIN to PGND.

Internal Supply (VL)

In order to provide the internal circuitry of the

SiP11203/SiP11204 with a stable supply voltage (VL),

the SiP11203/SiP11204 incorporate a linear pre-

regulator. Operating from VIN, the pre-regulator

provides a fixed VL of 5 V for use by the majority of the

chip. VL is regulated by VREFINT

, and therefore does

not depend upon the voltage at the VREF pin. For

proper IC operation, a bypass capacitor on the order

of 1µF should be connected between VL and GND.

In normal operation, VL is intended to accommodate

the internal light load requirements, such as bias

networks and the sourcing capability of the error

amplifier’s output.

Start-up Considerations

The average pre-regulator output current available to

charge the VL bypass capacitor, and the value of that

capacitor, play an important part in the start-up

sequencing of the SiP11203/SiP11204. Until VL

reaches the Chip Undervoltage Lockout threshold

(CUVLO), the part is held in a low-current standby

state. When VL exceeds the CUVLO voltage of 3.55 V,

the majority of the on-chip circuitry is enabled, with the

exception of the reference voltage buffer and the

output drivers (OUTA and OUTB). Finally, when the

main Undervoltage Lockout threshold (UVLOR) is

reached, which occurs when VL reaches 90 % of its

final value, the VREF buffer and the output drivers are

enabled. This in turn allows the VREF pin to source

current, and the outputs to respond to the INA and INB

inputs. See Figure 4, in the Applications Information

Section.

The I-V characteristic of the pre-regulator approximates

that of a constant current source. With V

= 7.5 V

, the

typical IOUT at the VL pin for voltages between 0 V and

the final regulated voltage of 5 V is 35 mA.

REFERENCE VOLTAGE (VREF)

The SiP11203/SiP11204 incorporate an internal

voltage reference of 2.5 V. This is scaled and buffered

to drive the VREF pin at 1.225 V. The accuracy of VREF

is ± 1 % at 25 °C, with a temperature coefficient of

± 160 µV/°C, yielding a worst-case accuracy over

temperature of ± 3 % (- 40 °C to + 85 °C).

Start-up and Soft-Start Considerations

VREF is held at 0 V until VL has exceeded its UVLOR

threshold. This allows a soft-start function to be

implemented by controlling the rate of rise of voltage

on the VREF pin, which in turn causes a gradual rise in

the target voltage of the error amplifier and its

associated voltage control loop. See Figure 4, in the

Applications Information Section.

The charging rate (dV/dt) of VREF is user-settable by

choice of VREF bypass capacitor value. The I-V

characteristic of the reference output approximates

that of a constant current source, with the typical IOUT

at the VREF pin for voltages between 0 V and the final

regulated voltage of 1.225 V being 410 µA. See the

graph “VREF Start-up.”

ERROR AMPLIFIER

The error amplifier is biased from the internal 5 V

supply (VL). The input common mode range extends

down to ground and up to 3.5 V. The output stage can

source in excess of 4 mA and can sink 1 mA. The

output stage is comprised of a class-A source follower

working into a 1 mA pull down (current sink), and is

designed to drive light loads such as an optocoupler

and the series resistor. The output source current IOH

is limited by an internal 500  resistor, to protect the

output in the event of a short to GND. When sourcing

current in excess of 1 mA, the voltage drop across this

resistor should be taken into account (see graph of

VOH vs. ILOAD). The 1 MHz amplifier has 75 degrees of

phase margin, and a large signal slew rate is (1 V/µs)

in a unitygain configuration. The input offset voltage is

typically 3 mV at 25 °C, and the offset voltage

temperature coefficient is typically 30 uV/°C. Due to its

CMOS inputs, the amplifier has low input bias and

offset currents. Both amplifier inputs as well as the

output are accessible, to facilitate meeting the

compensation requirements of specific applications.

Note that the error amplifier output is clamped low until

the VL voltage has increased past the CUVLOR

voltage level.

Document Number: 73868

S11-0975–Rev. C, 16-May-11

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Vishay Siliconix

SiP11203, SiP11204

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MOSFET RECTIFIER DRIVERS

Start-Up

At converter start-up, VL will typically be at or near 0 V.

Until such time as the UVLOR threshold is exceeded,

the main synchronous rectifier drivers are disabled, as

the supply voltage for the IC may be insufficient to

ensure that the output drivers will fully respond to input

commands. Without precautionary measures,

capacitive coupling between the drains and gates of

the synchronous rectifiers could cause spurious

conduction in the rectifiers. To prevent this, special

hold-off MOSFETs are switched in until the main

drivers are enabled. These internal hold-off

MOSFETs, which connect from OUTA to PGND and

OUTB to PGND, can typically conduct in excess of

400 mA with 1 V on OUTA or OUTB (ZOUT 2.5 ).

Once VL rises above UVLOR, the main drivers are

enabled and the part assumes its normal mode of

operation, with pulses at INA being used to control

OUTA and pulses at INB being used to control OUTB.

Figure 3 and its related text provide additional details

on this topic.

Normal Operation

When enabled, the main driver outputs are non-

inverting with respect to the input signal. The drivers

are designed to provide the high peak currents

(2 - 4 A) required to rapidly charge and discharge the

gates of large synchronous rectifier MOSFETs, with a

greater turn-off (pull-down) current than turn-on

(pull-up) current, to prevent shoot-through in the

synchronous rectifiers.

Shut-Down

In the typical application circuit, cessation of primary

timing signals at INA and INB would cause both OUTA

and OUTB to be pulled high, which at the system level

would short-circuit of the converter output to ground

via the synchronous rectifiers. To avoid possible

negative effects of such an event, the SiP11203/

SiP11204 uses a missing-pulses detector to monitor

INA and INB and, if necessary, set the main output

drivers to a high-impedance state. At the same time

that the main drivers are disabled, a pull-down device

(current sink) of user-settable value is enabled on each

output, to gradually discharge OUTA and OUTB,

thereby performing a soft turn-off of the rectifier

MOSFETs. The pull-down current is set by the RPD

resistor, and is given by the formula

IPULL-DOWN = 500 V/RPD. Such an event also causes

bypass capacitor at the the VREF pin to be discharged,

preparing the IC for a voltage-loop soft-start should the

primary resume sending timing signals. Further details

are given in the Applications Information section.

Synchronous Rectifier Phase-In

With a resistor connected between the RDEL pin and

ground, the SiP11203/SiP11204 will increase the low-

to-high propagation delay time from INA and INB to

OUTA and OUTB by an amount TDEL. This interval

is proportional to the resistance used, and inversely

proportional to the voltage on VREF (TDEL = k x RDEL/

VREF). As this delay occurs for high-going input

transitions only, it constitutes a hold-off time for the

synchronous rectifiers. As can be seen, TDEL

decreases as VREF ramps from a low level to its final

1.225 V level at start-up, or following any soft-start

event. If TDEL is set to start at a sufficient value to

allow only diode-mode conduction in the rectifier

MOSFETs, the result will be a gentle transition from

diode-mode operation to fully synchronous

rectification, thereby avoiding a sudden change in the

average voltage drop seen at the output rectifiers.

Conventional operation can be achieved by tying the

RDEL pin to VL. The synchronous rectifier phase-in

function is explained in more detail in the Applications

Information section.

Output Over-voltage Protection: SiP11203 versus

SiP11204

For maximum flexibility in the way that the SiP11203/

SiP11204 parts react to an output over-voltage event,

the input to the over-voltage protect comparator

(OVPIN) is brought out separately from the error

amplifier inputs. Additionally, the outputs of the

SiP11203 and the SiP11204 respond differently to

an over-voltage: the SiP11203 is designed to rapidly

discharge an output bus that is experiencing an over-

voltage, while the SiP11204 is designed to avoid

sinking current from other supplies feeding the same

bus, relying instead upon system-level intervention to

provide complete load protection. The OVPIN function

is explained in more detail in the Applications

Information section.

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Document Number: 73868

S11-0975–Rev. C, 16-May-11

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SiP11203, SiP11204

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APPLICATIONS INFORMATION

Powering SiP11203/SiP11204

The SiP11203/SiP11204 has an internal pre-regulator

to provide 5 V at VL, which biases many of the internal

sub-circuits. This allows the IC to operate from any

input voltage within the allowable VIN range. At the

same time, VIN provides the supply voltage to the gate

driver outputs (OUTA and OUTB) directly. The gate

drive level to the synchronous rectifier MOSFETs is

determined by VIN

The VIN voltage can be derived using conventional

methods, such as an extra winding on the power

transformer or on the output inductor. Alternatively,

this supply can be derived from the pulse transformer

used to transmit synchronous rectifier timing signals

from the primary to the secondary, as shown in Figure

2 below. The voltage level on VIN will be determined by

the turn ratio of the pulse transformer and the

differential voltage between SRL of the Si9122,

Si9122A, Si9122E and SRH of of the Si9122, Si9122A,

Si9122E. Note that this circuit will cause the voltages

at INA and INB to be twice that of VIN. Therefore it may

be necessary to limit the voltage seen by INA and INB

in order to avoid exceeding their recommended

operating values.

START-UP DRIVER OPERATION

During start-up of the SiP11203/SiP11204, the

MOSFET drivers (OUTA and OUTB) are disabled until

VL is at 90 % of its final value. To fully prevent any

spurious turn-on of the synchronous rectifier

MOSFETs, the gates of the MOSFETs are held off

during this start up period. Until the main drivers are

enabled, the INA and INB drive paths are re-routed, or

“swapped,” inside the IC. In conjunction with a

dedicated n-channel hold-off MOSFET “inverter”

placed in parallel with each main driver, this allows the

IC to ground the appropriate synchronous rectifier gate

at the necessary time. See Figure 3.

If the first two pulses coming through the pulse

transformer are considered, the following sequence of

events follows:

• INA goes low, which would normally command the

OUTA driver to go low. This would prevent spurious

turn-on of the associated synchronous rectifier.

However, since the voltage to the IC is below its

normal operating level, it cannot be guaranteed that

OUTA can in fact go to its necessary state. For this

reason, the OUTA and OUTB drivers are disabled

while VL < UVLOR.

• When INA goes low, INB will be driven to a level of

2 x VIN. This is due to the way in which the

secondary of the pulse transformer is rectified to

provide VIN. Specifically, this results from the

rectifier diodes clamping the secondary’s negative

excursions one diode drop below ground (See

Figure 2).

Figure 2. Typical schematic showing how the VIN supply for SiP11203/SiP11204 is generated using the pulse transformer providing the

synchronous rectifier timing signals

SRH

SRL

INA

INB

GND

SiP11203

SiP11204

SRH

SRL

INA

INB

GND

SiP11203

SiP11204

SiP11203

SiP11204

Document Number: 73868

S11-0975–Rev. C, 16-May-11

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SiP11203, SiP11204

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• While VL is below the UVLOR threshold, the IC

“swaps” the synchronous rectifier drive paths. This

causes the high-going signal on INB to be applied

to the gate of an n-channel hold-off MOSFET,

which is in parallel with the main OUTA driver. This

MOSFET inverts the signal from INB, which causes

its drain to be pulled towards ground. This holds

OUTA low.

• During the deadtime in which neither INB nor INA is

driven high, the voltage on INA and that on INB will

be equal to the voltage on VIN. Depending upon the

exact value of VIN, this may or may not result in

both OUTA and OUTB being pulled low by their

associated inverter MOSFETs.

• During the next cycle of converter operation, all of

the above applies with the exception that INB is

now driven low, which will cause INA to be driven

high. This will in turn cause the hold-off MOSFET in

parallel with the main OUTB driver to conduct,

thereby holding OUTB low.

In this way, the SiP11203/SiP11204 “swap and invert”

function prevents any unwanted turn-on of the

synchronous rectifiers during start-up. Once VL

reaches 90 % of its final value, the drive path inside the

IC is no longer swapped, and the inverting hold-off

MOSFETs are disabled.

FUNCTIONAL BLOCK DIAGRAM

START-UP DRIVER OPERATION

Assuming that VIN rises with suitable rapidity to a

voltage greater than 5.5 V, the factors controlling the

rate of rise of VL are the external VL bypass capacitor

value and the pre-regulator’s current limit. This gives

the following two equations:

• The time from start-up to

CUVLOR  (4.45 V/35 mA) x CVL, and

• The time from start-up to

UVLOR (4.45 V/35 mA) x CVL.

Once VL has reached 90 % of its final value, the clamp

holding VREF at 0 V is released, allowing the voltage on

the VREF pin to rise at a rate set by the value of the

VREF capacitor. This gives the following equation:

• The time from UVLOR to VREF attaining a voltage of

1.1 V (1.1 V/410 µA) x CVREF.

These relationships are shown in Figure 4.

Figure 3. During converter startup, the synchronous MOSFET gate-driver outputs of the SiP11203/SiP11204 are reversed and inverted

to prevent spurious MOSFET switching

Hold-off

MOSFET

Hold-off

MOSFET

SW1 and SW2 are closed at start-up.

SW1 and SW2 open when V

> UVLO

SW1

SW2

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Document Number: 73868

S11-0975–Rev. C, 16-May-11

Vishay Siliconix

SiP11203, SiP11204

This document is subject to change without notice.

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NORMAL DRIVER OPERATION

In normal operation, OUTA responds to INA, and

OUTB to INB. The signal path from input to output is

non-inverting. The output drivers have high and

deliberately asymmetrical current sink and source

capabilities (4 A ISINK, 2.2 A ISOURCE). The high

currents allow driving large synchronous rectifiers at

the switching frequencies found in modern power

converters. At the same time, the driver asymmetry

enforces a rapid turn-off of the rectifier MOSFETs

relative to their turn-on, to avoid rectifier

crossconduction, and the low driver impedances to

PGND help ensure that the rectifier MOSFETs do not

exhibit unwanted turn-on during converter operation.

As with most logic circuits, OUTA and OUTB do not

exhibit indeterminate output states even the transitions

at INA and INB are excessively slow. The solid and

sharp driving signals from OUTA and OUTB will ensure

the proper function of the rectifier MOSFETs in the

final application circuit.

POWER-DOWN DRIVER OPERATION

If the timing pulses from the primary of the DC-DC

converter cease, the SiP11203/SiP11204 must

assume that the power to the primary of the DC-DC

converter has failed. Upon detecting this condition, the

part must put the main synchronous rectifier drivers

into a “safe” condition, and simultaneously ensure that

the rectifier MOSFETs are turned off. A unique feature

of the SiP11203/SiP11204 is their ability to turn off the

synchronous rectifiers via a controlled excursion

through their linear region. This can help to prevent

output ringing at turn-off.

A missing-pulses detector is provided on the IC to

initiate the soft power down. This detector, which is

enabled once the VREF pin has reached 1.1 V,

continually monitors INA and INB for lack of switching

activity. An external resistor from RPD to ground

defines a current out of CPD (I = 2.5 V/RPD), which is

used to charge an external capacitor from CPD to

ground. The voltage on CPD is internally compared to

the 2.5 V developed by VREFINT

. Whenever either input

goes low, the voltage at CPD is reset to 0 V. However, if

both inputs are high for a period of RPD × CPD, the

voltage at CPD will exceed the 2.5 V comparison

threshold, and the power-down latch will be set (See

Figure 6).

• The VREF pin bypass capacitor is discharged

towards 0 V, to ensure an orderly soft-start cycle

when operation resumes,

• The main drivers are forced into a high-impedance

state,

• Internal pull-downs (current sinks) from the OUTA

and OUTB pins to ground are enabled,

• The pull-down currents on OUTA and OUTB are set

by RPD, to allow a “soft” turn-off of the synchronous

rectifiers.

Figure 4. Soft-start parameters of the SiP11203/SiP11204 are programmable with external components

REF

0.9* VL

3.55 V

time

1.225 V

5 V

Internal

logic

circuits

enabled

REF

released to

rise

Rate of rise determined by

external V

REF

capacitor

Rate of rise determined by

external V

capacitor

2.5 V

REFINT

Enabled by CUVLO

Document Number: 73868

S11-0975–Rev. C, 16-May-11

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Vishay Siliconix

SiP11203, SiP11204

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POWER-DOWN DRIVER OPERATION (CONT’D)

The internal pull-downs ensure that the synchronous

rectifiers are in the off state before the bias supply to

the IC has collapsed (See Figure 5). Since these pull-

downs have a lower current-sinking capability than the

main OUTA and OUTB drivers, they can cause the

rectifier MOSFETs to transition from full conduction to

the off state via their linear region of operation. This

soft turn-off allows the use of the gradually increasing

rectifier channel impedances to help damp LC

oscillations that might otherwise occur at the

converter's output. The gate pull-down current value,

and therefore the interval during which the rectifier

MOSFETs are in transition from fully on to fully off, is

programmed by the resistor from RPD to ground. This

current is given by IPULL-DOWN = 200* VREFINT/RPD.

This programmability allows the choice of a gate

discharge time which best accommodates the design

variables of LOUT

, COUT

, and synchronous rectifier

MOSFET characteristics.

The power-down latch will be reset, and a soft-start

cycle will occur, when the logical and of two conditions

is true:

•

The voltage on the V

REF

capacitor is 20 % (245 mV)

of its nominal 1.225 V, and

• The exclusive-or of INA and INB is true, that is, one

input is in low while the other is high.

Note that low values of RPD will increase the main

supply current. It is recommended that RPD be kept

15 k to prevent excessive power dissipation.

SYNCHRONOUS RECTIFIER PHASE-IN AND

RISING EDGE DELAY

The SiP11203/SiP11204 has the ability to “phase in”

the synchronous rectifiers at start-up. This causes the

rectifier MOSFETs to initially be used as conventional

PN (or Schottky) diodes, then as synchronous

rectifiers for an increasing percentage of each

switching cycle, until finally they are operating

completely as synchronous switches. When this

feature of the IC is used, the resistance RDEL, which is

connected between the RDEL pin and ground,

determines the time required for the transition from

diode-mode operation to fully synchronous

rectification.

To achieve this phase-in of the synchronous rectifiers,

an internally extended propagation delay (TDEL) is

introduced between the rising edge of each input (INA

or INB) and the rising edge of the corresponding output

(OUTA or OUTB). The length of this delay is

proportional to RDEL and inversely proportional to

VREF: TDEL (1.5 ns x RDEL x 1.225 V)/(1 k x VREF).

Therefore TDEL decreases throughout the interval

during which VREF is rising (i.e., during the time

following converter start-up or a SiP11203/SiP11204

soft-start event). When the phase-in period has ended,

the final high-going propagation delay is TDEL(FINAL) =

Tpdr + TDEL(FINAL) = Tpdr + [(1.5 ns x RDEL)/1 k], as

shown in the typical curves.

Figure 5. The shutdown sequence of SiP11203/SiP11204

prevents the synchronous MOSFET of a half-bridge converter

from discharging a prebiased output when supplied power is

removed

INA/B

OUTA/B

CPD

VREF

2.5V

VIN

RESTARTSHUTDOW

Figure 6. Power Down Detect and “Soft” Turn-Off

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Document Number: 73868

S11-0975–Rev. C, 16-May-11

Vishay Siliconix

SiP11203, SiP11204

This document is subject to change without notice.

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SYNCHRONOUS RECTIFIER PHASE-IN AND

RISING EDGE DELAY

(CONT’D)

The three modes of operation experienced during

synchronous rectifier phase-in are, in order:

• Some number of converter switching cycles may

occur during which TDEL 2/fCONVERTER. During

this interval, the synchronous rectifiers are held off

for a long enough time that they will act as conven

ional diodes only. This interval of operation will be

some portion of the time it takes for the voltage on

the VREF pin to climb to its final 1.225 V value.

• Some number of converter switching cycles will

occur during which 2/fCONVERTER > TDEL >

TDEL(FINAL). During this interval, the synchronous

rectifiers are held off for a portion of their possible

conduction interval, with that percentage

decreasing in a 1/x fashion from 100 % of their

possible conduction time to a percentage set by

RDEL and fCONVERTER. This interval of operation

will be the remainder of the time it takes for the

voltage on the VREF pin to climb to its final 1.225 V

value.

• When VREF is equal to 1.225 V, normal converter

operation occurs, with the synchronous rectifiers

being held off for a time TDEL(FINAL). This final delay

time can be made equal to the inherent propagation

delay of the IC’s output drivers, as described below.

The synchronous rectifier phase-in is diagrammed in

Figure 7.

Connecting RDEL to VL will completely disable the

synchronous rectifier phase-in circuitry. The rectifier

MOSFETs will then transition directly from diode-mode

full synchronous rectifier operation when the IC’s VL

supply exceeds the UVLOR threshold. The residual

rising-edge delay otherwise introduced by RDEL will

also be set to zero. (Note: By examination of the above

equations, grounding the RDEL pin could be another

means of setting TDEL to zero. Doing so is not

recommended in practice as this will cause

unnecessary power dissipation in the IC: the supply

current will increase by 0.15 mA if RDEL is connected

to VL, but by 0.5 mA if this pin is shorted to ground.

Also, due to the internal circuitry of the ICs, the

propagation delay time is reduced by several

nanoseconds when the RDEL pin is connected to VL as

opposed to when it is grounded.)

In some applications it is desirable to make use of the

rectifier phase-in feature while eliminating the residual

TDEL. To achieve this, the appropriate resistance

should be connected from the RDEL pin to ground, and

the RDEL pin should be pulled up to VL using a suitable

op-amp or comparator, such as the LMV321M7, once

the output voltage of the converter approaches its final

value. In such a circuit, VCC for the op-amp or

comparator should be obtained from VL of the

SiP11203/SiP11204.

The phase-in of synchronous rectification helps to

prevent disturbances in the output voltage at start-up,

which could occur due to the differential in output

voltage drop which occurs when the rectifier

MOSFETs make an abrupt transition from operation as

diodes to operation as synchronous rectifiers.

Figure 7. The SiP11203/SiP11204 gate-drive output signals are delayed during phase-in prevent disturbing the output voltage

time

OUT

Rising edge delay reduces during phase-in. Phase-in

period set R

DEL

OUT

Rising edge delay during normal operation. Period set

by R

DEL

(Note: can be set to zero)

Phase-In finished

Phase-In period

Document Number: 73868

S11-0975–Rev. C, 16-May-11

www.vishay.com

Vishay Siliconix

SiP11203, SiP11204

This document is subject to change without notice.

THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

The Figure 8 below shows how the rising edge delay is

implemented in conjunction with the Si9122 and allows

the effective BBM2 and BBM4 falling delays to be

modified independently of rising delays BBM1 and

BBM3. For definition of the BBM delays please see the

Si9122 datasheet.

OUTPUT OVER-VOLTAGE PROTECTION

The SiP11203/SiP11204 provide output over-voltage

protection (OVP) by means of a dedicated internal

comparator. One input of the OVP comparator is

brought out to the OVPIN pin, and the other is returned

to an internal reference voltage that is fixed at 120 %

of the 1.225 V VREF value, or 1.47 V. A voltage in

excess of 1.47 V at the OVPIN pin indicates an OVP

fault.

The OVP circuitry operates in two different ways,

depending upon whether the SiP11203/SiP11204 is in

start-up mode, or in normal operation. In this context,

start-up mode is defined as device operation during

that period for which V

REF

is less than 90 % of its 1.225 V

value, or 1.1 V

Start-Up Mode:

If the 1.47 V OVP threshold is exceeded during start-

up, the driver outputs OUTA and OUTB are held low

until the voltage on the VREF pin has exceeded 1.1 V.

The driver outputs are then released to respond to INA

and INB.

Normal Operation Mode:

If the OVP threshold is exceeded, or remains

exceeded, after VREF has reached 1.1 V, the OVP latch

will be set. This will cause the driver outputs to be

forced high for SiP11203, or forced low for SiP11204.

At the same time, an on-chip transistor will discharge

the bypass capacitor at the VREF pin towards ground.

The OVP latch is reset when the logical and of two

conditions:

•

The voltage on the V

REF

pin must be





20 % (245 mV)

of its nominal 1.225 V level, to ensure an orderly

soft-start cycle when operation resumes, and

• The voltage at the OVPIN pin must be 1.1 V,

indicating that the OVP fault has been cleared.

When the OVP latch is reset, the SiP11203/SiP11204

will release their outputs, and return to normal

operation via a soft-start cycle.

To prevent spurious activation of the over-voltage

function, the over-voltage condition must be present for

five switching instances, where a switching instance is

defined as activity on either INA or INB. On the fifth

switching instance the overvoltage condition is latched.

If the over voltage condition disappears the IC will not

recognize an over-voltage as being present and the

counter will be reset to zero.

Note that the OVPIN threshold voltage is derived from

the internal 2.5 V reference voltage VREFINT

, which is

derived from VIN, and therefore is not delayed by the

rise time of either VL or VREF

Figure 8. The delay of SiP11203 and SiP11204 gate-drive output signals compensate the break-before-make switching action

discrepancies arising from propagation delays

PWM PWM

PWM

DL DL

OUT A OUT A

BBM1 BBM2 BBM3 BBM4

Rising edge

delay set by R

DEL

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Document Number: 73868

S11-0975–Rev. C, 16-May-11

Vishay Siliconix

SiP11203, SiP11204

This document is subject to change without notice.

THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

TYPICAL CHARACTERISTICS

VREF vs. Temperature

Error Amp VOH vs. IOH

Supply Current Without Load vs. VIN

1.16

1.18

1.2

1.22

1.24

1.26

1.28

- 50 0 50 100 150

Temperature (°C)

VREF (V)

VIN = 7.5 V

0.5

1.5

2.5

3.5

0 1 2 3 4

IOH (mA)

O)V

(

5 7 9 11 13 15

VIN

(V)

INI(mA)

fIN

= 1 MHz

fIN

= 500 kHz

fIN

= 250 kHz

VL vs. Temperature

Error Amp VOL vs. IOL

250 kHz Supply Current vs. CL

4.75

4.8

4.85

4.9

4.95

5.05

5.1

5.15

5.2

5.25

- 50 0 50 100 150

Temperature (°C)

VL(V)

V = 7.5 V

= 3 mA

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0 0.4 0.8 1.2 1.6

IOL

(mA)

VOL(V)

5 7 9 11 13

VIN

(V)

IIN(mA)

CL = 6 nF

CL = 3 nF

= 0 nF

Document Number: 73868

S11-0975–Rev. C, 16-May-11

www.vishay.com

Vishay Siliconix

SiP11203, SiP11204

This document is subject to change without notice.

THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

TYPICAL CHARACTERISTICS

Quiescent Current vs. RDEL

Quiescent Current vs. RPD

RD(SOURCE) vs. Temperature

3.5

3.6

3.7

3.8

3.9

4.1

4.2

0 10 20 30

RDEL

(kΩ)

I (mA)

VIN = 7.5 V

CPD

= 10 nF

0 5 10 15 20 25 30

RPD

(kΩ)

I (mA)

VIN = 7.5 V

CPD = 10 nF

1.2

1.6

2.4

2.8

3.2

- 50 0 50 100 150

Temperature (°C)

RD(SOURCE)(Ω)

VIN = 5.5 V

VIN = 7.5 V

VIN

= 13 V

Rise Delay vs. RDEL

Powerdown Timeout vs. RPD

RD(SINK) vs. Temperature

0 5 10 15 20 25 30

RDEL

(kΩ)

Rise Delay (ns)

VIN

= 7.5 V

1.5 ns/ kΩ

100

150

200

250

300

0 10 20 30

RPD

(kΩ)

RDP C// DP (ns)

1.1

1.2

1.3

1.4

1.5

1.6

- 50 0 50 100 150

Temperature (°C)

RD(SINK) (Ω)

VIN = 5.5 V

VIN = 7.5 V

VIN = 1.3 V

Terminal Tip

Index Area

(Dń2 Eń2)

ÉÉÉ

Exposed Pad 8

-B-

D/2

E/2

-A-

Caaa 2 X

Top View

AA1 A3

-C-

Seating Plane

Side View

Detail A

C0.08

Cccc//

D2/2

Detail B

(NE-1) x e

N L

E2/2

Detail A

N-1N

(ND-1) x e

Bottom View

Cbbb MA B

N b5

Datum A or B

N r

Terminal Tip

Even Terminal/Side Odd Terminal/Side

Detail B

e/2

Caaa 2 X

Package Information

Vishay Siliconix

Document Number: 72802

16-May-05

www.vishay.com

PowerPAKr MLP44-16 (POWER IC ONLY)

JEDEC Part Number: MO-220

NOTES:

1. Dimensioning and tolerancing conform to ASME Y14.5M-1994.

2. All dimensions are in millimeters. All angels are in degrees.

3. N is the total number of terminals.

4. The terminal #1 identifier and terminal numbering convention shall conform to JESD 95-1 SPP-012. Details of terminal #1 identifier are optional, but must

be located within the zone indicated. The terminal #1 identifier may be either a molded or marked feature. The X and Y dimension will vary according to

lead counts.

5. Dimension b applies to metallized terminal and is measured between 0.25 mm and 0.30 mm from the terminal tip.

6. ND and NE refer to the number of terminals on the D and E side respectively.

7. Depopulation is possible in a symmetrical fashion.

8. Variation HHD is shown for illustration only.

9. Coplanarity applies to the exposed heat sink slug as well as the terminals.

Package Information

Vishay Siliconix

www.vishay.com

Document Number: 72802

16-May-05

PowerPAKr MLP44-16 (Power IC Only)

JEDEC Part Number: MO-220

MILLIMETERS* INCHES

Dim Min Nom Max Min Nom Max Notes

A 0.80 0.90 1.00 0.0315 0.0354 0.0394

A1 0 0.02 0.05 0 0.0008 0.0020

A3 −0.20 Ref − − 0.0079 −

AA −0.345 − − 0.0136 −

aaa −0.15 − − 0.0059 −

BB −0.345 − − 0.0136 −

b 0.25 0.30 0.35 0.0098 0.0118 0.138 5

bbb −0.10 − − 0.0039 −

CC −0.18 − − 0.0071 −

ccc −0.10 − − 0.0039 −

D4.00 BSC 0.1575 BSC

D2 2.55 2.7 2.8 0.1004 0.1063 0.1102

DD −0.18 − − 0.0071 −

E4.00 BSC 0.1575 BSC

E2 2.55 2.7 2.8 0.1004 0.1063 0.1102

e0.65 BSC 0.0256 BSC

L 0.3 0.4 0.5 0.0118 0.0157 0.0197

N 16 16 3, 7

ND −4− − 4−6

NE −4− − 4−6

r b(min)/2 − − b(min)/2 − −

* Use millimeters as the primary measurement.

ECN: S-50794—Rev. B, 16-May-05

DWG: 5905

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