X76F641XG - IC Microsystems Sdn. Bhd.

∧Xicor, Inc. 1994, 1995, 1996 Patents

Pending 9900-5004.5 3/9/99 EP 1

Characteristics subject to change without notice

64K

X76F641

8Kx8

+

32x8

Functional Diagram

Secure Serial Flash

FEATURES

•64

-

bit Password Security

—Five 64-bit Passwords for Read, Program

and Reset

•8192 Byte+32 Byte Password Protected Arrays

—

Seperate Read Passwords

—Seperate Write Passwords

—

Reset Password

•Programmable Passwords

•Retry Counter Register

—

Allows 8 tries before clearing of both arrays

—Password Protected Reset

•32

-

bit Response to Reset (RST Input)

•32 byte Sector Program

•400kHz Clock Rate

•2 wire Serial Interface

•Low Power CMOS

—

2.0 to 5.5V operation

—Standby current Less than 1µA

—Active current less than 3 mA

•High Reliability Endurance:

—100,000 Write Cycles

•Data Retention: 100 years

•Available in:

—

8 lead EIAJ SOIC

—SmartCard Module

DESCRIPTION

The X76F641 is a Password Access Security Supervisor,

containing one 65536-bit Secure Serial Flash array and

one 256-bit Secure Serial Flash array. Access to each

memory array is controlled by five 64-bit passwords

each. These passwords protect read and write opera-

tions of the memory array. A separate RESET password

is used to reset the passwords and clear the memory

arrays in the event the read and write passwords are lost.

The X76F641 features a serial interface and software

protocol allowing operation on a popular two wire bus.

The bus signals are a clock Input (SCL) and a bidirec-

tional data input and output (SDA).

The X76F641 also features a synchronous response to reset

providing an automatic output of a hard-wired 32-bit

data stream conforming to the industry standard for

memory cards.

The X76F641 utilizes Xicor’s proprietary Direct Write

TM

cell,

providing a minimum endurance of 100,000 cycles

and a minimum data retention of 100 years.

LOGIC

SCL

SDA

RST

INTERFACE

8K BYTE

DATA TRANSFER

ARRAY ACCESS

ENABLE

RESET

RESPONSE REGISTER

PASSWORD ARRAY

AND PASSWORD

VERIFICATION LOGIC

RETRY COUNTER

SerialFlash ARRAY

32 BYTE

SerialFlash ARRAY

ARRAY 0

ARRAY 1

(PASSWORD PROTECTED)

7025 FM 01

This X76F641 device has been acquired by

IC MICROSYSTEMS from Xicor, Inc.

ICmic

IC MICROSYSTEMS

TM

X76F641

2

PIN DESCRIPTIONS

Serial Clock (SCL)

The SCL input is used to clock all data into and out of the

device.

Serial Data (SDA)

SDA is a true three state serial data input/output pin. During

a read cycle, data is shifted out on this pin. During a

write cycle, data is shifted in on this pin. In all

other cases, this pin is in a high impedance state.

Reset (RST)

RST is a device reset pin. When RST is pulsed high the

X76F641 will output 32 bits of fixed data which conforms

to the standard for “synchronous response to reset”.

The part

must not be in a write cycle for the response to reset to

occur. See Figure 11. If there is power interrupted dur-

ing the Response to Reset, the response to reset will be

aborted and the part will return to the standby state. The

response to reset is "mask programmable" only!

DEVICE OPERATION

There are two primary modes of operation for

the X76F641; Protected READ and protected WRITE.

Protected operations must be performed with one of four

8-byte passwords.

The basic method of communication for the device is

generating a start condition, then transmitting a com-

mand, followed by the correct password. All parts will be

shipped from the factory with all passwords equal to ‘0’.

The user must perform ACK Polling to determine the

validity of the password, before starting a data transfer

(see Acknowledge Polling.) Only after the correct pass-

word is accepted and a ACK polling has been performed,

can the data transfer occur.

To ensure the correct communication, RST must remain

LOW under all conditions except when running a

“Response to Reset sequence”.

Data is transferred in 8-

bit segments, with each transfer being

followed by an ACK, generated by the receiving

device.

If the X76F641 is in a nonvolatile write cycle a “no A

CK”

(SDA=High) response will be issued in response to loading

of the command byte. If a stop is issued prior to the

nonvolatile write cycle the write operation will be terminated

and the part will reset and enter into a standby

mode.

The basic sequence is illustrated in Figure 1.

PIN NAMES

PIN CONFIGU

RATION

After each transaction is completed, the X76F641 will

reset and enter into a standby mode. This will also be the

response if an unsuccessful attempt is made to access a

protected array.

Symbol

Description

SDA

Serial Data Input/Output

SCL

Serial Clock Input

RST

Reset Input

Vcc

Supply Voltage

Vss

Ground

NC

No Connect

SDA

V

CC

RST

SCL

NC

1

2

3

4

7

8

6

5

EIAJ SOIC

V

CC

RST

SCL

V

SS

NC

SDA

Smart Card

NC

7025 FM 02

NC

GND

NC

X76F641

3

Figure 1.

X76F641 Device Operation

Retry Counter

The X76F641 contains a retry counter. The retry counter

allows 8 accesses with an invalid password before any

action is taken. The counter will increment with any com-

bination of incorrect passwords. If the retry counter over-

flows, all memory areas are cleared and the device is

locked by preventing any read or write array password

matches. The passwords are unaffected. If a correct

password is received prior to retry counter overflow, the

retry counter is reset and access is granted. In order to

reset the operation of a locked up device, a special reset

command must be used with a RESET password.

Device Protocol

The X76F641 supports a bidirectional bus oriented proto-

col. The protocol defines any device that sends data onto

the bus as a transmitter and the receiving device as a

receiver. The device controlling the transfer is a master

and the device being controlled is the slave. The master will

always initiate data transfers and provide the clock for

both transmit and receive operations. Therefore, the

X76F641 will be considered a slave in all applications.

Clock and Data Conventions

Data states on the SDA line can change only during SCL

LOW. SDA changes during SCL HIGH are reserved for

indicating start and stop conditions. Refer to Figure 2 and

Figure 3.

Start Condition

All commands are preceded by the start condition,

which is a HIGH to LOW transition of SDA when SCL is

HIGH. The X76F641 continuously monitors the SDA and

SCL lines for the start condition and will not respond to

any command until this condition is met.

A start may be issued to terminate the input of a control

byte or the input data to be written. This will reset the

device and leave it ready to begin a new read or write

command. Because of the push/pull output, a start can-

not be generated while the part is outputting data. Starts are

inhibited while a write is in progress.

Stop Condition

All communications must be terminated by a stop condi-

tion. The stop condition is a LOW to HIGH transition of

SDA when SCL is HIGH. The stop condition is also used to

reset the device during a command or data input

sequence and will leave the device in the standby power

mode. As with starts, stops are inhibited when outputting

data and while a write is in progress.

Acknowledge

Acknowledge is a software convention used to indicate

successful data transfer. The transmitting device, either

master or slave, will release the bus after transmitting

eight bits. During the ninth clock cycle the receiver will

pull the SDA line LOW to acknowledge that it received the

eight bits of data.

The X76F641 will respond with an acknowledge after

recognition of a start condition and its slave address. If

both the device and a write condition have been

selected, the X76F641 will respond with an acknowledge

after the receipt of each subsequent eight-bit word.

Reset Device Command

The reset device command is used to clear the retry

counter and reactivate the device. When the reset device

command is used prior to the retry counter overflow, the retry

counter is reset and no arrays or passwords are

affected. If the retry counter has overflowed, all memory

areas are cleared and all commands are blocked and the

retry counter is disabled. Issuing a valid reset device

command (with reset password) to the device resets and

re-enables the retry counter and re-enables the other

commands. Again, the passwords are not affected.

Reset Password Command

A reset password command will clear both arrays and set all

passwords to all zero.

LOAD COMMAND BYTE

LOAD 2 BYTE ADDRESS

LOAD 8-BYTE

PASSWORD

VERIFY PASSWORD

ACCEPTANCE BY

USE OF PASSWORD ACK POLLING

READ/WRITE

DATA BYTES

7025 FM 03

Twc OR DATA ACK POLLING

X76F641

4

Figure 2. Data Validity

Figure 3. Definition of Start and Stop Conditions

Table 1. X76F641 Instruction Set

Notes:

Illegal command codes will be disregarded. The part will respond with a “no-A

CK” to the illegal byte and then return to the standby mode.

All write/read operations require a password.

1st Byte

after Start

1st Byte

after

Password

2nd Byte

after

Password

Comma

nd Description

Password

used

1000 0000 High Address Low address Read (Array 0) Read 0

1000 1000 High Address Low address Read (Array 1) Read 1

1001 0000 High Address Low address Sector Write (Array 0) Write 0

1001 1000 High Address Low address Sector Write (Array 1) Write 1

1010 0000 0000 0000 0000 0000 Change Read 0 Password Read 0

1010 1000 0000 0000 0000 0000 Change Read 1 Password Read 1

1011 0000 0000 0000 0000 0000 Change Write 0 Password Write 0

1011 1000 0000 0000 0000 0000 Change Write 1 Password Write 1

1100 0000 0000 0000 0000 0000 Change Reset Password Reset

1110 0000 not used

not used

Reset Password Command Reset

1110 1000 not used

not used

Reset Device Command Reset

1111 0000 not used

not used

ACK Polling command (Ends Password operation)

None

All the rest

Reserved

SCL

SDA

Data Stable Data

Change

7025 FM 04

SCL

SDA

Start Condition Stop Condition 7025 FM 05

7025 FM T04

X76F641

5

PROGRAM OPERATIONS

Sector Programming

The sector program mode requires issuing the 8-bit write

command followed by the password, password Ack

command, the address and then the data bytes trans-

ferred as illustrated in figure 4. Up to 32 bytes may be

transferred. After the last byte to be transferred is

acknowledged a stop condition is issued which starts the

nonvolatile write cycle.

Figure 4. Sector Programming

Data 31

S

COMMAND

Write

Password

7

Write

Password

0

Data 0

S

SDA

Wait tWC Data

ACK Polling

. . .

Wait tWC

OR

ACK POLLING

S

ACK Polling

Repeated

COMMAND

Command

If ACK, Then

Password Matches

7025 FM 07

ACK

START

ACK

A15

A14

A13

A12

A11

A10

A9

A8

A7

A6

A5

A4

A3

A2

A1

A0

ACK

STOP

ACK

NACK

START

X76F641

6

ACK Polling

Once a stop condition is issued to indicate the end of the

host’s write sequence, the X76F641 initiates the internal

nonvolatile write cycle. In order to take advantage of the

typical 5ms write cycle, ACK polling can begin

immediately. This involves issuing the start condition

followed by the new command code of 8 bits (1st byte of

the protocol.) If the X76F641 is still busy with the non

volatile write operation, it will issue a “no-A CK” in

response. If the nonvolatile write operation has completed,

an “ACK” will be returned and the host can

then proceed with the rest of the protocol.

After the password sequence, there is always a nonvolatile

write cycle. This is done to discourage random

guesses of the password if the device is being tampered

with. In order to continue the transaction, the

X76F641

requires the master to perform an ACK polling with the

specific code of F0h. As with regular Acknowledge polling

the user can either time out for 10ms, and then issue the ACK

polling once, or continuously loop as described in

the flow.

If the password that was inserted was correct, then an

“ACK” will be returned once the nonvolatile cycle is over,

in response to the ACK polling cycle immediately following

it.

If the password that was inserted was incorrect, then a

“no A

CK” will be returned even if the nonvolatile cycle is

over. Therefore, the user cannot be certain that the pass-

word is incorrect until the 10ms write cycle time has

elapsed.

Data ACK Polling Sequence

ACK

RETURNED?

ISSUE NEW

COMMAND

CODE

WRITE SEQUENCE

COMPLETED

ENTER ACK POLLING

ISSUE START

NO

YES

PROCEED

7025 FM 08

Password ACK Polling Sequence

ACK

RETURNED?

ISSUE

PASSWORD

ACK COMMAND

PASSWORD LOAD

COMPLETED

ENTER ACK POLLING

ISSUE START

NO

YES

PROCEED

7025 FM 09

X76F641

7

Figure 5. Acknowledge Polling

8th clk.

of 8th

pwd. byte

‘ACK’

clk

8th

clk

‘ACK’

clk

‘ACK’

START

condition

8th bit

ACK or

no ACK

SCL

SDA

7025 FM 10

READ OPERATIONS

Read operations are initiated in the same manner as write

operations but with a different command code.

Random Read

The master issues the start condition and a Read instruc-

tion and password, performs a Password Ack Polling, then

issues the word address. Once the password has been

acknowledged and first byte has been read, another start

can be issued followed by a new 8-bit address. Random

reads are allowed, but only the low order 8 bits can

change. This limits random reads to a 256 byte block.

Therefore, with a single password cycle only a 256 byte

block of array 0 may be accessed randomly. To randomly

access another block of array 0, a stop must be issued fol-

lowed by a new command/address/password sequence.

A random read of the array 1 can access all locations with-

out another password command sequence.

Sequential Read

The host can read sequentially within an array after the

password acceptance sequence. The data output is

sequential, with the data from address n followed by the data

from n+1. The address counter for read operations

increments all address bits, allowing the entire memory

array contents to be serially read during one operation. At

the end of the address space (address 1FFFh for array 0,

1Fh for array 1), the counter “rolls o

ver” to address 0 and the

X76F641 continues to output data for each acknowl- edge

received. Refer to figure 7 for the address, acknowledge

edge and data transfer sequence. An acknowledge must

follow each 8-bit data transfer. After the last bit has been

read, a stop condition is generated without a preceding

acknowledge.

Figure 6. Random Read

S

Data Y

S

COMMAND

Read

Password

7

Read

Password

0

S

SDA

Data X

Wait tWC

OR

ACK POLLING

S

ACK Polling

Repeated

COMMAND

Command

If ACK, then

Password Matches

7025 FM 11

ACK

STOP

A

7

A6

A5

A4

A3

A2

A1

A0

START

ACK

A15

A14

A13

A12

A11

A10

A9

A8

A7

A6

A5

A4

A3

A2

A1

A0

START

ACK

NACK

X76F641

8

Figure 7. Sequential Read

Data X

S

COMMAND

Read

Password

7

Read

Password

0

S

SDA

Data 0

If ACK, then

Wait tWC

OR

ACK POLLING

S

ACK Polling

Repeated

COMMAND

Command

Password Matches

7025 FM 12

PASSWORDS

The sequence in Figure 8 shows how to change (pro-

gram) the passwords. The programming of passwords is

done twice prior to the nonvolatile write cycle in order to

verify that the new password is consistent. After the eight

bytes are entered in the second pass, a comparison

takes place. A mismatch will cause the part to reset and

enter into the standby mode.

Data ACK polling can be used to determine if a password

has been loaded correctly, however the data ACK com-

mand must be issued less than 2ms after the stop bit.

After this time, it cannot be determined if the password

has been loaded correctly, without trying the new pass-

word. To determine if the new password has been loaded

correctly the data ACK polling command is issued imme-

diately following the stop bit. If it returns an ACK, then the

two passes of the new password entry do not match. If it

returns a "no ACK" then the passwords match and a high

voltage cycle is in progress. The high voltage cycle is

complete when a subsequent data ACK command

returns an "ACK".

There is no way to read any of the passwords.

Figure 8. Change Passwords

COMMAND

Old

Password

7

Old

Password

0

S

SDA

New

Password

7

Password

0

New

Password

7

New

Password

0

S

If ACK, then

Two bytes of “0”

Wait tWC

OR

ACK POLLING

S

ACK Polling

Repeated

COMMAND

Command

Password Matches

If immediate ACK,

then New Password error

Data ACK

Polling

If immediate NACK,

then New Password OK

followed by ACK after ~5ms

7025 FM 13

ACK

START

ACK

A15

A14

A13

A12

A11

A10

A9

A8

A7

A6

A5

A4

A3

A2

A1

A0

A

CK

START

ACK

NACK

STOP

START

ACK

STOP

ACK

START

ACK

NACK

X76F641

9

Figure 9. Reset Password

Figure 10

. Reset Device

Reset Password

Reset

Password

7

Reset

Password

0

S

SDA

Wait tWC

OR

ACK POLLING

S

ACK Polling

Repeated

COMMAND

Command

S

If ACK, then

Device reset

COMMAND

7025 FM 14

Reset Device

Reset

Password

7

Reset

Password

0

S

SDA

Wait tWC

OR

ACK POLLING

S

ACK Polling

Repeated

COMMAND

Command

S

If ACK, then

Device reset

COMMAND

7025 FM 15

RESPONSE TO RESET (DEFAULT = 19 41 AA 55)

The ISO Response to reset is controlled by the RST and

CLK pins. When RST is pulsed high during a clock pulse,

the device will output 32 bits of data, one bit per clock,

and it resets to the standby state. This conforms to the

ISO standard for “synchronous response to reset”.

The part

must not be in a write cycle for the response to reset to

occur.

After initiating a nonvolatile write cycle the RST pin must

not be pulsed until the nonvolatile write cycle is complete.

If not, the ISO response will not be activated. If the RST

is pulsed HIGH and the CLK is within the RST pulse

(meet the t

NOL

spec.) in the middle of an ISO transaction,

it will output the 32 bit sequence again (starting at bit 0).

Otherwise, this aborts the ISO operation and the part

returns to standby state. If the RST is pulsed HIGH and the

CLK is outside the RST pulse (in the middle of an

ISO transaction), this aborts the ISO operation and the

part returns to standby state.

If there is power interrupted during the Response to

Reset, the response to reset will be aborted and the part

will return to the stan

dby state. A Response to Reset is not

available during a nonvolatile write cycle.

START

ACK

START

ACK

NACK

STOP

START

ACK

START

ACK

NACK

STOP

X76F641

10

RECOMMENDED OPERATING CONDITIONS

7025 FM T05 7025 FM T06

Temp

Min.

Max.

Commercial 0°C

+70°C

Extended

–20°C

+85°C

Supply Voltage

Limits

X76F641

4.5V to 5.5V

X76F641 – 2.0

2.0V to 3.6V

ABSOLUTE MAXIMUM RATINGS*

Temperature under Bias ...................... –65°C to +135°C

Storage Temperature ........................... –65°C to +150°C

Voltage on any Pin with

Respect to V

SS

...................................... –1V to +7V

D.C. Output Current .................................................. 5mA

Lead Temperature

(Soldering, 10 seconds) ................................. 300°C

*COMMENT

Stresses above those listed under “Absolute Maximum

Ratings” may cause permanent damage to the device.

This is a stress rating onl

y and the functional operation of the

device at these or any other conditions above those

listed in the operational sections of this specification is

not implied. Exposure to absolute maximum rating condi-

tions for extended periods may affect device reliability.

Figure 11. Response to RESET (RST)

SCK

SO

RST

Byte

0

MSB

LSB

MSB

1

LSB

MSB

LSB

MSB

2

3

10

0

00

11

1

0

1

0000

0

1

0

1

0

1

0

X76F641

11

EQUIVALENT A.C. LOAD CIRCUIT

A.C. TEST CONDITIONS

7002 FM T09

3V

1.3K

Ο

OUTPUT

100pF

5V

1533

Ο

OUTPUT

100pF

7025 FM 17

Input Pulse Levels

V

CC

x 0.1 to V

CC

x 0.9

Input Rise and Fall Times 10ns

Input and Output Timing Level

V

CC

x 0.5

Output Load 100pF

D.C. OPERATING CHARACTERISTICS

(Over the recommended operating conditions unless otherwise specified.)

7002 FM T07

CAPACITANCE T

A

= +25°C, f = 1MHz, V

CC

= 5V

7002 FM T08

NOTES:

(1)

Must perform a stop command after a read command prior to measurement

(2)

V

IL

min. and V

IH

max. are for reference only and are not tested.

(3)

This parameter is periodically sampled and not 100% tested.

Symbol

Parameter

Limits

Units

Test Conditions

Min.

Max.

I

CC1

V

CC Supply Current

(Read) 1

mA

fSCL = VCC x 0.1/VCC x 0.9 Levels @ 400 KHz, SDA =

Open

RST = V

SS

I

CC2

(3)

V

CC Supply Current

(Write) 3

mA

fSCL = VCC x 0.1/VCC x 0.9 Levels @ 400 KHz, SDA =

Open

RST = V

SS

I

SB1

(1)

V

CC Supply Current

(Standby) 50

µA

V

IL = VCC x 0.1, VIH = VCC x 0.9 fSCL

= 400 KHz, f

S

DA

= 400 KHz

I

SB2

(1)

V

CC Supply Current

(Standby) 1

µA

V

SDA = VSCC = VCC Other =

GND or V

CC

–0.3V

I

LI

Input Leakage Current 10

µA

V

IN

= V

SS

to V

CC

I

LO

Output Leakage Current 10

µA

V

OUT

= V

SS

to V

CC

V

IL1

(2)

Input LOW Voltage –0.5

V

CC

x 0.3

V

CC

= 5.5V

V

IH1

(2)

Input HIGH Voltage

V

CC

x 0.7V

CC

+ 0.5

V

CC

= 5.5V

V

IL2

(2)

Input LOW Voltage –0.5

V

CC

x 0.1

V

CC

= 2.0V

V

IH2

(2)

Input HIGH Voltage

V

CC

x 0.9V

CC

+ 0.5

V

CC

= 2.0V

V

OL

Output LOW Voltage 0.4

V

I

OL

= 3mA

Symbol

Test

Max.

Units

Conditions

C

OUT

(3)

Output Capacitance (SDA) 8

pF

V

I/O

= 0V

C

IN

(3)

Input Capacitance (RST, SCL) 6

pF

V

IN

= 0V

X76F641

12

AC CHARACTERISTICS

AC Specifications

(Over the recommended operating conditions)

Notes:

1.

Typical values are for T

A

= 25˚C and V

CC

= 5.0V

Notes:

2.

C

b

= Total Capacitance of one bus line in pf.

Symbol

Parameter

Min

Typ

(1)

Max

Units

f

SCL

SCL Clock Frequency 0

400

KHz

t

IN

(1)

Pulse width of spikes which must be suppressed by the

input filter 50

100

ns

t

AA

SCL LOW to SDA Data Out Valid 0.1

0.3

0.9

∝

s

t

BUF

Time the bus must be free before a new transmit

can start 1.3

∝

s

t

LOW

Clock LOW Time 1.3

∝

s

t

HIGH

Clock HIGH Time 0.6

∝

s

t

SU:STA

Start Condition Setup Time 0.6

∝

s

t

HD:STA

Start Condition Hold Time 0.6

∝

s

t

SU:DAT

Data In Setup Time 100

ns

t

HD:DAT

Data In Hold Time 0

∝

s

t

SU:STO

Stop Condition Setup Time 0.6

∝

s

t

DH

Data Output Hold Time 50

300

ns

t

R

SDA and SCL Rise Time 20 + 0.1 x C

b

(2)

300

ns

t

F

SDA and SCL Fall Time 20 + 0.1 x C

b

(2)

300

ns

f

SCL_RST

SCL Clock Frequency during Response to Reset 400

kHz

t

SR

Device Select to RST active 200

ns

t

NOL

RST to SCL Non-Overlap 500

ns

t

RST

RST High Time 2.25

∝

s

t

SU:RST

Response to Reset Setup Time 1.25

∝

s

t

LOW_RST

Clock LOW during Response to Reset 1.25

∝

s

t

HIGH_RST

Clock HIGH during Response to Reset 1.25

∝

s

t

RDV

RST LOW to SDA Valid During Response to Reset 0

500

ns

t

CDV

CLK LOW to SDA Valid During Response to Reset 0

500

ns

t

DHZ

Device Deselect to SDA high impedance 0

500

ns

7025 FM T14

X76F641

13

RESET AC SPECIFICATIONS

Power Up Timing

Notes:

1.

Delays are measured from the time VCC is stable until the specified operation can be initiated. These parameters are periodically

sampled and not 100% tested.

2.

Typical values are for T

A

= 25˚C and V

CC

= 5.0V

Nonvolatile Write Cycle Timing

Notes:

1.

tWC is the time from a valid stop condition at the end of a write sequence to the end of the self-timed internal nonvolatile write cycle.

It is the minimum cycle time to be allowed for any nonvolatile write by the user, unless Acknowledge Polling is used.

TIMING DIAGRAMS

Bus Timing

Write Cycle Timing

Symbol

Parame

ter

Min.

Typ

(2)

Max.

Units

t

PUR

(1)

Time from Power Up to Read 1

mS

t

PUW

(1)

Time from Power Up to Write 5

mS

Symbol

Parameter

Min.

Typ.(1)

Max.

Units

t

WC

(1)

Write Cycle Time 5

10

mS

t

SU:STO

t

DH

t

HIGH

t

SU:STA

t

HD:STA

t

HD:DAT

t

SU:DAT

SCL

SDA IN

SDA OUT

t

F

t

LOW

t

BUF

t

AA

t

R

7025 FM 18

SCL

SDA

t

WC

8th bit of last byte

ACK

Stop

Condition

Start

Condition

7025 FM 19

7025 FM T11

7025 FM T12

X76F641

14

RST Timin

g Diagram

–

Response to a Synchronous Reset

GUIDELINES FOR CALCULATING TYPICAL VALUES OF BUS PULL UP RESISTORS

t

RST

t

NOL

t

HIGH_RST

t

LOW_RST

t

CDV

t

RDV

t

SU:RST

DATA BIT (1) DATA BIT (2)

1st

clk

pulse

2nd

clk

pulse

3rd

clk

pulse

I/O

CLK

RST

t

NOL

DATA BIT (N) DATA BIT (N+1)

I/O

CLK

RST

(N+2)

7025 FM 21

100

80

60

40

20

Bus capacitance in pF

R

MIN

R

MAX

20

40

60

80

100

R

MIN

V

CCMAX

I

OLMIN

-------------------------- 1.8K

Ο

=

R

MAX

t

R

C

BUS

----------------

-

=

t

R

= maximum allowable SDA rise time

7025 FM 22

Pull Up Resistance in K

Ο

X76F641

15

NOTE:

1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)

2. PACKAGE DIMENSIONS EXCLUDE MOLDING FLASH

0.020 (.508)

0.012 (.305)

.080 (2.03)

.070 (1.78)

.213 (5.41)

.205 (5.21)

0

8

.330 (8.38)

.300 (7.62)

.212 (5.38)

.203 (5.16)

.035 (.889)

.020 (.508)

.010 (.254)

.007 (.178)

REF

PIN 1 ID

.050 (1.27) BSC

8

-

LEAD PLASTIC, 0.200” WIDE SMALL OUTLINE

GULLWING PACKAGE TYP “A” (EIAJ SOIC)

.013 (.330)

.004 (.102)

7025 FM 24

X76F641

16

8 PAD CHIP ON BOARD SMART CARD MODULE TYPE X

NOTE: ALL MEASUREMENTS IN MILLIMETERS

8 CONTACT MODULE

11.4

1

.

59

0.15

1.215

2.54

6 CONTACT MODULE

8

1.3

0.2

REJECT

PUNCH

POSITION

1.422

35

23.02

8.82

1

35mm TAPE

12.6

90°

4.75

X76F641

17

ORDERING INFORMATION

VCC Limits

Blank = 5V ±10%

2.0 = 2.0V to 3.6V

Temperature Range

Blank = Commercial = 0°C to +70°C

E = Extended = –20°C to +85°C

Package

A = 8-Lead SOIC (EIAJ)

H = Die in Waffle Packs

W = Die in Wafer Form

X = Smart Card Module

Devi

ce

X76F641

P

T

G

–

V

LIMITED WARRANTY

Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes no warranty, express,

statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. Xicor, Inc. makes

no warranty of merchantability or fitness for any purpose. Xicor, Inc. reserves the right to discontinue production and change specifications and prices at any time and

without notice.

Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, licenses are implied.

U.S. PATENTS

Xicor products are covered by one or more of the following U.S. Patents: 4,263,664; 4,274,012; 4,300,212; 4,314,265; 4,326,134; 4,393,481; 4,404,475;

4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846; 4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829, 482; 4,874, 967; 4,883, 976. Foreign patents and additional

patents pending.

LIFE RELATED POLICY

In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error detec- tion and

correction, redundancy and back-up features to prevent such an occurence.

Xicor’s products are not authorized for use in critical components in life support devices or systems.

1.

Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to

perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user.

2.

A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life sup

- port

device or system, or to affect its safety or effectiveness.

G=

RoHS Compliant Lead Free package

Blank = Standard package. Non lead free