REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Technical changes were made in table I, Editorial changes throughout. 90-08-15 William K. Heckman B Changes in accordance with NOR 5962-R023-92. 91-10-30 Monica L.Poelking C Changes in accordance with NOR 5962-R189-93. 93-07-07 Joe Dupay D Add devices 03, 04, 05, and 06. Editorial changes throughout. 94-11-26 Monica L.Poelking E Changes in accordance with NOR 5962-R001-01. - LTG 00-12-21 Thomas M. Hess F Update boilerplate to the requirements of MIL-PRF-38535. Editorial changes throughout. - TVN 01-12-03 Thomas M. Hess THE ORIGINAL FIRST SHEET OF THIS DRAWING HAS BEEN REPLACED. REV 35 36 37 38 39 40 41 42 SHEET F F F F F F F F REV F F F F F F F F F F F F F F F F F F F F SHEET 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 REV F F F F F F F F F F F F F F SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 14 REV STATUS OF SHEETS PREPARED BY PMIC N/A DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216 http://www.dscc.dla.mil Tim Noh STANDARD MICROCIRCUIT DRAWING THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS AND AGENCIES OF THE DEPARTMENT OF DEFENSE CHECKED BY Tim Noh APPROVED BY William K.Heckman DRAWING APPROVAL DATE 89-02-16 REVISION LEVEL F AMSC N/A MICROCIRCUIT, DIGITAL, CMOS, 16-BIT MICROPROCESSOR, MONOLITHIC SILICON SIZE A SHEET DSCC FORM 2233 APR 97 DISTRIBUTION STATEMENT A. Approved for public release; distribution is unlimited. CAGE CODE 5962-88501 67268 1 OF 42 5962-E094-02 1. SCOPE 1.1 Scope. This drawing describes device requirements for MIL-STD-883 compliant, non-JAN class level B microcircuits in accordance with MIL-PRF-38535, appendix A. 1.2 Part or Identifying Number (PIN). The complete PIN is as shown in the following example: 5962-88501 01 Drawing number Device type (see 1.2.1) Y X Case outline (see 1.2.2) Lead finish (see 1.2.3) 1.2.1 Device type(s). The device type(s) identify the circuit function as follows: Device type Generic number Frequency M80C186 M80C186 M80C186XL M80C186XL M80C186XL M80C186XL 10 MHz 12.5 MHz 20 MHz 16 MHz 12.5 MHz 10 MHz 01 02 03 04 05 06 Circuit function 16-bit CHMOS microprocessor 16-bit CHMOS microprocessor 16-bit CHMOS microprocessor 16-bit CHMOS microprocessor 16-bit CHMOS microprocessor 16-bit CHMOS microprocessor 1.2.2 Case outline(s). The case outline(s) are as designated in MIL-STD-1835 and as follows: Outline letter Descriptive designator Terminals Y Z See figure 1 CMGA3-P68 68 68 Package style Ceramic quad package Pin grid array package 1.2.3 Lead finish. The lead finish is as specified in MIL-PRF-38535, appendix A. 1.3 Absolute maximum ratings. Voltage on any pin (referenced to GND).................................................... Maximum power dissipation (PD) ............................................................... Storage temperature range ........................................................................ Thermal resistance, junction-to-case (JC): Case Y.................................................................................................... Case Z .................................................................................................... Junction temperature (TJ)........................................................................... Lead temperature (soldering, 5 seconds) .................................................. -1.0 V dc to +7.0 V dc 1W -65C to +150C 13C/W See MIL-STD-1835 +150C +260C 1.4 Recommended operating conditions. Supply voltage range (VCC): Device types 01, 02 ................................................................................ Device types 03 - 06............................................................................... Frequency of operation: Device type 01........................................................................................ Device type 02........................................................................................ Device type 03........................................................................................ Device type 04........................................................................................ Device type 05........................................................................................ Device type 06........................................................................................ Case operating temperature range (TC) ..................................................... STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 DSCC FORM 2234 APR 97 4.75 V dc to 5.25 V dc 4.5 V dc to 5.5 V dc 10 MHz 12.5 MHz 20 MHz 16 MHz 12.5 MHz 10 MHz -55C to +125C SIZE 5962-88501 A REVISION LEVEL F SHEET 2 2. APPLICABLE DOCUMENTS 2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those listed in the issue of the Department of Defense Index of Specifications and Standards (DoDISS) and supplement thereto, cited in the solicitation. SPECIFICATION DEPARTMENT OF DEFENSE MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for. STANDARDS DEPARTMENT OF DEFENSE MIL-STD-883 MIL-STD-1835 - Test Method Standard Microcircuits. Interface Standard Electronic Component Case Outlines. HANDBOOKS DEPARTMENT OF DEFENSE MIL-HDBK-103 MIL-HDBK-780 - List of Standard Microcircuit Drawings. Standard Microcircuit Drawings. (Unless otherwise indicated, copies of the specification, standards, and handbooks are available from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.) 2.2 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained. 3. REQUIREMENTS 3.1 Item requirements. The individual item requirements shall be in accordance with MIL-PRF-38535, appendix A for non-JAN class level B devices and as specified herein. Product built to this drawing that is produced by a Qualified Manufacturer Listing (QML) certified and qualified manufacturer or a manufacturer who has been granted transitional certification to MIL-PRF-38535 may be processed as QML product in accordance with the manufacturers approved program plan and qualifying activity approval in accordance with MIL-PRF-38535. This QML flow as documented in the Quality Management (QM) plan may make modifications to the requirements herein. These modifications shall not affect form, fit, or function of the device. These modifications shall not affect the PIN as described herein. A "Q" or "QML" certification mark in accordance with MIL-PRF-38535 is required to identify when the QML flow option is used. This drawing has been modified to allow the manufacturer to use the alternate die/fabrication requirements of paragraph A.3.2.2 of MIL-PRF-38535 or other alternative approved by the Qualifying Activity. 3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in MIL-PRF-38535, appendix A and herein. 3.2.1 Case outlines. The case outlines shall be in accordance with 1.2.2 and figure 1 herein. 3.2.2 Terminal connections. The terminal connections shall be as specified on figure 2. 3.2.3 Functional block diagram. The functional block diagram shall be as specified on figure 3. 3.2.4 Timing waveforms. The timing waveforms shall be as specified on figure 4. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 DSCC FORM 2234 APR 97 SIZE 5962-88501 A REVISION LEVEL F SHEET 3 3.3 Electrical performance characteristics. Unless otherwise specified herein, the electrical performance characteristics are as specified in table I and shall apply over the full case operating temperature range. 3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table II. The electrical tests for each subgroup are described in table I. 3.5 Marking. Marking shall be in accordance with MIL-PRF-38535, appendix A. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturer's PIN may also be marked as listed in MIL-HDBK-103 (see 6.7 herein). For packages where marking of the entire SMD PIN number is not feasible due to space limitations, the manufacturer has the option of not marking the "5962-" on the device. 3.5.1 Certification/compliance mark. A compliance indicator "C" shall be marked on all non-JAN devices built in compliance to MIL-PRF-38535, appendix A. The compliance indicator "C" shall be replaced with a "Q" or "QML" certification mark in accordance with MIL-PRF-38535 to identify when the QML flow option is used. For product built in accordance with A.3.2.2 of MIL-PRF-38535, or as modified in the manufacturer's QM plan, the "QD" certification mark shall be used in place of the "Q" or "QML" certification mark. 3.6 Certificate of compliance. A certificate of compliance shall be required from a manufacturer in order to be listed as an approved source of supply in MIL-HDBK-103 (see 6.7 herein). The certificate of compliance submitted to DSCC-VA prior to listing as an approved source of supply shall affirm that the manufacturer's product meets the requirements of MIL-PRF-38535, appendix A and the requirements herein. 3.7 Certificate of conformance. A certificate of conformance as required in MIL-PRF-38535, appendix A shall be provided with each lot of microcircuits delivered to this drawing. 3.8 Notification of change. Notification of change to DSCC-VA shall be required in accordance with MIL-PRF-38535, appendix A. 3.9 Verification and review. DSCC, DSCC's agent, and the acquiring activity retain the option to review the manufacturer's facility and applicable required documentation. Offshore documentation shall be made available onshore at the option of the reviewer. 4. QUALITY ASSURANCE PROVISIONS 4.1 Sampling and inspection. Sampling and inspection procedures shall be in accordance with MIL-PRF-38535, appendix A. 4.2 Screening. Screening shall be in accordance with method 5004 of MIL-STD-883, and shall be conducted on all devices prior to quality conformance inspection. The following additional criteria shall apply: a. Burn-in test, method 1015 of MIL-STD-883. (1) Test condition D. The test circuit shall be maintained by the manufacturer under document revision level control and shall be made available to the preparing or acquiring activity upon request. The test circuit shall specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in test method 1015 of MIL-STD-883. (2) TA = +125C, minimum. b. Interim and final electrical test parameters shall be as specified in table II herein, except interim electrical parameter tests prior to burn-in are optional at the discretion of the manufacturer. 4.3 Quality conformance inspection. Quality conformance inspection shall be in accordance with method 5005 of MIL-STD-883 including groups A, B, C, and D inspections. The following additional criteria shall apply. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 DSCC FORM 2234 APR 97 SIZE 5962-88501 A REVISION LEVEL F SHEET 4 TABLE I. Electrical performance characteristics. Test Symbol Conditions 1/ -55C TC +125C unless otherwise specified Device type Group A subgroups Limits Unit Min Max Low level input voltage, except X1 VIL All 1, 2, 3 -0.5 0.2VCC -0.3 V High level input voltage, VIH1 01, 02 1, 2, 3 0.2VCC +1.1 VCC+0.5 V 0.2VCC +0.9 VCC+0.5 all except X1, RES 03-06 High level input voltage, VIH2 All 1, 2, 3 3.0 VCC+0.5 V High level input voltage, at ARDY/SRDY VIH3 01, 02 1, 2, 3 0.2VCC +1.3 VCC+0.5 V Low level output voltage VOL IOL = 2.5 mA for S0 - S2 IOL = 2.0 mA for all other outputs All 1, 2, 3 0.45 V High level output voltage VOH IOH = -200 A at 0.8VCC 01, 02 1, 2, 3 0.8VCC VCC 2/ V IOH = -200 A at VCC - 0.5 V 03-06 VCC-0.5 VCC 2/ IOH = -2.4 mA at 2.4 V All 2.4 VCC 2/ VCC = Max 4/ 01 at RES Power supply current 3/ ICC 1, 2, 3 140 02 160 03 100 04 90 05 80 06 70 mA Input leakage current IIL 0.45 V < VIN < VCC Output leakage current IOL 0.45 V < VOUT < VCC At 0.5 MHz Low level clock output voltage VCLO ICLO = 4.0 mA High level clock output voltage VCHO Low level clock input voltage (X1) VCLI All 1, 2, 3 -0.5 +0.6 V High level clock input voltage (X1) VCHI All 1, 2, 3 3.9 VCC+0.5 V 5/ All 1, 2, 3 10 A All 1, 2, 3 10 A 01, 02 1, 2, 3 0.5 V 03-06 ICHO = -500 A 01, 02 0.45 1, 2, 3 03-06 0.8VCC V VCC-0.5 See footnotes at end of table. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 DSCC FORM 2234 APR 97 SIZE 5962-88501 A REVISION LEVEL F SHEET 5 TABLE I. Electrical performance characteristics - Continued. Test Symbol Input capacitance CIN I/O capacitance CIO Functional test Data in set-up (A/D) Data in hold (A/D) tDVCL Conditions 1/ -55C TC +125C unless otherwise specified Device type Group A subgroups See 4.3.1c f = 1 MHz All 4 See 4.3.1d All 7, 8 See figure 4 01, 02 9, 10, 11 Asynchronous ready (ARDY) set-up time ARDY active hold time ARDY inactive hold time Synchronous ready (SRDY) transition set-up time SRDY transition hold time Hold set-up 6/ Min Unit Max 10 pF 20 tCLDX 10 04-06 15 01, 02 tARYCH 01, 02 tARYLCL 9, 10, 11 tARYCHL tSRYCL 30 03 15 04-06 25 9, 10, 11 10 04-06 15 9, 10, 11 10 04-06 15 10 04-06 15 10 04-06 15 9, 10, 11 ns 20 03 01, 02 ns 20 03 9, 10, 11 ns 15 03 9, 10, 11 ns 15 03 01, 02 tHVCL 9, 10, 11 ns 20 15 01, 02 tCLSRY 9, 10, 11 04-06 01, 02 ns 3 10 01, 02 ns 5 03 01, 02 tCLARX 20 03 03-06 ARDY resolution transition set-up time 6/ Limits ns 20 03 10 04-06 15 ns See footnotes at end of table. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 DSCC FORM 2234 APR 97 SIZE 5962-88501 A REVISION LEVEL F SHEET 6 TABLE I. Electrical performance characteristics - Continued. Test INTX, NMI, TEST , TMRIN set-up time 6/ DRQ0, DRQ1 set-up time 6/ Address valid delay Address hold Symbol tINVCH Conditions 1/ -55C TC +125C unless otherwise specified See figure 4 tINVCL Device type Group A subgroups 01, 02 9, 10, 11 04-06 15 9, 10, 11 10 04-06 15 Command lines float delay 02 5 37 03 1 27 04 1 33 05 3 36 06 3 44 Command lines valid delay (after float) 01 tCHCZ 9, 10, 11 ns 0 2/ 30 02 tCLAX 25 03-04 tCLAX 20 05 tCLAX 25 06 tCLAX 30 9, 10, 11 9, 10, 11 33 03 25 04 28 05 33 06 40 9, 10, 11 ns 40 02 01 ns 0 tCLAX 01 tCHCV ns 50 01, 02 tCLAZ ns 5 03-06 Address float delay Max 20 03 9, 10, 11 Unit 20 10 01 tCLAX Min 03 01, 02 tCLAV Limits ns 45 02 37 03 26 04 32 05 36 06 44 ns See footnotes at end of table. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 DSCC FORM 2234 APR 97 SIZE 5962-88501 A REVISION LEVEL F SHEET 7 TABLE I. Electrical performance characteristics - Continued. Test ALE width Symbol tLHLL Conditions 1/ -55C TC +125C unless otherwise specified See figure 4 Device type Group A subgroups 01, 02 9, 10, 11 03-06 ALE active delay ALE inactive delay Address hold to ALE inactive tCHLH 01 tCHLL tLLAX Data valid delay Data hold time Data hold after WR (min) tCLDV See figure 4 tWHDX ns tCLCL-15 30 20 05 25 06 30 02 25 03-04 20 05 25 06 30 9, 10, 11 ns ns tCHCL-20 02 tCHCL-15 03 tCHCL-10 04-06 tCHCL-15 9, 10, 11 5 40 02 5 36 03 1 27 04 1 33 05 3 36 06 3 40 9, 10, 11 ns 3 03, 04 1 05, 06 3 9, 10, 11 ns 30 9, 10, 11 01 Equal loading See figure 4 tCLCL-30 03-04 01, 02 See figure 4 Max 25 01 tCLDOX Unit 02 01 Equal loading See figure 4 Min 9, 10, 11 01 See figure 4 Limits ns tCLCL-34 02 tCLCL-20 03 tCLCL-15 04-05 tCLCL-20 06 tCLCL-34 ns See footnotes at end of table. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 DSCC FORM 2234 APR 97 SIZE 5962-88501 A REVISION LEVEL F SHEET 8 TABLE I. Electrical performance characteristics - Continued. Test Symbol WR inactive to DEN inactive tWHDEX WR inactive to ALE high tWHLH Control active delay 1 Control active delay 2 Control inactive delay DEN inactive delay (nonwrite cycle) tCVCTV Conditions 1/ -55C TC +125C unless otherwise specified Device type Group A subgroups See figure 4 01, 02 9, 10, 11 Equal loading See figure 4 03-06 See figure 4 01, 02 Equal loading See figure 4 03-06 See figure 4 01 tCHCTV Max tCLCH-10 ns tCLCH-10 9, 10, 11 tCLCH-14 ns tCLCH-14 56 02 3 47 03 1 22 04 1 31 05 3 37 06 3 44 5 44 02 5 37 03 1 22 04 1 31 05 3 37 06 3 44 3 44 02 3 37 03 1 25 04 1 31 05 3 37 06 3 44 5 56 02 5 47 03 1 22 04 1 31 05 3 37 06 3 44 01 tCVDEX Min Unit 3 01 tCVCTX Limits 01 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 ns ns ns ns See footnotes at end of table. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 DSCC FORM 2234 APR 97 SIZE 5962-88501 A REVISION LEVEL F SHEET 9 TABLE I. Electrical performance characteristics - Continued. Test Symbol Address float to RD active 2/ tAZRL RD active delay tCLRL RD inactive delay RD inactive to ALE high RD inactive to address active (min) Conditions 1/ -55C TC +125C unless otherwise specified See figure 4 tCLRH tRHLH tRHAV RD pulse width (min) tCLHAV All 9, 10, 11 0 01 9, 10, 11 5 44 02 5 37 03 1 27 04 1 31 05 3 37 06 3 44 5 44 02 5 37 03 1 27 04 1 31 05 3 37 06 3 44 01, 02 Equal loading See figure 4 03-06 Unit Max ns tCLCH-14 ns ns ns tCLCL-40 tCLCL-20 03-06 tCLCL-15 9, 10, 11 3 40 02 3 33 03 1 22 04 1 25 05 3 33 06 3 40 01 ns tCLCH-14 02 01 tRLRH 9, 10, 11 9, 10, 11 01 See figure 4 Min 9, 10, 11 See figure 4 Equal loading See figure 4 HLDA valid delay Group A subgroups 01 See figure 4 Limits Device type 9, 10, 11 2tCLCL-46 02 2tCLCL-40 03 2tCLCL-20 04-05 2tCLCL-25 06 2tCLCL-30 ns ns See footnotes at end of table. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 DSCC FORM 2234 APR 97 SIZE 5962-88501 A REVISION LEVEL F SHEET 10 TABLE I. Electrical performance characteristics - Continued. Test WR pulse width (min) Address valid to ALE low (min) Symbol tWLWH tAVLL Conditions 1/ -55C TC +125C unless otherwise specified See figure 4 See figure 4 Status inactive delay Timer output delay tCHSV See figure 4 01 9, 10, 11 Limits Min 2tCLCL-30 03 2tCLCL-20 04-05 2tCLCL-25 06 2tCLCL-30 9, 10, 11 Unit Max 2tCLCL-34 02 ns tCLCH-19 02 tCLCH-15 03 tCLCH-10 04-05 tCLCH-15 06 tCLCH-18 01 tCLSH tCLTMV Group A subgroups 01 Equal loading See figure 4 Status active delay Device type 5 45 02 5 35 03 1 25 04 1 31 05 3 35 06 3 45 5 50 02 5 35 03 1 25 04 1 30 05 3 35 06 3 46 01 9, 10, 11 ns 9, 10, 11 CL = 100 pF maximum at 10 MHz See figure 4 01 9, 10, 11 48 See figure 4 02 40 03 22 04 27 05 33 06 40 ns ns ns See footnotes at end of table. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 DSCC FORM 2234 APR 97 SIZE 5962-88501 A REVISION LEVEL F SHEET 11 TABLE I. Electrical performance characteristics - Continued. Test Reset delay Symbol tCLR0 Queue status delay Conditions 1/ -55C TC +125C unless otherwise specified See figure 4 tCHQSV Device type Group A subgroups 01 9, 10, 11 Limits Min Unit Max 48 02 40 03 22 04 27 05 33 06 40 01-02 28 9, 10, 11 03 27 04 30 05 32 06 37 ns ns RES set-up tRESIN 03-06 9, 10, 11 15 ns Status hold time tCHDX 01-02 9, 10, 11 5 ns Address valid to clock high tAVCH All 9, 10, 11 0 ns LOCK valid/invalid delay tCLLV 01 9, 10, 11 3 45 02 3 40 03 1 22 04 1 35 05 3 37 06 3 40 DEN inactive to DT/ R low Chip-select active delay tDXDL tCLCSV See figure 4 01, 02 Equal loading See figure 4 03-06 See figure 4 01 9, 10, 11 0 ns ns 0 9, 10, 11 45 02 ns 33 03 1 25 04 1 30 05 3 33 06 3 42 See footnotes at end of table. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 DSCC FORM 2234 APR 97 SIZE 5962-88501 A REVISION LEVEL F SHEET 12 TABLE I. Electrical performance characteristics - Continued. Test Symbol Chip-select hold from command inactive tCXCSX Chip-select inactive delay tCHCSX CLKIN period Conditions 1/ -55C TC +125C unless otherwise specified Device type Group A subgroups See figure 4 01, 02 9, 10, 11 Equal loading See figure 4 03-06 See figure 4 01 tCKIN Limits Min Unit Max tCLCH-10 ns tCLCH-10 9, 10, 11 5 40 02 5 36 03 1 20 04 1 35 05 3 30 06 3 35 50 1000 02 40 1000 03 25 04 31.25 05 40 06 50 01 9, 10, 11 ns ns RD valid to clock high tRVCH 01, 02 9, 10, 11 25 ns Chip select valid to ALE low tCSVLL 01, 02 9, 10, 11 tCLCH-14 ns CLKIN fall time 2/ tCKHL 3.5 V to 1.0 V See figure 4 7/ All 9, 10, 11 5 ns CLKIN rise time tCKLH 1.0 V to 3.5 V See figure 4 7/ All 9, 10, 11 5 ns tCLCK At 1.5 V See figure 4 7/ 01 9, 10, 11 2/ CLKIN low time 8/ 23 ns 02 18 03 10 04 13 05 16 06 20 See footnotes at end of table. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 DSCC FORM 2234 APR 97 SIZE 5962-88501 A REVISION LEVEL F SHEET 13 TABLE I. Electrical performance characteristics - Continued. Test CLKIN high time CLKIN to CLKOUT skew CLKOUT period CLKOUT low time CLKOUT high time CLKOUT rise time CLKOUT fall time Symbol tCHCK tCICO Conditions 1/ -55C TC +125C unless otherwise specified At 1.5 V See figure 4 7/ 8/ See figure 4 tCL2CL1 01 9, 10, 11 At 1.5 V CL = 100 pF See figure 4 23 ns 10 04 13 05 16 06 20 25 9, 10, 11 02 21 03-04 17 05 21 06 25 9, 10, 11 100 2000 02 80 2000 03 50 04 62.5 05 80 06 100 9, 10, 11 0.5tCLCL-8 02 0.5tCLCL-7 03-05 0.5tCLCL-5 06 0.5tCLCL-6 9, 10, 11 0.5tCLCL-7 03-05 0.5tCLCL-5 06 0.5tCLCL-6 9, 10, 11 10 8 04-06 10 9, 10, 11 ns ns 03 01, 02 ns ns 0.5tCLCL-8 02 01, 02 3.5 V to 1.0 V See figure 4 7/ Max 03 01 1.0 V to 3.5 V See figure 4 7/ Min Unit 18 01 7/ Limits 02 01 tCHCL tCH1CH2 Group A subgroups 01 tCLCL tCLCH Device type 10 03 8 04-06 10 ns ns See footnotes on next sheet. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 DSCC FORM 2234 APR 97 SIZE 5962-88501 A REVISION LEVEL F SHEET 14 TABLE I. Electrical performance characteristics - Continued. 1/ VCC = 5.0 V 5% for device types 01 and 02 and VCC = 5.0 V 10% for device types 03 through 06. All timings are measured at 1.5 V and 100 pF loading on CLKOUT unless specified. For device type 01, the outputs are measured with CL = 50 - 200 pF (10 MHz). For device type 02, CL = 50 - 100 pF (12.5 MHz). For device types 03 through 06, all outputs test conditions are with CL = 50 pF unless noted. For ac tests, input VIL = 0.45 V and VIH = 2.4 V except at X1 where VIH = VCC - 0.5 V. See figure 4. 2/ Guaranteed if not tested to the limits specified. 3/ Power save current (IPS) at +25C with VCC = 5.0 V is typically 10 mA per MHz + 20 mA. 4/ Current is measured with the device in RESET with X1 and X2 driven and all other nonpower pins open. 5/ Pins being floated during HOLD or by invoking the ONCE mode. 6/ To guarantee recognition at next CLK. 7/ Voltages indicated refer to voltage measurements on waveforms on figure 4. 8/ tCLCK and tCHCK (CLKIN low and high times) should not have a duration less than 45 percent of tCKIN. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 DSCC FORM 2234 APR 97 SIZE 5962-88501 A REVISION LEVEL F SHEET 15 Case Y FIGURE 1. Case outline. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 DSCC FORM 2234 APR 97 SIZE 5962-88501 A REVISION LEVEL F SHEET 16 Case Y Inches Symbol Millimeters Min Max Min Max A .080 .106 2.03 2.69 B .016 .020 0.41 0.51 B1 .040 .060 1.02 1.52 B2 .030 .040 0.76 1.02 B3 .005 .020 0.13 0.51 C .008 .012 0.20 0.31 D 1.640 1.870 41.66 47.50 D1 .935 .970 23.75 24.64 D2 .800 BSC 20.32 BSC e1 .050 BSC 1.27 BSC L .375 .450 9.53 11.43 L1 .040 .060 1.02 1.52 N 68 S .066 S1 .050 68 .087 1.68 2.21 1.27 FIGURE 1. Case outline - Continued. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 DSCC FORM 2234 APR 97 SIZE 5962-88501 A REVISION LEVEL F SHEET 17 Device type All Case outline Y Terminal number Terminal symbol Terminal number Terminal symbol Terminal number Terminal symbol 1 VCC 24 S2 47 PCS5 /A1 2 AD4 25 S1 48 PCS4 3 AD12 26 S0 49 PCS3 4 AD5 27 HLDA 50 PCS2 5 AD13 28 HOLD 51 PCS1 6 AD6 29 SRDY 52 VSS 7 AD14 30 LOCK 53 PCS0 8 AD7 31 TEST 54 RES 9 AD15 32 NMI 55 TMR OUT 1 10 A16/S3 33 INT0 56 TMR OUT 0 11 A17/S4 34 INT1 57 TMR IN 1 12 A18/S5 35 VCC 58 TMR IN 0 13 A19/S6 36 INT2/ INTA0 59 DRQ1 14 BHE /S7 37 INT3/ INTA1 60 DRQ0 15 WR /QS1 38 DT/ R 61 AD0 16 RD / QSMD 39 DEN 62 AD8 17 ALE/QS0 40 MCS0 63 AD1 18 VSS 41 MCS1 64 AD9 19 X1 42 MCS2 65 AD2 20 X2 43 MCS3 66 AD10 21 RESET 44 UCS 67 AD3 22 CLKOUT 45 LCS 68 AD11 23 ARDY 46 PCS6 /A2 FIGURE 2. Terminal connections. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 DSCC FORM 2234 APR 97 SIZE 5962-88501 A REVISION LEVEL F SHEET 18 Device type All Case outline Z Terminal number Terminal symbol Terminal number Terminal symbol Terminal number Terminal symbol A2 A16/S3 C11 SRDY J10 MCS0 A3 A18/S5 D1 AD13 J11 MCS1 A4 BHE /S7 D2 AD5 K1 AD0 A5 RD / QSMD D10 LOCK K2 DRQ1 A6 VSS D11 TEST K3 TMR IN 1 A7 X2 E1 AD12 K4 TMR OUT 1 A8 CLKOUT E2 AD4 K5 PCS0 A9 S2 E10 NMI K6 PCS1 A10 S0 E11 INT0 K7 PCS3 B1 AD15 F1 VCC K8 PCS5 /A1 B2 AD7 F2 AD11 K9 LCS B3 A17/S4 F10 INT1 K10 MCS2 B4 A19/S6 F11 VCC K11 MCS3 B5 WR /QS1 G1 AD3 L2 DRQ0 B6 ALE/QS0 G2 AD10 L3 TMR IN 0 B7 X1 G10 INT2/ INTA0 L4 TMR OUT 0 B8 RESET G11 INT3/ INTA1 L5 RES B9 ARDY H1 AD2 L6 VSS B10 S1 H2 AD9 L7 PCS2 B11 HLDA H10 DT/ R L8 PCS4 C1 AD14 H11 DEN L9 PCS6 /A2 C2 AD6 J1 AD1 L10 UCS C10 HOLD J2 AD8 FIGURE 2. Terminal connections - Continued. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 DSCC FORM 2234 APR 97 SIZE 5962-88501 A REVISION LEVEL F SHEET 19 Device types 01 and 02 FIGURE 3. Functional block diagram. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 DSCC FORM 2234 APR 97 SIZE 5962-88501 A REVISION LEVEL F SHEET 20 Device types 03 - 06 FIGURE 3. Functional block diagram - Continued. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 DSCC FORM 2234 APR 97 SIZE 5962-88501 A REVISION LEVEL F SHEET 21 FIGURE 4. Timing waveforms. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 DSCC FORM 2234 APR 97 SIZE 5962-88501 A REVISION LEVEL F SHEET 22 NOTES: 1. Following a write cycle, the local bus is floated by the devices only when the devices enter a "hold acknowledge" state. 2. INTA occurs one clock later in slave mode. 3. Status inactive just prior to T4. 4. Latched A1 and A2 have the same timings as PCS5 and PCS6 . 5. For write cycle followed by read. FIGURE 4. Timing waveforms - Continued. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 DSCC FORM 2234 APR 97 SIZE 5962-88501 A REVISION LEVEL F SHEET 23 FIGURE 4. Timing waveforms - Continued. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 DSCC FORM 2234 APR 97 SIZE 5962-88501 A REVISION LEVEL F SHEET 24 FIGURE 4. Timing waveforms - Continued. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 DSCC FORM 2234 APR 97 SIZE 5962-88501 A REVISION LEVEL F SHEET 25 FIGURE 4. Timing waveforms - Continued. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 DSCC FORM 2234 APR 97 SIZE 5962-88501 A REVISION LEVEL F SHEET 26 TABLE II. Electrical test requirements. MIL-STD-883 test requirements Subgroups (in accordance with MIL-STD-883, method 5005, table I) Interim electrical parameters (method 5004 or 5010) Final electrical test parameters (method 5004 or 5010) --1*, 2, 3, 7, 8, 9, 10, 11 Group A test requirements (method 5005 or 5010) 1, 2, 3, 4, 7, 8, 9, 10, 11 Groups C and D end-point electrical parameters (method 5005 or 5010) 1, 2, 3 or 2, 8A, 10 Additional electrical subgroups for group C periodic inspections --- * PDA applies to subgroup 1. 4.3.1 Group A inspection. a. Tests shall be as specified in table II herein. b. Subgroups 5 and 6 in table I, method 5005 of MIL-STD-883 shall be omitted. c. Subgroup 4 (CIN and COUT measurements) shall be measured only for the initial test and after process or design changes which may affect capacitance. A minimum sample size of 5 devices with zero rejects shall be required. d. Subgroups 7 and 8 shall include verification of the instruction set (see table III). 4.3.2 Groups C and D inspections. a. End-point electrical parameters shall be as specified in table II herein. b. Steady-state life test conditions, method 1005 of MIL-STD-883. (1) Test condition D. The test circuit shall be maintained by the manufacturer under document revision level control and shall be made available to the preparing or acquiring activity upon request. The test circuit shall specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in test method 1005 of MIL-STD-883. (2) TA = +125C, minimum. (3) Test duration: 1,000 hours, except as permitted by method 1005 of MIL-STD-883. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 DSCC FORM 2234 APR 97 SIZE 5962-88501 A REVISION LEVEL F SHEET 27 5. PACKAGING 5.1 Packaging requirements. The requirements for packaging shall be in accordance with MIL-PRF-38535, appendix A. 6. NOTES 6.1 Intended use. Microcircuits conforming to this drawing are intended for use for Government microcircuit applications (original equipment), design applications, and logistics purposes. 6.2 Replaceability. Microcircuits covered by this drawing will replace the same generic device covered by a contractor-prepared specification or drawing. 6.3 Configuration control of SMD's. All proposed changes to existing SMD's will be coordinated with the users of record for the individual documents. This coordination will be accomplished using DD Form 1692, Engineering Change Proposal. 6.4 Record of users. Military and industrial users shall inform Defense Supply Center Columbus when a system application requires configuration control and the applicable SMD. DSCC will maintain a record of users and this list will be used for coordination and distribution of changes to the drawings. Users of drawings covering microelectronics devices (FSC 5962) should contact DSCC-VA, telephone (614) 692-0544. 6.5 Comments. Comments on this drawing should be directed to DSCC-VA, Columbus, Ohio 43216-5000, or telephone (614) 692-0547. 6.6 Abbreviations, symbols, and definitions. The abbreviations, symbols, and definitions used herein are defined in MIL-PRF-38535, MIL-HDBK-1331, and table IV herein. 6.7 Approved sources of supply. Approved sources of supply are listed in MIL-HDBK-103. The vendors listed in MIL-HDBK-103 have agreed to this drawing and a certificate of compliance (see 3.6 herein) has been submitted to and accepted by DSCC-VA. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 DSCC FORM 2234 APR 97 SIZE 5962-88501 A REVISION LEVEL F SHEET 28 TABLE III. Instruction set summary. Function Clock cycles Format Comments DATA TRANSFER MOV = Move: Register to register/memory 1000100w mod reg r/m 2/12 Register/memory to register 1000101w mod reg r/m 2/9 Immediate to register/memory 1000111w mod 0 0 0 r/m data Immediate to register 1 0 1 1 w reg data Memory to accumulator 1010000w Accumulator to memory Register/memory to segment data if w = 1 12-13 8/16-bit data if w = 1 3-4 8/16-bit addr-low addr-high 8 1010001w addr-low addr-high 9 10001110 mod 0 reg r/m 2/9 10001110 mod 0 reg r/m 2/11 Memory 11111111 mode 1 1 0 r/m 16 Register 0 1 0 1 0 reg 10 Segment register 0 0 0 reg 1 0 1 9 Immediate 011010s0 PUSHA = Push All 01100000 register Segment register to register/memory PUSH = Push: data data if s = 0 10 36 POP = Pop: Memory 10001111 Register 0 1 0 1 1 reg Segment register 0 0 0 reg 1 1 1 POPA = Pop All 01100000 mode 1 1 0 r/m 20 10 (reg 0) 8 51 XCHG = Exchange: Register/memory with register 1000011w Register with accumulator 1 0 0 1 0 reg mode reg r/m 4/17 3 IN = Input from: Fixed port 1110010w Variable port 1110110w port 10 8 OUT = Output to: Fixed port 1110011w Variable port 1110111w STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 DSCC FORM 2234 APR 97 port 9 7 SIZE 5962-88501 A REVISION LEVEL F SHEET 29 TABLE III. Instruction set summary - Continued. Function Clock cycles Format Comments DATA TRANSFER - Continued XLAT = Translate byte to AL 11010111 11 LEA = Load EA to register 10001101 mod reg r/m LDS = Load pointer to DS 11000101 mod reg r/m (mod 11) 18 LES = Load pointer to ES 11000100 mod reg r/m (mod 11) 18 LAHF = Load AH with flags 10011111 2 SAHF = Store AH into flags 10011110 3 PUSHF = Push flags 10011100 9 POPF = Pop flags 10011101 8 CS 00101110 2 SS 00110110 2 DS 00111110 2 ES 00100110 2 6 SEGMENT = Segment override: ARITHMETIC ADD = Add: Reg/memory with register to 000000dw mod reg r/m 3/10 Immediate to register/memory 100000sw mod 0 0 0 r/m data Immediate to accumulator 0000010w data data if w = 1 000100dw mod reg r/m Immediate to register/memory 100000sw mod 0 1 0 r/m data Immediate to accumulator 0001010w data data if w = 1 Register/memory 1111111w mod 0 0 0 r/m Register 0 1 0 0 0 reg either data if sw = 01 4/16 3/4 8/16-bit ADC = Add with carry: Reg/memory with register to 3/10 either data if sw = 01 4/16 3/4 8/16-bit INC = Increment: STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 DSCC FORM 2234 APR 97 3/15 3 SIZE 5962-88501 A REVISION LEVEL F SHEET 30 TABLE III. Instruction set summary - Continued. Function Clock cycles Format Comments ARITHMETIC - Continued SUB = Subtract: Reg/memory and register to 001010dw mod reg r/m 3/10 Immediate from register/memory 100000sw mod 1 0 1 r/m data Immediate from accumulator 0010110w data data if w = 1 000110dw mod reg r/m Immediate from register/memory 100000sw mod 0 1 1 r/m data Immediate from accumulator 0001110w data data if w = 1 Register/memory 1111111w mod 0 0 1 r/m Register 0 1 0 0 1 reg either data if sw = 01 4/16 3/4 8/16-bit SBB = Subtract with borrow: Reg/memory and register to 3/10 either data if sw = 01 4/16 3/4 8/16-bit DEC = Decrement: 3/15 3 CMP = Compare: Register/memory with register 0011101w mod reg r/m 3/10 Register with register/memory 0011100w mod reg r/m 3/10 Immediate with register/memory 100000sw mod 1 1 1 r/m data Immediate with accumulator 001111 0w data data if w = 1 NEG = Change sign 1111011w mod 0 1 1 r/m data if sw = 01 3/10 3/4 8/16-bit 3/10 register/memory AAA = ASCII adjust for add 00110111 8 DAA = Decimal adjust for add 00100111 4 AAS = ASCII adjust for subtract 00111111 7 DAS = Decimal adjust for 00101111 4 subtract MUL = Multiply (unsigned): 1111011w mod 1 0 0 r/m Register-Byte 26-28 Register-Word 35-37 Memory-Byte 32-34 Memory-Word 41-43 STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 DSCC FORM 2234 APR 97 SIZE 5962-88501 A REVISION LEVEL F SHEET 31 TABLE III. Instruction set summary - Continued. Function Clock cycles Format Comments ARITHMETIC - Continued IMUL = Integer multiply 1111011w mod 1 0 1 r/m (signed): Register-Byte 25-28 Register-Word 34-37 Memory-Byte 31-34 Memory-Word 40-43 IMUL = Integer immediate 011010s1 mod reg r/m data data if s = 0 multiply (signed): DIV = Divide (unsigned): 22-25/ 29-32 1111011w mod 1 1 0 r/m Register-Byte 29 Register-Word 38 Memory-Byte 35 Memory-Word 44 IDIV = Integer divide (signed): 1111011w mod 1 1 1 r/m Register-Byte 44-52 Register-Word 53-61 Memory-Byte 50-58 Memory-Word 59-67 AAM = ASCII adjust for multiply 11010100 00001010 19 AAD = ASCII adjust for divide 11010101 00001010 15 CBW = Convert byte to word 10011000 2 CWD = Convert word to double 10011001 4 word LOGIC Shift/Rotate instructions: Register/memory by 1 1101000w mod TTT r/m 2/15 Register/memory by CL 1101001w mod TTT r/m 5+n/17+n Register/memory by count 1100000w mod TTT r/m count 5+n/17+n TTT instruction 000 ROL 001 ROR 010 RCL 011 RCR 1 0 0 SHL/SAL 101 SHR 111 SAR STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 DSCC FORM 2234 APR 97 SIZE 5962-88501 A REVISION LEVEL F SHEET 32 TABLE III. Instruction set summary - Continued. Function Clock cycles Format Comments LOGIC - Continued AND = And: Reg/memory and register to either 001000dw mod reg r/m 3/10 Immediate to register/memory 1000000w mod 1 0 0 r/m data Immediate to accumulator 0010010w data data if w = 1 Register/memory and register 1000010w mod reg r/m Immediate data and 1111011w mod 0 0 0 r/m data register/memory Immediate data and 1010100w data data if w = 1 Reg/memory and register to either 000010dw mod reg r/m Immediate to register/memory 1000000w mod 0 0 1 r/m data Immediate to accumulator 0000110w data data if w = 1 Reg/memory and register to either 001100dw mod reg r/m Immediate to register/memory 1000000w mod 1 1 0 r/m data Immediate to accumulator 0011010w data data if w = 1 NOT = Invert register/memory 1111011w mod 0 1 0 r/m data if w = 1 4/16 3/4 8/16-bit TEST = And function to flags, no result: 3/10 data if w = 1 4/10 3/4 8/16-bit accumulator OR = Or: 3/10 data if w = 1 4/16 3/4 8/16-bit XOR = Exclusive or: 3/10 data if w = 1 4/16 3/4 8/16-bit 3/10 STRING MANIPULATION MOVS = Move byte/word 1010010w 14 CMPS = Compare byte/word 1010011w 22 SCAS = Scan byte/word 1010111w 15 LODS = Load byte/wd to ALAX 1010110w 12 STOS = Store byte/wd from ALA 1010101w 10 INS = Input byte/wd from DX 0110110w 14 0110111w 14 port OUTS = Output byte/wd to DX port STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 DSCC FORM 2234 APR 97 SIZE 5962-88501 A REVISION LEVEL F SHEET 33 TABLE III. Instruction set summary - Continued. Function Clock cycles Format Comments STRING MANIPULATION - Continued Repeated by count in CX MOVS = Move string 11110010 1010010w 8+8n CMPS = Compare string 1111001z 1010011w 5+22n SCAS = Scan string 1111001z 1010111w 5+15n LODS = Load string 11110010 1010110w 6+11n STOS = Store string 11110010 1010101w 6+9n INS = Input string 11110010 0110110w 8+8n OUTS = Output string 11110010 0110111w 8+8n Direct within segment 11101000 disp-low Register/memory indirect 11111111 mod 0 1 0 r/m CONTROL TRANSFER CALL = Call: disp-high 15 13/19 within segment Direct intersegment 10011010 segment offset 23 segment selector Indirect intersegment 11111111 mod 0 1 1 r/m Short/long 11101011 disp-low Direct within segment 11101001 disp-low Register/memory indirect 11111111 mod 1 0 0 r/m (mod 11) 38 JMP = Unconditional jump: 14 disp-high 14 11/17 within segment Direct intersegment 11101010 segment offset 14 segment selector Indirect intersegment 11111111 (mod 11) mod 1 0 1 r/m 26 RET = Return from call: Within segment 11000011 Within seg adding immed to SP 11000010 Intersegment 11001011 Intersegment adding 11001010 16 data-low data-high 18 22 data-low data-high 25 immediate to SP STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 DSCC FORM 2234 APR 97 SIZE 5962-88501 A REVISION LEVEL F SHEET 34 TABLE III. Instruction set summary - Continued. Function Format Clock cycles Comments CONTROL TRANSFER - Continued JE/JZ = Jump on equal/zero 01110100 disp 4/13 JL/JNGE = Jump on less/not greater or equal 01111100 disp 4/13 JLE/JNG = Jump on less or equal/not greater 01111110 disp 4/13 JB/JNAE = Jump on below/not above or equal 01110010 disp 4/13 JBE/JNA = Jump on below or equal/not above 01110110 disp 4/13 JP/JPE = Jump on parity/parity even 01111010 disp 4/13 JO = Jump on overflow 01110000 disp 4/13 JS = Jump on sign 01111000 disp 4/13 JNE/JNZ = Jump on not equal/ not zero 01110101 disp 4/13 JNL/JGE = Jump on not less/greater or equal 01111101 disp 4/13 JNLE/JG = Jump on not less or equal/greater 01111111 disp 4/13 JNB/JAE = Jump on not below/above or equal 01110011 disp 4/13 JNBE/JA = Jump on not below or equal/above 01110111 disp 4/13 JNP/JPO = Jump on not par/par odd 01111011 disp 4/13 JNO = Jump on not overflow 01110001 disp 4/13 JNS = Jump on not sign 01111001 disp 4/13 JCXZ = Jump on CX zero 11100011 disp 5/15 LOOP = Loop CX times 11100010 disp 6/16 LOOPZ/LOOPE = Loop while zero/equal 11100001 disp 6/16 LOOPNZ/LOOPNE = Loop while not zero/equal 11100000 disp 6/16 ENTER = Enter procedure 11001000 data-low data-high JMP not taken/JMP taken LOOP not taken/LOOP taken L L=0 L=1 L>1 15 25 22+16(n-1) LEAVE = Leave procedure 11001001 8 INT = Interrupt: Type specified 11001101 Type 3 11001100 45 INTO = Interrupt on overflow 11001110 48/4 STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 DSCC FORM 2234 APR 97 type 47 SIZE if INT. taken/if INT. not taken 5962-88501 A REVISION LEVEL F SHEET 35 TABLE III. Instruction set summary - Continued. Function Clock cycles Format Comments CONTROL TRANSFER - Continued IRET = Interrupt return 11001111 BOUND = Detect value out of range 01100010 28 mod reg r/m 33-35 PROCESSOR CONTROL CLC = Clear carry 11111000 2 CMC = Complement carry 11110101 2 STC = Set carry 11111001 2 CLD = Clear direction 11111100 2 STD = Set direction 11111101 2 CLI = Clear interrupt 11111010 2 SLI = Set interrupt 11111011 2 HLT = Halt 11110100 2 WAIT = Wait 10011011 6 LOCK = Bus lock prefix 11110000 2 ESC = Processor extension escape 11011TTT mod LLL r/m if test = 0 6 (TTT LLL are opcode to processor extension) NOTES: The effective address (EA) of the memory operand is computed according to the mod and r/m fields: if mod = 11 then r/m is treated as a REG field if mod = 00 then DISP = 0*, disp-low and disp-high are absent if mod = 01 then DISP = disp-low sign-extended to 16-bits, disp-high is absent if mod = 10 then DISP = disp-high: disp-low if r/m = 000 then EA = (BX) + (SI) + DISP if r/m = 001 then EA = (BX) + (DI) + DISP if r/m = 010 then EA = (BP) + (SI) + DISP if r/m = 011 then EA = (BP) + (DI) + DISP if r/m = 100 then EA = (SI) + DISP STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 DSCC FORM 2234 APR 97 SIZE 5962-88501 A REVISION LEVEL F SHEET 36 TABLE III. Instruction set summary - Continued. if r/m = 101 then EA = (DI) + DISP if r/m = 110 then EA = (BP) + DISP* if r/m = 111 then EA = (BX) + DISP DISP follows 2 nd byte of instruction (before data if required) * Except if mod = 00 and r/m = 110 then EA = disp-high: disp-low. EA calculation time is 4 clock cycles for all modes, and is included in the execution times given whenever appropriate. Segment override prefix 0 0 1 reg 1 1 0 reg is assigned according to the folowing: reg Segment Register 00 01 10 11 ES CS SS DS REG is assigned according to the following table: 16-Bit (w = 1) 8-Bit (w = 0) 000 AX 001 CX 010 DX 011 BX 100 SP 101 BP 110 SI 111 DI 000 AL 001 CL 010 DL 011 BL 100 AH 101 CH 110 DH 111 BH The physical addresses of all operands addressed by the BP register are computed using the SS segment register. The physical addresses of the destination operands of the string primitive operations (those addressed by the DI register) are computed using the ES segment, which may not be overridden. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 DSCC FORM 2234 APR 97 SIZE 5962-88501 A REVISION LEVEL F SHEET 37 TABLE IV. Pin description. Symbol Name and Function VCC System power: +5 volt power supply. VSS System ground. RESET Reset output indicates that the device CPU is being reset, and can be used as a system reset. It is active HIGH, synchronized with the processor clock, and lasts an integer number of clock periods corresponding to the length of the RES signal. Reset goes inactive 2 clockout periods after RES goes inactive. When tied to the TEST /BUSY pin, Reset forces the devices into enhanced mode. X1, X2 Crystal inputs, X1 and X2, provide an external connections for a fundamental mode or third overtone parallel resonant crystal for the internal oscillator. X1 can interface to an external clock instead of a crystal. In this case, minimize the capacitance on X2 or drive X2 with complemented X1. The input or oscillator frequency is internally divided by two to generate the clock signal (CLKOUT). CLKOUT Clock output provides the system with a 50 percent duty cycle waveform. All device pin timings are specified relative to CLKOUT. CLKOUT has sufficient MOS drive capabilities for the numeric processor extension. RES System reset causes the device to immediately terminate its present activity, clear the internal logic, and enter a dormant state. This signal may be asynchronous to the device clock. The device begins fetching instructions approximately 61/2 clock cycles after RES is returned HIGH. For proper initialization, VCC must be within specifications and the clock signal must be stable for more than 4 clocks with RES held low. RES is internally synchronized. This input is provided with a Schmitt-trigger to facilitate power-on RES generation via an RC network. When RES occurs, the device will drive the status lines to an inactive level for one clock, and then float them. TEST /BUSY The TEST pin is sampled during and after reset to determine whether the device is to enter compatible or enhanced mode. Enhanced mode requires TEST to be high on the rising edge of RES and low four clocks later. Any other combination will place the device in compatible mode. A weak internal pullup insures a high state when the pin is not driven. TEST , in compatible mode, this pin is configured to operate as TEST . This pin is examined by the WAIT instruction. If the TEST input is high when WAIT execution begins, instruction execution will suspend. TEST will be resampled every five clocks until it goes low, at which time execution will resume. If interrupts are enabled while the device is waiting for TEST , interrupts will be serviced. BUSY, in enhanced mode, this pin is configured to operate as BUSY. The BUSY input is used to notify the device of numerics processor extension activity. Floating point instructions executing in the device sample the BUSY pin to determine when the numeric processor is ready to accept a new coninand. BUSY is active high. TMR IN 0, TMR IN 1 Timer inputs are used either as clock or control signals, depending upon the programmed timer mode. These inputs are active high (or low-to-high transitions are counted) and internally synchronized. TMR OUT 0, TMR OUT 1 Timer outputs are used to provide single pulse or continuous waveform generation, depending upon the timer mode selected. DRQ0, DRQ1 DMA request is driven high by an external device when it desires that a DMA (channel 0 or 1) perform a transfer. These signals are active high, level-triggered, and internally synchronized. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 DSCC FORM 2234 APR 97 SIZE 5962-88501 A REVISION LEVEL F SHEET 38 TABLE IV. Pin description - Continued. Symbol Name and Function NMI Nonmaskable interrupt is an edge-triggered input which causes a type 2 interrupt. NMI is not maskable internally. A transition from a low to high initiates the interrupt at the next instruction boundary. NMI is latched internally. An NMI duration of one clock or more will guarantee service. This input is internally synchronized. INT0, INT1, Maskable interrupt requests can be requested by activating one of these pins. When configured as inputs, these pins are active high. Interrupt requests are synchronized internally. INT2 and INT3 may be configured via software to provide active-low interrupt-acknowledge output signals. All interrupt inputs may be configured via software to be either edge- or level-triggered. To ensure recognition, all interrupt requests must remain active until the interrupt is acknowledged. When slave mode is selected, the function of these pins changes. INT2/ INTA0 , INT3/ INTA1 A19/S6, A18/S5, A17/S4, A16/S3 Address bus outputs (16-19) and bus cycle status (3-6) reflect the four most significant address bits during T1. These signals are active high. During T2, T3, Tw, and T4, status information is available on these lines as encoded below: S6 Low High Processor cycle DMA cycle S3, S4, and S5 are defined as LOW during T2-T4. AD15 - AD0 Address/data bus (0-15) signals constitute the time multiplexed memory or I/O address (T1) and data (T2. T3, Tw, and T4) bus. The bus is active high A0 is analogous to BHE for the lower byte of the data bus, pins D7 through D0. It is low during T1 when a byte is to be transferred onto the lower portion of the bus in memory of I/O operations. BHE /S7 The BHE (bus high enable) signal is analogous to A0 in that it is used to enable data on to the most significant half of the data bus, pins D15-D8. BHE will be low during T1 when the upper byte is transferred and will remain low through T3 and Tw. BHE does not need to be latched. BHE will float during hold or reset. In enhanced mode, BHE will also be used to signify DRAM refresh cycles. A refresh cycle is indicated by BHE and A0 being high. BHE and A0 encodings ALE/QS0 BHE value A0 value Function 0 0 0 1 Byte transfer on upper half of data bus (D15-D8) 1 0 Byte transfer on lower half of data bus (D7-D0) 1 1 Refresh Word tranfer Address latch enable/queue status 0 is provided by the device to latch the address. ALE is active high. Addresses are guaranteed to be valid on the trailing edge of ALE. The ALE rising edge is generated off the rising edge of the CLKOUT immediately preceding T1 of the associated bus cycle. The trailing edge is generated off the CLKOUT rising edge in T1. Note that ALE is never floated. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 DSCC FORM 2234 APR 97 SIZE 5962-88501 A REVISION LEVEL F SHEET 39 TABLE IV. Pin description - Continued. Symbol Name and Function Write strobe/queue status 1 indicates that the data on the bus is to be written into a memory or an I/O WR /QS1 device. WR is active for T2, T3, and Tw of any write cycle. It is active low, and floats during "HOLD" or "Reset". It is driven high for one clock during reset, and then floated. When the device is in queue status mode, the ALE/QS0 and WR /QS1 pins provide information about processor instruction queue interaction. RD / QSMD QS1 QS0 Queue operation 0 0 No queue operation 0 1 First opcode byte fetched from the queue 1 1 Subsequent byte fetched from the queue 1 0 Empty the queue Read strobe indicates that the device is performing a memory or I/O read cycle. RD is active low for T2, T3. and Tw of any read cycle. It is guaranteed not to go low in T2 until after the address bus is floated. RD is active low, and floats during "HOLD". RD is driven high for one clock during reset, and then the output driver is floated. A weak internal pull-up mechanism on the RD line holds it high when the line is not driven. During RESET the pin is sampled to determine whether the device should provide ALE, WR , and RD , or if the queue-status should be provided. RD should be connected to GND to provide queue-status data. ARDY Asynchronous ready informs the device that the addressed memory space or I/O device will complete a data transfer. The ARDY input pin will accept an asynchronous input, and is active high. Only the rising edge is internally synchronized by the device. This means that the falling edge of ARDY must be synchronized to the device clock. If connected to VCC, no WAIT states are inserted. Asynchronous ready (ARDY) or synchronous ready (SRDY) must be active to terminate a bus cycle. If unused, this line should be tied LOW to yield control to the SRDY pin. SRDY Synchronous ready must be synchronized externally to the device. The use of SRDY provides a relaxed system-timing specification on the ready input. This is accomplished by eliminating the one-half clock cycle which is required for internally resolving the signal level when using the ARDY input. This line is active high. If this line is connected to VCC, no WAIT states are inserted. Asynchronous ready (ARDY) or synchronous ready (SRDY) must be active before a bus cycle is terminated. If unused, this line should be tied LOW to yield control to the ARDY pin. LOCK LOCK output indicates that other system bus masters are not to gain control of the system bus while LOCK is active low. The LOCK signal is requested by the LOCK prefix instruction and is activated at the beginning of the first data cycle associated with the instruction following the LOCK prefix. It remains active until the completion of the instruction following the LOCK prefix. No prefetches will occur while LOCK is asserted. LOCK is active low and is driven high for one clock during RESET. LOCK on devices 03-06 stay high during reset, while it is floated on the 01 and 02 devices. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 DSCC FORM 2234 APR 97 SIZE 5962-88501 A REVISION LEVEL F SHEET 40 TABLE IV. Pin description - Continued. Symbol S0 , S1, S2 Name and Function Bus cycle status S0 - S2 are encoded to provide bus-transaction information. Queue operation S2 S1 S0 0 0 0 Interrupt acknowledge 0 0 1 Read I/O 0 1 0 Write I/O 0 1 1 Halt 1 0 0 Instruction fetch 1 0 1 Read data from memory 1 1 0 Write data to memory 1 1 1 Passive (no bus cycle) The status pins float during "HOLD/HLDA". S2 may be used as a logical M/I O indicator, and S1 as a DT/ R indicator. The status lines are driven high for one clock during reset, and then floated until a bus cycle begins. HOLD (input) HLDA (output) HOLD indicates that another bus master is requesting the local bus. The HOLD input is active high. HOLD may be asynchronous with respect to the device clock. The device will issue a HLDA (high) in response to a HOLD request at the end of T4 or T1. Simultaneous with the issuance of HLDA the device will float the local bus and control lines. After HOLD is detected as being LOW, the device will lower HLDA. When the device needs to run another bus cycle, it will again drive the local bus and control lines. In enhanced mode, HLDA will go low when a DRAM refresh cycle is pending in the device and an external bus master has control of the bus. It will be up to the external master to relinquish the bus by lowering HOLD so that the device may execute the refresh cycle. Lowering HOLD for four clocks and returning high will insure only one refresh cycle to the external master. HLDA will immediately go active after the refresh cycle has taken place. Upper memory chip select is an active LOW output whenever a memory reference is made to the defined upper portion (1K-256K block) of memory. This line is not floated during bus HOLD. The UCS address range activating UCS is software programmable. UCS and LCS are sampled upon the rising edge of RES . If both pins are held low, the device will enter ONCE mode. In ONCE mode all pins assume a high impedance state and remain so until a subsequent RESET. UCS has weak internal pullup for normal operation. Lower memory chip select is an active LOW whenever a memory reference is made to the defined lower portion (1K-256K block) of memory. This line is not floated during bus HOLD. The address range LCS activating LCS is software programmable. UCS and LCS are sampled upon the rising edge of RES . If both pins are held low, the device will enter ONCE mode. In ONCE mode all pins assume a high impedance state and remain so until a subsequent RESET. UCS has weak internal pullup for normal operation. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 DSCC FORM 2234 APR 97 SIZE 5962-88501 A REVISION LEVEL F SHEET 41 TABLE IV. Pin description - Continued. Symbol MCS0 /PEREQ MCS1/ ERROR Name and Function Mid-range memory chip select signals are active low when a memory reference is made to the defined mid-range portion of memory (8K-512K). These lines are not floated during bus HOLD. The address ranges activating MCS0 -3 are software programmable. MCS2 MCS3 / NPS In enhanced mode, MCS0 becomes a PEREQ input (processor extension request). When connected to the numerics processor extension, this input is used to signal the device when to make numeric data transfers to and from the NPX. MCS3 becomes NPS (numeric processor select) which may only be activated by communication to the numeric processor extension. MCS1 becomes ERROR in enhanced mode and is used to signal numeric coprocessor errors. Peripheral chip select signals 0-4 are active low when a reference is made to the defined peripheral area (64K byte I/O space). These lines are not floated during bus HOLD. The address ranges PCS0 PCS1 -4 activating PCS0 -4 are software programmable. Peripheral chip select 5 or latched A1 may be programmed to provide a sixth peripheral chip select, or PCS5 /A1 to provide an internally latched A1 signal. The address range activating PCS5 is software programmable. When programmed to provide latched A1, rather than PCS5 , this pin will retain the previously latched value of A1 during a bus HOLD. A1 is active high. Peripheral chip select 6 or latched A2 may be programmed to provide a seventh peripheral chip select, PCS6 /A2 or to provide an internally latched A2 signal. The address range activating PCS6 is software progranmiable. When programmed to provide latched A2, rather than PCS6 , this pin will retain the previously latched value of A2 during a bus HOLD. A2 is active HIGH. Data transmit/receive controls the direction of data flow through the external data bus transceiver. When low, data is transferred to the device. When high, the device places write data on the data bus. DT/ R Data enable is provided as a data bus transceiver output enable. DEN is active low during each DEN memory and I/O access. DEN is high whenever DT/ R changes state. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 DSCC FORM 2234 APR 97 SIZE 5962-88501 A REVISION LEVEL F SHEET 42 STANDARD MICROCIRCUIT DRAWING BULLETIN DATE: 01-12-03 Approved sources of supply for SMD 5962-88501 are listed below for immediate acquisition information only and shall be added to MIL-HDBK-103 and QML-38535 during the next revision. MIL-HDBK-103 and QML-38535 will be revised to include the addition or deletion of sources. The vendors listed below have agreed to this drawing and a certificate of compliance has been submitted to and accepted by DSCC-VA. This bulletin is superseded by the next dated revision of MIL-HDBK-103 and QML-38535. Standard microcircuit drawing PIN 1/ Vendor CAGE number Vendor similar PIN 2/ 5962-8850101ZA 3V146 MG80C186-10/BZA 5962-8850101ZC 3V146 MG80C186-10/BZC 5962-8850101YA 3V146 MQ80C186-10/BYA 5962-8850101YC 3V146 MQ80C186-10/BYC 5962-8850102ZA 3V146 MG80C186-12/BZA 5962-8850102ZC 3V146 MG80C186-12/BZC 5962-8850102YA 3V146 MQ80C186-12/BYA 5962-8850102YC 3V146 MQ80C186-12/BYC 5962-8850103ZA 3/ MG80C186XL-20/B 5962-8850104ZA 3/ MG80C186XL-16/B 5962-8850105ZA 3/ MG80C186XL-12/B 5962-8850106ZA 3/ MG80C186XL-10/B 1/ The lead finish shown for each PIN representing a hermetic package is the most readily available from the manufacturer listed for that part. If the desired lead finish is not listed contact the vendor to determine its availability. 2/ Caution. Do not use this number for item acquisition. Items acquired to this number may not satisfy the performance requirements of this drawing. 3/ No longer available from an approved source of supply. Vendor CAGE number 63V146 Vendor name and address Rochester Electronics Inc. 10 Malcolm Hoyt Drive Newburyport, MA 01950 The information contained herein is disseminated for convenience only and the Government assumes no liability whatsoever for any inaccuracies in the information bulletin.