1
FEATURES
IN
GND
IN
EN
OUT
OUT
OUT
OC
DESCRIPTION
TPS2049
www.ti.com
......................................................................................................................................... SLVS713A – OCTOBER 2006 – REVISED SEPTEMBER 2007
SINGLE-CHANNEL 100 mA POWER SWITCH
•SOIC-8 Package•100-mA Continuous Current •Ambient Temperature Range: – 40 °C to 85 °C•600-m ΩHigh-Side MOSFET •2µS Response Time to Short Circuit•Thermal and Short-Circuit Protection•Operating Range: 2.7 V to 5.5 V•0.6-ms Typical Rise Time•Undervoltage Lockout•Deglitched Fault Report ( OC)•43 µA Quiescent Supply Current•1- µA Maximum Standby Supply Current
The TPS2049 power-distribution switch is intended for applications where heavy capacitive loads and shortcircuits are likely to be encountered. This device incorporates a 600-m ΩN-channel MOSFET power switch forpower-distribution systems that require only one power distribution path. The switch is controlled by a logicenable input. Gate drive is provided by an internal charge pump designed to control the power-switch rise timesand fall times to minimize current surges during switching. The charge pump requires no external componentsand allows operation from supplies as low as 2.7V.
When the output load exceeds the current-limit threshold or a short is present, the device limits the output currentto a safe level by switching into a constant-current mode, pulling the overcurrent ( OC) logic output low. Whencontinuous heavy overloads and short circuits increase the power dissipation in the switch, causing the junctiontemperature to rise, a thermal protection circuit shuts off the switch to prevent damage. Recovery from a thermalshutdown is automatic once the device has cooled sufficiently. Internal circuitry ensures the switch remains offuntil valid input voltage is present. This power-distribution switch is designed to set current limit at 150mAtypically.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications ofTexas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 2006 – 2007, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.
ABSOLUTE MAXIMUM RATINGS
DISSIPATING RATING TABLE
RECOMMENDED OPERATING CONDITIONS
TPS2049
SLVS713A – OCTOBER 2006 – REVISED SEPTEMBER 2007 .........................................................................................................................................
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foamduring storage or handling to prevent electrostatic damage to the MOS gates.
AVAILABLE OPTION AND ORDERING INFORMATION
(1)
RECOMMENDED MAXIMUM TYPICAL SHORT-CIRCUIT
NUMBER OFT
A
ENABLE CONTINUOUS LOAD CURRENT CURRENT LIMIT AT 25 °C SOIC (D)SWITCHES(mA) (mA)
– 40 °C to 85 °C Active low 100 150 Single TPS2049D
(2)
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TIwebsite at www.ti.com .(2) The package is available taped and reeled. Add an R suffix to device types (e.g., TPS2042BDR)
over operating free-air temperature range unless otherwise noted
(1)
VALUE UNIT
V
I(IN)
Input voltage range
(2)
– 0.3 to 6 VV
O(OUT)
Output voltage range
(2)
-0.3 to 6 VV
I( EN)
Input voltage range – 0.3 to 6 VV
I( OC)
Voltage range – 0.3 to 6 VI
O(OUT)
Continuous output current Internally limitedContinuous total power dissipation See Dissipation Rating TableT
J
Operating virtual junction temperature range – 40 to 125 °CT
stg
Storage temperature range – 65 to 150 °CLead temperature soldering 1,6 mm (1/16 inch) from case for 10 seconds 260 °CHuman body model MIL-STD-883C 2 kVElectrostatic discharge (ESD)protection
Charge device model (CDM) 500 V
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratingsonly, and functional operation of the device at these or any other conditions beyond those indicated under recommended operatingconditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.(2) All voltages are with respect to GND.
T
A
≤25 °C DERATING FACTOR T
A
= 70 °C T
A
= 85 °CPACKAGE
POWER RATING ABOVE T
A
= 25 °C POWER RATING POWER RATING
D-8 585.82 mW 5.8582 mW/C 322.20 mW 234.32 mW
MIN MAX UNIT
V
I(IN)
Input voltage 2.7 5.5 VV
I( EN)
Input voltage 0 5.5 VI
O(OUT)
Continuous output current 0 100 mAT
J
Operating virtual junction temperature – 40 125 °C
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Product Folder Link(s): TPS2049
ELECTRICAL CHARACTERISTICS
TPS2049
www.ti.com
......................................................................................................................................... SLVS713A – OCTOBER 2006 – REVISED SEPTEMBER 2007
over recommended operating junction temperature range, V
I(IN)
= 5.5 V, I
O
= 90 mA, V
I( EN)
= 0 V (unless otherwise noted)
PARAMETER TEST CONDITIONS
(1)
MIN TYP MAX UNIT
POWER SWITCH
Static drain-source
on-state resistance, 5-Vr
DS(on)
V
I(IN)
= 2.7 V or 5.5 V, I
O
= 90 A, – 40 °C < T
J
< 125 °C 400 650 m Ωoperation and 2.7-Voperationt
r
Rise time, output V
I(IN)
= 2.7 V C
L
= 1 F, R
L
= 50 Ω, T
J
= 25 °C 0.1 0.4 mst
f
Fall time, output V
I(IN)
= 2.7 V C
L
= 1 F, R
L
= 50 Ω, T
J
= 25 °C 0.03 0.3 ms
ENABLE INPUT EN
V
IH
High-level input voltage 2.7 V ≤V
I(IN)
≤5.5 V 2 VV
IL
Low-level input voltage 2.7 V ≤V
I(IN)
≤5.5 V 0.8 VI
I
Input current V
I( EN)
= 0 V or V
I(EN)
= V
I(IN)
– 0.5 0.5 µAt
on
Turnon time C
L
= 1 µF, R
L
= 50 Ω, T
J
= 25 °C 1 mst
off
Turnoff time C
L
= 1 F, R
L
= 50 Ω, T
J
= 25 °C 1 ms
CURRENT LIMIT
Short-circuit output V
I(IN)
= 5 V, OUT connected to GND, Device enabled intoI
OS
100 150 200 mAcurrent short-circuit, 10 °C < T
J
< 40 °CI
OC_trip
Overcurrent trip threshold 10 °C < T
J
< 40 °C, 100 A/sec current rate increase 325 mAShort-circuit response
2µstime
SUPPLY CURRENT
T
J
= 25 °C 0.5 1Supply current, low-level output No load on OUT V
I( EN)
= 5.5 V µA– 40C ≤T
J
≤125 °C 0.5 5T
J
= 25 °C 43 60Supply current, high-level output No load on OUT V
I( EN)
= 0 V µA– 40C ≤T
J
≤125 °C 43 70OUT connected toLeakage current V
I( EN)
= 5.5 V, – 40C ≤T
J
≤125 °C 1 µAground
V
I(OUT)
= 5.5 V,Reverse leakage current IN = ground T
J
= 25 °C 0 µAV
I( EN)
= 0 V
UNDERVOLTAGE LOCKOUT
IN Low-level input voltage 2 2.5 VIN Hysteresis T
J
= 25C 75 mV
OVERCURRENT OC
V
OL( OC)
Output low voltage I
O( OC)
= 5 mA 0.4 VOff-state current V
O( OC)
= 5 V or 3.3 V 1 µAOC deglitch OC assertion or de-assertion 4 8 15 ms
THERMAL SHUTDOWN
(2)
Thermal shutdown threshold 135 °CRecovery from thermal shutdown 125 °CHysteresis 10 °C
(1) Pulse-testing techniques maintain junction temperature close to ambient temperature; thermal effects must be taken into accountseparately.
(2) The thermal shutdown only reacts under overcurrent conditions.
Copyright © 2006 – 2007, Texas Instruments Incorporated Submit Documentation Feedback 3
Product Folder Link(s): TPS2049
TPS2049
SLVS713A – OCTOBER 2006 – REVISED SEPTEMBER 2007 .........................................................................................................................................
www.ti.com
FUNCTIONAL BLOCK DIAGRAM
TERMINAL FUNCTIONS
TERMINAL
I/O DESCRIPTIONNAME NO.
EN1 4 I Enable input, logic low turns on power switchGND 1 I GroundIN 2, 3 I Input voltageOC 5 O Overcurrent, report, active-low, open-drain outputOUT 6, 7, 8 O Power-switch output
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Product Folder Link(s): TPS2049
PARAMETER MEASUREMENT INFORMATION
RLCL
OUT
trtf
90% 90%
10%
10%
50% 50%
90%
10%
VO(OUT)
VI(EN)
VO(OUT)
VOLTAGE WAVEFORMS
TEST CIRCUIT
ton toff
50% 50%
90%
10%
VI(EN)
VO(OUT)
ton toff
V
2V/div
I( )EN
V
2V/div
O(OUT)
t-Time-100 s/divm
R =50
C =1 F
L
L
W
m
R =50
C =1 F
L
L
W
m
V
2V/div
I( )EN
V
2V/div
O(OUT1)
t-Time-100 s/divm
TPS2049
www.ti.com
......................................................................................................................................... SLVS713A – OCTOBER 2006 – REVISED SEPTEMBER 2007
Figure 1. Test Circuit and Voltage Waveforms
Figure 2. Turnon Delay and Rise Time With 1- µF Load Figure 3. Turnoff Delay and Fall Time With 1- µF Load
Copyright © 2006 – 2007, Texas Instruments Incorporated Submit Documentation Feedback 5
Product Folder Link(s): TPS2049
V
5V/div
I( )EN
V
5V/div
I(OUT)
t-Time-2 s/divm
OC
200ms/div
EnableIntoaShort
Watching Flag’sDelayOC
Hotshort5 onOutput
WatchCurrentLimit
ResponseTime.
Ω
I
200mA/div
O(OUT1)
V
5V/div
O(OUT1)
t-Time-2 s/divm
TPS2049
SLVS713A – OCTOBER 2006 – REVISED SEPTEMBER 2007 .........................................................................................................................................
www.ti.com
PARAMETER MEASUREMENT INFORMATION (continued)
Figure 4. Device Enabled Into a Short Figure 5. 5- ΩLoad Connected to Enabled Device
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APPLICATION INFORMATION
2,3
5
4
6,7,8
POWER-SUPPLY CONSIDERATIONS
OVERCURRENT
OC RESPONSE
TPS2049
www.ti.com
......................................................................................................................................... SLVS713A – OCTOBER 2006 – REVISED SEPTEMBER 2007
Figure 6. Typical Application
A 0.01- µF to 0.1- µF ceramic bypass capacitor between IN and GND, close to the device, is recommended.Placing a high-value electrolytic capacitor on the output pin(s) is recommended when the output load is heavy.This precaution reduces power-supply transients that may cause ringing on the input. Additionally, bypassing theoutput with a 0.01- µF to 0.1- µF ceramic capacitor improves the immunity of the device to short-circuit transients.
A sense FET is employed to check for overcurrent conditions. Unlike current – sense resistors, sense FETs do notincrease the series resistance of the current path. When an overcurrent condition is detected, the devicemaintains a constant output current and reduces the output voltage accordingly. Complete shutdown occurs onlyif the fault is present long enough to activate thermal limiting.
Three possible overload conditions can occur. In the first condition, the output has been shorted before thedevice is enabled or before VI(IN) has been applied (see Figure 6 ). The TPS2049 senses the short andimmediately switches into a constant-current output.
In the second condition, a short or an overload occurs while the device is enabled. At the instant the overloadoccurs, very high currents may flow for a short period of time before the current-limit circuit can react. After thecurrent-limit circuit has tripped (reached the overcurrent trip threshold) the device switches into constant-currentmode.
In the third condition, the load has been gradually increased beyond the recommended operating current. Thecurrent is permitted to rise until the current-limit threshold is reached or until the thermal limit of the device isexceeded. The TPS2049 is capable of delivering current up to the current-limit threshold without damaging thedevice. Once the threshold has been reached, the device switches into its constant-current mode.
The OC open-drain output is asserted (active low) when an overcurrent or overtemperature shutdown conditionis encountered after a 10-ms deglitch timeout. The output remains asserted until the overcurrent orovertemperature condition is removed. Connecting a heavy capacitive load to an enabled device can cause amomentary overcurrent condition; however, no false reporting on OC occurs due to the 10-ms deglitch circuit.The TPS2049 is designed to eliminate false overcurrent reporting. The internal overcurrent deglitch eliminatesthe need for external components to remove unwanted pulses. OC is not deglitched when the switch is turned offdue to an overtemperature shutdown.
Figure 7. Typical Circuit for the OC Pin
Copyright © 2006 – 2007, Texas Instruments Incorporated Submit Documentation Feedback 7
Product Folder Link(s): TPS2049
POWER DISSIPATION AND JUNCTION TEMPERATURE
THERMAL PROTECTION
UNDERVOLTAGE LOCKOUT (UVLO)
TPS2049
SLVS713A – OCTOBER 2006 – REVISED SEPTEMBER 2007 .........................................................................................................................................
www.ti.com
The low on-resistance on the n-channel MOSFET allows small surface-mount packages to pass large currents.The thermal resistance of these packages are high compared to those of power packages; it is good designpractice to check power dissipation and junction temperature. Begin by determining the r
DS(on)
of the N-channelMOSFET relative to the input voltage and operating temperature. As an initial estimate, use the highest operatingambient temperature of interest. Using this value, the power dissipation per switch can be calculated by:P
D
= r
DS(on)
×I
2
Finally, calculate the junction temperature:T
J
= P
D
×R
ΘJA
+ T
A
Where:
T
A
= Ambient temperature °CR
ΘJA
= Thermal resistanceP
D
= Total power dissipation based on number of switches being used.
Compare the calculated junction temperature with the initial estimate. If they do not agree within a few degrees,repeat the calculation, using the calculated value as the new estimate. Two or three iterations are generallysufficient to get a reasonable answer.
Thermal protection prevents damage to the IC when heavy-overload or short-circuit faults are present forextended periods of time. The TPS2049 implement a thermal sensing to monitor the operating junctiontemperature of the power distribution switch. In an overcurrent or short-circuit condition the junction temperaturewill rise due to excessive power dissipation. Once the die temperature rises to approximately 140 °C due toovercurrent conditions, the internal thermal sense circuitry turns the power switch off, thus preventing the powerswitch from damage. Hysteresis is built into the thermal sense circuit, and after the device has cooledapproximately 10 °C, the switch turns back on. The switch continues to cycle in this manner until the load fault orinput power is removed. The OC open-drain output is asserted (active low) when an overtemperature shutdownor overcurrent occurs.
An undervoltage lockout ensures that the power switch is in the off state at power up. Whenever the inputvoltage falls below approximately 2 V, the power switch will be quickly turned off. This facilitates the design ofhot-insertion systems where it is not possible to turn off the power switch before input power is removed. TheUVLO will also keep the switch from being turned on until the power supply has reached at least 2 V, even if theswitch is enabled. Upon reinsertion, the power switch will be turned on, with a controlled rise time to reduce EMIand voltage overshoots.
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Product Folder Link(s): TPS2049
GENERIC HOT-PLUG APPLICATIONS (see Figure 8 )
DETAILED DESCRIPTION
POWER SWITCH
CHARGE PUMP
DRIVER
ENABLE ( EN)
TPS2049
www.ti.com
......................................................................................................................................... SLVS713A – OCTOBER 2006 – REVISED SEPTEMBER 2007
In many applications it may be necessary to remove modules or pc boards while the main unit is still operating.These are considered hot-plug applications. Such implementations require the control of current surges seen bythe main power supply and the card being inserted. The most effective way to control these surges is to limit andslowly ramp the current and voltage being applied to the card, similar to the way in which a power supplynormally turns on. Due to the controlled rise times and fall times of the TPS2049, these devices can be used toprovide a softer start-up to devices being hot-plugged into a powered system. The UVLO feature of the TPS2049also ensures the switch will be off after the card has been removed, and the switch will be off during the nextinsertion. The UVLO feature insures a soft start with a controlled rise time for every insertion of the card ormodule.
Figure 8. Typical Hot-Plug Implementation
By placing the TPS2049 between the V
CC
input and the rest of the circuitry, the input power reaches thesedevices first after insertion. The typical rise time of the switch is approximately 1 ms, providing a slow voltageramp at the output of the device. This implementation controls system surge currents and provides ahot-plugging mechanism for any device.
The power switch is an N-channel MOSFET with a low on-state resistance. Configured as a high-side switch, thepower switch prevents current flow from OUT to IN and IN to OUT when disabled. The power switch supplies aminimum current of 90 mA.
An internal charge pump supplies power to the driver circuit and provides the necessary voltage to pull the gateof the MOSFET above the source. The charge pump operates from input voltages as low as 2.7 V and requireslittle supply current.
The driver controls the gate voltage of the power switch. To limit large current surges and reduce the associatedelectromagnetic interference (EMI) produced, the driver incorporates circuitry that controls the rise times and falltimes of the output voltage.
The logic enable pin disables the power switch and the bias for the charge pump, driver, and other circuitry toreduce the supply current. The supply current is reduced to less than 1 µA when a logic high is present on EN. Alogic zero input on EN restores bias to the drive and control circuits and turns the switch on. The enable input iscompatible with both TTL and CMOS logic levels.
Copyright © 2006 – 2007, Texas Instruments Incorporated Submit Documentation Feedback 9
Product Folder Link(s): TPS2049
OVERCURRENT ( OC)
CURRENT SENSE
THERMAL SENSE
UNDERVOLTAGE LOCKOUT
TPS2049
SLVS713A – OCTOBER 2006 – REVISED SEPTEMBER 2007 .........................................................................................................................................
www.ti.com
The OC open-drain output is asserted (active low) when an overcurrent or overtemperature condition isencountered. The output remains asserted until the overcurrent or overtemperature condition is removed. A10-ms deglitch circuit prevents the OC signal from oscillation or false triggering. If an overtemperature shutdownoccurs, the OC is asserted instantaneously.
A sense FET monitors the current supplied to the load. The sense FET measures current more efficiently thanconventional resistance methods. When an overload or short circuit is encountered, the current-sense circuitrysends a control signal to the driver. The driver in turn reduces the gate voltage and drives the power FET into itssaturation region, which switches the output into a constant-current mode and holds the current constant whilevarying the voltage on the load.
The TPS2049 implements a thermal sensing to monitor the operating temperature of the power distributionswitch. In an overcurrent or short-circuit condition, the junction temperature rises. When the die temperature risesto approximately 140 °C due to overcurrent conditions, the internal thermal sense circuitry turns off the switch,thus preventing the device from damage. Hysteresis is built into the thermal sense, and after the device hascooled approximately 10 degrees, the switch turns back on. The switch continues to cycle off and on until thefault is removed. The open-drain false reporting output ( OC) is asserted (active low) when an overtemperatureshutdown or overcurrent occurs.
A voltage sense circuit monitors the input voltage. When the input voltage is below approximately 2V, a controlsignal turns off the power switch.
10 Submit Documentation Feedback Copyright © 2006 – 2007, Texas Instruments Incorporated
Product Folder Link(s): TPS2049
PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
TPS2049D ACTIVE SOIC D 8 75 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS2049DG4 ACTIVE SOIC D 8 75 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS2049DR ACTIVE SOIC D 8 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS2049DRG4 ACTIVE SOIC D 8 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com 25-Sep-2007
Addendum-Page 1
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
TPS2049DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 12-Jul-2011
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TPS2049DR SOIC D 8 2500 340.5 338.1 20.6
PACKAGE MATERIALS INFORMATION
www.ti.com 12-Jul-2011
Pack Materials-Page 2
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