ICS854057AGLFT - Integrated Device Technology

854057AG www.icst.com/products/hiperclocks.html REV. A OCTOBER 29, 2008

Integrated

Circuit

Systems, Inc.

ICS854057

4:1 OR 2:1 LVDS CLOCK MULTIPLEXER

WITH INTERNAL INPUT TERMINATION

GENERAL DESCRIPTION

The ICS854057 is a 4:1 or 2:1 LVDS Clock Mul-

tiplexer which can operate up to 2GHz and is a

member of the HiPerClockS™ family of High Per-

formance Clock Solutions from ICS. The PCLK,

nPCLK pairs can accept most standard differen-

tial input levels. Internal termination is provided on each dif-

ferential input pair. The ICS854057 operates using a 2.5V sup-

ply voltage. The fully differential architecture and low propa-

gation delay make it ideal for use in high speed multiplexing

applications. The select pins have internal pulldown resistors.

Leaving one input unconnected (pulled to logic low by the in-

ternal resistor) will transform the device into a 2:1 multiplexer.

The SEL1 pin is the most significant bit and the binary num-

ber applied to the select pins will select the same numbered

data input (i.e., 00 selects PCLK0, nPCLK0).

FEATURES

•High speed differential multiplexer. The device can be

configured as either a 4:1 or 2:1 multiplexer

•Single LVDS output

•4 selectable PCLK, nPCLK inputs with internal termination

•PCLK, nPCLK pairs can accept the following differential

input levels: LVPECL, LVDS, CML, SSTL

•Output frequency: >2GHz

•Part-to-part skew: 200ps (maximum)

•Propagation delay: 800ps (maximum)

•Additive phase jitter, RMS: 66fs (typical)

•2.5V operating supply

•-40°C to 85°C ambient operating temperature

•Available in both, Standard and RoHS/Lead-Free compliant

packages

HiPerClockS™

ICS

BLOCK DIAGRAM PIN ASSIGNMENT

VDD

PCLK0

VT0

nPCLK0

SEL1

SEL0

PCLK1

VT1

nPCLK1

GND

VDD

PCLK3

VT3

nPCLK3

PCLK2

VT2

nPCLK2

GND

ICS854057

20-Lead TSSOP

4.40mm x 6.50mm x 0.925mm body package

G Package

Top View

VT0

PCLK0

nPCLK0

VT1

PCLK1

nPCLK1

VT2

PCLK2

nPCLK2

VT3

PCLK3

nPCLK3

50 50

SEL1

SEL0

Pulldown

854057AG www.icst.com/products/hiperclocks.html REV. A OCTOBER 29, 2008

Integrated

Circuit

Systems, Inc.

ICS854057

4:1 OR 2:1 LVDS CLOCK MULTIPLEXER

WITH INTERNAL INPUT TERMINATION

TABLE 2. PIN CHARACTERISTICS

TABLE 1. PIN DESCRIPTIONS

TABLE 3. CONTROL INPUT FUNCTION TABLE

rebmuNemaNepyTnoitpircseD

02,1V

rewoP.snipylppusevitisoP

20KLCPtupnIR.tupnikcolclaitnereffidLCEPVLgnitrevni-noN

05= Ω.0TVotnoitanimret

30TVtupnI .gnitaolfevael,tupniSDVLroF.tupninoitanimreT

05= Ω.0TVotnoitanimret

40KLCPntupnIR.tupnikcolclaitnereffidLCEPVLgnitrevnI

05= Ω0TVotnoitanimret

51LEStupnInwodlluP.slevelecafretniLTTVL/SOMCVL.tupnitceleskcolC

60LEStupnInwodlluP.slevele

cafretniLTTVL/SOMCVL.tupnitceleskcolC

71KLCPtupnIR.tupnikcolclaitnereffidLCEPVLgnitrevni-noN

05= Ω.1TVotnoitanimret

81TVtupnI .gnitaolfevael,tupniSDVLroF.tupninoitanimreT

05= Ω.1TVotnoitanimret

91KLCPntupnIR.tupnikcolclaitnereffidLCEPVLgnitrevnI

05= Ω.1TVotnoitanimret

11,01DNGrewoP.dnuorgylppusrewoP

212KLCPntupnIR.tupnikcolclaitnereffidLCEPVLgnitrevnI

05= Ω.2TVotnoitanimret

312TVtupnI .gnitaolfevael,tupniSDVLroF.tupninoitanimreT

05= Ω.2TVotnoitanimret

412KLCPtupnIR.tupnikcolclaitnereffidLCEPVLgnitrevni-noN

05= Ω.2TVotnoitanimret

61,51Q,QntuptuO.slevelecafretniSDVL.sriaptuptuolaitnereffiD

713KLCPntupnIR.tupnikcolcla

itnereffidLCEPVLgnitrevnI

05= Ω.3TVotnoitanimret

813TVtupnI .gnitaolfevael,tupniSDVLroF.tupninoitanimreT

05= Ω.3TVotnoitanimret

913KLCPtupnIR.tupnikcolclaitnereffidLCEPVLgnitrevni-noN

05= Ω.3TVotnoitanimret

:ETON

nwodlluP

.seulavlacipytrof,scitsiretcarahCniP,2elbaTeeS.srotsisertupnilanretniotsrefer

lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU

ecnaticapaCtupnI 5.1Fp

NWODLLUP

rotsiseRnwodlluPtupnI 05kΩ

rotsiseRnoitanimreTtupnI 05 Ω

stupnItuOkcolC

1LES0LESxKLCPn/xKLCP

00 0KLCPn,0KLCP

01 1KLCPn,1KLCP

10 2KLCPn,2KLCP

11 3KLCPn,3KLCP

854057AG www.icst.com/products/hiperclocks.html REV. A OCTOBER 29, 2008

Integrated

Circuit

Systems, Inc.

ICS854057

4:1 OR 2:1 LVDS CLOCK MULTIPLEXER

WITH INTERNAL INPUT TERMINATION

TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = 2.5V ± 5%, TA = -40°C TO 85°C

TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, VDD = 2.5V ± 5%, TA = -40°C TO 85°C

lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU

egatloVylppuSevitisoP 573.25.2526.2V

tnerruCylppuSrewoP 06Am

TABLE 4C. LVPECL DC CHARACTERISTICS, VDD = 2.5V ± 5%, TA = -40°C TO 85°C

lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU

tnerruChgiHtupnIV

V526.2=051Aµ

tnerruCwoLtupnIV

V,V526.2=

V0=051-Aµ

egatloVkaeP-ot-kaeP 51.02.1V

RMC

2,1ETON;egatloVtupnIedoMnommoC 2.1V

VsadenifedsiegatlovtupniedomnommoC:1ETON

VsixKLCPn,xKLCProfegatlovtupnimumixameht,snoitacilppadedneelgnisroF:2ETON

.V3.0+

lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU

egatloVhgiHtupnI V*7.0

3.0+V

egatloVwoLtupnI 3.0-V*3.0

tnerruChgiHtupnI1LES,0LESV

V526.2=051Aµ

tnerruCwoLtupnI1LES,0LESV

V,V526.2=

V0=051-Aµ

ABSOLUTE MAXIMUM RATINGS

Supply Voltage, V

DD 4.6V

Inputs, VI-0.5V to VDD + 0.5 V

Outputs, IO

Continuous Current 10mA

Surge Current 15mA

Package Thermal Impedance, θ

JA 73.2°C/W (0 lfpm)

Storage Temperature, T

STG -65°C to 150°C

NOTE: Stresses beyond those listed under Absolute

Maximum Ratings may cause permanent damage to the

device. These ratings are stress specifications only. Functional

operation of product at these conditions or any conditions be-

yond those listed in the

DC Characteristics

AC Character-

istics

is not implied. Exposure to absolute maximum rating

conditions for extended periods may affect product reliability.

854057AG www.icst.com/products/hiperclocks.html REV. A OCTOBER 29, 2008

Integrated

Circuit

Systems, Inc.

ICS854057

4:1 OR 2:1 LVDS CLOCK MULTIPLEXER

WITH INTERNAL INPUT TERMINATION

TABLE 5. AC CHARACTERISTICS, VDD = 2.5V ± 5%, TA = -40°C TO 85°C

lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU

XAM

ycneuqerFtuptuO 2>zHG

1ETON;yaleDnoitagaporP003008sp

tij ;SMR,rettiJesahPevitiddAreffuB

noitceSrettiJesahPevitiddAotrefer

,zHM80.226

zHM02-zHk21 66sf

)i(kswekStupnI 04sp

)pp(ks3,2ETON;wekStraP-ot-traP 002sp

emiTllaF/esiRtuptuO%08ot%0205052sp

cdoelcyCytuDtuptuO 7435%

≤zHM007 9415%

xum

NOITALOSI

noitalosIXUMzHM005=f55-mBd

ƒtaderusaemerasretemarapllA:ETON ≤.esiwrehtodetonsselnuzHG9.1

.tniopgnissorctupt

uolaitnereffidehtottniopgnissorctupnilaitnereffidehtmorfderusaeM:1ETON

dnasegatlovylppusemasehttagnitareposecivedtnereffidneewtebwekssadenifeD:2ETON

derusaemsituptuoeht,ecivedhcaenostupnifoepytemasehtgnisU.snoitidnocdaollauqehtiw

.tniopssorclaitnereffidehtta

.56dradnatSCEDEJhtiwecnadroccanidenifedsiretemar

apsihT:3ETON

TABLE 4D. LVDS DC CHARACTERISTICS, VDD = 2.5V ± 5%, TA = -40°C TO 85°C

lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU

egatloVtuptuOlaitnereffiD 522523524Vm

ΔV

egnahCedutingaM 453Vm

egatloVtesffO 521.152.1573.1V

ΔV

egnahCedutingaM 552Vm

854057AG www.icst.com/products/hiperclocks.html REV. A OCTOBER 29, 2008

Integrated

Circuit

Systems, Inc.

ICS854057

4:1 OR 2:1 LVDS CLOCK MULTIPLEXER

WITH INTERNAL INPUT TERMINATION

ADDITIVE PHASE JITTER

Additive Phase Jitter @ 622.08MHz

(12kHz to 20MHz)

= 66fs typical

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

-110

-120

-130

-140

-150

-160

-170

-180

-190

100 1k 10k 100k 1M 10M 100M 500M

The spectral purity in a band at a specific offset from the funda-

mental compared to the power of the fundamental is called the

dBc Phase Noise.

This value is normally expressed using a

Phase noise plot and is most often the specified plot in many

applications. Phase noise is defined as the ratio of the noise

power present in a 1Hz band at a specified offset from the fun-

damental frequency to the power value of the fundamental. This

ratio is expressed in decibels (dBm) or a ratio of the power in

As with most timing specifications, phase noise measurements

have issues. The primary issue relates to the limitations of the

equipment. Often the noise floor of the equipment is higher than

the noise floor of the device. This is illustrated above. The de-

the 1Hz band to the power in the fundamental. When the re-

quired offset is specified, the phase noise is called a

dBc

value,

which simply means dBm at a specified offset from the funda-

mental. By investigating jitter in the frequency domain, we get a

better understanding of its effects on the desired application over

the entire time record of the signal. It is mathematically possible

to calculate an expected bit error rate given a phase noise plot.

vice meets the noise floor of what is shown, but can actually be

lower. The phase noise is dependant on the input source and

measurement equipment.

OFFSET FROM CARRIER FREQUENCY (HZ)

SSB PHASE NOISE dBc/HZ

854057AG www.icst.com/products/hiperclocks.html REV. A OCTOBER 29, 2008

Integrated

Circuit

Systems, Inc.

ICS854057

4:1 OR 2:1 LVDS CLOCK MULTIPLEXER

WITH INTERNAL INPUT TERMINATION

PARAMETER MEASUREMENT INFORMATION

PART-TO-PART SKEW

PROPAGATION DELAY OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD

DIFFERENTIAL INPUT LEVEL

INPUT SKEW

2.5V OUTPUT LOAD AC TEST CIRCUIT

CMR

Cross Points

GND

PCLK0:

PCLK3

nPCLK0:

nPCLK3

VDD

tsk(pp)

PART 1

PART 2

PCLK0:

PCLK3

nPCLK0:

nPCLK3

PERIOD

odc = x 100%

SCOPE

nQx

LVD S

2.5V±5%

POWER SUPPLY

Float GND

VDD

PD2

PD1

tsk(i) = |tPD1 - tPD2|

tsk(i)

PCLKx

nPCLKx

PCLKy

nPCLKy

854057AG www.icst.com/products/hiperclocks.html REV. A OCTOBER 29, 2008

Integrated

Circuit

Systems, Inc.

ICS854057

4:1 OR 2:1 LVDS CLOCK MULTIPLEXER

WITH INTERNAL INPUT TERMINATION

Clock

Outputs 20%

80% 80%

20%

DIFFERENTIAL OUTPUT VOLTAGE SETUP

OUTPUT RISE/FALL TIME

OFFSET VOLTAGE SETUP

out

LVD S

DC Input

➤

/Δ V

➤

100

out

LVD S

DC Input VOD/Δ VOD

VDD

854057AG www.icst.com/products/hiperclocks.html REV. A OCTOBER 29, 2008

Integrated

Circuit

Systems, Inc.

ICS854057

4:1 OR 2:1 LVDS CLOCK MULTIPLEXER

WITH INTERNAL INPUT TERMINATION

APPLICATION INFORMATION

2.5V LVDS DRIVER T ERMINATION

Figure 1

shows a typical termination for LVDS driver in charac-

teristic impedance of 100Ω differential (50Ω single) transmis-

FIGURE 1. TYPICAL LVDS DRIVER TERMINATION

sion line environment. For buffer with multiple LDVS driver, it is

recommended to terminate the unused output.

2.5V

100

LVDS_Driver

100 Ohm Differiential Trans m i ss i on Li ne

PCLK

nPCLK

680

2.5V 2.5V

Receiver

with

Built-In

50 Oh m

680

FIGURE 2. UNUSED INPUT HANDLING

2.5V DIFFERENTIAL INPUT WITH BUILT-IN 50ΩΩ

ΩΩ

Ω TERMINATION UNUSED INPUT HANDLING

To prevent oscillation and to reduce noise, it is recommended to

have pull up and pull down connected to true and complement of

the unused input as shown in

Figure 2.

854057AG www.icst.com/products/hiperclocks.html REV. A OCTOBER 29, 2008

Integrated

Circuit

Systems, Inc.

ICS854057

4:1 OR 2:1 LVDS CLOCK MULTIPLEXER

WITH INTERNAL INPUT TERMINATION

LVPECL INPUT WITH BUILT-IN 50ΩΩ

ΩΩ

Ω TERMINATIONS INTERFACE

The PCLK /nPCLK with built-in 50Ω terminations accepts

LVDS, LVPECL, LVHSTL, CML, SSTL and other differential

signals. Both VSWING and VOH must meet the VPP and VCMR

input requirements.

Figures 3A to 3E

show interface

examples for the HiPerClockS PCLK/nPLCK input with built-in

50Ω terminations driven by the most common driver types. The

input interfaces suggested here are examples only. If the driver

is from another vendor, use their termination recommendation.

Please consult with the vendor of the driver component to

confirm the driver termination requirements.

FIGURE 3A. HIPERCLOCKS PCLK/nPCLK INPUT WITH

BUILT-IN 50ΩΩ

ΩΩ

Ω DRIVEN BY AN LVDS DRIVER

FIGURE 3B. HIPERCLOCKS PCLK/nPCLK INPUT WITH

BUILT-IN 50ΩΩ

ΩΩ

Ω DRIVEN BY AN LVPECL DRIVER

nIN

2.5V

LVDS

3.3V or 2.5V

Zo = 50 Ohm

Receiver

With

Built-In

50 Ohm

Zo = 50 Ohm

Receiver

With

Built-In

50 O hm

Zo = 50 Ohm

nIN

2.5V2.5V

2. 5V LVPECL

FIGURE 3E. HIPERCLOCKS PCLK/nPCLK INPUT WITH

BUILT-IN 50ΩΩ

ΩΩ

Ω DRIVEN BY AN SSTL DRIVER

FIGURE 3C. HIPERCLOCKS PCLK/nPCLK INPUT WITH

BUILT-IN 50ΩΩ

ΩΩ

Ω DRIVEN BY AN OPEN COLLECTOR

CML DRIVER

FIGURE 3D. HIPERCLOCKS PCLK/nPCLK INPUT WITH

BUILT-IN 50ΩΩ

ΩΩ

Ω DRIVEN BY A CML DRIVER

WITH BUILT-IN 50ΩΩ

ΩΩ

Ω PULLUP

Z o = 50 Ohm

2.5V

Z o = 50 Ohm

nIN

Receiver

With

Built-In

50 Ohm

2.5V

CML - Open Collector

nIN

Receiver

With

Built-In

50 Ohm

2.5V

Z o = 50 Ohm

CML - Built -in 50 Ohm P ull-up

2.5V

SSTL

R1 25

R2 25

nIN

Receiver With Built-In 50Ω

Zo = 50 Ohm

854057AG www.icst.com/products/hiperclocks.html REV. A OCTOBER 29, 2008

Integrated

Circuit

Systems, Inc.

ICS854057

4:1 OR 2:1 LVDS CLOCK MULTIPLEXER

WITH INTERNAL INPUT TERMINATION

SCHEMATIC EXAMPLE

Figure 4

shows a schematic example of the ICS854057. In this

example, the PCLK0/nPCLK0 and PCLK1/nPCLK1 inputs are

FIGURE 4. EXAMPLE ICS854057 LVDS SCHEMATIC

used. The decoupling capacitors should be physically located

near the power pin.

INPUTS:

PCLK/nPCLK INPUT:

For applications not requiring the use of a differential input, both

the PCLK and nPCLK pins can be left floating. Though not

required, but for additional protection, a 1kΩ resistor can be tied

from PCLK to ground.

RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS

OUTPUTS:

LVDS OUTPUT

All unused LVDS outputs can be left floating. We recommend

that there is no trace attached. Both sides of the differential

output pair should either be left floating or terminated.

(U1,20)

680

Zo = 50

VDD

680

Zo = 50

100

680

U1 ICS854057

10 11

VDD

PCLK0

VT0

nPCLK0

SEL1

SEL0

PCLK1

VT1

nPCLK1

GND GND

nPCLK2

VT2

PCLK2

VDD

PCLK3

VT3

nPCLK3

Zo = 50

VDD

LVDS

680

Zo = 50

VDD

VDD=2.5V

LVDS

LVPECL C2

0.1u

(U1,1)

0.1u

854057AG www.icst.com/products/hiperclocks.html REV. A OCTOBER 29, 2008

Integrated

Circuit

Systems, Inc.

ICS854057

4:1 OR 2:1 LVDS CLOCK MULTIPLEXER

WITH INTERNAL INPUT TERMINATION

RELIABILITY INFORMATION

TRANSISTOR COUNT

The transistor count for ICS854057 is: 346

TABLE 7. θJAVS. AIR FLOW TABLE FOR 20 LEAD TSSOP

θθ

θJA by Velocity (Linear Feet per Minute)

0 200 500

Single-Layer PCB, JEDEC Standard Test Boards 114.5°C/W 98.0°C/W 88.0°C/W

Multi-Layer PCB, JEDEC Standard Test Boards 73.2°C/W 66.6°C/W 63.5°C/W

NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.

854057AG www.icst.com/products/hiperclocks.html REV. A OCTOBER 29, 2008

Integrated

Circuit

Systems, Inc.

ICS854057

4:1 OR 2:1 LVDS CLOCK MULTIPLEXER

WITH INTERNAL INPUT TERMINATION

PACKAGE OUTLINE - G SUFFIX FOR 20 LEAD TSSOP

TABLE 8. PACKAGE DIMENSIONS

Reference Document: JEDEC Publication 95, MO-153

LOBMYS sretemilliM

muminiMmumixaM

N02

A--02.1

1A50.051.0

2A08.050.1

b91.003.0

c90.002.0

D04.606.6

ECISAB04.6

1E03.405.4

eCISAB56.0

4.057.0

α°0°8

aaa--01.0

854057AG www.icst.com/products/hiperclocks.html REV. A OCTOBER 29, 2008

Integrated

Circuit

Systems, Inc.

ICS854057

4:1 OR 2:1 LVDS CLOCK MULTIPLEXER

WITH INTERNAL INPUT TERMINATION

TABLE 9. ORDERING INFORMATION

While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use

or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use

in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not

recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product

for use in life support devices or critical medical instruments.

rebmuNredrO/traPgnikraMegakcaPgnigakcaPgnippihSerutarepmeT

GA750458 GA750458SCIPOSSTdael02ebutC°58otC°04-

TGA

750458 GA750458SCIPOSSTdael02leer&epat0052C°58otC°04-

FLGA750458 LGA750458SCIPOSST"eerF-daeL"dael02ebutC°5

8otC°04-

TFLGA750458 LGA750458SCIPOSST"eerF-daeL"dael02leer&epat0052C°58otC°04-

.tnailpmocSHoReradnanoita

rugifnoceerF-bPehterarebmuntrapehtotxiffus"FL"nahtiwderedroeratahtstraP:ETON

The aforementioned trademark, HiPerClockS™ is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.