ICS854057 Integrated Circuit Systems, Inc. 4:1 OR 2:1 LVDS CLOCK MULTIPLEXER WITH INTERNAL INPUT TERMINATION GENERAL DESCRIPTION FEATURES The ICS854057 is a 4:1 or 2:1 LVDS Clock Multiplexer which can operate up to 2GHz and is a HiPerClockSTM member of the HiPerClockSTM family of High Performance Clock Solutions from ICS. The PCLK, nPCLK pairs can accept most standard differential input levels. Internal termination is provided on each differential input pair. The ICS854057 operates using a 2.5V supply voltage. The fully differential architecture and low propagation delay make it ideal for use in high speed multiplexing applications. The select pins have internal pulldown resistors. Leaving one input unconnected (pulled to logic low by the internal resistor) will transform the device into a 2:1 multiplexer. The SEL1 pin is the most significant bit and the binary number applied to the select pins will select the same numbered data input (i.e., 00 selects PCLK0, nPCLK0). * High speed differential multiplexer. The device can be configured as either a 4:1 or 2:1 multiplexer ICS * Single LVDS output * 4 selectable PCLK, nPCLK inputs with internal termination * PCLK, nPCLK pairs can accept the following differential input levels: LVPECL, LVDS, CML, SSTL * Output frequency: >2GHz * Part-to-part skew: 200ps (maximum) * Propagation delay: 800ps (maximum) * Additive phase jitter, RMS: 66fs (typical) * 2.5V operating supply * -40C to 85C ambient operating temperature * Available in both, Standard and RoHS/Lead-Free compliant packages BLOCK DIAGRAM PIN ASSIGNMENT VT0 50 VDD PCLK0 VT0 nPCLK0 SEL1 SEL0 PCLK1 VT1 nPCLK1 GND 50 PCLK0 nPCLK0 VT1 50 50 PCLK1 nPCLK1 00 VT2 50 01 50 PCLK2 nPCLK2 10 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 VDD PCLK3 VT3 nPCLK3 Q nQ PCLK2 VT2 nPCLK2 GND ICS854057 Q nQ 20-Lead TSSOP 4.40mm x 6.50mm x 0.925mm body package G Package Top View 11 VT3 50 50 PCLK3 nPCLK3 SEL1 Pulldown SEL0 Pulldown 854057AG www.icst.com/products/hiperclocks.html 1 REV. A OCTOBER 29, 2008 ICS854057 Integrated Circuit Systems, Inc. 4:1 OR 2:1 LVDS CLOCK MULTIPLEXER WITH INTERNAL INPUT TERMINATION TABLE 1. PIN DESCRIPTIONS Number Name Type Description 1, 20 VDD Power Positive supply pins. 2 PCLK0 Input 3 VT0 Input 4 nPCLK0 Input Non-inver ting LVPECL differential clock input. RT = 50 termination to VT0. Termination input. For LVDS input, leave floating. RT = 50 termination to VT0. Inver ting LVPECL differential clock input. RT = 50 termination to VT0 5 SEL1 Input Pulldown Pulldown Clock select input. LVCMOS / LVTTL interface levels. 6 SEL0 Input 7 PCLK1 Input 8 VT1 Input 9 nPCLK1 Input Non-inver ting LVPECL differential clock input. RT = 50 termination to VT1. Termination input. For LVDS input, leave floating. RT = 50 termination to VT1. Inver ting LVPECL differential clock input. RT = 50 termination to VT1. 10, 11 GN D Power Power supply ground. 12 nPCLK2 Input 13 VT2 Input Inver ting LVPECL differential clock input. RT = 50 termination to VT2. Termination input. For LVDS input, leave floating. RT = 50 termination to VT2. Non-inver ting LVPECL differential clock input. RT = 50 termination to VT2. 14 PCLK2 Input 15, 16 nQ, Q Output 17 nPCLK3 Input 18 VT 3 Input 19 PCLK3 Input Clock select input. LVCMOS / LVTTL interface levels. Differential output pairs. LVDS interface levels. Inver ting LVPECL differential clock input. RT = 50 termination to VT3. Termination input. For LVDS input, leave floating. RT = 50 termination to VT3. Non-inver ting LVPECL differential clock input. RT = 50 termination to VT3. NOTE: Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol Parameter Test Conditions Minimum Typical Maximum Units CIN Input Capacitance 1.5 pF RPULLDOWN Input Pulldown Resistor 50 k RT Input Termination Resistor 50 TABLE 3. CONTROL INPUT FUNCTION TABLE Inputs Clock Out SEL1 SEL0 PCLKx/nPCLKx 0 0 PCLK0, nPCLK0 0 1 PCLK1, nPCLK1 1 0 PCLK2, nPCLK2 1 1 PCLK3, nPCLK3 854057AG www.icst.com/products/hiperclocks.html 2 REV. A OCTOBER 29, 2008 ICS854057 Integrated Circuit Systems, Inc. 4:1 OR 2:1 LVDS CLOCK MULTIPLEXER WITH INTERNAL INPUT TERMINATION ABSOLUTE MAXIMUM RATINGS Supply Voltage, VDD 4.6V Inputs, VI -0.5V to VDD + 0.5 V Outputs, IO Continuous Current Surge Current 10mA 15mA Package Thermal Impedance, JA 73.2C/W (0 lfpm) Storage Temperature, TSTG -65C to 150C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = 2.5V 5%, TA = -40C TO 85C Symbol Parameter VDD Positive Supply Voltage Test Conditions IDD Power Supply Current Minimum Typical Maximum Units 2.375 2.5 2.625 V 60 mA Maximum Units TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, VDD = 2.5V 5%, TA = -40C TO 85C Symbol Parameter Test Conditions Minimum Typical VIH Input High Voltage 0.7 * VDD VDD + 0.3 V VIL Input Low Voltage -0.3 0.3 * VDD V IIH Input High Current SEL0, SEL1 VDD = VIN = 2.625V 150 A IIL Input Low Current SEL0, SEL1 VDD = 2.625V, VIN = 0V -150 A TABLE 4C. LVPECL DC CHARACTERISTICS, VDD = 2.5V 5%, TA = -40C TO 85C Symbol Parameter Test Conditions IIH Input High Current VDD = VIN = 2.625V IIL Input Low Current VDD = 2.625V, VIN = 0V VPP Peak-to-Peak Voltage VCMR Common Mode Input Voltage; NOTE 1, 2 Minimum Typical Maximum Units 150 A -150 A 0.15 1.2 V 1.2 VDD V NOTE 1: Common mode input voltage is defined as VIH. NOTE 2: For single ended applications, the maximum input voltage for PCLKx, nPCLKx is VDD + 0.3V. 854057AG www.icst.com/products/hiperclocks.html 3 REV. A OCTOBER 29, 2008 ICS854057 Integrated Circuit Systems, Inc. 4:1 OR 2:1 LVDS CLOCK MULTIPLEXER WITH INTERNAL INPUT TERMINATION TABLE 4D. LVDS DC CHARACTERISTICS, VDD = 2.5V 5%, TA = -40C TO 85C Symbol Parameter VOD Differential Output Voltage VOD VOD Magnitude Change VOS Offset Voltage VOS VOS Magnitude Change Test Conditions Minimum Typical Maximum Units 225 325 425 mV 4 35 mV 1.25 1.375 V 5 25 mV Typical Maximum Units 1.125 TABLE 5. AC CHARACTERISTICS, VDD = 2.5V 5%, TA = -40C TO 85C Symbol Parameter Test Conditions fMAX Output Frequency tPD tsk(i) Propagation Delay; NOTE 1 Buffer Additive Phase Jitter, RMS; refer to Additive Phase Jitter Section Input Skew tsk(pp) Par t-to-Par t Skew; NOTE 2, 3 tR / tF Output Rise/Fall Time tjit odc Output Duty Cycle muxISOLATION MUX Isolation Minimum >2 30 0 622.08MHz, 12kHz - 20MHz 20% to 80% 700MHz f = 500MHz GHz 800 66 ps fs 40 ps 200 ps 50 250 ps 47 53 % 49 51 % -55 dBm NOTE: All parameters are measured at 1.9GHz unless noted otherwise. NOTE 1: Measured from the differential input crossing point to the differential output crossing point. NOTE 2: Defined as skew between different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the output is measured at the differential cross point. NOTE 3: This parameter is defined in accordance with JEDEC Standard 65. 854057AG www.icst.com/products/hiperclocks.html 4 REV. A OCTOBER 29, 2008 ICS854057 Integrated Circuit Systems, Inc. 4:1 OR 2:1 LVDS CLOCK MULTIPLEXER WITH INTERNAL INPUT TERMINATION ADDITIVE PHASE JITTER the 1Hz band to the power in the fundamental. When the required offset is specified, the phase noise is called a dBc value, which simply means dBm at a specified offset from the fundamental. By investigating jitter in the frequency domain, we get a better understanding of its effects on the desired application over the entire time record of the signal. It is mathematically possible to calculate an expected bit error rate given a phase noise plot. The spectral purity in a band at a specific offset from the fundamental compared to the power of the fundamental is called the dBc Phase Noise. This value is normally expressed using a Phase noise plot and is most often the specified plot in many applications. Phase noise is defined as the ratio of the noise power present in a 1Hz band at a specified offset from the fundamental frequency to the power value of the fundamental. This ratio is expressed in decibels (dBm) or a ratio of the power in 0 -10 Additive Phase Jitter @ 622.08MHz -20 (12kHz to 20MHz) = 66fs typical -30 -40 -50 SSB PHASE NOISE dBc/HZ -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 -190 100 1k 10k 100k 1M 10M 100M 500M OFFSET FROM CARRIER FREQUENCY (HZ) vice meets the noise floor of what is shown, but can actually be lower. The phase noise is dependant on the input source and measurement equipment. As with most timing specifications, phase noise measurements have issues. The primary issue relates to the limitations of the equipment. Often the noise floor of the equipment is higher than the noise floor of the device. This is illustrated above. The de- 854057AG www.icst.com/products/hiperclocks.html 5 REV. A OCTOBER 29, 2008 ICS854057 Integrated Circuit Systems, Inc. 4:1 OR 2:1 LVDS CLOCK MULTIPLEXER WITH INTERNAL INPUT TERMINATION PARAMETER MEASUREMENT INFORMATION VDD VDD nPCLK0: nPCLK3 Qx SCOPE V LVDS V Cross Points PP 2.5V5% POWER SUPPLY + Float GND - CMR PCLK0: PCLK3 nQx GND 2.5V OUTPUT LOAD AC TEST CIRCUIT DIFFERENTIAL INPUT LEVEL nPCLKx PCLKx nQ PART 1 Q nPCLKy PCLKy nQ nQ PART 2 Q tsk(pp) Q tPD2 tPD1 tsk(i) tsk(i) = |tPD1 - tPD2| INPUT SKEW PART-TO-PART SKEW nPCLK0: nPCLK3 nQ PCLK0: PCLK3 Q t PW t nQ Q tPD odc = PERIOD t PW x 100% t PERIOD OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD PROPAGATION DELAY 854057AG www.icst.com/products/hiperclocks.html 6 REV. A OCTOBER 29, 2008 ICS854057 Integrated Circuit Systems, Inc. 4:1 OR 2:1 LVDS CLOCK MULTIPLEXER WITH INTERNAL INPUT TERMINATION VDD LVDS 100 20% 20% out tF tR OUTPUT RISE/FALL TIME VOD/ VOD DC Input VOD Clock Outputs out 80% 80% DIFFERENTIAL OUTPUT VOLTAGE SETUP VDD out LVDS DC Input out VOS/ VOS OFFSET VOLTAGE SETUP 854057AG www.icst.com/products/hiperclocks.html 7 REV. A OCTOBER 29, 2008 ICS854057 Integrated Circuit Systems, Inc. 4:1 OR 2:1 LVDS CLOCK MULTIPLEXER WITH INTERNAL INPUT TERMINATION APPLICATION INFORMATION 2.5V LVDS DRIVER TERMINATION Figure 1 shows a typical termination for LVDS driver in characteristic impedance of 100 differential (50 single) transmis- sion line environment. For buffer with multiple LDVS driver, it is recommended to terminate the unused output. 2.5V 2.5V LVDS_Driv er + R1 100 - 100 Ohm Differiential Transmission Line FIGURE 1. TYPICAL LVDS DRIVER TERMINATION 2.5V DIFFERENTIAL INPUT WITH TERMINATION UNUSED INPUT HANDLING BUILT-IN 50 To prevent oscillation and to reduce noise, it is recommended to have pull up and pull down connected to true and complement of the unused input as shown in Figure 2. 2.5V 2.5V R1 680 PCLK VT nPCLK R2 680 Receiver with Built-In 50 Ohm FIGURE 2. UNUSED INPUT HANDLING 854057AG www.icst.com/products/hiperclocks.html 8 REV. A OCTOBER 29, 2008 ICS854057 Integrated Circuit Systems, Inc. 4:1 OR 2:1 LVDS CLOCK MULTIPLEXER WITH INTERNAL INPUT TERMINATION TERMINATIONS INTERFACE LVPECL INPUT WITH BUILT-IN 50 The PCLK /nPCLK with built-in 50 terminations accepts LVDS, LVPECL, LVHSTL, CML, SSTL and other differential signals. Both VSWING and VOH must meet the VPP and VCMR input requirements. Figures 3A to 3E show interface examples for the HiPerClockS PCLK/nPLCK input with built-in 3.3V or 2.5V 50 terminations driven by the most common driver types. The input interfaces suggested here are examples only. If the driver is from another vendor, use their termination recommendation. Please consult with the vendor of the driver component to confirm the driver termination requirements. 2.5V 2.5V 2.5V Zo = 50 Ohm Zo = 50 Ohm IN IN VT Zo = 50 Ohm nIN LVDS nIN Receiver With Built-In 50 Ohm Receiver With Built-In 50 Ohm 2.5V LVPECL R1 18 FIGURE 3A. HIPERCLOCKS PCLK/nPCLK INPUT WITH DRIVEN BY AN LVDS DRIVER BUILT-IN 50 2.5V VT Zo = 50 Ohm FIGURE 3B. HIPERCLOCKS PCLK/nPCLK INPUT WITH DRIVEN BY AN LVPECL DRIVER BUILT-IN 50 2.5V 2.5V 2.5V Zo = 50 Ohm Zo = 50 Ohm IN IN VT Zo = 50 Ohm nIN CML - Open Collector Zo = 50 Ohm VT nIN Receiver With Built-In 50 Ohm CML - Built-in 50 Ohm Pull-up FIGURE 3C. HIPERCLOCKS PCLK/nPCLK INPUT WITH DRIVEN BY AN OPEN COLLECTOR BUILT-IN 50 CML DRIVER Receiver With Built-In 50 Ohm FIGURE 3D. HIPERCLOCKS PCLK/nPCLK INPUT WITH DRIVEN BY A CML DRIVER BUILT-IN 50 PULLUP WITH BUILT-IN 50 2.5V 2.5V R1 25 Zo = 50 Ohm IN Zo = 50 Ohm VT nIN R2 SSTL 25 Receiver With Built-In 50 FIGURE 3E. HIPERCLOCKS PCLK/nPCLK INPUT WITH DRIVEN BY AN SSTL DRIVER BUILT-IN 50 854057AG www.icst.com/products/hiperclocks.html 9 REV. A OCTOBER 29, 2008 ICS854057 Integrated Circuit Systems, Inc. 4:1 OR 2:1 LVDS CLOCK MULTIPLEXER WITH INTERNAL INPUT TERMINATION RECOMMENDATIONS FOR UNUSED INPUT INPUTS: OUTPUT PINS OUTPUTS: AND PCLK/nPCLK INPUT: For applications not requiring the use of a differential input, both the PCLK and nPCLK pins can be left floating. Though not required, but for additional protection, a 1k resistor can be tied from PCLK to ground. LVDS OUTPUT All unused LVDS outputs can be left floating. We recommend that there is no trace attached. Both sides of the differential output pair should either be left floating or terminated. SCHEMATIC EXAMPLE Figure 4shows a schematic example of the ICS854057. In this example, the PCLK0/nPCLK0 and PCLK1/nPCLK1 inputs are used. The decoupling capacitors should be physically located near the power pin. VDD VDD VDD LVDS VDD VDD U1 Zo = 50 ICS854057 R1 680 R1 1K 1 2 3 4 5 6 7 8 9 10 Zo = 50 VDD VDD PCLK0 VT0 nPCLK0 SEL1 SEL0 PCLK1 VT1 nPCLK1 GND VDD PCLK3 VT3 nPCLK3 Q nQ PCLK2 VT2 nPCLK2 GND 20 19 18 17 16 15 14 13 12 11 R5 100 Zo = 50 R2 680 LVPECL R6 18 VDD (U1,1) + Zo = 50 Zo = 50 R1 1K R3 680 LVDS R4 680 (U1,20) Zo = 50 C1 0.1u C2 0.1u VDD=2.5V FIGURE 4. EXAMPLE ICS854057 LVDS SCHEMATIC 854057AG www.icst.com/products/hiperclocks.html 10 REV. A OCTOBER 29, 2008 ICS854057 Integrated Circuit Systems, Inc. 4:1 OR 2:1 LVDS CLOCK MULTIPLEXER WITH INTERNAL INPUT TERMINATION RELIABILITY INFORMATION TABLE 7. JAVS. AIR FLOW TABLE FOR 20 LEAD TSSOP JA by Velocity (Linear Feet per Minute) 0 Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 114.5C/W 73.2C/W 200 98.0C/W 66.6C/W 500 88.0C/W 63.5C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. TRANSISTOR COUNT The transistor count for ICS854057 is: 346 854057AG www.icst.com/products/hiperclocks.html 11 REV. A OCTOBER 29, 2008 ICS854057 Integrated Circuit Systems, Inc. PACKAGE OUTLINE - G SUFFIX FOR 4:1 OR 2:1 LVDS CLOCK MULTIPLEXER WITH INTERNAL INPUT TERMINATION 20 LEAD TSSOP TABLE 8. PACKAGE DIMENSIONS Millimeters SYMBOL Minimum N A Maximum 20 -- 1.20 A1 0.05 0.15 A2 0.80 1.05 b 0.19 0.30 c 0.09 0.20 D 6.40 6.60 E E1 6.40 BASIC 4.30 e 4.50 0.65 BASIC L 0.45 0.75 0 8 aaa -- 0.10 Reference Document: JEDEC Publication 95, MO-153 854057AG www.icst.com/products/hiperclocks.html 12 REV. A OCTOBER 29, 2008 ICS854057 Integrated Circuit Systems, Inc. 4:1 OR 2:1 LVDS CLOCK MULTIPLEXER WITH INTERNAL INPUT TERMINATION TABLE 9. ORDERING INFORMATION Part/Order Number 854057AG Marking Package Shipping Packaging Temperature ICS854057AG 20 lead TSSOP tube -40C to 85C 854057AGT ICS854057AG 20 lead TSSOP 2500 tape & reel -40C to 85C 854057AGLF ICS854057AGL 20 lead "Lead-Free" TSSOP tube -40C to 85C 854057AGLFT ICS854057AGL 20 lead "Lead-Free" TSSOP 2500 tape & reel -40C to 85C NOTE: Par ts that are ordered with an "LF" suffix to the par t number are the Pb-Free configuration and are RoHS compliant. The aforementioned trademark, HiPerClockSTM is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 854057AG www.icst.com/products/hiperclocks.html 13 REV. A OCTOBER 29, 2008