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FEATURES APPLICATIONS
DESCRIPTION
PCM1742
SBAS176A – DECEMBER 2000 – REVISED APRIL 2005
24-Bit, 192-kHz Sampling, Enhanced Multilevel, Delta-Sigma,Audio Digital-to-Analog Converter
•AV Receivers•24-Bit Resolution
•DVD Movie Players•Analog Performance (V
CC
= 5 V):
•DVD Add-On Cards for High-End PCs– Dynamic Range:
•DVD Audio Players•106 dB, Typical (PCM1742KE)
•HDTV Receivers•100 dB, Typical (PCM1742E)
•Car Audio Systems– SNR:
•Other Applications Requiring 24-Bit Audio•106 dB, Typical (PCM1742KE)•100 dB, Typical (PCM1742E)– THD+N:
The PCM1742 is a CMOS, monolithic, integrated•0.002%, Typical (PCM1742KE)
circuit which includes stereo digital-to-analog con-verters (DACs) and support circuitry in a small•0.003%, Typical (PCM1742E)
SSOP-16 package. The data converters use Texas– Full-Scale Output: 3.1 V
p-p
, Typical
Instruments' enhanced multilevel delta-sigma archi-•4x/8x Oversampling Digital Filter:
tecture that employs fourth-order noise shaping andStop-Band Attenuation: –55 dB
8-level amplitude quantization to achieve excellentPass-Band Ripple: ±0.03 dB
dynamic performance and improved tolerance toclock jitter. The PCM1742 accepts industry-standard•Sampling Frequency: 5 kHz to 200 kHz
audio data formats with 16- to 24-bit data, providing•System Clock: 128 f
S
, 192 f
S
, 256 f
S
, 384 f
S
,
easy interfacing to audio DSP and decoder chips.512 f
S
, 768 f
S
With Autodetect
Sampling rates up to 200 kHz are supported. A full•Accepts 16-, 18-, 20-, and 24-Bit Audio Data
set of user-programmable functions is accessiblethrough a 3-wire serial control port that supports•Data Formats: Standard, I
2
S, and
register write functions.Left-Justified
•User-Programmable Mode Controls:Digital Attenuation: 0 dB to –63 dB, 0.5dB/Step
Digital De-Emphasis
Digital Filter Rolloff: Sharp or SlowSoft MuteZero Flags for Each Output•Dual-Supply Operation: 5-V Analog, 3.3-VDigital
•5-V Tolerant Digital Inputs•Small SSOP-16 Package
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.FilterPro is a trademark of Texas Instruments.System Two, Audio Precision are trademarks of Audio Precision, Inc.All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Copyright © 2000–2005, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.
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ABSOLUTE MAXIMUM RATINGS
(1)
RECOMMENDED OPERATING CONDITIONS
ELECTRICAL CHARACTERISTICS
PCM1742
SBAS176A – DECEMBER 2000 – REVISED APRIL 2005
over operating free-air temperature range (unless otherwise noted)
Power supply voltage, V
DD
–0.3 V to 4 VPower supply voltage, V
CC
–0.3 V to 6.5 VSupply voltage difference, V
CC
, V
DD
V
CC
– V
DD
< 3 VGround voltage differences ±0.1 VDigital input voltage –0.3 V to 6.5 VInput current (except power supply pins) ±10 mAAmbient temperature under bias –40°C to 125°CStorage temperature, T
stg
–55°C to 150°CJunction temperature, T
J
150°CLead temperature (soldering) 260°C, 5 sPackage temperature (IR reflow, peak) 235°C
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratingsonly, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operatingconditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
over operating free-air temperature range
MIN NOM MAX UNIT
Digital supply voltage, V
DD
3 3.3 3.6 VAnalog supply voltage, V
CC
4.5 5 5.5 VDigital input logic family TTLSystem clock 8.192 36.864 MHzDigital input clock frequency
Sampling clock 32 192 kHzAnalog output load resistance 5 k ΩAnalog output load capacitance 50 pFDigital output load capacitance 20 pFOperating free-air temperature, T
A
–25 85 °C
All specifications at T
A
= 25°C, V
CC
= 5 V, V
DD
= 3.3 V, f
S
= 44.1 kHz, system clock = 384 f
S
, and 24-bit data (unlessotherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Resolution 24 Bits
DATA FORMAT
Audio data interface formats Standard, I
2
S, left-justifiedAudio data bit length 16-, 18-, 20-, 24-bit selectableAudio data format MSB-first, binary 2s complementf
S
Sampling frequency 5 200 kHzSystem clock frequency 128, 192, 256, 384, 512, 768 f
S
DIGITAL INPUT/OUTPUT
Logic family TTL compatible
Input Logic Level
V
IH
High-level input votlage 2 VdcV
IL
Low-level input voltage 0.8 Vdc
2
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PCM1742
SBAS176A – DECEMBER 2000 – REVISED APRIL 2005
ELECTRICAL CHARACTERISTICS (continued)All specifications at T
A
= 25°C, V
CC
= 5 V, V
DD
= 3.3 V, f
S
= 44.1 kHz, system clock = 384 f
S
, and 24-bit data (unlessotherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Input Logic Current
I
IH
High-level input current
(1)
V
IN
= V
DD
10 µAI
IL
Low-level input current
(1)
V
IN
= 0 V –10 µAI
IH
High-level input current
(2)
V
IN
= V
DD
65 100 µAI
IL
Low-level input current
(2)
V
IN
= 0 V –10 µA
Output Logic Level
V
OH
High-level output voltage
(3)
I
OH
= –2 mA 2.4 VdcV
OL
Low-level output voltage
(3)
I
OL
= 2 mA 1 Vdc
DYNAMIC PERFORMANCE
(4) (5)
PCM1742E
V
OUT
= 0 dB, f
S
= 44.1 kHz 0.003% 0.008%V
OUT
= 0 dB, f
S
= 96 kHz 0.004%V
OUT
= 0 dB, f
S
= 192 kHz 0.005%THD+N Total harmonic distortion + noise
V
OUT
= –60 dB, f
S
= 44.1 kHz 1.2%V
OUT
= –60 dB, f
S
= 96 kHz 1.6%V
OUT
= –60 dB, f
S
= 192 kHz 1.8%EIAJ, A-weighted, f
S
= 44.1 kHz 94 100Dynamic range A-weighted, f
S
= 96 kHz 98 dBA-weighted, f
S
= 192 kHz 96EIAJ, A-weighted, f
S
= 44.1 kHz 94 100SNR Signal-to-noise ratio A-weighted, f
S
= 96 kHz 98 dBA-weighted, f
S
= 192 kHz 96f
S
= 44.1 kHz 91 98Channel separation f
S
= 96 kHz 96 dBf
S
= 192 kHz 94Level linearity error V
OUT
= –90 dB ±0.5 dB
(1) Pins 1, 2, 3, 16 (SCK, BCK, LRCK, DATA).(2) Pins 13–15 (MD, MC, ML).(3) Pins 11, 12 (ZEROR, ZEROL).(4) Analog performance specifications are tested with a Shibasoku #725 THD meter with 400-Hz HPF on, 30-kHz LPF on, and an averagemode with 20-kHz bandwidth limiting. The load connected to the analog output is 5 k Ωor larger, via capacitive coupling.(5) Conditions in 192-kHz operation are: system clock = 128 f
S
and oversampling rate = 64 f
S
(under register control).
3
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PCM1742
SBAS176A – DECEMBER 2000 – REVISED APRIL 2005
ELECTRICAL CHARACTERISTICS (continued)All specifications at T
A
= 25°C, V
CC
= 5 V, V
DD
= 3.3 V, f
S
= 44.1 kHz, system clock = 384 f
S
, and 24-bit data (unlessotherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
PCM1742KE
V
OUT
= 0 dB, f
S
= 44.1 kHz 0.002% 0.006%V
OUT
= 0 dB, f
S
= 96 kHz 0.003%V
OUT
= 0 dB, f
S
= 192 kHz 0.004%THD+N Total harmonic distortion + noise
V
OUT
= –60 dB, f
S
= 44.1 kHz 0.65%V
OUT
= –60 dB, f
S
= 96 kHz 0.8%V
OUT
= –60 dB, f
S
= 192 kHz 0.95%EIAJ, A-weighted, f
S
= 44.1 kHz 100 106Dynamic range A-weighted, f
S
= 96 kHz 104 dBA-weighted, f
S
= 192 kHz 102EIAJ, A-weighted, f
S
= 44.1 kHz 100 106SNR Signal-to-noise ratio A-weighted, f
S
= 96 kHz 104 dBA-weighted, f
S
= 192 kHz 102f
S
= 44.1 kHz 97 103Channel separation f
S
= 96 kHz 101 dBf
S
= 192 kHz 100Level linearity error V
OUT
= –90 dB ±0.5 dB
DC ACCURACY
Gain error ±1 ±6 % of FSRGain mismatch, channel-to-channel ±1 ±3 % of FSRBipolar zero error V
OUT
= 0.5 V
CC
at bipolar zero ±30 ±60 mV
ANALOG OUTPUT
Output voltage Full scale (0 dB) 0.62 V
CC
Vp-pCenter voltage 0.5 V
CC
VdcLoad Impedance AC load 5 k Ω
DIGITAL FILTER PERFORMANCE
Filter Characteristics, Sharp Rolloff
Pass band ±0.03 dB 0.454 f
S
Pass band –3 dB 0.487 f
S
Stop band 0.546 f
S
Pass-band ripple ±0.03 dBStop band = 0.546 f
S
–50Stop-band attenuation dBStop band = 0.567 f
S
–55
Filter Characteristics, Slow Rolloff
Pass band ±0.5 dB 0.198 f
S
Pass band –3 dB 0.39 f
S
Stop band 0.884 f
S
Pass-band ripple ±0.5 dBStop-band attenuation Stop band = 0.884 f
S
–40 dBDelay time 20/f
S
sDe-emphasis error ±0.1 dB
ANALOG FILTER PERFORMANCE
f = 20 kHz –0.03Frequency response dBf = 44 kHz –0.20
4
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Functional Block Diagram
Audio
Serial
Port
Output Amp and
Low−Pass Filter
DAC
4x/8x
Oversampling
Digital Filter
with
Function
Controller
Enhanced
Multilevel
Delta−Sigma
Modulator
Output Amp and
Low−Pass Filter
DAC
BCK
LRCK
DATA
ML
MC
MD
Serial
Control
Port
System Clock
Manager Zero Detect Power Supply
VOUTL
VCOM
VOUTR
VDD
DGND
ZEROL
ZEROR
SCK
System Clock
VCC
AGND
PCM1742
SBAS176A – DECEMBER 2000 – REVISED APRIL 2005
ELECTRICAL CHARACTERISTICS (continued)All specifications at T
A
= 25°C, V
CC
= 5 V, V
DD
= 3.3 V, f
S
= 44.1 kHz, system clock = 384 f
S
, and 24-bit data (unlessotherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
POWER SUPPLY REQUIREMENTS
(6)
V
DD
3 3.3 3.6Voltage range VdcV
CC
4.5 5 5.5f
S
= 44.1 kHz 6 10I
DD
Supply current f
S
= 96 kHz 13 mAf
S
= 192 kHz 16f
S
= 44.1 kHz 8.5 13I
CC
Supply current f
S
= 96 kHz 9 mAf
S
= 192 kHz 9f
S
= 44.1 kHz 62 98Power dissipation f
S
= 96 kHz 88 mWf
S
= 192 kHz 98
TEMPERATURE RANGE
T
A
Operation temperature –25 85 °Cθ
JA
Thermal resistance 115 °C/W
(6) Conditions in 192-kHz operation are: system clock = 128 f
S
and oversampling rate = 64 f
S
(under register control).
5
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PIN ASSIGNMENTS
BCK
DATA
LRCK
DGND
VDD
VCC
VOUTL
VOUTR
SCK
ML
MC
MD
ZEROL/NA
ZEROR/ZEROA
VCOM
AGND
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
PCM1742
PCM1742
SBAS176A – DECEMBER 2000 – REVISED APRIL 2005
PCM1742DBQ PACKAGE
(TOP VIEW)
TERMINAL FUNCTIONS
TERMINAL
I/O DESCRIPTIONNAME NO.
AGND 9 – Analog groundBCK 1 I Audio data bit clock input
(1)
DATA 2 I Audio data digital input
(1)
DGND 4 – Digital groundLRCK 3 I L-channel and R-channel audio-data latch-enable input
(1)
MC 14 I Mode control clock input
(2)
MD 13 I Mode control data input
(2)
ML 15 I Mode control latch input
(2)
SCK 16 I System clock input
(1)
V
CC
6 – Analog power supply, 5 VV
COM
10 – Common voltage decouplingV
DD
5 – Digital power supply, 3.3 VV
OUT
L 7 O Analog output for L-channelV
OUT
R 8 O Analog output for R-channelZEROL/NA 12 O Zero-flag output for L-channel/No assignZEROR/ZEROA 11 O Zero-flag output for R-channel/Zero-flag output for L-/R-channel
(1) Schmitt-trigger input, 5-V tolerant.(2) Schmitt-trigger input with internal pulldown, 5-V tolerant.
6
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TYPICAL PERFORMANCE CURVES
Digital Filter (De-Emphasis Off)
0
−20
−40
−60
−80
−100
−120
−140 0 1 2 3 4
Frequency (x fS)
Amplitude (dB)
0.05
0.04
0.03
0.02
0.01
0
−0.01
−0.02
−0.03
−0.04
−0.05 0 0.1 0.2 0.3 0.4 0.5
Frequency (x fS)
Amplitude (dB)
0
−20
−40
−60
−80
−100
−120
−140 0 1 2 3 4
Frequency (x fS)
Amplitude (dB)
5
4
3
2
1
0
−1
−2
−3
−4
−5 0 0.1 0.2 0.3 0.4 0.5
Frequency (x fS)
Amplitude (dB)
PCM1742
SBAS176A – DECEMBER 2000 – REVISED APRIL 2005
All specifications at T
A
= 25°C, V
CC
= 5 V, V
DD
= 3.3 V, f
S
= 44.1 kHz, system clock = 384 f
S
, and 24-bit input data, unlessotherwise noted
FREQUENCY RESPONSE (SHARP ROLLOFF) PASS-BAND FREQUENCY RESPONSE (SHARP ROLLOFF)
Figure 1. Figure 2.
FREQUENCY RESPONSE (SLOW ROLLOFF) TRANSITION CHARACTERISTICS (SLOW ROLLOFF)
Figure 3. Figure 4.
7
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TYPICAL PERFORMANCE CURVES (continued)
Digital Filter (De-Emphasis)
0.0
−1.0
−2.0
−3.0
−4.0
−5.0
−6.0
−7.0
−8.0
−9.0
−10.0 0 2 4 6 8 10 12 14
Frequency (kHz)
Level (dB)
0.5
0.4
0.3
0.2
0.1
0.0
−0.1
−0.2
−0.3
−0.4
−0.5 0 2 4 6 8 10 12 14
Frequency (kHz)
Error (dB)
PCM1742
SBAS176A – DECEMBER 2000 – REVISED APRIL 2005
All specifications at T
A
= 25°C, V
CC
= 5 V, V
DD
= 3.3 V, f
S
= 44.1 kHz, system clock = 384 f
S
, and 24-bit input data, unlessotherwise noted
DE-EMPHASIS (f
S
= 32 kHz) DE-EMPHASIS ERROR (f
S
= 32 kHz)
Figure 5. Figure 6.
DE-EMPHASIS (f
S
= 44.1 kHz) DE-EMPHASIS ERROR (f
S
= 44.1 kHz)
Figure 7. Figure 8.
DE-EMPHASIS (f
S
= 48 kHz) DE-EMPHASIS ERROR (f
S
= 48 kHz)
Figure 9. Figure 10.
8
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TYPICAL PERFORMANCE CURVES (continued)
ANALOG DYNAMIC PERFORMANCE
Supply Voltage Characteristics
110
108
106
104
102
100
98
96 4 4.5 5 5.5 6
VCC (V)
Dynamic Range (dB)
44.1kHz, 384fS
96kHz, 384fS
192kHz, 384fS
44.5 55.5 6
VCC (V)
THD+N (%)
−60dB/96kHz, 384fS
−60dB/44.1kHz, 384fS
0dB/96kHz, 384fS
0dB/44.1kHz, 384fS
−60dB/192kHz, 384fS
0dB/192kHz, 384fS
10
1
0.1
0.01
0.001
0.0001
110
108
106
104
102
100
98
96 4 4.5 5 5.5 6
VCC (V)
SNR (dB)
44.1kHz, 384fS
96kHz, 384fS
192kHz, 384fS
110
108
106
104
102
100
98
96 4 4.5 5 5.5 6
VCC (V)
Channel Separation (dB)
44.1kHz, 384fS
96kHz, 384fS
192kHz, 384fS
PCM1742
SBAS176A – DECEMBER 2000 – REVISED APRIL 2005
All specifications at T
A
= 25°C, V
CC
= 5 V, V
DD
= 3.3 V, and 24-bit input data, unless otherwise specified. Conditions in192-kHz operation are system clock = 128 f
S
and oversampling rate = 64 f
S
(under register control).
TOTAL HARMONIC DISTORTION + NOISE DYNAMIC RANGEvs vsV
CC
(V
DD
= 3.3 V) V
CC
(V
DD
= 3.3 V)
Figure 11. Figure 12.
SIGNAL-TO-NOISE RATIO CHANNEL SEPARATIONvs vsV
CC
(V
DD
= 3.3 V) V
CC
(V
DD
= 3.3 V)
Figure 13. Figure 14.
9
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TYPICAL PERFORMANCE CURVES (continued)
ANALOG DYNAMIC PERFORMANCE (continued)
Temperature Characteristics
110
108
106
104
102
100
98
96 −50 −25 0 25 50 75 100
Dynamic Range (dB)
44.1kHz, 384fS
96kHz, 384fS
192kHz, 384fS
Temperature (°C)
10
1
0.1
0.01
0.001
0.0001 −50 −25 0 25 50 75 100
THD+N (%)
−60dB/96kHz, 384fS
−60dB/44.1kHz, 384fS
0dB/96kHz, 384fS
0dB/44.1kHz, 384fS
0dB/192kHz, 384fS
−60dB/192kHz, 384fS
Temperature (°C)
110
108
106
104
102
100
98
96 −50 −25 0 25 50 75 100
SNR (dB)
44.1kHz, 384fS
96kHz, 384fS
192kHz, 384fS
Temperature (°C)
110
108
106
104
102
100
98
96 −50 −25 0 25 50 75 100
Channel Separation (dB)
44.1kHz, 384fS
96kHz, 384fS
192kHz, 384fS
Temperature (°C)
PCM1742
SBAS176A – DECEMBER 2000 – REVISED APRIL 2005
All specifications at T
A
= 25°C, V
CC
= 5 V, V
DD
= 3.3 V, and 24-bit input data, unless otherwise specified. Conditions in192-kHz operation are system clock = 128 f
S
and oversampling rate = 64 f
S
(under register control).
TOTAL HARMONIC DISTORTION + NOISE DYNAMIC RANGEvs vsTEMPERATURE (T
A
) TEMPERATURE (T
A
)
Figure 15. Figure 16.
SIGNAL-TO-NOISE RATIO CHANNEL SEPARATIONvs vsTEMPERATURE (T
A
) TEMPERATURE (T
A
)
Figure 17. Figure 18.
10
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SYSTEM CLOCK AND RESET FUNCTIONS
SYSTEM CLOCK INPUT
tSCKH
tSCKL
2 V
0.8 V
System Clock
H
L
tSCKY
PCM1742
SBAS176A – DECEMBER 2000 – REVISED APRIL 2005
The PCM1742 requires a system clock for operating the digital interpolation filters and multilevel delta-sigmamodulators. The system clock is applied at the SCK input (pin 16). Table 1 shows examples of system clockfrequencies for common audio sampling rates.
Figure 19 shows the timing requirements for the system clock input. For optimal performance, it is important touse a clock source with low phase jitter and noise. The PLL1700 multiclock generator from Texas Instruments isan excellent choice for providing the PCM1742 system clock.
Table 1. System Clock Rates for Common Audio Sampling Frequencies
SAMPLING FREQUENCY SYSTEM CLOCK FREQUENCY (f
SCLK
) (MHz)
128 f
S
192 f
S
256 f
S
384 f
S
512 f
S
768 f
S
8 kHz
(1) (1)
2.048 3.072 4.096 6.14416 kHz
(1) (1)
4.096 6.144 8.192 12.28832 kHz
(1) (1)
8.192 12.288 16.384 24.57644.1 kHz
(1) (1)
11.2896 16.9344 22.5792 33.868848 kHz
(1) (1)
12.288 18.432 24.576 36.86488.2 kHz
(1) (1)
22.5792 33.8688 45.1584
(1)
96 kHz
(1) (1)
24.576 36.864 49.152
(1)
192 kHz 24.576 36.864
(1) (1) (1) (1)
(1) This system clock is not supported for the given sampling frequency.
SYMBOL DESCRIPTION MIN MAX UNIT
t
SCKY
System clock cycle time
(1)
20 nst
SCKH
System clock pulse duration, HIGH 7 nst
SCKL
System clock pulse duration, LOW 7 ns
(1) 1/128 f
S
, 1/192 f
S
, 1/256 f
S
, 1/384 f
S
, 1/512 f
S
, or 1/768 f
S
Figure 19. System Clock Input Timing
11
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POWER-ON RESET FUNCTIONS
1024 System Clocks
Reset Reset Removal
VDD
Internal Reset
2.4V
2.0V
1.6V
0V
System Clock
Don’t Care
AUDIO SERIAL INTERFACE
PCM1742
SBAS176A – DECEMBER 2000 – REVISED APRIL 2005
The PCM1742 includes a power-on-reset function, as shown in Figure 20 . With the system clock active and V
DD> 2 V (typical, 1.6 V to 2.4 V), the power-on-reset function is enabled. The initialization sequence requires 1024system clocks from the time V
DD
> 2 V. After the initialization period, the PCM1742 is set to its reset defaultstate, as described in the Mode Control Registers section of this data sheet.
During the reset period (1024 system clocks), the analog outputs are forced to the bipolar zero level, or V
CC
/2.After the reset period, all the mode control registers are initialized in the next 1/f
S
period and, if SCK, BCK, andLRCK are provided continuously, the PCM1742 provides proper analog output with group delay corresponding tothe input data.
Figure 20. Power-On-Reset Timing
The audio serial interface for the PCM1742 comprises a 3-wire synchronous serial port. It includes LRCK (pin 3),BCK (pin 1), and DATA (pin 2). BCK is the serial audio bit clock, which is used to clock the serial data present onDATA into the audio interface serial shift register. Serial data is clocked into the PCM1742 on the rising edge ofBCK. LRCK is the serial audio left/right word clock used to latch serial data into the serial audio interface internalregisters.
Both LRCK and BCK must be synchronous to the system clock. Ideally, it is recommended that LRCK and BCKbe derived from the system clock input, SCK. LRCK is operated at the sampling frequency, f
S
. BCK can beoperated at 32 (16-bit, right-justified only), 48, or 64 times the sampling frequency. Internal operation of thePCM1742 is synchronized with LRCK. Accordingly, internal operation of the device is suspended when thesampling rate clock of LRCK is changed or SCK and/or BCK is interrupted at least for three bit-clock cycles. IfSCK, BCK, and LRCK are provided continuously after this suspended state, the internal operation isresynchronized automatically within a period of less than 3/f
S
. During this resynchronization period and for a 3/f
Stime thereafter, the analog output is forced to the bipolar zero level, or V
CC
/2. External resetting is not required.
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AUDIO DATA FORMATS AND TIMING
1/fS
L−Channel R−Channel
LRCK
BCK
(= 48 or 64fS)
18−Bit Right−Justified
DATA
DATA
(2) I2S Data Format: L−Channel = LOW, R−Channel = HIGH
(3) Left−Justified Data Format: L−Channel = HIGH, R−Channel = LOW
(1) Standard Data Format: L−Channel = HIGH, R−Channel = LOW 1/fS
L−Channel R−Channel
LRCK
BCK
(= 32, 48 or 64fS)
1 2 3 N−2 N−1 N 1 2 1 23 N−2 N−1 N
1/fS
L−Channel
R−Channel
LRCK
BCK
(= 48 or 64fS)
211 2 3 N−2 N−1 N 1 2 3 N−2 N−1 N
14 15 16
16 17 18
18 19 20
14 15 161 2 3DATA
22 23 24 22 23 241 2 3
DATA
18 19 201 2 3DATA
16 17 181 2 3
DATA
24−Bit Right−Justified
14 15 161 2 3
22 23 241 2 3
18 19 201 2 3
17 181 2
20−Bit Right−Justified
LSBMSB LSBMSB
LSBMSB
LSBMSBLSBMSB
LSBMSB LSBMSB
LSBMSB
LSBMSB
LSBMSB
LSBMSB
LSBMSB
14 15 16 14 15 161 2 3
DATA
16−Bit Right−Justified, BCK = 32fS
14 15 161 2 3
LSBMSB LSBMSB
16−Bit Right−Justified, BCK = 48fSor 64fS
PCM1742
SBAS176A – DECEMBER 2000 – REVISED APRIL 2005
The PCM1742 supports industry-standard audio data formats, including standard, I
2
S, and left-justified, as shownin Figure 21 . Data formats are selected using the format bits, FMT[2:0], in control register 20. The default dataformat is 24-bit, left-justified. All formats require binary 2s complement, MSB-first audio data. See Figure 22 for adetailed timing diagram of the serial audio interface.
Figure 21. Audio Data Input Formats
13
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LRCK
BCK
DATA
50% of VDD
50% of VDD
50% of VDD
tBCH tBCL tLB
tBL
tDS tDH
tBCY
PCM1742
SBAS176A – DECEMBER 2000 – REVISED APRIL 2005
SYMBOL DESCRIPTION MIN MAX UNIT
t
BCY
BCK pulse cycle time 1/(64 f
S
)
(1)
t
BCH
BCK high-level time 35 nst
BCL
BCK low-level time 35 nst
BL
BCK rising edge to LRCK edge 10 nst
LB
LRCK falling edge to BCK rising edge 10 nst
DS
DATA setup time 10 nst
DH
DATA hold time 10 ns
(1) f
S
is the sampling frequency (e.g., 44.1 kHz, 48 kHz, 96 kHz, etc.).
Figure 22. Audio Interface Timing
14
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SERIAL CONTROL INTERFACE
REGISTER WRITE OPERATION
IDX5IDX60 IDX4 IDX2IDX3 IDX1 IDX0 D7 D6 D5 D4 D3 D2 D1 D0
MSB
Register Index (or Address) Register Data
LSB
0 D7 D6 D5 D4 D3 D2 0 IDX6D1 D0X X XIDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0
ML
MC
MD
PCM1742
SBAS176A – DECEMBER 2000 – REVISED APRIL 2005
The serial control interface is a 3-wire serial port that operates asynchronously to the serial audio interface. Theserial control interface is used to program the on-chip mode registers. The serial control interface includesMD (pin 13), MC (pin 14), and ML (pin 15). MD is the serial data input, used to program the mode registers; MCis the serial bit clock, used to shift data into the control port; and ML is the control-port latch clock.
All write operations for the serial control port use 16-bit data words. Figure 23 shows the control data wordformat. The most significant bit must be a 0. Seven bits, labeled IDX[6:0], set the register index (or address) forthe write operation. The least significant eight bits, D[7:0], contain the data to be written to the register specifiedby IDX[6:0].
Figure 23. Control Data Word Format for MD
Figure 24 shows the functional timing diagram for writing to the serial control port. ML is held at a logic-1 stateuntil a register needs to be written. To start the register write cycle, ML is set to logic-0. Sixteen clocks are thenprovided on MC, corresponding to the 16 bits of the control data word on MD. After the sixteenth clock cycle hascompleted, ML is set to logic-1 to latch the data into the indexed mode control register.
Figure 24. Register Write Operation
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CONTROL INTERFACE TIMING REQUIREMENTS
50% of VDD
50% of VDD
50% of VDD
ML
MC
MD
tML S tMCH
tMCY
tMDS tMDH
tMCL
tMHH
tMLH
LSB
MODE CONTROL REGISTERS
User-Programmable Mode Controls
PCM1742
SBAS176A – DECEMBER 2000 – REVISED APRIL 2005
See Figure 25 for a detailed timing diagram of the serial control interface. These timing parameters are critical forproper control port operation.
SYMBOL PARAMETER MIN TYP MAX UNIT
t
MCY
MC pulse cycle time 100 nst
MCL
MC low-level time 50 nst
MCH
MC high-level time 50 nst
MHH
ML high-level time 3/(256 × f
S
)
(2)
nst
MLS
ML falling edge to MC rising edge 20 nst
MLH
ML hold time
(1)
20 nst
MDH
MD hold time 15 nst
MDS
MD setup time 20 ns
(1) MC rising edge for LSB to ML rising edge(2) f
S
= sampling rate
Figure 25. Control Interface Timing
The PCM1742 includes a number of user-programmable functions that are accessed via control registers. Theregisters are programmed using the serial control interface that is discussed in a preceding section of this datasheet. Table 2 lists the available mode control functions, along with their reset default conditions and associatedregister index.
Table 2. User-Programmable Mode Controls
FUNCTION RESET DEFAULT CONTROL INDEX IDX[6:0]REGISTER
Digital attenuation control, 0 dB to –63 dB in 0.5-dB steps 0 dB, no attenuation 16 and 17 AT1[7:0], AT2[7:0]Soft mute control Mute disabled 18 MUT[2:0]Oversampling rate control (64 f
S
or 128 f
S
) 64-f
S
oversampling 18 OVERDAC operation control DAC1 and DAC2 enabled 19 DAC[2:1]De-emphasis function control De-emphasis disabled 19 DM12De-emphasis sample rate selection 44.1 kHz 19 DMF[1:0]Audio data format control 24-bit, left-justified 20 FMT[2:0]Digital filter rolloff control Sharp rolloff 20 FLTZero-flag function select L-/R-channels independent 22 AZROOutput phase select Normal phase 22 DREVZero-flag polarity select High 22 ZREV
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Register Map
REGISTER DEFINITIONS
ATx[7:0] – Digital Attenuation Level Setting
PCM1742
SBAS176A – DECEMBER 2000 – REVISED APRIL 2005
The mode control register map is shown in Table 3 . Each register includes an index (or address) indicated by theIDX[6:0] bits.
Table 3. Mode Control Register MapIDX REGIS- B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0(B14–B8) TER
10h 16 0 IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 AT17 AT16 AT15 AT14 AT13 AT12 AT11 AT10
11h 17 0 IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 AT27 AT26 AT25 AT24 AT23 AT22 AT21 AT20
12h 18 0 IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 RSV
(1)
OVER RSV
(1)
RSV
(1)
RSV
(1)
RSV
(1)
MUT2 MUT1
13h 19 0 IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 RSV
(1)
DMF1 DMF0 DM12 RSV
(1)
RSV
(1)
DAC2 DAC1
14h 20 0 IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 RSV
(1)
RSV
(1)
FLT RSV
(1)
RSV
(1)
FMT2 FMT1 FMT0
15h 21 0 IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 RSV
(1)
RSV
(1)
RSV
(1)
RSV
(1)
RSV
(1)
RSV
(1)
RSV
(1)
RSV
(1)
16h 22 0 IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 RSV
(1)
RSV
(1)
RSV
(1)
RSV
(1)
RSV
(1)
AZRO ZREV DREV
(1) RSV: Reserved for test operation. It should be set to 0 during normal operation.
B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0REGISTER 16 0 IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 AT17 AT16 AT15 AT14 AT13 AT12 AT11 AT10
REGISTER 17 0 IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 AT27 AT26 AT25 AT24 AT23 AT22 AT21 AT20
where x = 1 or 2, corresponding to the DAC output V
OUT
L (x = 1) and V
OUT
R (x = 2).
Default value: 1111 1111b
Each DAC channel (V
OUT
L and V
OUT
R) includes a digital attenuator function. The attenuation level can be setfrom 0 dB to –63 dB, in 0.5-dB steps. Changes in attenuation levels are made by incrementing or decrementing,by one step (0.5 dB), for every 8/f
S
time interval until the programmed attenuator setting is reached. Alternatively,the attenuation level can be set to infinite attenuation, or mute. The attenuation data for each channel can be setindividually.
The attenuation level is calculated using the following formula:
Attenuation level (dB) = 0.5 (ATx[7:0]
DEC
– 255)
where: ATx[7:0]
DEC
= 0 through 255
for: ATx[7:0]
DEC
= 0 through 128, the attenuator is set to infinite attenuation.
The following table shows attenuator levels for various settings.ATx[7:0] DECIMAL VALUE ATTENUATOR LEVEL SETTING
1111 1111b 255 0 dB, no attenuation (default)1111 1110b 254 –0.5 dB1111 1101b 253 –1 dB:::1000 0011b 131 –62 dB1000 0010b 130 –62.5 dB1000 0001b 129 –63 dB1000 0000b 128 Mute:::0000 0000b 0 Mute
17
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MUTx – Soft Mute Control
OVER – Oversampling Rate Control
PCM1742
SBAS176A – DECEMBER 2000 – REVISED APRIL 2005
B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0REGISTER 18 0 IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 RSV OVER RSV RSV RSV RSV MUT2 MUT1
where x = 1 or 2, corresponding to the DAC output V
OUT
L (x = 1) and V
OUT
R (x = 2).
Default value: 0MUTx = 0 Mute disabled (default)MUTx = 1 Mute enabled
The mute bits, MUT1 and MUT2, are used to enable or disable the soft mute function for the corresponding DACoutputs, V
OUT
L and V
OUT
R. The soft mute function is incorporated into the digital attenuators. When mute isdisabled (MUTx = 0), the attenuator and DAC operate normally. When mute is enabled by setting MUTx = 1, thedigital attenuator for the corresponding output is decreased from the current setting to the infinite attenuationsetting by one attenuator step (0.5 dB) at a time for every 8/f
S
period. This provides a pop-free muting of theDAC output.
By setting MUTx = 0, the attenuator is increased by one step for every 8/f
S
period to the previously programmedattenuation level.
Default value: 0
System clock rate = 256 f
S
, 384 f
S
, 512 f
S
, or 768 f
S
OVER = 0 64× oversampling (default)OVER = 1 128× oversampling
System clock rate = 128 f
S
or 192 f
S
OVER = 0 32× oversampling (default)OVER = 1 64× oversampling
The OVER bit is used to control the oversampling rate of the delta-sigma DACs. The OVER = 1 setting isrecommended when the oversampling rate is 192 kHz (system clock is 128 f
S
or 192 f
S
).
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DACx – DAC Operation Control
DM12 – Digital De-Emphasis Function Control
DMF[1:0] – Sampling Frequency Selection for the De-Emphasis Function
PCM1742
SBAS176A – DECEMBER 2000 – REVISED APRIL 2005
B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0REGISTER 19 0 IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 RSV DMF1 DMF0 DM12 RSV RSV DAC2 DAC1
where x = 1 or 2, corresponding to the DAC output V
OUT
L (x = 1) or V
OUT
R (x = 2).
Default value: 0DACx = 0 DAC operation enabled (default)DACx = 1 DAC operation disabled
The DAC operation controls are used to enable and disable the DAC outputs, V
OUT
L and V
OUT
R. When DACx =0, the corresponding output generates the audio waveform dictated by the data present on the DATA pin. WhenDACx = 1, the corresponding output is set to the bipolar zero level, or V
CC
/2.
Default value: 0DM12 = 0 De-emphasis disabled (default)DM12 = 1 De-emphasis enabled
The DM12 bit is used to enable or disable the digital de-emphasis function. Refer to the Typical PerformanceCurves section of this data sheet for more information.
Default value: 00DMF[1:0] De-Emphasis Sample Rate Selection
00 44.1 kHz (default)01 48 kHz10 32 kHz11 Reserved
The DMF[1:0] bits select the sampling frequency used for the digital de-emphasis function when it is enabled.
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FMT[2:0] – Audio Interface Data Format
FLT – Digital Filter Rolloff Control
PCM1742
SBAS176A – DECEMBER 2000 – REVISED APRIL 2005
B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0REGISTER 20 0 IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 RSV RSV FLT RSV RSV FMT2 FMT1 FMT0
Default value: 101
The FMT[2:0] bits are used to select the data format for the serial audio interface. The following table shows theavailable format options.FMT[2:0] Audio Data Format Selection
000 24-bit standard format, right-justified data001 20-bit standard format, right-justified data010 18-bit standard format, right-justified data011 16-bit standard format, right-justified data100 I
2
S format, 16- to 24-bit101 Left-justified format, 16- to 24-bit (default)110 Reserved111 Reserved
Default value: 0FLT = 0 Sharp rolloff (default)FLT = 1 Slow rolloff
The FLT bit allows the user to select the digital filter rolloff that is best suited to their application. Two filter rolloffselections are available: sharp or slow. The filter responses for these selections are shown in the TypicalPerformance Curves section of this data sheet.
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DREV – Output Phase Select
ZREV – Zero-Flag Polarity Select
AZRO – Zero-Flag Function Select
PCM1742
SBAS176A – DECEMBER 2000 – REVISED APRIL 2005
B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0REGISTER 22 0 IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 RSV RSV RSV RSV RSV AZRO ZREV DREV
Default value: 0DREV = 0 Normal output (default)DREV = 1 Inverted output
The DREV bit is used to set the output phase of V
OUT
L and V
OUT
R.
Default value: 0ZREV = 0 Zero-flag pins HIGH at a zero detect (default)ZREV = 1 Zero-flag pins LOW at a zero detect
The ZREV bit allows the user to select the active polarity of zero-flag pins.
Default value: 0AZRO = 0 L-/R-channel independent zero flags (default) Pin 11: ZEROR; zero-flag output for R-channelPin 12: ZEROL; zero flag output for L-channelAZRO = 1 L-/R-channel common zero flag Pin 11: ZEROA; zero flag output for L-/R-channelPin 12: NA; not assigned
The AZRO bit allows the user to select the function of the zero-flag pins
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ANALOG OUTPUTS
0.1 1 10 100 1K 10K
0
−10
−20
−30
−40
−50
−60
Response (dB)
Frequency (kHz)
PCM1742
SBAS176A – DECEMBER 2000 – REVISED APRIL 2005
The PCM1742 includes two independent output channels: V
OUT
L and V
OUT
R. These are unbalanced outputs,each capable of driving 3.1 Vp-p typical into a 5-k Ωac-coupled load. The internal output amplifiers for V
OUT
L andV
OUT
R are biased to the dc common-mode (or bipolar zero) voltage, equal to V
CC
/2.
The output amplifiers include an RC continuous-time filter that helps to reduce the out-of-band noise energypresent at the DAC outputs, due to the noise shaping characteristics of the PCM1742 delta-sigma DACs. Thefrequency response of this filter is shown in Figure 26 . By itself, this filter is not enough to attenuate theout-of-band noise to an acceptable level for many applications; therefore, an external low-pass filter is required toprovide sufficient out-of-band noise rejection. Further discussion of DAC post-filter circuits is provided in theApplications Information section of this data sheet.
Figure 26. Output Filter Frequency Response
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V
COM
OUTPUT
−
R1R3
R2C1
C2
VCC
10 F
(a) Using VCOM to Bias a Single−Supply Filter Stage
(b) Using a Voltage Follower to Buffer VCOM When Biasing Multiple Nodes
(c) Using an INA134 for DC−Coupled Output
x = L or R 10 F
Filtered
Output
OPA337
2
3
1
AV=−1, where AV=R2
R1
VOUTx
VCOM
VCOM
PCM 1742
+
+
Buffered
VCOM
VCC
V+
V−
VCC
+
1/2
OPA2353
10 F
PCM1742
25kΩ
25kΩ
49.9kΩ
1%
25kΩ
25kΩ
SENSE
OUT
−IN
+IN
REF
x = L or R
10 F
To Low−Pass
Filter Stage
INA134
VOUTx
VCOM
PCM 1742
+
µ
µ
µ
µ
PCM1742
SBAS176A – DECEMBER 2000 – REVISED APRIL 2005
One unbuffered common-mode voltage output pin, V
COM
(pin 10), is brought out for decoupling purposes. Thispin is nominally biased to a dc voltage level equal to V
CC
/2. This pin can be used to bias external circuits. Anexample of using the V
COM
pin for external biasing applications is shown in Figure 27 .
Figure 27. Biasing External Circuits Using the V
COM
Pin
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ZERO FLAGS
Zero-Detect Condition
Zero Output Flags
PCM1742
SBAS176A – DECEMBER 2000 – REVISED APRIL 2005
Zero detection for each output channel is independent from the other. If the data for a given channel remains at a0 level for 1024 sample periods (or LRCK clock periods), a zero-detect condition exists for that channel.
Given that a zero-detect condition exists for one or more channels, the zero-flag pins for those channels are setto a logic-1 state. The zero-flag pins for each channel are ZEROL (pin 12) and ZEROR (pin 11). These pins canbe used to operate external mute circuits, or used as status indicators for a microcontroller, audio signalprocessor, or other digitally controlled function.
The active polarity of the zero-flag output can be inverted by setting the ZREV bit of control register 22 to 1. Thereset default is active-high output, or ZREV = 0.
The L-channel and R-channel common zero flag can be selected by setting the AZRO bit of control register 22to 1. The reset default is L-channel and R-channel independent zero flag, or AZRO = 0.
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APPLICATION INFORMATION
Connection Diagram
1
2
3
4
5
6
7
8
BCK
DATA
LRCK
DGND
VDD
VCC
VOUTL
VOUTR
16
15
14
13
12
11
10
9
SCK
ML
MC
MD
ZEROL/NA
ZEROR/ZEROA
VCOM
AGND
Post LPF
+3.3V
Regulator
Mode
Control
Zero Mute
Control
System Clock
PCM
Audio Data
Input
+5V VCC
L−Chan OUT
10 F
10µF
+
+
10µF
+
Post LPF
R−Chan OUT
µ
Power Supplies and Grounding
DAC Output Filter Circuits
PCM1742
SBAS176A – DECEMBER 2000 – REVISED APRIL 2005
A basic connection diagram is shown in Figure 28 , with the necessary power-supply bypassing and decouplingcomponents. Texas Instruments recommends using the component values shown in Figure 28 for all designs.
Figure 28. Basic Connection Diagram
The use of series resistors (22 Ωto 100 Ω) is recommended for the SCK, LRCK, BCK, and DATA inputs. Theseries resistor combines with stray PCB and device input capacitance to form a low-pass filter that reduceshigh-frequency noise emissions and helps to dampen glitches and ringing present on clock and data lines.
The PCM1742 requires a 5-V analog supply (V
CC
) and a 3.3-V digital supply (V
DD
). The 5-V supply is used topower the DAC analog and output-filter circuitry, while the 3.3-V supply is used to power the digital filter andserial interface circuitry. For best performance, the 3.3-V supply should be derived from the 5-V supply using alinear regulator, as shown in Figure 28 . The REG1117-3.3 from Texas Instruments is an ideal choice for thisapplication.
Proper power-supply bypassing is shown in Figure 28 . The 10- µF capacitors should be tantalum or aluminumelectrolytic.
Delta-sigma DACs use noise-shaping techniques to improve in-band signal-to-noise ratio (SNR) performance atthe expense of generating increased out-of-band noise above the Nyquist frequency, or f
S
/2. The out-of-bandnoise must be low-pass filtered in order to provide the optimal converter performance. This is accomplished by acombination of on-chip and external low-pass filtering.
Figure 27 (a) and Figure 29 show the recommended external low-pass active filter circuits for single- anddual-supply applications. These circuits are second-order Butterworth filters using a multiple feedback (MFB)circuit arrangement that reduces sensitivity to passive component variations over frequency and temperature. Formore information regarding MFB active filter design, see FilterPro™ MFB and Sallen-Key Low-Pass Filter DesignProgram (SBFA001 ), available from the TI Web site at http://www.ti.com.
25
www.ti.com
R1R3R4
R2C1
C2
VIN VOUT
OPA2134
2
3
1
R2
R1
AV≈−
PCB LAYOUT GUIDELINES
PCM1742
VCC
VDD
DGND
Return Path for Digital Signals
Analog
Ground
Digital
Ground
AGND
Output
Circuits
DIGITAL SECTION ANALOG SECTION
Digital Logic
and
Audio
Processor
Digital Power
+VDDGND
Analog Power
+5VA+VS
AGND
REG
−VS
PCM1742
SBAS176A – DECEMBER 2000 – REVISED APRIL 2005
APPLICATION INFORMATION (continued)
Figure 29. Dual-Supply Filter Circuit
Because the overall system performance is defined by the quality of the DACs and their associated analogoutput circuitry, high-quality audio operational amplifiers are recommended for the active filters. The OPA2353and OPA2134 dual operational amplifiers from Texas Instruments are recommended for use with the PCM1742;see Figure 27 (a) and Figure 29 .
A typical PCB floor plan for the PCM1742 is shown in Figure 30 . A ground plane is recommended, with theanalog and digital sections being isolated from one another using a split or cut in the circuit board. The PCM1742should be oriented with the digital I/O pins facing the ground plane split/cut to allow for short, direct connectionsto the digital audio interface and control signals originating from the digital section of the board.
Separate power supplies are recommended for the digital and analog sections of the board. This prevents theswitching noise present on the digital supply from contaminating the analog power supply and degrading thedynamic performance of the PCM1742. In cases where a common 5-V supply must be used for the analog anddigital sections, an inductance (RF choke, ferrite bead) should be placed between the analog and digital 5-Vsupply connections to avoid coupling of the digital switching noise into the analog circuitry. Figure 31 shows therecommended approach for single-supply applications.
Figure 30. Recommended PCB Layout
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PCM1742
VCC
VDD
DGND Output
Circuits
RF Choke or Ferrite Bead
Common
Ground
AGND
DIGITAL SECTION ANALOG SECTION
VDD
Power Supplies
+5V +VS
AGND
REG
−VS
Digital Logic
and
Audio
Processor
THEORY OF OPERATION
+
Z−1
8−Level Quantizer
+Z−1 +Z−1
−
+Z−1
+
+
8fS
64fS
PCM1742
SBAS176A – DECEMBER 2000 – REVISED APRIL 2005
APPLICATION INFORMATION (continued)
Figure 31. Single-Supply PCB Layout
The delta-sigma section of the PCM1742 is based on an 8-level amplitude quantizer and a fourth-order noiseshaper. This section converts the oversampled input data to 8-level delta-sigma format. A block diagram of the8-level delta-sigma modulator is shown in Figure 32 . This 8-level delta-sigma modulator has the advantage ofstability and clock jitter sensitivity over the typical one-bit (2-level) delta-sigma modulator. The combinedoversampling rate of the delta-sigma modulator and the interpolation filter is 64 f
S
.
The theoretical quantization noise performance of the 8-level delta-sigma modulator is shown in Figure 33 . Theenhanced multilevel delta-sigma architecture also has advantages for input clock-jitter sensitivity due to themultilevel quantizer, with the simulated jitter sensitivity, as shown in Figure 34 .
Figure 32. 8-Level Delta-Sigma Modulator
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0 1 2 3 4 5 6 7 8
0
−20
−40
−60
−80
−100
−120
−140
−160
−180
Amplitude (dB)
Frequency (fS)
QUANTIZATION NOISE SPECTRUM
(64x Oversampling) QUANTIZATION NOISE SPECTRUM
(128x Oversampling)
0 1 2 3 4 5 6 7 8
0
−20
−40
−60
−80
−100
−120
−140
−160
−180
Amplitude (dB)
Frequency (fS)
0 100 200 300 400 500 600
125
120
115
110
105
100
95
90
Dynamic Range (dB)
Jitter (ps)
JITTER DEPENDENCE (64x Oversampling)
PCM1742
SBAS176A – DECEMBER 2000 – REVISED APRIL 2005
THEORY OF OPERATION (continued)
Figure 33. Quantization Noise Spectrum
Figure 34. Jitter Sensitivity
28
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KEY PERFORMANCE PARAMETERS AND MEASUREMENT
Total Harmonic Distortion + Noise
S/PDIF
Receiver
Evaluation Board
f−3dB = 54kHz or 108kHz
PCM1742
DEM−DAI1742
2nd−Order
Low−Pass
Filter
Notch FilterBand Limit
HPF = 22Hz
LPF = 30kHz fC= 1kHzrms Mode0dBFS,
1kHz Sine Wave
S/PDIF
Output
Analyzer
and
Display
20kHz
Apogee
Filter
Digital
Generator
Dynamic Range
PCM1742
SBAS176A – DECEMBER 2000 – REVISED APRIL 2005
This section provides information on how to measure key dynamic performance parameters for the PCM1742. Inall cases, a System Two™ Cascade audio measurement system by Audio Precision™ or equivalent audiomeasurement system is used to perform the testing.
Total harmonic distortion + noise (THD+N) is a significant figure of merit for audio DACs, because it takes intoaccount both harmonic distortion and all noise sources within a specified measurement bandwidth. The true rmsvalue of the distortion and noise is referred to as THD+N. Figure 35 shows the test setup for THD+Nmeasurements.
For the PCM1742, THD+N is measured with a full-scale, 1-kHz digital sine wave as the test stimulus at the inputof the DAC. The digital generator is set to a 24-bit audio word length and a sampling frequency of 44.1 kHz or 96kHz. The digital generator output is taken from the unbalanced S/PDIF connector of the measurement system.The S/PDIF data is transmitted via a coaxial cable to the digital audio receiver on the DEM-DAI1742demonstration board. The receiver is then configured to output 24-bit data in either I
2
S or left-justified dataformat. The DAC audio interface format is programmed to match the receiver output format. The analog output isthen taken from the DAC post filter and connected to the analog analyzer input of the measurement system. Theanalog input is band-limited using filters resident in the analyzer. The resulting THD+N is measured by theanalyzer and displayed by the measurement system.
Figure 35. Test Setup for THD+N Measurements
Dynamic range is specified as A-weighted, THD+N measured with a –60-dBFS, 1-kHz digital sine wave stimulusat the input of the DAC. This measurement is designed to give a good indicator of the DAC performance given alow-level input signal.
The measurement setup for the dynamic range measurement is shown in Figure 36 and is similar to the THD+Ntest setup discussed previously. The differences include the band limit filter selection, the additional A-weightingfilter, and the –60-dBFS input level.
29
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S/PDIF
Receiver
Evaluation Board
PCM1742(1)
DEM−DAI1742
2nd−Order
Low−Pass
Filter
Notch FilterBand Limit
HPF = 22Hz
LPF = 22kHz fC= 1kHz
f−3dB = 54kHz or 108kHz
0% Full−Scale,
Dither Off (SNR)
−60dBFS,
1kHz Sine Wave
(Dynamic Range)
S/PDIF
Output
A−Weight
Filter(2)
rms Mode
Analyzer
and
Display
Digital
Generator
Idle-Channel Signal-to-Noise Ratio
PCM1742
SBAS176A – DECEMBER 2000 – REVISED APRIL 2005
KEY PERFORMANCE PARAMETERS AND MEASUREMENT (continued)
(1) Infinite-zero-detect mute disabled(2) Results without A-weighting are approximately 3 dB worse.
Figure 36. Test Setup Dynamic Range and SNR Measurements
The SNR test provides a measure of the noise floor of the DAC. The input to the DAC is all-0s data, and theDAC infinite-zero-detect mute function must be disabled (default condition at power up for the PCM1742). Thisensures that the delta-sigma modulator output is connected to the output amplifier circuit so that idle tones (ifpresent) can be observed and affect the SNR measurement. The dither function of the digital generator mustalso be disabled to ensure an all-0s data stream at the input of the DAC. The measurement setup for SNR isidentical to that used for dynamic range, with the exception of the input signal level (see the notes provided inFigure 36 ).
30
www.ti.com
REVISION HISTORY
PCM1742
SBAS176A – DECEMBER 2000 – REVISED APRIL 2005
DATE REV PAGE SECTION DESCRIPTION
Apr 2005 A – Global Changed to new format2 Absolute Maximum Ratings Changed values for power supply voltage, digital input voltage, leadtemperature, and package temperature. Added supply voltagedifference, V
CC
– V
DD
< 3 V.2 Electrical Characteristics Corrected maximum sampling frequency from 100 kHz to 200 kHz.Added new values of 128 f
S
and 192 f
S
for system clock frequency.2 Package/Ordering Information Table removed from page 2, reformatted, and appended at end ofdata sheet.2 Recommended Operating Con- New table added to data sheet.ditions6 Pin Assignments and Terminal Moved from page 4Functions9, 10 Typical Performance Curves In Figure 11 , corrected Y-axis scale and X-axis scale.In Figure 15 , corrected frequency from 96 kHz to 192 kHz on graphlabel.11 System Clock Input In Figure 19 , added 1/128 f
S
and 1/192 f
S
to note for clock cycletime.13, 14 Audio Data Formats and Timing In Figure 21 , Audio Data Input Formats, removed 32-f
S
availabilityfrom left-justified format. In Figure 22 , Audio Interface Timing,corrected specification for BCK pulse cycle time.17 Register Map For Table 3 , Mode Control Register Map, added note to explain theRSV table entry.18 Register Definitions For MUTx – Soft Mute Control, added description about in-crementing/decrementing attenuation level by one step for every8/f
S
period.25 Connection Diagram In Figure 28 , corrected capacitor polarity for V
DD
decouplingcapacitor.26, 27 PCB Layout Guidelines In Figure 30 and Figure 31 , deleted extraneous signal lines. InFigure 31 , changed leftmost block to Digital Logic and AudioProcessor.30 Dynamic Range Corrected parameters in test setup diagram, Figure 36 .
31
PACKAGE OPTION ADDENDUM
www.ti.com 16-Aug-2012
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
PCM1742E ACTIVE SSOP DBQ 16 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PCM1742E/2K ACTIVE SSOP DBQ 16 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PCM1742E/2KG4 ACTIVE SSOP DBQ 16 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PCM1742EG4 ACTIVE SSOP DBQ 16 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PCM1742KE ACTIVE SSOP DBQ 16 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PCM1742KE/2K ACTIVE SSOP DBQ 16 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PCM1742KE/2KG4 ACTIVE SSOP DBQ 16 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PCM1742KEG4 ACTIVE SSOP DBQ 16 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
PACKAGE OPTION ADDENDUM
www.ti.com 16-Aug-2012
Addendum-Page 2
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
PCM1742E/2K SSOP DBQ 16 2000 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
PCM1742KE/2K SSOP DBQ 16 2000 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 16-Aug-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
PCM1742E/2K SSOP DBQ 16 2000 367.0 367.0 35.0
PCM1742KE/2K SSOP DBQ 16 2000 367.0 367.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 16-Aug-2012
Pack Materials-Page 2
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