EP2SGX55EF1152C4N - ALTERA - Datasheet.Directory

LTC2911

2911f

TYPICAL APPLICATION

DESCRIPTION

Precision Triple Supply

Monitor with Power-Fail

Comparator

The LTC

2911 is a low power, high accuracy triple supply

monitor with a power-fail comparator. Reset timeout may

be selected with an external capacitor or set to an internally

generated 200ms.

The V1 pin monitors a 3.3V supply. The V2 pin monitors a

5V, 2.5V, 1.8V, 1.2V or adjustable supply. A third adjustable

input has a nominal 0.5V threshold allowing a resistive

divider to conﬁgure its threshold. All three comparators

feature a tight 1.5% threshold accuracy over the entire

operating temperature range while a glitch ﬁlter ensures

reliable reset operation.

A spare comparator can be conﬁgured to provide early

warning of a low voltage condition. It causes the PFO output

to pull low when the voltage of the PFI input falls below 0.5V,

allowing the power-fail threshold to be conﬁgured with

a resistive divider. A latch feature on the TMR pin allows

the RST output to be latched to prevent system resets,

simplifying margin testing.

FEATURES

APPLICATIONS

n Ultralow Voltage Reset: VCC = 0.5V Guaranteed

n Monitors Three Inputs Simultaneously:

3.3V, 5V, ADJ (LTC2911-1)

3.3V, 2.5V, ADJ (LTC2911-2)

3.3V, 1.8V, ADJ (LTC2911-3)

3.3V, 1.2V, ADJ (LTC2911-4)

3.3V, ADJ, ADJ (LTC2911-5)

n ±1.5% Threshold Accuracy

n Power-Fail Monitor

n RST State Can Be Held for Margining

n Low Supply Current: 30µA Typical

n Input Glitch Immunity

n Adjustable Reset Timeout Period

n Selectable Internal Timeout Saves Components

n Space Saving 8-Lead TSOT-23 and 3mm × 2mm DFN

Packages

n Network Servers

n Desktop and Notebook Computers

n Automotive and Industrial Electronics

RST Output Voltage With 10k Pull-Up to V1

LTC2911-2

76.8k

10k

3.3V

2.5V

1.0V

100k

576k

Li-Ion

BATTERY

STACK 100k

TMR

ADJ

RESET

LOBAT

RST

PFO

PFI

tRST = 200ms

2911 TA01a

GND

SYSTEM

LOGIC

DC/DC

CONVERTER

L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear

Technology Corporation. All other trademarks are the property of their respective owners.

Protected by U.S. Patents, including 6949965, 7292076.

V1 (V)

RST

(V)

0.5 1.5 2.5 3.5

2911 TA01b

5.50 1 2 3 4 4.5 5

V1 = V2

LTC2911

2911f

Supply Voltages

V1, V2 ................................................... –0.3V to 6.5V

Input Voltages

ADJ ....................................................... –0.3V to 6.5V

PFI ........................................................... –0.3V to 2V

TMR ............................................–0.3V to (V1 + 0.3V)

Output Voltages

RST, PFO .............................................. –0.3V to 6.5V

ORDER INFORMATION

ABSOLUTE MAXIMUM RATINGS

PFI 1

ADJ 2

TMR 3

GND 4

8 V2

7 V1

6 PFO

5 RST

TOP VIEW

TS8 PACKAGE

8-LEAD PLASTIC TSOT-23

TJMAX = 150°C, θJA = 195°C/W

TOP VIEW

GND

DDB PACKAGE

8-LEAD (3mm × 2mm) PLASTIC DFN

1V2

PFO

RST

PFI

ADJ

TMR

GND

TJMAX = 150°C, θJA = 76°C/W

EXPOSED PAD (PIN 9) IS GND, PCB CONNECTION OPTIONAL

PIN CONFIGURATION

(Notes 1, 2, 3)

Operating Temperature Range

LTC2911C ................................................ 0°C to 70°C

LTC2911I.............................................. –40°C to 85°C

LTC2911H .......................................... –40°C to 125°C

Storage Temperature Range ................... –65°C to 150°C

Lead Temperature (Soldering, 10 sec)

TSOT-23 ............................................................ 300°C

LTC2911 C DDB –1 #TRM PBF

LEAD FREE DESIGNATOR

PBF = Lead Free Finish Parts

None = Lead Based Finish Parts

TAPE AND REEL

#TR = Tape and Reel

#TRM = 500-Piece Tape and Reel

PRODUCT SELECTION

–1, –2, –3, –4, –5

See Product Selection Guide for Details

PACKAGE TYPE

DDB = 8-Lead (3mm × 2mm) Plastic DFN

TS8 = 8-Lead Plastic TSOT-23

TEMPERATURE GRADE

C = Commercial Temperature Range (0°C to 70°C)

I = Industrial Temperature Range (–40°C to 85°C)

H = Automotive Temperature Range (–40°C to 125°C)

PRODUCT PART NUMBER

Consult LTC Marketing for parts speciﬁed with wider operating temperature ranges.

Consult LTC Marketing for information on non-standard lead based ﬁnish parts.

For more information on lead free part marking, go to: http://www.linear.com/leadfree/

For more information on tape and reel speciﬁcations, go to: http://www.linear.com/tapeandreel/

LTC2911

2911f

PRODUCT SELECTION GUIDE

PART NUMBER PART MARKING PACKAGE DESCRIPTION V1 V2

LTC2911-1 LFHZ 8-Lead (3mm × 2mm) Plastic DFN 3.3V 5V

LTC2911-2 LFPG 8-Lead (3mm × 2mm) Plastic DFN 3.3V 2.5V

LTC2911-3 LFPJ 8-Lead (3mm × 2mm) Plastic DFN 3.3V 1.8V

LTC2911-4 LFPM 8-Lead (3mm × 2mm) Plastic DFN 3.3V 1.2V

LTC2911-5 LFPP 8-Lead (3mm × 2mm) Plastic DFN 3.3V ADJ

LTC2911-1 LTFJB 8-Lead Plastic TSOT-23 3.3V 5V

LTC2911-2 LTFPH 8-Lead Plastic TSOT-23 3.3V 2.5V

LTC2911-3 LTFPK 8-Lead Plastic TSOT-23 3.3V 1.8V

LTC2911-4 LTFPN 8-Lead Plastic TSOT-23 3.3V 1.2V

LTC2911-5 LTFPQ 8-Lead Plastic TSOT-23 3.3V ADJ

ELECTRICAL CHARACTERISTICS

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

VRT33 3.3V, 5% Reset Threshold V1 Input l3.036 3.086 3.135 V

VRT50 5V, 5% Reset Threshold V2 Input (LTC2911-1) l4.600 4.675 4.750 V

VRT25 2.5V, 5% Reset Threshold V2 Input (LTC2911-2) l2.300 2.338 2.375 V

VRT18 1.8V, 5% Reset Threshold V2 Input (LTC2911-3) l1.656 1.683 1.710 V

VRT12 1.2V, 5% Reset Threshold V2 Input (LTC2911-4) l1.104 1.122 1.140 V

VRTA ADJ Pin Threshold ADJ Input and V2 Input of

LTC2911-5

l492.5 500 507.5 mV

VPFT PFI Pin Threshold PFI Input Threshold (Falling) l492.5 500 507.5 mV

∆VPFT PFI Hysteresis l10 15 19 mV

VCC,OP Minimum Operating Voltage to Guarantee PFO

High (Note 3)

VPFI = 0.55V l2.3 V

IV1 V1 input Current (Note 4) V1 = 3.3V, V1 > V2 l10 30 80 µA

V1 = 3.3V, V1 < V2 l3 10 30 µA

IV2 V2 Input Current (Note 4) V2 = 5V (LTC2911-1)

V2 = 2.5V (LTC2911-2)

V2 = 1.8V (LTC2911-3)

V2 = 1.2V (LTC2911-4)

V2 = 0.55V (LTC2911-5)

C-Grade/I-Grade

H-Grade

±15

±40

µA

IADJ ADJ Input Current VADJ = 0.55V (C-Grade) (I-Grade)

VADJ = 0.55V (H-Grade)

±15

±40

IPFI PFI Input Current VPFI = 0.55V (C-Grade) (I-Grade)

VPFI = 0.55V (H-Grade)

±15

±40

ITMR(UP) TMR Pull-Up Current VTMR = 1V l–1.5 –2.2 –2.9 µA

ITMR(DOWN) TMR Pull-Down Current VTMR = 1V l1.5 2.2 2.9 µA

IPU RST, PFO Pull-Up Current VPIN = 0V l–20 –29 –40 µA

The l denotes the speciﬁcations which apply over the full operating

temperature range, otherwise speciﬁcations are at TA = 25°C. VADJ = 0.55V, VPFI = 0.55V, V1 = 3.3V unless otherwise noted. (Notes 2, 3)

LTC2911

2911f

ELECTRICAL CHARACTERISTICS

The l denotes the speciﬁcations which apply over the full operating

temperature range, otherwise speciﬁcations are at TA = 25°C. VADJ = 0.55V, VPFI = 0.55V, V1 = 3.3V unless otherwise noted. (Notes 2, 3)

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

tP,PF PFI Comparator Propagation Delay to PFO VPFI Driven Beyond Threshold

VPFT by More Than 10%

l8 30 80 µs

tUV V1, V2, ADJ Undervoltage Detect to RST Low VX Less Than Threshold VRTX by

More Than 10%

l8 30 80 µs

VOH RST, PFO Output Voltage High (Note 5) IRST = –1µA lV1 – 1 V1 V

VOL RST, PFO Output Voltage Low (Note 6) VCC = 0.5V, I = 5µA

VCC = 1V, I = 100µA

VCC = 3V, I = 2.5mA

0.01

0.10

0.15

0.30

tRST(EXT) Reset Timeout Period, External CTMR = 2.2nF l15 20 27 ms

tRST(INT) Reset Timeout Period, Internal VTMR = V1 l140 200 280 ms

VTMR(INT) Timer Internal Mode Threshold VTMR Rising lV1 – 0.40 V1 – 0.020 V1 – 0.10 V

∆VTMR(INT) Timer Internal Mode Hysteresis VTMR Falling l40 100 160 mV

VTMR(LATCH) Timer Latch Mode Threshold VTMR Falling l0.10 0.20 0.40 V

∆VTMR(LATCH) Timer Latch Mode Hysteresis VTMR Rising l40 75 160 mV

tP, LR Latch Release Propagation Delay to RST Low VTMR Rising, Step 0V to 0.6V l0.5 3 µs

tSU,MON Monitor Input Setup Time to Latch Enable (Note 7)

Monitor Input Setup Time to Latch Release

VTMR Falling, Step 0.6V to 0V

VTMR Rising, Step 0V to 0.6V

l2 ms

tHD, MON Monitor Input Hold Time to Latch Enable

Monitor Input Hold Time to Latch Release

VTMR Falling, Step 0.6V to 0V

VTMR Rising, Step 0V to 0.6V

l0 µs

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

Note 2: All currents into pins are positive; all voltages are referenced to

GND unless otherwise noted.

Note 3: The internal supply voltage (VCC) is generated from the greater of

the voltages on the V1 and V2 inputs. VCC = V1 for the LTC2911-5.

Note 4: Under typical operating conditions, quiescent current is drawn

from the greater of the voltages on the V1 and V2 inputs. For the

LTC2911-5 only V1 supplies the quiescent current.

Note 5: The RST and PFO output pins on the LTC2911 have internal pull-

ups to V1. However, for faster rise times or for VOH voltages greater than

V1, use an external pull-up resistor.

Note 6: The RST and PFO pull-down currents are derived from V1 and V2

except for the LTC2911-5 where the pull-down strength is derived only

from V1.

Note 7: tSU,MON is required to latch a low RST state and tSU,MON + tRST is

required to latch a high RST state.

LTC2911

2911f

TYPICAL PERFORMANCE CHARACTERISTICS

PFI Hysteresis vs Temperature

Reset Timeout Period vs

Temperature

RST, PFO Voltage Output Low

vs Sink Current

RST, PFO Voltage Output High

vs Source Current

RST, PFO Voltage Output High

vs VCC

RST, PFO Pin Source Current

vs V1

Normalized Reset and Power-Fail

Threshold Voltages vs Temperature

Quiescent Supply Current

vs Temperature

Allowable Glitch Duration

vs Overdrive

TEMPERATURE (°C)

–50

0.985

NORMALIZED THRESHOLD VOLTAGE (V/V)

0.990

0.995

1.000

1.005

0 50 100 125

2911 G01

1.010

1.015

–25 25 75

TEMPERATURE (°C)

–50

QUIESCENT SUPPLY CURRENT (µA)

0 50 100 125

2911 G02

–25 25 75

IV2 FOR LTC2911-1

OVERDRIVE (%)

0.1

GLITCH DURATION (µs)

300

400

500

1 10 100

2911 G03

200

100

TAMB (°C)

–50

HYSTERESIS (mV)

16.0

17.0

125

2911 G04

15.0

14.0 050 100

–25 25 75

18.0

15.5

16.5

14.5

17.5

TEMPERATURE (°C)

–50

140

TIMEOUT PERIOD (ms)

160

180

200

220

0 50 100 125

2911 G05

240

260

–25 25 75

INTERNAL

EXTERNAL

CTMR = 22nF

SINK CURRENT (mA)

VOLTAGE OUTPUT LOW (V)

0.2

0.4

0.6

0.8

1.0

510 15 20

2911 G06

25 30

–40°C

25°C

85°C

125°C

150°C

VCC = 3V

SOURCE CURRENT (µA)

VOLTAGE OUTPUT HIGH (V)

2.0

2.5

3.0

15 25

2911 G07

1.5

1.0

5 10 20 30 35

0.5

V1 = 3.135V, V2 = 5V FOR RST

VCC (V)

–1

VOLTAGE OUTPUT HIGH (V)

0.5 2.5 3.5

2911 G08

24.5 5.55

11.5 3 4

V1 = V2 = ADJ = PFI

10k PULL-UP TO VCC

RST FOR

LTC2911-1

RST FOR

LTC2911-2

LTC2911-3

LTC2911-4

LTC2911-5

PFO

V1 (V)

OUTPUT SOURCE CURRENT (µA)

100

2911 G09

010 5 6

234

RST

PFO

LTC2911

2911f

PIN FUNCTIONS

ADJ: Adjustable Voltage Monitor Input. Input to a voltage

monitor comparator with a 0.5V nominal threshold. Tie

to V1 if unused.

Exposed Pad (DFN Only): Exposed pad may be left open

or connected to device ground.

GND: Device Ground.

PFI: Power-Fail Voltage Monitor Input. Input to the power-

fail comparator with a 500mV threshold at the falling

edge and a 515mV threshold at the rising edge, giving

a 3% hysteresis for noise rejection. Tie to V1 or GND if

unused.

PFO: Power-Fail Logic Output. This pin asserts low when

the PFI input voltage is below its threshold and goes high

when the PFI input voltage is above its threshold. This pin

provides a weak pull-up current to V1. This current is typi-

cally 29µA at V1 = 3.3V. The pin can be pulled to voltages

higher than V1 by external pull-up resistors. PFO provides

an early warning signal of a system power failure.

RST: Reset Logic Output. This pin asserts low when any

of the V1, V2, or ADJ inputs are below their reset thresh-

olds. Pulls high when all the monitored inputs are above

their thresholds for longer than a timeout period. This pin

provides a weak pull-up current to V1. This current is typi-

cally 29µA at V1 = 3.3V. The pin can be pulled to voltages

higher than V1 by external pull-up resistors. The status of

RST can be latched by holding the TMR pin at GND.

TMR: Reset Timeout Control. Attach an external capacitor,

CTMR, to GND to set a reset timeout period of 9.4ms/nF. A

low leakage ceramic capacitor is recommended for timer

accuracy. A 2.2nF capacitor generates a 20ms timeout.

Leaving the TMR pin open without a capacitor generates

a minimum timeout of approximately 400µs which will

vary depending on the parasitic capacitance on the pin.

Tying this pin to V1 enables the internal 200ms timeout.

Pulling this pin to GND latches the reset state.

V1: 3.3V Monitor and Power Supply Input. V1 is an accu-

rate 3.3V, –5% undervoltage supply monitor. The internal

VCC is generated from the greater of the voltages at the

V1 and V2 inputs for the LTC2911-1/LTC2911-2/LTC2911-

3/LTC2911-4 options. The LTC2911-5 option always derives

its power supply from the V1 pin. Bypass this pin to GND

with a 0.1µF (or greater) capacitor for the LTC2911-2

through LTC2911-5.

V2: Voltage Monitor and Power Supply Input. V2 is a

–5% undervoltage supply monitor for a 5V, 2.5V, 1.8V

or 1.2V supply for the LTC2911-1/LTC2911-2/LTC2911-

3/LTC2911-4 options, respectively. Because the internal

VCC is generated from the greater of the V1 and V2 inputs

for these options, the V2 pin should be bypassed to GND

with a 0.1µF (or greater) capacitor for the LTC2911-1. The

V2 pin of the LTC2911-5 is a high impedance input with a

0.5V threshold, allowing the trip threshold of the monitored

supply to be conﬁgured with a resistive divider.

LTC2911

2911f

BLOCK DIAGRAM

–

V2 COMP

–

ADJ COMP

ADJ

*FOR OPTIONS LTC2911-1 THROUGH LTC2911-4 ONLY. **OMIT THE RESISTIVE DIVIDER FOR THE LTC2911-5.

0.5V

1.36M

RX**

231k**

263k

PFI PFO

–

V1 COMP

–

PFI COMP

ADJUSTABLE

PULSE

GENERATOR

LOW

VOLTAGE

PULL-DOWN

200ms

PULSE

GENERATOR

LATCH

VCC

GND

2911 BD

VCC

114k

V2*

TMR

RST

LOW

VOLTAGE

PULL-DOWN

POWER

DETECT

THREE-STATE

DECODE

LTC2911

MONITORED VOLTAGES

LTC2911-1 LTC2911-2 LTC2911-3 LTC2911-4 LTC2911-5

1.93M

2.5V

850k

1.8V

547k

1.2V

288k

ADJ

–

LTC2911

2911f

TIMING DIAGRAMS

Input Valid to Latch Enable

Setup and Hold Timing

tRST

VTMR(LATCH) VTMR(LATCH) +

∆VTMR(LATCH)

2911 TD04

t > tSU,MON

RST

ADJ, V1, V2

TMR

VRTX

tSU,MON tHD,MON

LATCH IN

NOTE: FOR THE LTC2911-5, V1 LOW RESETS RST TO A LOW STATE

–3% OVERDRIVE

INPUT RETURNING TO ABOVE VRTX

FOR t > tSU,MON, RST PIN STAYS HIGH

3% OVERDRIVE

MARGINING

POWER UP

Input Valid to Latch Release

Setup Timing

Input Invalid to Latch Enable

Setup and Hold Timing

Input Invalid to Latch

Release Setup Timing

TMR

RST

ADJ, V1, V2

tSU,MON

tUV

tHD,MON

LATCH IN

NOTE: FOR THE LTC2911-5, V1 LOW RESETS RST TO A LOW STATE

VTMR(LATCH)

VRTX

VTMR(LATCH) +

∆VTMR(LATCH)

t > tSU,MON

VRTX

–3% OVERDRIVE

2911 TD05

–3% OVERDRIVE

3% OVERDRIVE

MARGINING

INPUT RETURNING TO BELOW VRTX

FOR t > tSU,MON, RST PIN STAYS LOW

Undervoltage and Reset Timing

Latch Release to RST Low Timing

VRTX

tUV tRST

1.0V

2911 TD01

RST

TMR 0.4V

1.0V

2911 TD02

NOTE: ADJ FORCED LOW BEFORE TMR RELEASE

tP,LR

Power-Fail Timing

PFI VPFT

tP,PF tP,PF

1.0V 2911 TD03

PFO

Latching RST High

Latching RST Low

LTC2911

2911f

APPLICATIONS INFORMATION

The LTC2911 is a low power, high accuracy triple supply

monitor with power-fail comparator.

For the LTC2911-1,

LTC2911-2, LTC2911-3 and LTC2911-4 options, the V1

and V2 pins monitor two supplies. Their thresholds are

preset internally based on the option chosen. A resistive

divider connected to the ADJ pin conﬁgures the third

threshold. For the LTC2911-5, the V2 pin is a high imped-

ance adjustable input similar to the ADJ pin.

Reset timeout of the device may be selected with an external

capacitor or set to an internally generated 200ms. The ADJ,

V1 and V2 inputs must be valid (above their thresholds)

for longer than the reset timeout period before the RST

pin transitions high.

The power-fail comparator causes the PFO pin to pull

low when the PFI pin falls below 0.5V. A resistive divider

connected to the PFI pin conﬁgures the threshold of the

monitored voltage. The PFO output typically provides

an early warning of imminent power failure so that the

system may begin shutdown procedures such as supply

sequencing and/or storage of system state in nonvolatile

memory.

Power-Up

The LTC2911-1, LTC2911-2, LTC2911-3 and LTC2911-4

supervisors are powered from the V1 and V2 pins, auto-

matically selecting the pin with the higher potential. The

exception in the device family, the LTC2911-5, derives

its internal supply voltage (VCC) only from V1. When all

monitor inputs are above their thresholds, the quiescent

supply current drawn from VCC is typically 30µA (35µA

for the LTC2911-1). When the three monitor inputs (V1,

V2 and ADJ) rise above their thresholds, the appropriate

timeout delay begins, after which RST pulls to V1. Once

the PFI input rises above 515mV, the PFO output signals

high indicating that the supply or voltage monitored by

PFI is above threshold.

The LTC2911 uses proprietary low voltage drive circuitry

for the RST and PFO pins which holds them low with

VCC (the higher of V1 and V2) as low as 0.5V. This helps

prevent indeterminate voltages from appearing on the

outputs during power-up. For additional details refer to

the Output Pin Characteristics section.

When V1 and V2 are ramped simultaneously (for

LTC2911-1/LTC2911-2/LTC2911-3/LTC2911-4), the pull-

down current from the RST and PFO pins is about twice

the current available when V1 or V2 is grounded.

Power Down

On power-down, when the voltage monitored by the power-

fail comparator falls below the threshold conﬁgured by its

resistive divider, the PFO pin pulls low to provide an early

warning of imminent power failure. In a typically conﬁg-

ured system, this occurs before the supplies monitored

by V1, V2 or ADJ fall below their thresholds and cause

the RST pin to pull low. The RST and PFO pins maintain

a logic low output for VCC as low as 0.5V. See the Output

PIn Characteristics section for additional details.

Power-Fail Monitoring and PFO Signaling

The LTC2911’s PFI input monitors a voltage through a

resistive divider and compares it to the internal power-fail

threshold. When PFI drops below 0.50V (the power-fail

threshold) the PFO output pulls low to provide an early

warning of a low voltage condition. When the PFI pin rises

above 0.515V again, the PFO output signals high indicating

a valid supply condition.

The PFI input typically monitors the primary power supply

of a system. For example, the PFI pin may monitor the

input supply of a DC/DC converter or a Li-Ion battery stack

voltage. The PFO output typically provides a warning to

the system that the power supply is on the verge of fail-

ing so that it can prepare for a controlled shutdown. For

LTC2911

2911f

APPLICATIONS INFORMATION

example, the PFO pin may connect to a processor non-

maskable interrupt. When the battery pack voltage drops

below the shutdown threshold, as sensed at PFI, the PFO

pin pulls low to issue an interrupt. Next, the processor

begins shutdown procedures which may include supply

sequencing and/or storage/erasure of system state in

nonvolatile memory.

Threshold Accuracy

Specifying the minimum supply voltage for a system

requires the designer to consider three factors: minimum

supply voltage for proper operation, power supply toler-

ance, and supervisor reset threshold accuracy. Highly

accurate supervisors ease the design challenge by de-

creasing the overall voltage margin required for reliable

system operation.

The reset threshold band and the power supply tolerance

bands should not overlap. This prevents false or nuisance

resets when the power supply is actually within its speciﬁed

tolerance band. The actual reset threshold of supervisors

varies over a speciﬁed band. The LTC2911 supervisor

varies ±1.5% around its nominal threshold voltage over

temperature.

Figure 1 illustrates a typical 3.3V monitor. The LTC2911

has ±1.5% reset threshold accuracy. The nearest practical

supervisor trip point is the sum of power supply toler-

ance and the LTC2911 tolerance. So a “5%” threshold

is typically set to –6.5%, excluding resistor errors. Thus

for a 3.3V “5%” threshold, the practical supervisor trip

point is at 3.086V. The threshold is guaranteed to lie in

the band between 3.036V and 3.135V over the operating

temperature range. This 3.135V maximum threshold is at

the lower limit of supply tolerance (3.3V – 5%) to prevent

false tripping.

The system must operate reliably a little below 3.036V

(or 3.3V, –8%), or risk malfunction before a reset signal

is properly issued. A less accurate supervisor increases

the supply voltage tolerance requirements and the risk

of system malfunction. The LTC2911’s ±1.5% threshold

voltage speciﬁcation minimizes these requirements.

V1 and V2 Supply Monitors

All the LTC2911 options have a V1 threshold equal to

3.086V (3.3V – 6.5%). The V2 thresholds are 4.675V

(5V – 6.5%), 2.338V (2.5V – 6.5%), 1.683V (1.8V – 6.5%)

and 1.122V (1.2V – 6.5%) for options LTC2911-1,

3.3V

3.135V

±1.5%

THRESHOLD

BAND

3.086V

3.036V

REGION OF POTENTIAL MALFUNCTION

–5%

SUPPLY TOLERANCE

IDEAL

SUPERVISOR

THRESHOLD

MINIMUM

RELIABLE

SYSTEM

VOLTAGE

NOMINAL

SUPPLY

VOLTAGE

–6.5%

–8%

2911 F01

Figure 1. 1.5% Threshold Accuracy Improves System Reliability

LTC2911

2911f

LTC2911-2, LTC2911-3 and LTC2911-4 respectively. V2

of the LTC2911-5 option is a high impedance input with

a nominal 0.5V threshold.

Input Noise Filtering for RST

The V1, V2 and ADJ comparators have a response time that

is inversely proportional to overdrive. This characteristic

is illustrated in the Typical Performance Characteristics

as the graph Allowable Glitch Duration versus Overdrive.

The ADJ and the LTC2911-5’s V2 pin may be bypassed

with a capacitor to increase the ﬁltering in applications that

demand it. The resultant RC lowpass ﬁlter at the inputs will

further reject high frequency components, at the cost of

slowing the monitor’s response to fault conditions.

Resistor Selection for ADJ

The threshold of the supply monitored by the ADJ pin is

conﬁgured with an external resistive divider (R2 and R1)

connected between the supply and ground. The tap point

for the divider is connected to the adjustable input (ADJ)

which has a 0.5V threshold. (See Figure 2)

Normally, the user selects a trip voltage based on the sup-

ply and acceptable tolerances, and a value of R1 based on

current drawn. For a given current, I, R1 is given by:

R1=0.5V

To minimize errors arising from the ADJ input bias current,

a value of less than 100k is recommended for R1.

R2 is then chosen by:

R2 =R1•VTRIP_ ADJ

0.5V – 1











where, VTRIP_ADJ is the supply threshold when the ADJ

pin falls below its 0.5V threshold.

For accurate monitoring, the resistor tolerance should be

as small as possible. Resistor tolerance of 0.1% or some

trimming of components should be considered for R2/R1

in applications that require an accurate trip point.

Resistor Selection for PFI

An external resistive divider (R3 and R4) connected between

the supply and ground conﬁgures the threshold of the

supply monitored by the power-fail comparator. The tap

point for the divider is connected to the PFI input which

has a 0.5V threshold. (See Figure 3a)

Resistor selection follows a process similar to that for

the ADJ pin.

R3 is given by:

R3 =0.5V

APPLICATIONS INFORMATION

–

0.5V

2911 F02

ADJ

LTC2911

VTRIP

Figure 2. Setting the Adjustable (ADJ) Trip Point

LTC2911

2911f

Again, to minimize errors arising from the PFI input bias

current, a value of less than 100k is recommended for

R3.

R4 can be chosen either using the PFI falling threshold or

the PFI rising threshold.

For the falling edge threshold, use the equation:

R4 =R3 •VTRIP_ PFI_ FALL

0.5V – 1











Alternatively, for the rising edge threshold, use the

equation:

R4 =R3 •VTRIP_ PFI_ RISE

0.515V – 1











where VTRIP_PFI_FALL is the supply threshold when the PFI

pin falls below the 0.5V falling threshold, and VTRIP_PFI_RISE

is the supply threshold when the PFI pin rises above the

0.515V rising threshold.

Note that VTRIP_PFI_RISE is typically 3% above the

VTRIP_PFI_FALL due to the fact that the PFI 515mV rising

threshold is 3% above its 500mV falling threshold.

In applications that require an accurate trip point, the R4

and R3 resistors should have small tolerances.

Hysteresis for Power-Fail Comparator

The power-fail comparator uses a positive 3% accurate

hysteresis to combat spurious triggering while maintain-

ing accurate thresholds for both the rising and falling

edges. The nominal threshold is 500mV at the falling edge

and 515mV at the rising edge. The hysteresis prevents

oscillation when the monitored voltage passes through

the thresholds. If the PFI pin is connected to an external

resistive divider, it may be bypassed with a capacitor for

additional noise ﬁltering.

Increasing the Power-Fail Hysteresis

The power-fail comparator hysteresis can be increased by

adding two resistors, R5 and R6, as shown in Figure 3b.

When PFO is low, R5 sinks current from the center tap

of the R3 and R4 resistive divider. The upper threshold is

therefore given by:

VH=0.515V 1+R4

R3 +R4











When PFO is high, the series combination of R5 and R6

sources current into the center tap of the R3 and R4 resis-

tive divider. This leads to a lower threshold of:

VL=0.5V 1+R4









–3.3V – 0.5V

( )

R5+R6

The addition of R5 and R6 increases the hysteresis to:

VHYST =VH– VL

=0.015 1+R4









+0.515 R4









+3.3V – 0.5V

( )

R5+R6

APPLICATIONS INFORMATION

Figure 3a. Setting the Power-Fail (PFI) Trip Point

–

0.5V

2911 F03a

PFI

114k

PFO

LTC2911

VTRIP

Figure 3b. Increasing Power-Fail Hysteresis

–

0.5V

2911 F03b

PFI

PFO

LTC2911

R4 R6

VTRIP 114k

LTC2911

2911f

Resistor Selection for Combined Reset

and Power-Fail Divider

When the power-fail and reset signals are based on the

same supply, the PFI and ADJ inputs may be connected

to a single resistive divider formed from three resistors.

The conﬁguration is shown in Figure 4. For a given bias

current I, RA, RB and RC can be calculated from:

RA=0.5V

RB=RA•VTRIP_ PFI_ FALL

VTRIP _ ADJ

– 1











RC=RA•VTRIP_ ADJ

0.5V – 1









•VTRIP_ PFI_FALL

VTRIP_ ADJ











For example, consider monitoring a 5V, ±5% supply with

VTRIP_PFI_FALL = 4.5V and VTRIP_ADJ = 4V. The resulting

VTRIP_PFI_RISE is equal to 4.63V or 3% above VTRIP_PFI_FALL.

The maximum VTRIP_PFI_RISE should not overlap the mini-

mum power supply voltage level for PFO to deassert when

the supply recovers. Mathematically, after factoring in the

sum of the power supply tolerance and the LTC2911 toler-

ance, the VTRIP_PFI_RISE should be lower than 5V – 6.5%.

APPLICATIONS INFORMATION

See Threshold Accuracy section for more details. In the

design, if we wish to consume about 5µA in the divider,

RA = 100k. We then ﬁnd RB = 12.4k and RC = 787k (nearest

1% standard values).

Setting the Reset Timeout

RST goes high after the V1, V2 and ADJ inputs are above

their thresholds for a reset timeout period. Connecting

the TMR pin to V1 enables the internal 200ms timer.

To conﬁgure a different reset timeout period connect a

capacitor between the TMR pin and ground.

The following formula approximates the value of capacitor

needed for a particular timeout:

CTMR = tRST • 106.5 [pF/ms]

Leaving the TMR pin open with no external capacitor

generates a reset timeout of approximately 400µs. Larger

capacitors may be used to increase the timeout, but the

capacitor leakage current must not exceed 500nA. Other-

wise, the timer accuracy will be severely affected.

Suitable values of CTMR for a given tRST may be selected

from Figure 5.

–

0.5V

2911 F04

PFI

ADJ

LTC2911

VTRIP

Figure 4. Combining PFI/ADJ Monitoring of One Supply

with Three Resistors

Figure 5. External Timeout vs CTMR

CTMR (F)

10p

0.1

EXTERNAL TIMEOUT, tRST (ms)

10000

100p 1n 10n 100n 1µ

2911 F05

100

1000

LTC2911

2911f

APPLICATIONS INFORMATION

Reset Latch Mode

At any time, the TMR pin can be pulled low to latch the

RST pin status, overriding the reset operation. This feature

is useful when testing a system at supply voltages that

might otherwise cause the RST pin to assert.

If the RST pin is unasserted (high) before the latch is

enabled (by pulling the TMR pin low), RST will remain

unasserted after the TMR pin is released. This is true

provided that all reset monitor inputs are valid when TMR

releases, regardless of their state while the TMR pin was

low. However, if RST was unasserted before TMR was

pulled low, and now one of the inputs is invalid when TMR

is released, RST will assert after a tPL,LR propagation delay

(see Figure 6a). Conversely, if RST was asserted (low)

LATCH RELEASE

TMR

ADJ, V1, V2

t > tSU,MON

VTMR(LATCH)

VRTX

VTMR(LATCH) + ∆VTMR

1.0V

2911 F06a

tP,LR

RST

Figure 6a. Input Toggled Low While Timer Latched.

RST Goes Low tP,LR After Latch Release

TMR

LATCH RELEASE

VRTX

1.0V

2911 F06b

t > tSU,MON

tRST

ADJ, V1, V2

RST

VTMR(LATCH)

VTMR(LATCH) +

∆VTMR

Figure 6b. Input Toggled High While Timer Latched.

RST Goes High tRST After Latch Release

TMR

tRST

1.0V

2911 F06c

t < tRST

VTRM(LATCH)

VRTX

RST

ADJ, V1, V2

LATCH RELEASE

VTMR(LATCH) +

∆VTMR

Figure 6c. Timer Latched Before Timeout. After Latch Release,

RST Stays Low for a Full Timeout Before Going High

TMR

VTRX

1.0V

t > tHD,MON t > tSU,MON

2911 F06d

RECOUNTING

tRST

t > tRST

ADJ, V1, V2

RST

VTRM(LATCH)

LATCH RELEASE

MARGINING

VTMR(LATCH)

+ ∆VTMR

Figure 6d. Timer Latched After Timeout and RST High.

RST Stays High After Margining if Inputs are Restored

Before Release

before TMR was pulled low, and all inputs are valid when

TMR is released, RST will deassert (go high) after a tRST

delay (see Figures 6b and 6c). The RST pin remains as-

serted for a full tRST timeout after the TMR pin is released,

regardless of the state of the tRST timer before the latch

was enabled. The reset latch mode is useful for perform-

ing supply margining tests without resetting the system

(see Figure 6d).

At least 2.9µA of pull-up or pull-down current is required

to hold the TMR pin high or low to conﬁgure the internal

timer or reset latch mode. However, during the timer mode

transition, 100µA will be required to switch the TMR ﬂoat-

ing state to ground or V1. Connecting the TMR pin to any

voltage other than ground or V1 may have unpredictable

results.

LTC2911

2911f

Output Pin Characteristics

The DC characteristics of the RST and PFO pull-down

strength are shown in the Typical Performance Character-

istics. The circuits that drive the pull-down of the output

pins are powered by the internal VCC (the greater voltage

of V1 or V2). During power-up, a VCC of at least 0.5V en-

sures a low output state. The VOL voltage depends on the

current sunk by RST and PFO as shown in the Figure 8.

The open-drain nature of the RST and PFO pins allows for

wire-ORed connections. For example, multiple LTC2911s

may be wire-ORed to monitor additional supplies, or open-

drain logic can be connected to allow other conditions to

issue the reset and/or power-fail signals.

Output Pin Rise and Fall Time

The open-drain output pins (RST and PFO) contain weak

pull-up circuitry to V1. Use an external pull-up resistor

when the outputs need to pull beyond V1 and/or require

a faster rise time. Use external pull-up resistor values of

100k or less.

When output pins are externally pulled up to voltages higher

than V1, an internal network automatically protects the

weak pull-up circuitry from reverse currents. For a given

external load capacitance or CLOAD, the rise and fall times

can be estimated using Figure 9. The output pins have very

strong pull-down capability. With a 150pF load capacitance

the reset line can pull down in about 30ns.

During power-up, with a capacitor connected to the TMR

pin, the part remains in the reset latch mode described

above until the 2.2µA ﬂowing out of the TMR pin charges

the capacitor beyond the VTMR(LATCH) threshold. For this

reason, large capacitors will extend the RST timeout during

power-up. For example, if CTMR = 1µF, the LTC2911 leaves

the reset latch mode 90ms after power-up and the RST

pin goes high after a 9 second timeout.

Figures 7a and 7b show how the TMR pin can be driven

low to latch the state of the RST pin or ﬂoated or driven

high for external and internal reset timing, respectively.

TMR

2911 F07a

SYSTEM

LOGIC

TMR

2911 F07b

SYSTEM

LOGIC

Figure 7a. Open-Drain (or Three-State Buffer) Output.

Grounds TMR to Latch the State of RST. Floats TMR for

External Reset Timing

Figure 7b. V1 Powered Inverter. Grounds TMR

to Latch the State of RST. Drives TMR High for

Internal Reset Timing

APPLICATIONS INFORMATION

ISINK (µA)

VOLTAGE OUTPUT LOW (mV)

1200

1600

2000

2911 F08

800

400

02010 4030 60 70 90

50 100

VCC = 0.5V

Figure 8. Voltage Output Low vs ISINK at VCC = 0.5V

CLOAD (F)

10n

tFALL OR tRISE (s)

1µ

100µ

100n

10µ

10m

100p 1n 10n

2911 F09

10p

tRISE LTC2911-1

tFALL LTC2911-1

Figure 9. tRISE and tFALL vs CLOAD

LTC2911

2911f

TYPICAL APPLICATIONS

Triple Supply Monitor and Overtemperature Signal

LTC2911-1

100k

270k

*THERMISTOR MURATA NTC NCP15WM474J03RC TOLERANCE 5%.

NTC RESISTANCE IS 474k AT ROOM, 35.8k AT 85°C

**OPTIONAL BYPASS CAPACITOR FOR SUPPLY TRANSIENT NOISE FILTERING

2.05M

R31*

200k

VTRIP = 10.75V

3.3V

12V

3.3V

12V

PFI

RESET

OVERTEMP

RST

PFO

TMR

ADJ

CTMR

2.2nF

tRST = 20ms

TRIP TEMPERATURE = 90°C

RECOVER TEMPERATURE = 89°C

C1**

10nF

0.1µF

2911 TA02

GND

Quad Supply Monitor

LTC2911-2

100k

BAS119

383k

806k

3.3V

2.5V

12V

VTRIP = 4.53V

VTRIP = 10.5V

1.62M

PFI

RESET

RST

PFO

TMR

ADJ

CTMR

2.2nF

tRST = 20ms

0.1µF

2911 TA03

GND

LTC2911

2911f

48V Telecom UV/OV Monitor with Hysteresis

LTC2911-1

V1 V2

ADJ

2911 TA04

5.6V

RPU1

10k

RCC

27k

0.25W

0.1µF

16V

RST

PFO

TMR

PFI

GND

13.7k

M1: FDG6301N OR SIMILAR

VUV(RISING) = 43.3V

VUV(FALLING) = 38.7V

VOV(RISING) = 70.8V

VOV(FALLING) = 68.8V

1.87M

18.7k

R2B

169k

R2A

1.43M

VIN

36V TO 72V

TYPICAL APPLICATIONS

4-Cell NiMH Stack Voltage Monitor with Input Overvoltage Signaling

LTC2911-2

V1 V2

ADJ

tRST = 200ms

0.1µF

2911 TA05

LOBAT

RST

PFO

TMR

PFI

GND

102k

BATTERY LOW RESET THRESHOLD = 3.38V

OVERVOLTAGE TRIP THRESHOLD = 6.47V

OVERVOLTAGE RECOVER THRESHOLD = 6.28V

1.18M

100k

576k

1.2V

1N5817

1.2V

FROM

CHARGER +

4-Cell Alkaline Stack Voltage Monitor with Early Power-Fail Warning

LTC2911-2

V1 V2

ADJ

LOBAT

0.1µF

tRST = 200ms

2911 TA06

RESET

RST

PFO

TMR

PFI

GND

100k

POWER-FAIL FALLING THRESHOLD = 3.90V

POWER-FAIL RISING THRESHOLD = 4.02V

RESET THRESHOLD = 3.39V

665k

15k

1.5V

LTC2911

2911f

PACKAGE DESCRIPTION

TS8 Package

8-Lead Plastic TSOT-23

(Reference LTC DWG # 05-08-1637)

1.50 – 1.75

(NOTE 4)

2.80 BSC

0.22 – 0.36

8 PLCS (NOTE 3)

DATUM ‘A’

0.09 – 0.20

(NOTE 3) TS8 TSOT-23 0802

2.90 BSC

(NOTE 4)

0.65 BSC

1.95 BSC

0.80 – 0.90

1.00 MAX 0.01 – 0.10

0.20 BSC

0.30 – 0.50 REF

PIN ONE ID

NOTE:

1. DIMENSIONS ARE IN MILLIMETERS

2. DRAWING NOT TO SCALE

3. DIMENSIONS ARE INCLUSIVE OF PLATING

4. DIMENSIONS ARE EXCLUSIVE OF MOLD FLASH AND METAL BURR

5. MOLD FLASH SHALL NOT EXCEED 0.254mm

6. JEDEC PACKAGE REFERENCE IS MO-193

3.85 MAX

0.52

MAX

0.65

REF

RECOMMENDED SOLDER PAD LAYOUT

PER IPC CALCULATOR

1.4 MIN

2.62 REF

1.22 REF

LTC2911

2911f

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-

tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

PACKAGE DESCRIPTION

DDB Package

8-Lead Plastic DFN (3mm × 2mm)

(Reference LTC DWG # 05-08-1702 Rev B)

2.00 ±0.10

(2 SIDES)

NOTE:

1. DRAWING CONFORMS TO VERSION (WECD-1) IN JEDEC PACKAGE OUTLINE M0-229

2. DRAWING NOT TO SCALE

3. ALL DIMENSIONS ARE IN MILLIMETERS

4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE

MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE

5. EXPOSED PAD SHALL BE SOLDER PLATED

6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE

0.40 ± 0.10

BOTTOM VIEW—EXPOSED PAD

0.56 ± 0.05

(2 SIDES)

0.75 ±0.05

R = 0.115

TYP

R = 0.05

TYP

2.15 ±0.05

(2 SIDES)

3.00 ±0.10

(2 SIDES)

PIN 1 BAR

TOP MARK

(SEE NOTE 6)

0.200 REF

0 – 0.05

(DDB8) DFN 0905 REV B

0.25 ± 0.05

0.50 BSC

PIN 1

R = 0.20 OR

0.25 × 45°

CHAMFER

0.25 ± 0.05

2.20 ±0.05

(2 SIDES)

RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS

0.61 ±0.05

(2 SIDES)

1.15 ±0.05

0.70 ±0.05

2.55 ±0.05

PACKAGE

OUTLINE

0.50 BSC

LTC2911

2911f

Linear Technology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

(408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com

 LINEAR TECHNOLOGY CORPORATION 2010

LT 0910 • PRINTED IN USA

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LTC2911-3

76.8k

RESD*

10k

100k

1.43M

Li-Ion

*OPTIONAL RESISTOR FOR ADDED ESD PROTECTION

VTRIP = 3.37V

VTRIP = 0.88V

3.3V

1.8V

1.0V

249k

ADJ

RESET

LOBAT

RST

PFO

TMR VN2222

PFI

CTMR

2.2nF

0.1µF

RST_LATCH

SIGNAL HIGH

TO PERFORM

MARGINING

2911 TA07

GND

SYSTEM

LOGIC

DC/DC

CONVERTER