DATA SHEET NEC / MOS INTEGRATED CIRCUIT uPD43256B-X 256K-BIT CMOS STATIC RAM 32K-WORD BY 8-BIT EXTENDED TEMPERATURE OPERATION Description The pPD43256B-X is a high speed, low power, and 262, 144 bits (82,788 words by 8 bits) CMOS static RAM. This device is an extended-operating-temperature version of the #PD43256B (X version, -25 to +85 C}. And AandB versions are wide voltage operations. Battery backup is available. The pPD43256B-X is packed in 28-pin plastic TSOP (1). Features * 32,768 words by 8 bits organization Fast access time: 70, 85, 100, 120, 150 ns (MAX.) * Extended temperature (X version: Ta = 25 to +85 C} * Wide voltage range (A version: Vec = 3.0 to 5.5 V, B version: Vcc = 2.7 to 5.5 V) * 2V data retention * OE input for easy application . Operating Operating Standby Data retention Access time Note 1 Part number MAX supply voltage temperature supply current supply currentre ns (MAX.) Vv C uA (MAX.) uA (MAX.} uPD43256B-X 70, 85, 100 45to 5.5 25 to +85 50 2 * uPD43256B-AX g5Note2 109, 3.0 to 5.5 {2qNote 2 * uPD43256B-BX 100, 12QNote 2, 2.7 to 5.5 150Note 2 Notes 1. Ta< 40C, Veco =3V * 2. 100 ns (MAX.) (Veco = 4.5 to 5.5 V) * Version X (DIP, SOP, TSOP (I)) This data sheet can be applied to the version X (DIP, SOP, TSOP (I}}. Each version is identified with its lot number. Letter X in the fifth character position in a lot number signifies version X. NI EC JAPAN D43256B-X O000 x00co0 Lot number The information in this document is subject to change without notice. Document No. M11012EJ3VODS00 (3rd edition) The mark * shows major revised points. Date Published July 1997 N Printed in Japan NEC Comoraton 1995NEC uPD43256B-X Ordering Information O : O : Part numb Pack Access time oy walt t eerate Remark emar art number ackage ns (MAX.) supply voltage empera ure Vv Cc uPD43256BGW-70X-3JL 28-pin plastic 70 4.5 to 5.5 25 to +85 #PD43256BGW-a5x-9UL | TSOP () 85 (8 x 13.4 mm) uPD43256BGW-10X-9JL 100 (Normal bent) HPD43256BGW-A85X-3JL 85 3.0 to 5.5 A version uPD43256BGW-A10X-9JL 100 BPD43256BGW-A12X-9JL 120 HPD43256BGW-B10X-9JL 100 2.7 to 5.5 B version uPD43256BGW-B12X-9JL 120 BPD43256BGW-B15X-9JL 150 HPD43256BGW-70X-9KL | 28-pin plastic 70 4.5 to 5.5 uPD43256BGW-85X-9KL | TSOP (1) 85 (8 x 13.4 mm) HPD43256BGW-10X-9KL 100 (Reverse bent) uPD43256BGW-A85X-9KL 85 3.0 to 5.5 A version HPD43256BGW-A10X-9KL 100 uPD43256BGW-A12X-9KL 120 uPD43256BGW-B10X-9KL 100 2.7 to 5.5 B version BPD43256BGW-B12X-9KL 120 uPD43256BGW-B15X-9KL 150NEC uPD43256B-X Pin Contiguration (Marking Side) 28-pin plastic TSOP (I) (8 x 13.4mm) (Normal bent) [vPD43256BGW-X-9JL] OE 1 Aia Att 2 O cs Ag 3 O08 AB 4 \O7 A183 5 O08 WE 6 VO5 Voc 7 VO4 Al4 8 GND Al2 g 03 AZ iT) Oz AG 1 vot A5 12 AQ Ad 13 O Al A3 14 A2 28-pin plastic TSOP (I) (8 x 13.4mm) (Reverse bent) [vPD43256BGW-X-9KL] A10 OQ 1 OE cs 2 Alt oe 3 Ag VO7 4 A&B O68 5 AI3 VO5 6 WE VO4 QO 7 Voc GND 8 Al4 03 g Al2 Oz 10 A? vor 11 AG AQ 12 AS At 13 A4 A2 14 A3 AO -A14 : Address Input 01 - /O8: Data Input/Output cs : Chip Select Input OQ WE : Write Enable Input OE : Output Enable Input Vcc : Power Supply GND : GroundNEC Block Diagram AQ Al4 uPD43256B-X Vor | VO8 a/ controller 2 5 Z 8 2 8 Memory cell array 3 GC 262,144 bits 3 5 =z cc \ Input data DS Sense/Switch > Cutan gala A Column decoder TT Address buffer ry v9 a Dee L) WE = Veo GND Truth Table cs OE WE Mode 0 Supply current H x x Not selected High impedance Ise L H H Output disable loca L x L Write Din L L H Read Dout Remark x: Dont careNEC uPD43256B-X Electrical Characteristics Absolute Maximum Ratings Parameter Symbol Rating Unit Supply voltage Vcc -0,5Note to 47.0 Vv Input/Output voltage Vt 0.5Note to Veco + 0.5 Vv Operating ambient temperature Ta 25 to +85 C Storage temperature Tstg 55 to +125 c Note -3.0 V (MIN.) (Pulse width 50 ns) Caution Exposing the device to stress above those listed in absolute maximum ratings could cause permanent damage. The device is not meant to be operated under conditions outside the limits described in the operational sections of this characteristics. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Recommended Operating Conditions HPD43256B-X | wPD43256B-AX | uPD43256B-BXxX Parameter Symbol Unit MIN. MAX. MIN. MAX. MIN. MAX. Supply voltage Voc 4.5 5.5 3.0 5.5 2.7 5.5 Vv High level input voltage Vin 2.4 Vec + 0.5 2.4 Vec + 0.5 2.4 Veo + 0.5 Vv Low level input voltage Vit -0,aNete) 40.6 |-o.3Nete! 40.4 |-a.gNote) 40.4 Vv Operating ambient temperature Ta -25 +85 -25 +85 -25 +85 CS Note -3.0 V (MIN.) (Pulse width 50 ns}NEC uPD43256B-X * DC Characteristics (Recommended operating conditions unless otherwise noted) (1/2) uPD43256B-X Parameter Symbol Test condition Unit MIN. TYP. MAX. Input leakage current lu Vin = 0 V to Voc -1.0 +1.0 HA Output leakage current ILe Vio = 9 V to Voc -1.0 +1.0 BA OE = Viv or CS = Vin or WE = ViL Operating supply current loca CS = Vi, uPD43256B-70X 45 mA lvo = 0 mA, uPD43256B-85X 45 Minimum cycle time PD43256B-10X 40 locaz CS = Vi, lio =OmA 15 Iccas =| CS 0.2 V, Cycle = 1 MHz, 15 lvo=OmA, Vi. <= 0.2 V, Vip > Vcc -0.2V Standby supply current Isp CS = Vn 3 mA Ise1 CS 2Vcc-0.2V 1.0 50 BA High level output voltage Vout loH = 1.0 mA 2.4 Vv Vone loH = 0.1 mA Voc -0.5 Low level output voltage VoL lo. = +2.1 mA 0.4 Vv Remarks 1. Vin: Input voltage 2. These DC characteristics are in common regardless of package types.NEC uPD43256B-X DC Characteristics (Recommended operating conditions unless otherwise noted) (2/2) uPD43256B-AX | pPD43256B-BX Parameter Symbol Test conditions MIN. TYP. MAX.| MIN. TYP. MAX. Unit Input leakage Iu Vin = 0 V to Vcc -1.0 +1.0]-1.0 41.0] BA current VO leakage ILo Vio = 0 V to Vcc -1.0 +1.0]-1.0 41.0] BA current GS = Viw or WE = Vii or OE = Vin Operating supply | Icca1 CS = Vu, #PD43256B-A85X 45 - mA current lve =O mA u#PD43256B-A10X 40 - Minimum cycle time uPD43256B-A12x 40 _ #PD43256B-B10X - 40 #PD43256B-B12X - 40 #PD43256B-B15X - 40 | Voco< 3.3 V - 25 Iccaz CS = Vit, lvo = OmA 15 15 | Vec< 3.3 V 10 Iccas CS < 0.2 V, Cycle = 1 MHz, 15 15 lwo =QmA, Vi <= 0.2 V, Vin = Voo- 0.2 V | Veco 3.95 V _ 10 Standby supply | Ise CS = Vi 3 3 mA current | VocS 3.3 V - 2 Isat CS > Voc -0.2V 1.0 | 50 1.0] 50 | gA | Veco 23.3 V - 25 High level output | Vou1 loH = 1.0 mA, Vcc 2 4.5 V 2.4 2.4 Vv voltage lon = -0.5 mA, Veo < 4.5 V 2.4 2.4 Vore loH = 0.02 mA Veo - 0.1 Veo - 0.1 Low level output | Vor lo. = 2.1 MA, Vcc 2 4.5 V 0.4 0.4 Vv voltage lo. = 1.0 mA, Voo< 4.5 V 0.4 0.4 Vout lo. = 0.02 mA 0.1 0.1 Remarks 1. Vin: Input voltage 2. These DG characteristics are in common regardless of package types. Capacitance (Ta = 25 C, f = 1 MHz) Parameter Symbol Test conditions MIN. TYP. MAX. Unit Input capacitance Cin Vin=OV 5 pF Input/Output capacitance Cre Vio = OV a pF Remarks 1. Vin: Input voltage 2. These parameters are periodically sampled and not 100 % tested.NEC uPD43256B-X AC Characteristics (Recommended operating conditions unless otherwise noted) AC Test Conditions Input waveform (Rise/fall time = 5 ns) Input pulse levels 06 Vie 2.4V: pPD43256B-X O4Vie 24 V: wPD43256B-AX, 43256B-BX x 15V Test points Output waveform wv x 15V _ Test points ev Output load HPD43256B-AX, 43256B-BX ; 1TTL + 50 pF HPD43256B-X : AC characteristics with notes should be measured with the output load shown in Figure 1 and Figure 2. Figure 1 (For taa, tacs, toe, ton) +5 V 1.8k2 VO (Output) ~ ) 990 = 100 pF Figure 2 (For tcnz, tciz, toHz, toLz, twHz, tow) +5 V 1.8kQ VO (Output) O 990 2 _ 5 pF CL TTF Remark Cu includes capacitances of the probe and jig, and stray capacitances.NEC uPD43256B-X Read Cycle (1/3) Veco? 4.5V uPD43256B-10X uPD43256B- Parameter Symbol pPD43256B-70X pPD43256B-85X ABSX/A1OX/A12X% | Unit | Condition uPD43256B- B10X/B12X/B15X MIN. MAX. MIN. MAX. MIN. MAX. Read cycle time tac 70 85 100 ns Address access time taa 70 85 100 ns | Note 1 CS access time tacs 70 85 100 ns OE access time toe 35 40 50 ns Outpul held from address change tou 10 10 10 ns CS to output in low impedance toLz 10 10 10 ns | Note 2 OE to output in low impedance toLz 5 5 5 ns CS to output in high impedance toHz 30 30 35 ns OE to output in high impedance touz 30 30 35 ns Notes 1. See the output load shown in Figure 1 except for uwPD43256B-AX, 43256B-BX. 2. See the output load shown in Figure 2 except for uzPD43256B-AX, 43256B-BX. Read Cycle (2/3) Veco > 3.0V Parameter Symbol | pPD43256B-A85X | pPD43256B-A10X | gPD43256B-A12X | Unit | Condition MIN. MAX. MIN. MAX. MIN. MAX. Read cycle time tac 85 100 120 ns Address access time {aa a5 100 120 ns Note CS access time tacs 85 100 120 ns OE access time toe 50 60 60 ns Output hold from address change tou 10 10 10 ns CS to output in low impedance toLz 10 10 10 ns OE to output in low impedance toiz 5 5 5 ns CS to output in high impedance tcHz 35 35 40 ns OE to output in high impedance touz 35 35 40 ns Note Loading condition is 1TTL + 50 pF.NEC uPD43256B-X * Read Cycle (3/3) Voc > 2.7 V Parameter Symbol | uPD43256B-B10X | uwPD43256B-B12X | wPD43256B-B15X | Unit | Concition MIN. MAX. MIN. MAX. MIN. MAX. Read cycle time tro 100 120 150 ns Address access time taa 100 120 150 ns Note CS access time tacs 100 120 150 ns OE access time toe 60 60 70 ns Output hold from address change tou 10 10 10 ns CS to output in low impedance toLz 10 10 10 ns OE to output in low impedance toiz 5 5 5 ns CS to output in high impedance tcHz 35 40 50 ns OE to output in high impedance toHz 35 40 50 ns Note Loading condition is 1TTL + 50 pF. Read Cycle Timing Chart tac \ Address (Input) . taa tony tacs os imu \\\\\ SII / I /// touz toHz | toe toHz toiz 1/0 (Output) ~ ~~ Highimeedane ___ {-( Data out XY eee Remark In read cycle, WE should be fixed to high level. 10NEC uPD43256B-X Write Cycle (1/3) Vec> 4.5 V uPD43256B-10X uPD43256B- Parameter Symbol uPD43256B-70X uPD43256B-85X ABSX/A1OX/A12X | Unit | Condition uPD43256B- B10X/B12X/B15X MIN. MAX. MIN. MAX. MIN. MAX. Write cycle time two 70 85 100 ns CS to end of write tow 60 70 80 ns Address valid to end of write taw 60 70 80 ns Write pulse width twe 55 60 70 ns Data valid to end of write tow 30 35 40 ns Data hold time tou 5 5 5 ns Address setup time tas 0 0 0 ns Write recovery time twr 0 0 0 ns WE to output in high impedance twuz 30 30 35 ns Note Output active from end of write tow 5 5 5 ns Note See the output load shown in Figure 2 except for wPD43256B-AX, 43256B-BX. Write Cycle (2/3) Veco 2 3.0 V Parameter Symbol | uPD43256B-A85xX | uzPD43256B-A10X | uPD43256B-A12X| Unit | Gandition MIN. MAX. MIN. MAX. MIN. MAX. Write cycle time twe 85 100 120 ns GS to end of write tow 70 70 90 ns Address valid to end of write taw 70 70 90 ns Write pulse width twe 60 60 80 ns Data valid to end of write tow 60 60 70 ns Data hold time tou 5 5 5 ns Address setup time tas 0 0 0 ns Write recovery time twr 0 0 0 ns WE to output in high impedance twHz 35 35 40 ns Note Output active from end of write tow 5 5 5 ns Note Loading condition is 1TTL + 50 pF. 11NEC uPD43256B-X * Write Cycle (3/3) Veo > 2.7 V Parameter Symbol |#PD43256B-B10X | uPD43256B-B12X| yPD43256B-B15X | Unit | Condition MIN. MAX. MIN. MAX. MIN. MAX. Write cycle time two 100 120 150 ns CS to end of write tow 70 90 100 ns Address valid to end of write taw 70 90 100 ns Write pulse width twe 60 80 90 ns Data valid to end of write tow 60 70 80 ns Data hold time toH 5 5 5 ns Address setup time tas 0 0 0 ns Write recovery time twr 0 0 0 ns WE to output in high impedance twuz 35 40 40 ns Note Output active from end of write tow 5 5 5 ns Note Loading condition is 1TTL + 50 pF. Write Cycle Timing Chart 1 (WE Controlled) two Address (Input) x x tow . 8 (input) \\\\X IIIS TI / taw . tas . twe __twR WE (Input) Y\ \ } tow twHz tow High . I/O (Input/Output) Indefinite data out ae Datain 4 impe- Indefinite data out Cautions 1. CS or WE should be fixed to high level during address transition. * 2. When I/O pins are in the output state, do not apply to the I/O pins signals that are opposite in phase with output signals. Remarks 1. Write operation is done during the overlap time of a low level CS and a low level WE. 2. When WE is at low level, the I/O pins are always high impedance. When WE is at high level, read operation is executed. Therefore OE should be at high level to make the I/O pins high impedance. 3. If CS changes to low level at the same time or after the change of WE to low level, the I/O pins will remain high impedance state. 12NEC uPD43256B-X Write Cycle Timing Chart 2 (CS Controlled) twe Address (Input) x x tas tow . CS (Input) AY x [ taw ~ twe {wR \ tow ~ ton ~ VO (Input) =~ 77 ao Pe ---- Data In High impedance Cautions1. CS or WE should be fixed to high level during address transition. 2. When I/O pins are in the output state, do not apply to the I/O pins signals that are opposite in phase with output signals. Remark Write operation is done during the overlap time of a low level CS and a low level WE. 13NEC uPD43256B-X Low Vcc Data Retention Characteristics (Ta = 25 to +85 C) Parameter Symbol Test conditions MIN. TYP. MAX. Unit Data retention supply voltage Vocor | CS 2 Vcc-0.2V 2.0 5.5 Vv Data retention supply current Iccor Veo = 3.0 V, CS > Voc -O.2V 0.5 2QNote HA Chip deselection to data tcor 0 ns retention mode Operation recovery time tr 5 ms Note 2 HA (Ta < 40 C), 7 HA (TA< 70 C) Data Retention Timing Chart tcp | Data retention mode tr Vin (MIN.} Vocpr 7 CS>Vcc-O.2V Vie (MAX) 0 Penn n nnn nnn an cnc en ances esas aes cnncs Note A Version: 3.0 V, B Version: 2.7 V Remark The other pins (address, OE, WE, I/Os) can be in high impedance state. 14NEC Package Drawings 28PIN PLASTIC TSOP (1) (8x13.4) 1 KL 228 oo oo oo a + SS =x I s oo SS +4 oo 140 15 P | J uPD43256B-X detail of lead end Ci K NOTE ITEM MILLIMETERS INCHES (1) Each lead centerline is located within 0.08 mm (0.003 inch) of A 8.00.1 0.31540.004 its true position (T.P.) at maximum material condition. B 0.6 MAX. 0.024 MAX. Cc 0.55 (T.P.) 0.022 (T.P.) (2) "A" excludes mold flash. {Includes mold flash : 8.4mm MAX. 10.08 <0.331 inch MAX.>) D 0.22"5'07 ~9.009+0.003 G 1.0 0.039 H 12.44+0.2 0.488+0.008 +0.004 11.840.1 0.46549 .008 +0.009 J 0.820.2 0.03175 bos K 0.145+9-025 9.0060.001 +0.004 L 0.540.1 0.02075 O05 M 9.08 9.003 N 0.10 0.004 +0.008 P 13.440.2 0.528" o09 Q 0.140.05 0.0044+0.002 o Oo R 347 3*7 Ss 1.2 MAX. 0.048 MAX. P28GW-55-9JL-1 15NEC uPD43256B-X 28PIN PLASTIC TSOP (I ) (8x13.4) 4 t 28 detail of lead end 7 rkK [ON | | H L ft __ im | J P NOTE ITEM MILLIMETERS INCHES {1} Each lead centerline is located within 0.08 mm (0.003 inch) of A 8.0+0.1 0.315+0.004 its true position (T.P.) at maximum material condition. B 0.6 MAX. 0.024 MAX. c 0.55 (T.P.) 0.022 (T.P) (2) "A" excludes mold flash. (Includes mold flash : 8.4mm MAX. 40.08 <0.331 inch MAX.>) D 0.227507 *.009+0.003 G 1.0 0.039 H 12.440.2 0.488+0.008 +0.004 11.820.1 0.465+0-008 +0.009 J 0.840.2 0.03175 508 0.025 K 0.145*0-o72 0.006+0.001 +0.004 L 0.5+0.1 0.02075 005 M 0.08 0.003 N 0.10 0.004 +0.008 P 13.440.2 0.52875 G09 Q 0.140.05 0.0044+0.002 o+7 o+7? R are are s 1.2 MAX. 0.048 MAX. P28GW-55-9KL-1 16NEC uPD43256B-X Recommended Soldering Conditions Please consult with our sales offices for soldering conditions of the pPD43256B-x. Types of Surface Mount Device HPD43256BGW-X-3JL : 28-pin Plastic TSOP (I) (8 x 13.4 mm) (Normal bent) HPD43256BGW-X-9KL: 28-pin Plastic TSOP (I) (8 x 13.4 mm) (Reverse bent) 17NEC uPD43256B-X [MEMO] 18NEC uPD43256B-X NOTES FOR CMOS DEVICES @) PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When itis dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. (2) HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS device behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to Vop or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. @) STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Produc- tion process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, |/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed imme- diately after power-on for devices having reset function. 19NEC uPD43256B-X [MEMO] No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEG Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. NE Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. While NEG Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. NEG devices are classified into the following three quality grades: "Standard", "Special", and "Specific. The Specific quality grade applies only to devices developed based ona customer designated "quality assurance program" for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.}, traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance. Anti-radioactive design is not implemented in this product. M4 96.5