HN29V102414T-50H - Renesas Technology / Hitachi Semiconductor

Regarding the change of names mentioned in the document, such as Hitachi

Electric and Hitachi XX, to Renesas Technology Corp.

The semiconductor operations of Mitsubishi Electric and Hitachi were transferred to Renesas

Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog

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corporate statement, no changes whatsoever have been made to the contents of the document, and

these changes do not constitute any alteration to the contents of the document itself.

Renesas Technology Home Page: http://www.renesas.com

Renesas Technology Corp.

Customer Support Dept.

April 1, 2003

To all our customers

Cautions

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HN29V102414T-50H

1G AND type Flash Memory

More than 32,113-sector (542,581,248-bit) × 2

ADE-203-1335A (Z)

Rev. 1.0

Apr. 5, 2002

Description

The Hitachi HN29V102414T-50H is a CMOS Flash Memory with AND type multi-level memory cells. It

has fully automatic programming and erase capabilities with a single 3.0 V power supply. The functions are

controlled by simple external commands. To fit the I/O card applications, the unit of programming and erase

is as small as (2048 + 64) bytes. Initial available sectors of HN29V102414T-50H are more than 64,226 (98%

of all sector address) and less than 65,536 sectors.

Features

• On-board single power supply (VCC): VCC = 2.7 V to 3.6 V

• Organization

 AND Flash Memory: (2048 + 64) bytes × (More than 32,113 sectors) × 2

 Data register: (2048 + 64) bytes × 2

• Multi-level memory cell

 2 bit/per memory cell

• Automatic programming

 Sector program time: 1.0 ms (typ)

 System bus free

 Address, data latch function

 Internal automatic program verify function

 Status data polling function

• Automatic erase

 Single sector erase time: 1.0 ms (typ)

 System bus free

 Internal automatic erase verify function

 Status data polling function

HN29V102414T-50H

• Erase mode

 Single sector erase ((2048 + 64) byte unit)

• Fast serial read access time:

 First access time: 50 µs (max)

 Serial access time: 50 ns (max)

• Low power dissipation:

 ICC1 = 2 mA (typ) (Read) (1-chip operation)

ICC1 = 4 mA (typ) (Read) (2-chip operation)

 ICC2 = 20 mA (max) (Read) (1-chip operation)

ICC2 = 40 mA (max) (Read) (2-chip operation)

 ISB2 = 50 µA (max) (Standby) (1-chip operation)

ISB2 = 100 µA (max) (Standby) (2-chip operation)

 ICC3/ICC4 = 40 mA (max) (Erase/Program) (1-chip operation)

ICC3/ICC4 = 80 mA (max) (Erase/Program) (2-chip operation)

 ISB3 = 20 µA (max) (Deep standby) (1-chip operation)

ISB3 = 40 µA (max) (Deep standby) (2-chip operation)

• The following architecture is required for data reliability.

 Error correction: more than 3-bit error correction per each sector read

 Spare sectors: 1.8% (579 sectors)/chip (min) within usable sectors

Ordering Information

Type No. Available sector Package

HN29V102414T-50H More than 64,226 sectors 12.0 × 20.00 mm2 0.5 mm pitch

48-pin plastic TSOP I (TFP-48DA)

HN29V102414T-50H

Pin Arrangement

VCC*2

NC*1, 2

VSS*2

RES*2

RDY/Busy*2

SC*2

OE*2

I/O0*2

I/O1*2

I/O2*2

I/O3*2

VCC*2

VSS*2

I/O4*2

I/O5*2

I/O6*2

I/O7*2

CDE*2

WE*2

CE*2

NC*1, 2

VSS*2

VCC*3

NC*1, 3

VSS*3

RES*3

RDY/Busy*3

SC*3

OE*3

I/O0*3

I/O1*3

I/O2*3

I/O3*3

VCC*3

VSS*3

I/O4*3

I/O5*3

I/O6*3

I/O7*3

CDE*3

WE*3

CE*3

NC*1, 3

VSS*3

(Top view)

48-pin TSOP

Note: 1. This pin can be used as the VSS pin.

2. Upper chip.

3. Lower chip.

HN29V102414T-50H

Pin Description

Pin name Function

I/O0 to I/O7 Input/output

CE Chip enable

OE Output enable

WE Write enable

CDE Command data enable

VCC*1Power supply

VSS*1Ground

RDY/Busy Ready/Busy

RES Reset

SC Serial clock

NC No connection

Note: 1. All VCC and VSS pins should be connected to a common power supply and a ground, respectively.

HN29V102414T-50H

Block Diagram

32768 × (2048 + 64) × 8

memory matrix

X-decoder

Upper chip

Data register (2048 + 64)

Input

data

control

Sector

address

buffer

Y-address

counter

2048 + 64

32113 - 32768

RES

Y-gating

Y-decoder

Read/Program/Erase control

Data

input

buffer

I/O0

I/O7

RDY/Busy

CDE

Multiplexer

Control

signal

buffer

Data

output

buffer

• • • • •

• •

•

••

•

••

•

32768 × (2048 + 64) × 8

memory matrix

X-decoder

Lower chip

Data register (2048 + 64)

Input

data

control

Sector

address

buffer

Y-address

counter

2048 + 64

32113 - 32768

RES

Y-gating

Y-decoder

Read/Program/Erase control

Data

input

buffer

I/O0

I/O7

RDY/Busy

CDE

Multiplexer

Control

signal

buffer

Data

output

buffer

• • • • •

• •

•

••

•

••

•

HN29V102414T-50H

Memory Map and Address

7FFFH

7FFEH

7FFDH

0002H

0001H

0000H

000H

2048 bytes

64 bytes

32113 - 32768 sectors *

800H 83FH

Control bytes

2048 + 64 bytes

Column address

Sector address

Address

Sector address

Column address

Cycles

SA (1): First cycle

SA (2): Second cycle

CA (1): First cycle

CA (2): Second cycle

I/O0

I/O1

I/O2

A10

I/O3

A11

I/O4

A12

I/O5

A13

I/O6

A14

I/O7

×*2

Notes: 1. Some failed sectors may exist in the device. The failed sectors can be recognized

by reading the sector valid data written in a part of the column address 800 to 83F

(The specific address is TBD.). The sector valid data must be read and kept outside

of the sector before the sector erase. When the sector is programmed, the sector

valid data should be written back to the sector.

2. An × means "Don't care". The pin level can be set to either VIL or VIH, referred

to DC characteristics.

HN29V102414T-50H

Pin Function

CE: CE is used to select the device. The status returns to the standby at the rising edge of CE in the reading

operation. However, the status does not return to the standby at the rising edge of CE in the busy state in

programming and erase operation.

OE: Memory data and status register data can be read, when OE is VIL.

WE: Commands and address are latched at the rising edge of WE.

SC: Programming and reading data is latched at the rising edge of SC.

RES: RES pin must be kept at the VILR (VSS ± 0.2 V) level when VCC is turned on and off. In this way, data

in the memory is protected against unintentional erase and programming. RES must be kept at the VIHR (VCC

± 0.2 V) level during any operations such as programming, erase and read.

CDE: Commands and data are latched when CDE is VIL and address is latched when CDE is VIH.

RDY/Busy: The RDY/Busy indicates the program/erase status of the flash memory. The RDY/Busy signal

is initially at a high impedance state. It turns to a VOL

level after the (40H) command in programming

operation or the (B0H) command in erase operation. After the erase or programming operation finishes, the

RDY/Busy signal turns back to the high impedance state.

I/O0 to I/O7: The I/O pins are used to input data, address and command, and are used to output memory data

and status register data.

Mode Selection

Mode CE OE WE SC RES CDE RDY/Busy*3I/O0 to I/O7

Deep standby ×*4×××VILR ×VOH High-Z

Standby VIH ×××VIHR ×VOH High-Z

Output disable VIL VIH VIH ×VIHR ×VOH High-Z

Status register read*1VIL VIL VIH ×VIHR ×VOH Status register outputs

Command write*2VIL VIH VIL VIL VIHR VIL VOH Din

Notes: 1. Default mode after the power on is the status register read mode (refer to status transition). From

I/O0 to I/O7 pins output the status, when CE = VIL and OE = VIL (conventional read operation

condition).

2. Refer to the command definition. Data can be read, programmed and erased after commands are

written in this mode.

3. The RDY/Busy bus should be pulled up to VCC to maintain the VOH level while the RDY/Busy pin

outputs a high impedance.

4. An × means “Don’t care”. The pin level can be set to either VIL or VIH referred to DC characteristics.

HN29V102414T-50H

Command Definition*1, 2

First bus cycle Second bus cycle

Command Bus

cycles Operation

mode*3Data in Operation

mode Data in Data out

Read Serial read (1) (Without CA) 3 Write 00H Write SA (1)*4

(With CA) 3 + 2h*6Write 00H Write SA (1)*4

Serial read (2) 3 Write F0H Write SA (1)*4

Read identifier codes 1 Write 90H Read ID*8, 9

Data recovery read 1 Write 01H Read Recovery

data

Auto erase Single sector 4 Write 20H Write SA (1)*4

Auto program Program (1) (Without

CA*7)4 Write 10H Write SA (1)*4

(With CA*7) 4 + 2h*6Write 10H Write SA (1)*4

Program (2)*10 4 Write 1FH Write SA (1)*4

Program (3) (Control bytes)*74 Write 0FH Write SA (1)*4

Program (4) (WithoutCA*7) 4 Write 11H Write SA (1)*4

(With CA*7) 4 + 2h*6Write 11H Write SA (1)*4

Reset 1 Write FFH

Clear status register 1 Write 50H

Data recovery write 4 Write 12H Write SA (1)*4

HN29V102414T-50H

Third bus cycle Fourth bus cycle

Command Bus

cycles Operation

mode Data in Operation

mode Data in

Read Serial read (1) (Without CA) 3 Write SA (2)*4

(With CA) 3 + 2h*6Write SA (2)*4Write CA (1)*5

Serial read (2) 3 Write SA (2)*4

Read identifier codes 1

Data recovery read 1

Auto erase Single sector 4 Write SA (2)*4Write B0H*11

Auto program Program (1) (Without

CA*7)4 Write SA (2)*4Write 40H*11, 12

(With CA*7) 4 + 2h*6Write SA (2)*4Write CA (1)

Program (2)*10 4 Write SA (2)*4Write 40H*11, 12

Program (3) (Control bytes)*74 Write SA (2)*4Write 40H*11, 12

Program (4) (WithoutCA*7) 4 Write SA (2)*4Write 40H*11, 12

(With CA*7) 4 + 2h*6Write SA (2)*4Write CA (1)

Reset 1

Clear status register 1

Data recovery write 4 Write SA (2)*4Write 40H*11, 12

HN29V102414T-50H

Fifth bus cycle Sixth bus cycle

Command Bus

cycles Operation

mode Data in Operation

mode Data in

Read Serial read (1) (Without CA) 3

(With CA) 3 + 2h*6Write CA (2)*5

Serial read (2) 3

Read identifier codes 1

Data recovery read 1

Auto erase Single sector 4

Auto program Program (1) (Without

CA*7)4

(With CA*7) 4 + 2h*6Write CA (2)*5Write 40H*11, 12

Program (2)*10 4

Program (3) (Control bytes)*74

Program (4) (WithoutCA*7)4

(With CA*7) 4 + 2h*6Write CA (2) Write 40H*11, 12

Reset 1

Clear status register 1

Data recovery write 4

Notes: 1. Commands and sector address are latched at rising edge of WE pulses. Program data is latched

at rising edge of SC pulses.

2. The chip is in the read status register mode when RES is set to VIHR first time after the power up.

3. Refer to the command read and write mode in mode selection.

4. SA (1) = Sector address (A0 to A7), SA (2) = Sector address (A8 to A14).

5. CA (1) = Column address (A0 to A7), CA (2) = Column address (A8 to A11).

(0 ≤ A11 to A0 ≤ 83FH)

6. The variable h is the input number of times of set of CA (1) and CA (2) (1 ≤ h ≤ 2048 + 64).

Set of CA (1) and CA (2) can be input without limitation.

7. By using program (1) and (3), data can additionally be programmed maximum 15 times for each

sector before erase.

8. ID = Identifier code; Manufacturer code (07H), Device code (9DH).

9. The manufacturer identifier code is output when CDE is low and the device identifier code is output

when CDE is high.

10.Before program (2) operations, data in the programmed sector must be erased.

11.No commands can be written during auto program and erase (when the RDY/Busy pin outputs a

VOL).

12.The fourth or sixth cycle of the auto program comes after the program data input is complete.

HN29V102414T-50H

Mode Description

Read

Serial Read (1): Memory data D0 to D2111 in the sector of address SA is sequentially read. Output data is

not valid after the number of the SC pulse exceeds 2112. When CA is input, memory data D (m) to D (m + j)

in the sector of address SA is sequentially read. Then output data is not valid after the number of the SC pulse

exceeds (2112 to m). The mode turns back to the standby mode at any time when CE is VIH.

Serial Read (2): Memory data D2048 to D2111 in the sector of address SA is sequentially read. Output data

is not valid after the number of the SC pulse exceeds 64. The mode turns back to the standby mode at any

time when CE is VIH.

Automatic Erase

Single Sector Erase: Memory data D0 to D2111 in the sector of address SA is erased automatically by

internal control circuits. After the sector erase starts, the erasure completion can be checked through the

RDY/Busy signal and status data polling. All the bits in the sector are "1" after the erase. The sector valid

data stored in a part of memory data D2048 to D2111 must be read and kept outside of the sector before the

sector erase.

Automatic Program

Program (1): Program data PD0 to PD2111 is programmed into the sector of address SA automatically by

internal control circuits. When CA is input, program data PD (m) to PD (m + j) is programmed from CA into

the sector of address SA automatically by internal control circuits. By using program (1), data can

additionally be programed 15 times for each sector before the following erase. When the column is

programmed, the data of the column must be [FF]. After the programming starts, the program completion can

be checked through the RDY/Busy signal and status data polling. Programmed bits in the sector turn from

"1" to "0" when they are programmed. The sector valid data should be included in the program data PD2048

to PD2111.

Program (2): Program data PD0 to PD2111 is programmed into the sector of address SA automatically by

internal control circuits. After the programming starts, the program completion can be checked through the

RDY/Busy signal and status data polling. Programmed bits in the sector turn from "1" to "0" when they are

programmed. The sector must be erased before programming. The sector valid data should be included in the

program data PD2048 to PD2111.

Program (3): Program data PD2048 to PD2111 is programmed into the sector of address SA automatically

by internal control circuits. By using program (3), data can additionally be programed 15 times for each

sector befor the following erase. When the column is programmed, the data of the column must be [FF].

After the programming starts, the program completion can be checked through the RDY/Busy signal and

status data polling. Programmed bits in the sector turn from "1" to "0" when they are programmed.

HN29V102414T-50H

Program (4): Program data PD0 to PD2111 is programmed into the sector of address SA automatically by

internal control circuits. When CA is input, program data PD (m) to PD (m + j) is programmed from CA into

the sector of address SA automatically by internal control circuits. By using program (4), data can be

rewritten for each sector before the following erase. So the column data before programming operation are

either "1" or "0". In this mode, E/W number of times must be counted whenever program (4) execute. After

the programming starts, the program completion can be checked through the RDY/Busy signal and status data

polling. The sector valid data should be included in the program data PD2048 to PD2111.

Memory array

32767

Sector

address

02111

Serial read (1) (Without CA)

Program (1) (Without CA)

Program (2)

32767

Sector

address

02111

Serial read (2)

Program (3)

2048

Memory array

32767

Sector

address

02111

Serial read (1) (With CA)

Program (1) (With CA)

Column address

Memory array

Status Register Read

The status returns to the status register read mode from standby mode, when CE and OE is VIL. In the status

function description.

Identifier Read

The manufacturer and device identifier code can be read in the identifier read mode. The manufacturer and

device identifier code is selected with CDE VIL and VIH, respectively.

HN29V102414T-50H

Data Recovery Read

When the programming was an error, the program data can be read by using data recovery read. When an

additional programming was an error, the data compounded of the program data and the origin data in the

sector address SA can be read. Output data are not valid after the number of SA pulse exeeds 2112. The

mode turns back to the standby mode at any time when CE is VIH. The read data are invalid when addresses

are latched at a rising edge of WE pulse after the data recovery read command is written.

Data Recovery Write

When the programming into a sector of address SA was an error, the program data can be rewritten

automatically by internal control circuit into the other selected sector of address SA’. Since the data recovery

write mode is internally Program (4) mode, rewritten sector of address SA’ needs no sector erase before

rewrite. After the data recovery write mode starts, the program completion can be checked through the

RDY/Busy signal and the status data polling.

HN29V102414T-50H

Command/Address/Data Input Sequence

Serial Read (1) (With CA before SC)

00H SA (1) SA (2) CA (1) CA (2) CA (1)' CA (2)'

Low

Data output Data output

Command

/Address

CDE

Serial Read (1) (With CA after SC)

00H SA (1) SA (2) CA (1)' CA (2)'CA (1) CA (2)

Low

Data output Data outputData output

Command

/Address

CDE

Serial Read (1) (Without CA), (2)

00H/F0H SA (1) SA (2)

Low

Data output

Command/Address

CDE

Single S ector Erase

20H B0HSA (1) SA (2)

Command/Address

CDE

SC Low Erase start

HN29V102414T-50H

Program (1), (4) (With CA before SC)

10H/11H SA (1) SA (2) CA (1) CA (2) CA (1)' CA (2)' 40H

Low

Data input Data input Program start

Command

/Address

CDE

Program (1), (4) (With CA after SC)

10H/11H SA (1) SA (2) CA (1) CA (2) 40H

Low

Data input Data input Program start

CA (1)' CA (2)'

Data input

Command

/Address

CDE

Program (1), (4) (Without CA)

Data input

10H/11H 40HSA (1) SA (2)

Command/Address

CDE

SC Low

Program start

Program (2)

Data input

1FH 40HSA (1) SA (2)

Command/Address

CDE

SC Low

Program start

HN29V102414T-50H

Program (3)

Data input

0FH 40HSA (1) SA (2)

Command/Address

CDE

SC Low

Program start

ID Read Mode

90H

Command/Address

CDE

SC Low Manufacture

code output Manufacture

code output

Device code

output

Data Recovery Read Mode

01H

Command/Address

CDE

SC Low Data output

Data Recovery Write Mode

12H 40HSA (1) SA (2)

Command/Address

CDE

SC Low Program start

HN29V102414T-50H

Status Transition

Deep

standby Power off

VCC

Status register

read

Status register

read

OE Status register

read

00H/F0H

FFH

SA (1), SA (2) OE, SC

SC, CDE

CA(1)

CA(2) CA(1)'

CA(2)'

CA(1)'

CA(2)'

CA(1)

CA(2)

RES

ID read

90H CDE, OE

Output

disable

Standby

Error

standby

FFH

Sector

Erase setup Sector

address input

20H SA (1), SA (2) Erase

start

B0H

FFH

Erase finish

Status register

read

Program

(1)/(4) setup Sector address

input

Column address

input

10H

/11H SA (1),

SA (2) Program

start

Program

data input

PD0 to

PD2111

PD(m)

PD(m+j)

FFH Program finish

Data recovery

read setup

01H*1

Data recovery

write setup Sector address

input

12H*1

FFH

40H

SA(1)

SA(2)

Data recovery

read

OE, SC

Read (1) / (2)

setup Sector address

input Read (1) / (2)

Column address

input

ID read setup

Status register

read

Program (2)/(3)

setup Sector address

input

1FH

/0FH SA (1),

SA (2) Program

start

Program

data input

PD0 to

PD2111*3

FFH

FFH*2

CE*2

Program finish

BUSY

40H

Output

disable

Status register clear 50H

ERROR

Program error or

Erase error

Notes: 1. (01H)/(12H) Data recovery read/write can be used only for Program (1), (2), (3), (4) errors.

2. When reset is done by CE or FFH, error status flag is cleared.

3. When Program (3) mode, input data is PD2048 to PD2111.

HN29V102414T-50H

Absolute Maximum Ratings

Parameter Symbol Value Unit Notes

VCC voltage VCC –0.6 to +4.6 V 1

VSS voltage VSS 0V

All input and output voltages Vin, Vout –0.6 to +4.6 V 1, 2

Operating temperature range Topr 0 to +70 ˚C

Storage temperature range Tstg –65 to +125 ˚C 3

Storage temperature under bias Tbias –10 to +80 ˚C

Notes: 1. Relative to VSS.

2. Vin, Vout = –2.0 V for pulse width ≤ 20 ns.

3. Device storage temperature range before programming.

Capacitance (Ta = 25˚C, f = 1 MHz)

Parameter Symbol Min Typ Max Unit Test conditions

Input capacitance Cin — — 6 pF Vin = 0 V

Output capacitance Cout — — 12 pF Vout = 0 V

HN29V102414T-50H

DC Characteristics (VCC = 2.7 V to 3.6 V, Ta = 0 to +70˚C)

Parameter Symbol Min Typ Max Unit Test conditions

Input leakage current ILI ——2 µA Vin = VSS to VCC

Output leakage current ILO ——2 µA Vout = VSS to VCC

Standby VCC current

(1-chip operation) ISB1 — 0.3 1 mA CE = VIH

(2-chip operation) ISB1 — 0.6 2 mA

(1-chip operation) ISB2 —3050 µACE = VCC ± 0.2 V,

RES = VCC ± 0.2 V

(2-chip operation) ISB2 — 60 100 µA

Deep standby VCC current

(1-chip operation) ISB3 —120 µARES = VSS ± 0.2 V

(2-chip operation) ISB3 —240 µA

Operating VCC current

(1-chip operation) ICC1 — 2 20 mA Iout = 0 mA, f = 0.2 MHz

(2-chip operation) ICC1 — 4 40 mA

(1-chip operation) ICC2 — 10 20 mA Iout = 0 mA, f = 20 MHz

(2-chip operation) ICC2 —2040 mA

Operating VCC current (Program)

(1-chip operation) ICC3 — 20 40 mA In programming

(2-chip operation) ICC3 —4080 mA

Operating VCC current (Erase)

(1-chip operation) ICC4 — 20 40 mA In erase

(2-chip operation) ICC4 —4080 mA

Input voltage VIL –0.3*1, 2 — 0.8 V

VIH 2.0 — VCC + 0.3*3V

Input voltage (RES pin) VILR –0.2 — 0.2 V

VIHR VCC –

0.2 —V

CC + 0.2 V

Output voltage VOL — — 0.4 V IOL = 2 mA

VOH 2.4 — — V IOH = –2 mA

Notes: 1. VIL min = –1.0 V for pulse width ≤ 50 ns in the read operation. VIL min = –2.0 V for pulse width ≤ 20

ns in the read operation.

2. VIL min = –0.6 V for pulse width ≤ 20 ns in the erase/data programming operation.

3. VIH max = VCC + 1.5 V for pulse width ≤ 20 ns. If VIH is over the specified maximum value, the

operations are not guaranteed.

HN29V102414T-50H

AC Characteristics (VCC = 2.7 V to 3.6 V, Ta = 0 to +70˚C)

Test Conditions

• Input pulse levels: 0.4 V/2.4 V

• Input pulse levels for RES: 0.2 V/VCC – 0.2 V

• Input rise and fall time: ≤ 5 ns

• Output load: 1 TTL gate + 100 pF (Including scope and jig.)

• Reference levels for measuring timing: 0.8 V, 1.8 V

HN29V102414T-50H

Power on and off, Serial Read Mode

Parameter Symbol Min Typ Max Unit Test conditions Notes

Write cycle time tCWC 120 — — ns

Serial clock cycle time tSCC 50——ns

CE setup time tCES 0 ——ns

CE hold time tCEH 0 ——ns

Write pulse time tWP 60——nsCE = VIL, OE = VIH

Write pulse high time tWPH 40——ns

Address setup time tAS 50——ns

Address hold time tAH 10——ns

Data setup time tDS 50——ns

Data hold time tDH 10——ns

SC to output delay tSAC ——50nsCE = OE = VIL, WE = VIH

OE setup time for SC tOES 0 ——ns

OE low to output low-Z tOEL 0 — 40 ns

OE setup time before read tOER 100 — — ns

OE setup time before

command write tOEWS 0 ——ns

SC to output hold tSH 15——nsCE = OE = VIL, WE = VIH

OE high to output float tDF ——40nsCE = VIL, WE = VIH 1

WE to SC delay time tWSD 50 — — µs2

RES to CE setup time tRP 0.3 — — ms

SC to OE hold time tSOH 50——ns

SC pulse width tSP 20——ns

SC pulse low time tSPL 20——ns

SC setup time for CE tSCS 0 ——ns

CDE setup time for WE tCDS 0 ——ns

CDE hold time for WE tCDH 20——ns

VCC setup time for RES tVRS 1——µsCE = VIH

RES to VCC hold time tVRH 1——µsCE = VIH

CE setup time for RES tCESR 1——µs

RDY/Busy undefined for VCC

off tDFP 0 ——ns

RES high to device ready tBSY — — 0.3 ms

CE pulse high time tCPH 200 — — ns

CE, WE setup time for RES tCWRS 0 ——ns

RES to CE, WE hold time tCWRH 0 ——ns

HN29V102414T-50H

Parameter Symbol Min Typ Max Unit Test conditions Notes

SC setup for WE tSW 50——ns

CE hold time for OE tCOH 0 ——ns

SA (2) to CA (2) delay time tSCD ——30µs

RDY/Busy setup for SC tRS 200 — — ns

Time to device busy tDB — — 150 ns

Busy time on read mode tRBSY —45—µs

Notes: 1. tDF is a time after which the I/O pins become open.

2. tWSD (min) is specified as a reference point only for SC, if tWSD is greater than the specified tWSD (min)

limit, then access time is controlled exclusively by tSAC.

HN29V102414T-50H

Program, Erase and Erase Verify

Parameter Symbol Min Typ Max Unit Test conditions Note

Write cycle time tCWC 120 — — ns

Serial clock cycle time tSCC 50——ns

CE setup time tCES 0 ——ns

CE hold time tCEH 0 ——ns

Write pulse time tWP 60——ns

Write pulse high time tWPH 40——ns

Address setup time tAS 50——ns

Address hold time tAH 10——ns

Data setup time tDS 50——ns

Data hold time tDH 10——ns

OE setup time before command

write tOEWS 0 ——ns

OE setup time before status

polling tOEPS 40——ns

OE setup time before read tOER 100 — — ns

Time to device busy tDB — — 150 ns

Auto erase time tASE — 1.0 10.0 ms

Auto program time

Program(1), (3) tASP — 1.5 20.0 ms

Program(2) tASP — 1.0 20.0 ms

Program(4),

Data recovery write tASP — 2.0 30.0 ms

WE to SC delay time tWSD 50 — — µs

CE pulse high time tCPH 200 — — ns

SC pulse width tSP 20——ns

SC pulse low time tSPL 20——ns

Data setup time for SC tSDS 0 ——ns

Data hold time for SC tSDH 30——nsCDE = VIL

SC setup for WE tSW 50——ns

SC setup for CE tSCS 0 ——ns

SC hold time for WE tSCHW 20——ns

HN29V102414T-50H

Parameter Symbol Min Typ Max Unit Test conditions Note

CE to output delay tCE — — 120 ns

OE to output delay tOE ——60ns

OE high to output float tDF ——40ns 1

RES to CE setup time tRP 0.3 — — ms

CDE setup time for WE tCDS 0 ——ns

CDE hold time for WE tCDH 20——ns

CDE setup time for SC tCDSS 1.5 — — µs

CDE hold time for SC tCDSH 30——ns

Next cycle ready time tRDY 0 ——ns

CDE to OE hold time tCDOH 50——ns

CDE to output delay tCDAC ——50ns

CDE to output invalid tCDF — — 100 ns

CE hold time for OE tCOH 0 ——ns

OE setup time for SC tOES 0 ——ns

OE low to output low-Z tOEL 0 — 40 ns

SC to output delay tSAC ——50ns

SC to output hold tSH 15——ns

RDY/Busy setup for SC tRS 200 — — ns

Busy time on read mode tRBSY —45—µs

Note: 1. tDF is a time after which the I/O pins become open.

HN29V102414T-50H

Timing Waveforms

Power on and off Sequence

tVRS

tRP tCES

tBSY

tCEH tCESR tRP

tBSY

tCES tCEH

tVRH tDFP

tCWRH

tCESR

tCWRS

VCC

RES

RDY

/Busy

*1*2*1

High-Z Ready

Notes: 1. RES must be kept at the VILR level referred to DC characteristics at the rising and falling edges of VCC

to guarantee data stored in the chip.

2. RES must be kept at the VIHR level referred to DC characteristics while I/O7 outputs the VOL level in the

status data polling and RDY/Busy outputs the VOL level.

3. : Undefined

HN29V102414T-50H

Serial Read (1) (2) Timing Waveform

CDE

RES

tCES

tCWC tCWC

tCEH

tCPH

tWPH tOER

tWPH

tWP tWP tWP

tSAC tSAC tSAC

tSP

tOES

tWSD tSCC tSCC tSOH

I/O0 to I/O7

tSCS tDS

tRP tDB

tRBSY tRS

tAS tAS

tDH tDS

tCDS

tDF

tSAC

tCDH

tWP

tCOH

tDH

tAH tAH

tOEL

High-Z

RDY

/Busy

D0out/D2048out D1out/D2049out D2111out/D2111out00H

/F0H SA(1)

Notes: 1. The status returns to the standby at the rising edge of CE.

2. Output data is not valid after the number of the SC pulse exceeds 2112 and 64 in the serial read mode (1)and (2), respectively.

3. After any commands are written, the status can return to the standby after the command FFH is input and CE turns to the VIH level.

tOEWS

tCDS tCDS

tCDH *2

*1*3

tSPL

tSH tSH

FFH

SA(2)

Serial Read (1) with CA before SC Timing Waveform

CDE

RES

tCES

tCWC tCWC tCWC tCWC

tCDS

tCPH tCEH

tWP tCDH

tWPH tWPH tOER

tWPH

tWP tWP tWP tWP tWP

tSCD tWSD tSCC

tSCC tSCC tSCC

tOES tOES

tWPH

tCWC

tOEWS

I/O0 to I/O7

tSCS tDS tAS tAS tAS tAS tAH tAH

tAS

tSH

tAS

tAH tAH tOEL

tAH tAH tSH tSH

tSAC tSAC tSAC tSAC tDF

tSP

tRP

tRBSY

tDB tRS

tDH

tOER

tWP

tSW

tSP tSPL

tWP

tCOH

h-1 cycle

High-Z

RDY

/Busy

D(n)out D(n+1)out D(n+i)out00H SA(1) CA(1) CA(2) CA(2)'CA(1)' D(m)out D(m+1)out D(m+j)out FFH

Notes: 1. The status returns to the Standby at the rising edge of CE.

2. Output data is not valid after the number of the SC pulse exceeds (2112-n). (i ≤ 2111-n, 0 ≤ n ≤ 2111)

3. Output data is not valid after the number of the SC pulse exceeds (2112-m). (j ≤ 2111-m, 0 ≤ m ≤ 2111)

4. After any commands are written, the status can return to the standby after the command FFH is input and CE turns

to the VIH level.

5. This interval can be repeated (h-1) cycle. (1≤ h ≤ 2048 + 64)

tOEWS

tCDS tCDS

tCDH *2

*2*3

tSOH tSOH

tSPL

tOEL tSAC tSAC tSAC tDF tDS tDH

tSAC

tSH

SA(2)

HN29V102414T-50H

Serial Read (1) with CA after SC Timing Waveform

CDE

RES

tCES

tCWC tCWC

tCDS

tCPH tCEH

tWP tCDH

tWPH tWPH tOER

tWP tWP tWP

tSCC

tWSD

tOES tSCC tSCC

tOES

tOEL

tWPH

tCWC

tOEWS

I/O0 to I/O7

tSCS tDS tAS tAS tSAC

tSP tSH

tAH tAH tSH tSH

tSPL tSAC tSAC tSAC tDF tAH tAH

tAS tAS

tRP

tDB tRBSY tRS

tDH

tOER

tWP

tSW

tSP tSPL

tWP

tCOH

h cycle

High-Z

RDY

/Busy

D0out D1out D(k)out

00H SA(1) CA(2)CA(1) D(m)out D(m+1)out D(m+j)out FFH

Notes: 1. The status returns to the Standby at the rising edge of CE.

2. Output data is not valid after the number of the SC pulse exceeds 2112. (0 ≤ k ≤ 2111)

3. Output data is not valid after the number of the SC pulse exceeds (2112-m). (j ≤ 2111-m, 0 ≤ m ≤ 2111)

4. After any commands are written, the status can return to the standby after the command FFH is input and CE turns to the VIH level.

5. This interval can be repeated h cycle. (1≤ h ≤ 2048 + 64)

tOEWS

tCDS tCDS

tCDH

*2*3

tSOH tSOH

tOEL tSAC

tSAC tSAC tDF tDS tDH

tSAC

tSH

SA(2)

Erase and Status Data Polling Timing Waveform (Sector Erase)

CDE

RES

tCES

tCWC tCWC tCWC

tCEH

tOEPS

tCE tOE

tRDY

tASE

tWPH tWPH

tWPH

tWPtWP tWP tWP

tCDH

tSCHW

I/O0 to I/O7

tSCS tDS tDS

tDB

tRP

tAS tAS

tDH tDH tDF tDF

tCDS

tAH tAH

High-Z High-Z

RDY

/Busy

IO7 = VOH

IO7 = VOL

20H SA(1) SA(2)

Notes: 1. Any commands,including reset command FFH, cannot be input while RDY/Busy outputs a VOL.

2. The status returns to the standby status after RDY/Busy returns to High-Z.

tOEWS

tCDS tCDS tCDS

tCDH tCDH

B0H

HN29V102414T-50H

Program (1) and Status Data Polling Timing Waveform

RES

RDY

/Busy

CDE

I/O0 to I/O7

tCES

tOEWS tCWC

tWPH

tWPtCDS

tCDS

tSCS

tRP

tCDH

tDS

tCDH

tOE

tCDSS

tWP tWP tSW

tSCHW

tCDH

tWP

tSPL

tSCC

tWPH

tCEH tCE

tRDY

tCWC

tDB

tOEPS

tASP

tDH

tAS tAS

tAH tSP tSP tDS tDH

40H10H PD0 PD1 PD2111 I/O7 = VOL I/O7 = VOH

SA (1) SA (2)

High-Z High-Z

tDF tDF

tCDS

Notes: 1. The programming operation is not guranteed when the number of the SC pulse exceeds 2112.

2. Any commands, including reset command FFH, cannot be input while RDY/Busy is VOL.

3. The status returns to the standby status after RDY/Busy returns to High-Z.

4. By using program (1), data can be programmed additionally for each sector before erase.

tAH tSDH

tSDS

HN29V102414T-50H

Program (1) with CA before SC and Status Data Polling Timing Waveform

I/O0 to I/O7

RES

RDY

/Busy

CDE

Notes: 1. The programming operation is not guaranteed when the number of the SC pulse exceeds (2112 – n).(i ≤ 2111 – n, 0 ≤ n ≤ 2111)

2. The programming operation is not guaranteed when the number of the SC pulse exceeds (2112 – m).(j ≤ 2111 – m, 0 ≤ m ≤ 2111)

3. Any commands, including reset command FFH, cannot be input while RDY/Busy is VOL.

4. The status returns to the standby status after RDY/Busy returns to High-Z.

5. By using program (1), data can be programmed additionally for each sector before erase.

6. This interval can be repeated (h – 1) cycle.(1 ≤ h ≤ 2048 + 64)

tCES

tWP

tCDS tCDS

tCDH tCDH

tCDSS

tCDH

tCDSH

tAS tAS tSDS tDS

tDB

tSCC

tAH tAH tSDH tDH tDF

tDF

tCDS

tSW

tCDSS

tDS tAS tAS tAS tAS tSDS

tDH

tAH tAH tAH tAH

tSCS

tWP

tRP

tWP tWP tWP tWP tWP tWP

tCEH tCE

tCDH

tSCHW

tOEPS tRDY

tOE

tSW

tCDS

tWPH

tCWC

tOEWS tCWC tCWC tCWC tCWC

tWPH tWPH tWPH tWPH

High-Z High-Z*4

10H SA(1) SA(2) CA(1) CA(2) CA(1)' CA(2)'PD(n) PD(n+1) PD(n+i)*1

*1*2

PD(m) PD(m+1)PD(m+j)*2

h–1 cycle*6

I/O7=VOL I/O7=VOH

tSDH

tSPL

tSP tSP tSP tSP

tSPL

tSCC

40H

tASP

Program (1) with CA after SC and Status Data Polling Timing Waveform

I/O0 to I/O7

RES

RDY

/Busy

CDE

Notes: 1. The programming operation is not guaranteed when the number of the SC pulse exceeds 2112.(0 ≤ k ≤ 2111)

2. The programming operation is not guaranteed when the number of the SC pulse exceeds (2112 – m).(j ≤ 2111 – m, 0 ≤ m ≤ 2111)

3. Any commands, including reset command FFH, cannot be input while RDY/Busy is VOL.

4. The status returns to the standby status after RDY/Busy returns to High-Z.

5. By using program (1), data can be programmed additionally for each sector before erase.

6. This interval can be repeated h cycle.(1 ≤ h ≤ 2048 + 64)

tCES

tWP

tCDS tCDS

tCDH tCDH

tCDSS

tCDH

tCDSH

tAS tAS tSDS tDS

tDB

tSCC

tAH tAH tSDH tDH tDF

tDF

tCDS

tSW

tCDSS

tDS tAS tAS tSDS

tDH

tAH tAH tSDH

tSCS

tWP

tRP

tWP tWP tWP tWP

tCEH tCE

tCDH

tSCHW

tOEPS tRDY

tOE

tSW

tCDS

tWPH

tCWC

tOEWS tCWC tCWC

tWPH tWPH

High-Z High-Z*4

10H SA(1) SA(2) PD0 PD1 CA(1) CA(2)

PD(k)*1

*1*2

PD(m) PD(m+1)PD(m+j)*2

h cycle*6

I/O7=VOL I/O7=VOH

tSPL

tSP tSP tSP tSP

tSPL

tSCC

40H

tASP

HN29V102414T-50H

Program (2) and Status Data Polling Timing Waveform

RES

RDY

/Busy

CDE

I/O0 to I/O7

tCES

tOEWS tCWC

tWPH

tWPtCDS

tCDS

tSCS

tRP

tCDH

tDS

tCDH

tOE

tCDSS

tWP tWP tSW

tSCHW

tCDH

tWP

tSPL

tSCC

tWPH

tCEH

tCDS

tCE

tRDY

tCWC

tDB

tOEPS

tASP

tDH

tAS tAS

tAH tSP tSP tDS tDH

40H1FH PD0 PD1 PD2111 I/O7 = VOL I/O7 = VOH

SA (1) SA (2)

High-Z High-Z

tDF tDF

Notes: 1. The programming operation is not guranteed when the number of the SC pulse exceeds 2112.

2. Any commands, including reset command FFH, cannot be input while RDY/Busy is VOL.

3. The status returns to the standby status after RDY/Busy returns to High-Z.

4. By using program (2), the programmed data of each sector must be erased before programming next data.

tAH tSDH

tSDS

HN29V102414T-50H

Program (3) and Status Data Polling Timing Waveform

RES

RDY

/Busy

CDE

I/O0 to I/O7

tCES

tOEWS tCWC

tWPH

tWPtCDS

tCDS

tSCS

tRP

tCDH

tDS

tCDH

tOE

tCDSS

tWP tWP tSW

tSCHW

tCDH

tWP

tSPL

tSCC

tCEH

tCDS

tCE

tRDY

tCWC

tDB

tOEPS

tASP

tDH

tAS tAS

tAH tSP tSP tDS tDH

40H0FH PD2048 PD2049 PD2111 I/O7 = VOL I/O7 = VOH

SA (1) SA (2)

High-Z High-Z

tDF tDF

Notes: 1. The programming operation is not guranteed when the number of the SC pulse exceeds 64.

2. Any commands, including reset command FFH, cannot be input while RDY/Busy is VOL.

3. The status returns to the standby status after RDY/Busy returns to High-Z.

4. By using program (3), the data can be programmed additionally for each sector before erase.

tAH tSDH

tSDS

HN29V102414T-50H

Program (4) and Status Data Polling Timing Waveform

RES

RDY

/Busy

CDE

I/O0 to I/O7

tCES

tOEWS tCWC

tWPH

tWPtCDS

tCDS

tSCS

tRP

tDB tDB

tRS

tRBSY

tCDH

tDS

tCDH

tWSD

tOE

tCDSS

tWP tWP tSW

tSCHW

tCDH

tCDS

tWP

tSPL

tSCC

tWPH

tCEH tCE

tRDY

tCWC

tDB

tOEPS

tASP

tDH

tAS tAS

tAH tSP tSP tDS tDH

40H11H PD0 PD1 PD2111 I/O7 = VOL I/O7 = VOH

SA (1) SA (2)

High-Z High-Z

tDF tDF

Notes: 1. The programming operation is not guranteed when the number of the SC pulse exceeds 2112.

2. Any commands, including reset command FFH, cannot be input while RDY/Busy is VOL.

3. The status returns to the standby status after RDY/Busy returns to High-Z.

4. By using program (4), data can be rewritten for each sector.

tAH tSDH

tSDS

HN29V102414T-50H

Program (4) with CA before SC and Status Data Polling Timing Waveform

I/O0 to I/O7

RES

RDY

/Busy

CDE

Notes: 1. The programming operation is not guaranteed when the number of the SC pulse exceeds (2112 – n).(i ≤ 2111 – n, 0 ≤ n ≤ 2111)

2. The programming operation is not guaranteed when the number of the SC pulse exceeds (2112 – m).(j ≤ 2111 – m, 0 ≤ m ≤ 2111)

3. Any commands, including reset command FFH, cannot be input while RDY/Busy is VOL.

4. The status returns to the standby status after RDY/Busy returns to High-Z.

5. By using program (4), data can be rewritten for each sector.

6. This interval can be repeated (h – 1) cycle.(1 ≤ h ≤ 2048 + 64)

tCES

tWP

tCDS tCDS

tCDH tCDHtWSD

tCDSS

tCDH

tCDSH

tAS tAS tSDS tDS

tDB

tSCC

tAH tAH tSDH tDH tDF

tDF

tCDS

tSW

tCDSS

tDS tAS tAS tAS tAS tSDS

tDH

tAH tAH tAH tAH

tSCS

tWP

tRP tDB tRBSY tRS

tWP tWP tWP tWP tWP tWP

tCEH tCE

tCDH

tSCHW

tOEPS tRDY

tOE

tSW

tCDS

tWPH

tCWC

tOEWS tCWC tCWC tCWC tCWC

tWPH tWPH tWPH tWPH

High-Z High-Z*4

11H SA(1) CA(1) CA(2) CA(1)' CA(2)'PD(n+1) PD(n+i)*1

*1*2

PD(m) PD(m+1)PD(m+j)*2

h–1 cycle*6

I/O7=VOL I/O7=VOH

tSDH

tSPL

tSP tSP tSP tSP

tSPL

tSCC

40H

SA(2) PD(n)

tASP

Program (4) with CA after SC and Status Data Polling Timing Waveform

I/O0 to I/O7

RES

RDY

/Busy

CDE

Notes: 1. The programming operation is not guaranteed when the number of the SC pulse exceeds 2112.(0 ≤ k ≤ 2111)

2. The programming operation is not guaranteed when the number of the SC pulse exceeds (2112 – m).(j ≤ 2111 – m, 0 ≤ m ≤ 2111)

3. Any commands, including reset command FFH, cannot be input while RDY/Busy is VOL.

4. The status returns to the standby status after RDY/Busy returns to High-Z.

5. By using program (4), data can be rewritten for each sector.

6. This interval can be repeated h cycle.(1 ≤ h ≤ 2048 + 64)

tCES

tWP

tCDS tCDS

tCDH tCDH

tWSD

tCDSS

tCDH

tCDSH

tAS tAS tSDS tDS

tDB

tSCC

tAH tAH tSDH tDH tDF

tDF

tCDS

tSW

tCDSS

tDS tAS tAS tSDS

tDH

tAH tAH tSDH

tSCS

tWP

tRP tDB tRS

tRBSY

tWP tWP tWP tWP

tCEH tCE

tCDH

tSCHW

tOEPS tRDY

tOE

tSW

tCDS

tWPH

tCWC

tOEWS tCWC tCWC

tWPH tWPH

High-Z High-Z*4

11H SA(1) PD1 CA(1) CA(2)

PD(k)*1

*1*2

PD(m) PD(m+1)PD(m+j)*2

h cycle*6

I/O7=VOL I/O7=VOH

tSPL

tSP tSP tSP tSP

tSPL

tSCC

40H

SA(2) PD0

tASP

HN29V102414T-50H

ID and Status Register Read Timing Waveform

CDE

RES

tCES

tCE

tCOH tCOH

tWP

tSCHW

I/O0 to I/O7

tSCS tDH tDF tOE

tSCS

tOE tCDAC tCDAC

tCDF tCDF

tRP

tDF

High-Z

RDY

/Busy

Status

90H Manufacturer

code Manufacturer

code

Device

code

Note: 1. The status returns to the standby at the rising edge of CE.

tOEWS tOEPS

tCDH tCDOH

tCDS

tDS

HN29V102414T-50H

Data Recovery Read Timing Waveform

CDE

RES

tCES

tCPH

tCOH tCEH

tWP tWP tCDH

tSCC

tSP

tSAC tSAC

tSCC tSOH

I/O0 to I/O7

tSCS tOEL

tOES tCDS

tDS

tDH

High-Z

High

RDY

/Busy

01H FFH

D0out D1out D2111out

Notes: 1. The status returns to the standby at the rising edge of CE.

2. Output data is not valid after the number of the SC pulse exceed 2112 in the recovery data read mode.

3. After any commands are written, the status can turns to the standby after the command FFH is input

and CE turns to the VIH level.

tOEWS tOER

tSH tSH tSAC tSAC

tCDS

tDS

tCDH

tDH

tSPL tDF

HN29V102414T-50H

Data Recovery Write Timing Waveform

CDE

RES

tCES

tCWC tCWC tCWC

tCEH

tOEPS

tASP

tCE tOE

tRDY

tWPH tWPH

tWPH

tWPtWP tWP tWP

tCDH

tSCHW

I/O0 to I/O7

tSCS tDS tDS

tDB

tAS tAS

tDH tDH tDF tDF

tCDS

tAH tAH

High-Z

High

High-Z

RDY

/Busy

IO7 = VOH

IO7 = VOL

12H SA(1) SA(2)

Notes: 1. Any commands,including reset command FFH, cannot be input while RDY/Busy is VOL.

2. The status returns to the standby status after RDY/Busy returns to High-Z.

tOEWS

tCDS tCDS tCDS

tCDH tCDH

40H

HN29V102414T-50H

Clear Status Register Timing Waveform

CDE

RES

RDY

/Busy

I/O0 to I/O7

CE tCES

tCDS

tSCS tDS tDH

tWP tCDH

tWPH

tCEH

tCDS

tCDH

tWP

tCPH tCES

tCDH

tWP

tSCS

tDS tDH tDS tDH

High-Z

Note 1. The status returns to the standby at the rising edge of CE.

Command Next

Command

50H

tOEWS

High

tOEWS

tCDS

HN29V102414T-50H

Function Description

Status Register: The HN29V102414T-50H outputs the operation status data as follows: I/O7 pin outputs a

VOL to indicate that the memory is in either erase or program operation. The level of I/O7 pin turns to a VOH

when the operation finishes. I/O5 and I/O4 pins output VOLs to indicate that the erase and program operations

complete in a finite time, respectively. If these pins output V OHs, it indicates that these operations have timed

out. If I/O6 pin outputs VOH, it indicates a possibility that can be corrected by ECC, choose data correction by

ECC or not by reading out the data. When these pins monitor, I/O7 pin must turn to a VOH. To execute other

erase and program operation, the status data must be cleared after a time out occurs. From I/O0 to I/O3 pins

are reserved for future use. The pins output VOLs and should be masked out during the status data read mode.

The function of the status register is summarized in the following table.

I/O Flag definition Definition

I/O7 Ready/Busy VOH = Ready, VOL = Busy

I/O6 Program/Erase ECC

check When I/O7 outputs VOH, VOH = ECC available, VOL = ECC not available.

I/O5 Erase check VOH = Fail, VOL = Pass

I/O4 Program check VOH = Fail, VOL = Pass

I/O3 Reserved Outputs a VOL and should be masked out during the status data poling mode.

I/O2 Reserved

I/O1 Reserved

I/O0 Reserved

ECC Applicability

I/O7 I/O6 I/O5 I/O4 System data correction by ECC

VOH VOH VOH VOL Needed

VOH VOL VOH VOL Not needed. Sector replacement

VOH VOH VOL VOH Needed

VOH VOL VOL VOH Not needed. Sector replacement

This device needs to be corrected failure data by ECC on system or Spare sectors, by reading out again the

failure sector data when program/erase error occures.

HN29V102414T-50H

Requirement for System

Specifications

Program/Erase Endurance: 3 × 105 cycles

Item Min Typ Max Unit

Usable sectors (initially) 64,226 — 65,536 sector

Spare sectors (1-chip operation) 579 — — sector

(2-chip operation) 1158 — — sector

ECC (Error Correction Code) 3 — — bit/sector

HN29V102414T-50H

Unusable Sector

Initially, the HN29V102414T-50H includes unusable sectors. The unusable sectors must be distinguished

from the usable sectors by the system as follows.

1. Check the partial invalid sectors in the devices on the system. The usable sectors were programmed the

following data. Refer to the flowchart “Indication of unusable sectors”.

Initial Data of Usable Sectors

Column address 0H to 81FH 820H 821H 822H 823H 824H 825H 826H to 83FH

Data FFH 1CH 71H C7H 1CH 71H C7H FFH

2. Do not erase and program to the partial invalid sectors by the system.

Sector number = 0

Read data

Bad sector*2

Sector number =

Sector number + 1

Column address = 820H to 825H

Yes

Check data*1

Sector number = 32,767

START

END

Notes: 1. Refer to table "Initial data of usable sectors".

2. Bad sectors are installed in system.

The Unusable Sector Indication Flow (1-chip)

HN29V102414T-50H

Requirements for High System Reliability

The device may fail during a program, erase or read operation due to write or erase cycles. The following

architecture will enable high system reliability if a failure occurs.

1. For an error in read operation: An ECC (Error Correction Code) or a similar function which can correct

3-bits per each sectors is required for data reliability. When error occurs, data must not be corrected by

replacing to spare sector.

2. For errors in program or erase operations: The device may fail during a program or erase operation due to

write or erase cycles. The status register indicates if the erase and program operation complete in a finite

time. When an error occured in the sector, try to reprogram the data into another sector. Avoid further

system access to the sector that error happens. Typically, recommended number of a spare sectors are

1.8% (579 sectors/chip (min)) of initial usable 32,113 sectors/chip (min.) by each device. For the

reprogramming, do not use the data from the failed sectors, because the data from the failed sectors are not

fixed. So the reprogram data must be the data reloaded from the external buffer, or use the Data recovery

read mode or the Data recovery write mode (see the “Mode Description” and under figure “Spare Sector

Replacement Flow after Program Error”). To avoid consecutive sector failures, choose addresses of spare

sectors as far as possible from the failed sectors. In this case, 105 cycles of program/erase endurance is

guaranteed.

3. Prolongation of flash memory life: Due to the life of the memory prolongation, to do ware leveling at

about 5000 each. The write/erase endurance is 3 × 105 cycles under the condition of the 3-bit error

correction and of ware leveling at 5000 each.

HN29V102414T-50H

Program start

Program end

Clear status register

Program start

Program end

Load data from

external buffer Data recovery read Data recovery write

Check RDY/Busy

Set an usable sector

Check RDY/Busy

Set another

usable sector

Yes

Check status

Check status: Status register read

Yes

Check status

START

END

Spare Sector Replacement Flow after Program Error

HN29V102414T-50H

For Errors in program or erase operations

The device may fail during a program or erase operation. Failure mode can be confirmed by read out the

status register after complete the erase and program operations. There are two failure modes specified by

each codes:

1: Status register error flag: I/O6 = VOL

Replace sector under the “Spare Sectors Replacement Flow at Status Register I/O6 Read”. Replacement must

be applied to one sector(2k bytes) which contains failure bits.

2: Status register error flag: I/O6 = VOH

Escape the program data temporary under the “Replacement Flow at Status Register I/O6 Read”. If failure

data can be corrected by ECC, do not replace to spare sector. If failure data can not be corrected by ECC,

replace to spare sector. Replacement must be applied to one sector(2k bytes) which contains failure bits.

Program start

Program end

Sector Replacement

Program end

Check RDY/Busy

Set an usable sector

Yes

Yes Yes

Check status

Yes

Check status

Check status Check ECC

Check I/O6

START

END

Escape program deta*

Read error sector

Note: 1. Refer to 'Spare sector replacement flow after program error' to escape the deta.

Check status: Status register read

Check I/O6: I/O6 output monitor

Check ECC: Correct by ECC?

Spare Sectors Replacement Flow at Status Register I/O6 Read

HN29V102414T-50H

Memory Structure

32,768 sectors

sector

2,112 bytes (16,896 bits)

byte (8 bits)

bit

Bit: Minimum unit of data.

Byte: Input/output data unit in programming and reading. (1 byte = 8 bits)

Sector: Page unit in erase, programming and reading. (1 sector = 2,112 bytes = 16,896 bits)

Device: 1 device = 32,768 sectors.

HN29V102414T-50H

Package Dimensions

HN29V102414T-50H (TFP-48DA)

0.10

0.08 M

0.50

12.00

*0.22 ± 0.08

20.00 ± 0.20

0.05 ± 0.05

1.20 Max

18.40

0˚ – 8˚

124

12.40 Max

0.45 Max

*0.17 ± 0.05

0.50 ± 0.10

0.80

0.20 ± 0.06

0.125 ± 0.04

Hitachi Code

JEDEC

JEITA

Mass

(reference value)

TFP-48DA

Conforms

0.52 g

*Dimension including the plating thickness

Base material dimension

As of January, 2002

Unit: mm

HN29V102414T-50H

Cautions

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Hitachi bears no responsibility for problems that may arise with third party’s rights, including intellectual

property rights, in connection with use of the information contained in this document.

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received the latest product standards or specifications before final design, purchase or use.

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contact Hitachi’s sales office before using the product in an application that demands especially high

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bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic,

safety equipment or medical equipment for life support.

4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly for

maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and

other characteristics. Hitachi bears no responsibility for failure or damage when used beyond the

guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable failure rates or

failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the

equipment incorporating Hitachi product does not cause bodily injury, fire or other consequential damage

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5. This product is not designed to be radiation resistant.

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products.

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