a intel 2732A 32K (4K x 8) UV ERASABLE PROMS m 200 ns (2732A-2) Maximum Access m Low Current Requirement Time ... HMOS*-E Technology 100 mA Active = Compatible with High-Speed 35 mA Standby Microcontrollers and Microprocessors g@ inteligent Identifier Mode ... Zero WAIT State ~ Automatic Programming Operation @ Two Line Control m Industry Standard Pinout ... JEDEC m 10% Vcc Tolerance Available Approved 24 Pin Ceramic Package (See Packaging Spec. Order # 231369) The Intel 2732A is a 5V-only, 32,768-bit ultraviolet erasable (cerdip) Electrically Programmable Read-Only Memory (EPROM). The standard 2732A access time is 250 ns with speed selection (2732A-2) available at 200 ns. The access time is compatible with high performance microprocessors such as the 8 MHz iAPX 186. in these systems, the 2732A allows the microprocessor to operate without the addition of WAIT states. An important 2732A feature is Output Enable (OE) which is separate from the Chip Enable (CE) control. The OE control eliminates bus contention in microprocessor systems. The CE is used by the 2732A to place it ina standby mode (CE = VjH) which reduces power consumption without increasing access time. The standby mode reduces the current requirement by 65%; the maximum active current is reduced from 100 mA to a standby current of 35 mA. *HMOS is a patented process of Inte! Corporation. DATA OUTPUTS Voc o-+ 00-07 GND o+> ttt PROGRAM ul | | | | | Pin Names ENVep -| OEAND [-~ &&++ CELoGic [| oureur auerens Addresses _. 4 | Enable Ager: | =|_pecoven f2.| YGATING AOORESS | inpuTS | --1 = x 32,768-BIT ==] OECOOER | CELL MATRIX 290081 -1 Figure 1. Block Diagram 27512 | 27256 | 27128A arene 2716 2732A 2716 oan 27128A| 27256 | 27512 27C512| 27C256 | 27C 128 87064 rrr 87064 27128| 27C256 | 27C512 Ais Vep Vep Vee q 5 Voc Voc Vec Vec Ara | At2 | Ara | Ata ai aby, PGM} PGM | Aiq | Ata Az Az A; A7 | Az 7 ce Veco} N.C. | Aig Ais Ata Ag | As | As | As | As As? 2spite Ag | Aa | As | Aa | As As | As | As | As | As ss zp Ms Ag | Aa | Ao | Ao | Ao Ag Ag Ag Ag | Ag aq 21 PA Vep| Art | And Any Ay Ag | Ag | Ag | Aa | Ag Ass 20 FOE /Vpp OE} OE | CE | DE lOEVpp Ag Ap Ae Ao | Aa ade 19 Aro Aio| Aio | Ato Ato Aio Ay Ay Ay Ar | Ay M7 18 CE CE | cee | CE cE CE Ao | Ao | Ao | Ao | Ao ots 17 O7 | O7 | O7 | O7 | 07 Oo Oo Oo OQ | O% Sts 165) % Og | O O5 O5 Og 0; O71 O71 O; 0; 01 CJ 10 159 Os Os Os Os Os Os O2 Oo O2 O2 Oo Ot 14) % O4 O4 O4 O4 O4 GND GND GND GND | GND GND (12 1392 Os O3 O3 O03 O3 Og 290081-2 NOTE: Intel Universal Site compatible EPROM configurations are shown in the blocks adjacent to the 2732A pins. Figure 2. Cerdip Pin Configuration September 1989 5-9 Order Number: 290081-004intel 2732A EXTENDED TEMPERATURE (EXPRESS) EPROMs The Intel EXPRESS EPROM family is a series of electrically programmable read only memories which have received additional processing to enhance product characteristics. EXPRESS processing is available for several densities of EPROM, allowing the choice of appropriate memory size to match sys- tem applications. EXPRESS EPROM products are available with 168 +8 hour, 125C dynamic burn-in using Intels standard bias configuration. This pro- cess exceeds or meets most industry specifications of burn-in. The standard EXPRESS EPROM operat- ing temperature range is 0C to 70C. Extended op- erating temperature range (40C to + 85C) EX- PRESS products are available. Like all Intel EPROMs, the EXPRESS EPROM family is inspected to 0.1% electrical AQL. This may allow the user to reduce or eliminate incoming inspection testing. READ OPERATION D.C. CHARACTERISTICS Electrical Parameters of EXPRESS EPROM prod- ucts are identical to standard EPROM parameters except for: EXPRESS EPROM PRODUCT FAMILY PRODUCT DEFINITONS Type| Operating Temperature] Burn-in 125C (hr) Q 0C to + 70C 168 +8 T 40C to + 85C None L 40C to + 85C 168 +8 TD2732A Sym-| parameter | LD2732A Test bol Conditions Min | Max isp Voc Standby 45 CE = Vin, Current (mA) OE = Vit Voc Active FE FRE 1 =CE= lec, ) Current (mA) 150 | OE = CE = Vit Voc Active | OE = CE= Vi, Current at High 125 |Vpp = Voc, Temperature (mA) Tambient = 85C NOTE: 1. Maximum current value is with outputs Op to O7 unloaded. EXPRESS OPTIONS 2732A Versions Versions 2 25 47} 246 Veco Ag 2 231 Ag Ag C3 221) Ag A,Cy4 21D Ay MS ay52q 20 OE/Vor A,T6 19 FF Aig Avc7 ISDE Yee Yoo foo 8 17 wet 0, > reo 9 16 Pwenp 06 Oy reo 10 15 p}-we 05 Og beawaJ 11 14 Pre % Vss C412 13 PFW" 0s 290081 -3 OE/Vpp = +5V,R = 1K9, Voc = +5V Vss = GND, CE = GND Any 290081 -4 Binary Sequence from Ag to Aq4 Burn-in Bias and Timing Diagramsintel 2732A ABSOLUTE MAXIMUM RATINGS* Operating Temp. During Read ....... 0C to + 70C Temperature Under Bias......... 10C to + 80C Storage Temperature .......... 65C to + 125C Ail Input or Output Voltages with Respect to Ground.............. 0.3V to +6V Voltage on AQ with Respect to Ground ................0.. 0.3V to + 13.5V Vpp Supply Voltage with Respect to Ground During Programming ........... 0.3V to + 22V Voc Supply Voltage with Respect to Ground ............ 0.3V to + 7.0V READ OPERATION NOTICE: This is a production data sheet. The specifi- cations are subject to change without notice. *WARNING: Stressing the device beyond the Absolute Maximum Ratings may cause permanent damage. These are stress ratings only. Operation beyond the Operating Conditions is not recommended and ex- tended exposure beyond the Operating Conditions may affect device reliability. D.C. CHARACTERISTICS orc < Ty < +70C Symbol Parameter Limits Units Conditions Min Typ(3) Max lu Input Load Current 10 pA Vin = 5.5V ILo Output Leakage Current 10 pA Vout = 5.5V Ispl2) Vcc Current (Standby) 35 mA CE = Vip, OE = Vit locos 2 Vcc Current (Active) 100 mA OE = CE = Vit Vit Input Low Voltage 0.1 0.8 Vv Vin Input High Voltage 2.0 Voc + 1 Vv VoL Output Low Voltage 0.45 Vv lop = 2.1MA VoH Output High Voltage 2.4 Vv lon = 400 pA A.C. CHARACTERISTICS 0C < Ta < 70C Versions Voc +5% 2732A-2 2732A Test Vec 10% 2732A-20 2732A-25 Units Conditions Symbol Parameter Min Max | Min | Max tacc Address to Output Delay 200 250 ns CE = OF = Vi toe CE to Output Delay - 200 250 ns OE = ViL toe OE/Vpp to Output Delay 70 100 ns CE = Vit tor (4) OE/Vpp High to Output Float 60 60 ns CE = Vit tou{4) Output Hold from Addresses, 0 ns CE = OE = Vi CE or OE/Vpp, Whichever Occurred First NOTES: 1. Voc must be applied simultaneously or before OE/Vpp and removed simultaneously or after OE/Vpp. 2. The maximum current value is with outputs Og to O7 unloaded. 3. Typical values are for Ta = 25C and nominal supply voltages. 4. This parameter is only sampled and is not 100% tested. Output Float is defined as the point where data is no longer drivensee timing diagram.intel 2732A CAPACITANCE (2) T, = 25C, f = 1 MHz Symbol Parameter Typ Max Unit Conditions Cina Input Capacitance 4 6 pF Vin = OV Except OE/Vpp Cine OE/Vpp Input 20 pF Vin = OV Capacitance Cout Output Capacitance 8 12 pF Vout = OV A.C. TESTING INPUT/OUTPUT WAVEFORM A.C. TESTING LOAD CIRCUIT 1.3V 2.4 1N914 2.0 4y 2.0 INPUT TEST POINTS OUTPUT x 08 = - <