CD/74HC4051, CD54/74HCT4051, CD54/74HC4052, SCHS122J - NOVEMBER 1997 - REVISED FEBRUARY 2011 www.ti.com CD74HCT4052, CD54/74HC4053, CD54/74HC54053 HIGH-SPEED CMOS LOGIC ANALOG MULTIPLEXERS/DEMULTIPLEXERS Check for Samples: CD/74HC4051, CD54/74HCT4051, CD54/74HC4052, FEATURES 1 * * * * * * * * - Direct LSTTL Input Logic Compatibility VIL = 0.8 V Max, VIH = 2 V Min Wide Analog Input Voltage Range. . 5 V Max - CMOS Input Compatibility Low ON Resistance I 1 A at VOL, VOH I - 70 Typical (VCC - VEE = 4.5 V) - 40 Typical (VCC - VEE = 9 V) DESCRIPTION Low Crosstalk Between Switches These devices are digitally controlled analog switches Fast Switching and Propagation Speeds which utilize silicon gate CMOS technology to Break-Before-Make Switching achieve operating speeds similar to LSTTL with the low power consumption of standard CMOS integrated Wide Operating Temperature Range circuits. -55C to 125C These analog multiplexers/demultiplexers control CD54HC/CD74HC Types analog voltages that may vary across the voltage - Operation Control Voltage . . . . . . 2 V to 6 V supply range (i.e., VCC to VEE). They are bidirectional - Switch Voltage . . . . . . . . . . . . . . 0 V to 10 V switches thus allowing any analog input to be used as an output and vice-versa. The switches have low ON resistance and low OFF leakages. In addition, all CD54HCT/CD74HCT Types three devices have an enable control which, when - Operation Control Voltage . . . 4.5 V to 5.5 V high, disables all switches to their OFF state. - Switch Voltage . . . . . . . . . . . . . . . 0 V to 10 V ORDERING INFORMATION (1) TEMP. RANGE (C) PACKAGE CD54HC4051F3A -55 to 125 16 Ld CERDIP CD54HC4052F3A -55 to 125 16 Ld CERDIP CD54HC4053F3A -55 to 125 16 Ld CERDIP CD54HCT4051F3A -55 to 125 16 Ld CERDIP CD74HC4051E -55 to 125 16 Ld PDIP CD74HC4051M -55 to 125 16 Ld SOIC CD74HC4051MT -55 to 125 16 Ld SOIC CD74HC4051M96G3 -55 to 125 16 Ld SOIC CD74HC4051NSR -55 to 125 16 Ld SOP CD74HC4051PWR -55 to 125 16 Ld TSSOP CD74HC4051PWT -55 to 125 16 Ld TSSOP CD74HC4052E -55 to 125 16 Ld PDIP CD74HC4052M -55 to 125 16 Ld SOIC CD74HC4052MT -55 to 125 16 Ld SOIC CD74HC4052M96G3 -55 to 125 16 Ld SOIC CD74HC4052NSR -55 to 125 16 Ld SOP CD74HC4052PW -55 to 125 16 Ld TSSOP CD74HC4052PWR -55 to 125 16 Ld TSSOP PART NUMBER (1) When ordering, use the entire part number. The suffixes 96 and R denote tape and reel. The suffix T denotes a small-quantity reel of 250. 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. (c) 1997-2011, Texas Instruments Incorporated CD/74HC4051, CD54/74HCT4051, CD54/74HC4052, SCHS122J - NOVEMBER 1997 - REVISED FEBRUARY 2011 www.ti.com ORDERING INFORMATION(1) (continued) TEMP. RANGE (C) PACKAGE CD74HC4052PWT -55 to 125 16 Ld TSSOP CD74HC4053E -55 to 125 16 Ld PDIP CD74HC4053M -55 to 125 16 Ld SOIC CD74HC4053MT -55 to 125 16 Ld SOIC CD74HC4053M96G3 -55 to 125 16 Ld SOIC CD74HC4053NSR -55 to 125 16 Ld SOP CD74HC4053PW -55 to 125 16 Ld TSSOP CD74HC4053PWRG3 -55 to 125 16 Ld TSSOP CD74HC4053PWT -55 to 125 16 Ld TSSOP CD74HCT4051E -55 to 125 16 Ld PDIP CD74HCT4051M -55 to 125 16 Ld SOIC CD74HCT4051MT -55 to 125 16 Ld SOIC CD74HCT4051M96 -55 to 125 16 Ld SOIC CD74HCT4052E -55 to 125 16 Ld PDIP CD74HCT4052M -55 to 125 16 Ld SOIC CD74HCT4052MT -55 to 125 16 Ld SOIC CD74HCT4052M96 -55 to 125 16 Ld SOIC CDHCT4053E -55 to 125 16 Ld PDIP CDHCT4053M -55 to 125 16 Ld SOIC CDHCT4053MT -55 to 125 16 Ld SOIC CDHCT4053M96 -55 to 125 16 Ld SOIC CDHCT4053PWR -55 to 125 16 Ld TSSOP CDHCT4053PWT -55 to 125 16 Ld TSSOP PART NUMBER 2 Submit Documentation Feedback (c) 1997-2011, Texas Instruments Incorporated Product Folder Link(s): CD/74HC4051, CD54/74HCT4051, CD54/74HC4052, CD/74HC4051, CD54/74HCT4051, CD54/74HC4052, SCHS122J - NOVEMBER 1997 - REVISED FEBRUARY 2011 www.ti.com CD54HC4051, CD54HCT4051 (CERDIP) CD74HC4051 (PDIP, SOIC, SOP, TSSOP) CD74HCT4051 (PDIP, SOIC) TOP VIEW A4 1 16 VCC A6 2 15 A2 A 3 14 A1 A7 4 13 A0 A5 5 12 A3 E 6 11 S0 7 10 S1 GND 8 9 S2 CHANNEL IN/OUT COM OUT/IN CHANNEL IN/OUT VEE CD54HC4052 (CERDIP) CD74HC4052 (PDIP, SOIC, SOP, TSSOP) CD74HCT4052 (PDIP, SOIC) TOP VIEW CHANNEL IN/OUT B0 1 16 VCC B2 2 15 A2 3 14 A1 CHANNEL IN/OUT B3 4 13 AN COM OUT/IN B1 5 12 A0 E 6 11 A3 COM OUT/IN BN CHANNEL IN/OUT CHANNEL IN/OUT ADDRESS SELECT VEE 7 10 S0 GND 8 9 S1 CHANNEL IN/OUT CD54HC4053 (CERDIP) CD74HC4053 (PDIP, SOIC, SOP, TSSOP) CD74HCT4053 (PDIP, SOIC, TSSOP) TOP VIEW CHANNEL IN/OUT B1 1 16 VCC B0 2 15 BN COM OUT/IN C1 3 14 AN COM OUT/IN COM OUT/IN CN (c) 1997-2011, Texas Instruments Incorporated 4 13 A1 IN/OUT C0 5 12 A0 E 6 11 S0 VEE 7 10 S1 GND 8 9 S2 CHANNEL IN/OUT Submit Documentation Feedback Product Folder Link(s): CD/74HC4051, CD54/74HCT4051, CD54/74HC4052, 3 CD/74HC4051, CD54/74HCT4051, CD54/74HC4052, SCHS122J - NOVEMBER 1997 - REVISED FEBRUARY 2011 www.ti.com FUNCTIONAL DIAGRAM OF HC/HCT4051 CHANNEL IN/OUT VCC A7 A6 A5 A4 A3 A2 A1 A0 16 4 2 5 1 12 15 14 13 TG TG S0 11 TG S1 TG 10 BINARY TO 1 OF 8 DECODER WITH ENABLE LOGIC LEVEL CONVERSION S2 3 A COMMON OUT/IN TG 9 TG TG E 6 TG 8 7 GND VEE Table 1. TRUTH TABLE 'HC/CD74HCT4051 (1) INPUT STATES (1) 4 ON CHANNELS ENABLE S2 S1 S0 L L L L A0 L L L H A1 L L H L A2 L L H H A3 L H L L A4 L H L H A5 L H H L A6 L H H H A7 H X X X None X = Don't care Submit Documentation Feedback (c) 1997-2011, Texas Instruments Incorporated Product Folder Link(s): CD/74HC4051, CD54/74HCT4051, CD54/74HC4052, CD/74HC4051, CD54/74HCT4051, CD54/74HC4052, SCHS122J - NOVEMBER 1997 - REVISED FEBRUARY 2011 www.ti.com FUNCTIONAL DIAGRAM OF HC4052, CD74HCT4052 A CHANNELS IN/OUT VCC A3 A2 A1 A0 11 15 14 12 16 TG TG TG S1 S0 9 BINARY TO 1 OF 4 DECODER WITH ENABLE LOGIC LEVEL CONVERSION TG 13 COMMON A OUT/IN TG 3 COMMON B OUT/IN 10 TG E 6 TG TG 8 7 1 5 2 4 GND VEE B0 B1 B2 B3 B CHANNELS IN/OUT Table 2. FUNCTION TABLE 'HC4052, CD74HCT4052 (1) INPUT STATES (1) ON CHANNELS ENABLE S1 L L S0 L A0, B0 L L H A1, B1 L H L A2, B2 L H H A3, B3 H X X None X = Don't care (c) 1997-2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): CD/74HC4051, CD54/74HCT4051, CD54/74HC4052, 5 CD/74HC4051, CD54/74HCT4051, CD54/74HC4052, SCHS122J - NOVEMBER 1997 - REVISED FEBRUARY 2011 www.ti.com FUNCTIONAL DIAGRAM OF 'HC4053, CD74HCT4053 VCC LOGIC LEVEL CONVERSION 16 BINARY TO 1 OF 2 DECODERS WITH ENABLE IN/OUT C1 C0 B1 B0 A1 A0 3 5 1 2 13 12 TG S0 11 S1 10 14 A COMMON OUT/IN 15 B COMMON OUT/IN 4 C COMMON OUT/IN TG TG TG S2 TG 9 TG E 6 8 7 GND VEE Table 3. FUNCTION TABLE 'HC4053, CD74HCT4053 (1) INPUT STATES (1) 6 ON CHANNELS ENABLE S0 S1 S2 L L L L C0, B0, A0 L H L L C0, B0, A1 L L H L C0, B1, A0 L H H L C0, B1, A1 L L L H C1, B0, A0 L H L H C1, B0, A1 L L H H C1, B1, A0 L H H H C1, B1, A1 H X X X None X = Don't care Submit Documentation Feedback (c) 1997-2011, Texas Instruments Incorporated Product Folder Link(s): CD/74HC4051, CD54/74HCT4051, CD54/74HC4052, CD/74HC4051, CD54/74HCT4051, CD54/74HC4052, SCHS122J - NOVEMBER 1997 - REVISED FEBRUARY 2011 www.ti.com Absolute Maximum Ratings (1) (2) over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT VCC - VEE DC supply voltage -0.5 10.5 V VCC DC supply voltage -0.5 7 V VEE DC supply voltage 0.5 -7 V IIK DC input diode current VI < - 0.5 V or VI > VCC + 0.5 V 20 mA IOK DC switch diode current VI < VEE - 0.5 V or VI > VCC + 0.5 V 20 mA DC switch current VI > VEE - 0.5 V or VI < VCC + 0.5 V 25 mA 50 mA -20 mA ICC DC VCC or ground current IEE DC VEE current Package thermal impedance (3) JA E (PDIP) package 67 M (SOIC) package 73 NS (SOP) package 64 PW (TSSOP) package 108 Maximum junction temperature -65 Maximum storage temperature range Maximum lead temperature (soldering 10 s) (1) (2) (3) C/W 150 C 150 C 300 C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltages referenced to GND unless otherwise specified. The package thermal impedance is calculated in accordance with JESD 51-7. Recommended Operating Conditions For maximum reliability, nominal operating conditions should be selected so that operation is always within the following ranges. PARAMETER VCC (1) VCC - VEE VEE (2) MIN Supply voltage range (TA = full package temperature range) CD54/74HC types Supply voltage range (TA = full package temperature range) Supply voltage range (TA = full package temperature range) MAX UNIT 2 6 4.5 5.5 CD54/74HC types, CD54/74HCT types (see Figure 1) 2 10 V CD54/74HC types, CD54/74HCT types (see Figure 2) 0 -6 V GND VCC V CD54/74HCT types V VI DC input control voltage VIS Analog switch I/O voltage VEE VCC V TA Operating temperature -55 125 C 2V 0 1000 4.5 V 0 500 6V 0 400 tr, tf (1) (2) Input rise and fall times ns All voltages referenced to GND unless otherwise specified. In certain applications, the external load resistor current may include both VCC and signal line components. To avoid drawing VCC current when switch current flows into the transmission gate inputs, the voltage drop across the bidirectional switch must not exceed 0.6 V (calculated from rON values shown in Electrical Specifications table). No VCC current will flow through RL if the switch current flows into terminal 3 on the HC/HCT4051; terminals 3 and 13 on the HC/HCT4052; terminals 4, 14, and 15 on the HC/HCT4053. (c) 1997-2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): CD/74HC4051, CD54/74HCT4051, CD54/74HC4052, 7 CD/74HC4051, CD54/74HCT4051, CD54/74HC4052, SCHS122J - NOVEMBER 1997 - REVISED FEBRUARY 2011 www.ti.com Recommended Operating Area as a Function of Supply Voltages 8 6 VCC - GND (V) VCC - GND (V) 8 HCT HC 4 2 0 0 2 4 6 8 10 12 6 HCT HC 4 2 0 VCC - VEE (V) 0 -2 -4 -6 -8 VEE - GND (V) Figure 1. Figure 2. DC Electrical Specifications AMBIENT TEMPERATURE, TA TEST CONDITIONS 25C PARAMETER VIS (V) VI (V) VEE (V) VCC (V) MIN TYP MAX -40C to 85C -55C to 125C MIN MIN MAX UNIT MAX HC Types VIH VIL High-level input voltage Low-level input voltage VCC or VEE rON ON resistance IO = 1 mA (see Figure 11) VIL or VIH VCC to VEE rON Maximum ON resistance between any two channels 1 and 2 channels IIZ Switch ON/OFF leakage current For switch OFF: When VIS = VCC, VOS = VEE , 4053 When VIS = VEE, 4 channels VOS = VCC, For switch ON: 4052 All applicable 8 channels combinations of VIS and VOS 4051 voltage levels IIL Control input leakage current ICC Quiescent device current 8 IO = 0 VIL or VIH VCC or GND When VIS = VEE, VOS = VCC When VIS = VCC, VOS = VEE Submit Documentation Feedback VCC or GND 2 1.5 1.5 1.5 4.5 3.15 3.15 3.15 6 4.2 4.2 4.2 0 2 0.5 0.5 0.5 4.5 1.35 1.35 1.35 6 1.8 1.8 1.8 0 4.5 70 160 200 240 0 6 60 140 175 210 -4.5 4.5 40 120 150 180 0 4.5 90 180 225 270 0 6 80 160 200 240 -4.5 4.5 45 130 162 195 0 4.5 10 8.5 V V 0 6 -4.5 4.5 0 6 0.1 1 1 -5 5 0.1 1 1 0 6 0.1 1 1 -5 5 0.2 2 2 5 A 0 6 0.2 2 2 -5 5 0.4 4 4 0 6 0.1 1 1 A 0 6 8 80 160 A -5 5 16 160 320 A (c) 1997-2011, Texas Instruments Incorporated Product Folder Link(s): CD/74HC4051, CD54/74HCT4051, CD54/74HC4052, CD/74HC4051, CD54/74HCT4051, CD54/74HC4052, SCHS122J - NOVEMBER 1997 - REVISED FEBRUARY 2011 www.ti.com DC Electrical Specifications (Continued) AMBIENT TEMPERATURE, TA TEST CONDITIONS 25C PARAMETER VIS (V) VI (V) VEE (V) VCC (V) MIN TYP MAX -40C to 85C -55C to 125C MIN MIN MAX UNIT MAX HCT Types VIH High-level input voltage 4.5 to 5.5 VIL Low-level input voltage 4.5 to 5.5 0 VCC or VEE rON ON resistance IO = 1 mA (see Figure 15) VIL or VIH 4053 Switch ON/OFF leakage current IIZ 4 channels 4052 8 channels 4051 IIL Quiescent device current ICC (1) (2) For switch OFF: When VIS = VCC, VOS = VEE, When VIS = VEE, VOS = VCC For switch ON: All applicable combinations of VIS and VOS voltage levels (2) When VIS = VCC, VOS = VEE Additional quiescent device current per input pin: 1 unit load 0.8 0.8 0.8 4.5 70 160 200 240 -4.5 4.5 40 120 150 180 0 4.5 90 180 225 270 -4.5 4.5 45 130 162 195 0 4.5 10 -4.5 4.5 5 0 6 0.1 1 1 VIL or VIH -5 5 0.1 1 1 0 6 0.1 1 1 -5 5 0.2 2 2 0 6 0.2 2 2 -5 ICC (2) V VCC or GND VCC - 2.1 A 5 0.4 4 4 5.5 0.1 1 1 A 0 5.5 8 80 160 A -4.5 5.5 16 160 320 A 360 450 490 A (1) When VIS = VEE, VOS = VCC IO = 0 V - Control input leakage current ICC 2 - Maximum ON resistance between any two channels 1 and 2 channels 2 - VCC to VEE rON 2 4.5 to 5.5 100 Any voltage between VCC and GND For dual-supply systems, theoretical worst-case (VI = 2.4 V, VCC = 5.5 V) specification is 1.8 mA. (c) 1997-2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): CD/74HC4051, CD54/74HCT4051, CD54/74HC4052, 9 CD/74HC4051, CD54/74HCT4051, CD54/74HC4052, SCHS122J - NOVEMBER 1997 - REVISED FEBRUARY 2011 www.ti.com Table 4. HCT INPUT LOADING TABLE INPUT UNIT LOADS (1) 4051, 4053 All 0.5 4052 All 0.4 TYPE (1) Unit load is ICC limit specified in DC Specifications table, e.g., 360 mA MAX at 25C. Switching Specifications VCC = 5 V, TA = 25C, input tr, tf = 6 ns TYPICAL PARAMETER TEST CONDITIONS CL (pF) 4051 HC tPHL, tPLH tPHZ, tPLZ Propagation delay tPZH, tPZL CPD (1) 10 (1) 4052 HCT HC 4053 HCT HC UNIT HCT Switch IN to OUT 15 4 4 4 4 4 4 Switch turn-off (S or E) 15 19 19 21 21 18 18 Switch turn-on (S or E) 15 19 23 27 29 18 20 50 52 74 76 38 42 Power dissipation capacitance ns pF CPD is used to determine the dynamic power consumption, per package. PD = CPD VCC 2 fI + (CL + CS) VCC 2 fO fO = output frequency fI = input frequency CL = output load capacitance CS = switch capacitance VCC = supply voltage Submit Documentation Feedback (c) 1997-2011, Texas Instruments Incorporated Product Folder Link(s): CD/74HC4051, CD54/74HCT4051, CD54/74HC4052, CD/74HC4051, CD54/74HCT4051, CD54/74HC4052, SCHS122J - NOVEMBER 1997 - REVISED FEBRUARY 2011 www.ti.com Switching Specifications CL = 50 pF, input tr, tf = 6 ns AMBIENT TEMPERATURE, TA PARAMETER Propagation delay, switch in to out 4051 tPHZ, tPLZ Maximum switch turn OFF delay from S or E to switch output 4052 4053 4051 tPZL, tPZH Maximum switch turn ON delay from S or E to switch output 4052 4053 CI Input (control) capacitance (c) 1997-2011, Texas Instruments Incorporated -55C to 125C VEE (V) VCC (V) 0 2 60 0 4.5 12 0 6 10 -4.5 4.5 0 2 225 0 4.5 45 0 6 38 -4.5 4.5 32 0 2 250 0 4.5 50 0 6 43 -4.5 4.5 38 0 2 210 0 4.5 42 0 6 36 -4.5 4.5 29 0 2 225 0 4.5 45 0 6 38 -4.5 4.5 32 0 2 325 0 4.5 65 0 6 55 -4.5 4.5 46 0 2 220 0 4.5 44 0 6 37 -4.5 4.5 31 34 39 43 47 51 10 10 10 10 10 10 HC MIN tPLH, tPHL -40C to 85C 25C HCT MAX 8 MIN HC MAX MIN HCT MAX MIN HC MAX 75 12 15 10 15 56 10 40 56 63 40 48 63 53 48 36 55 56 39 40 69 81 49 58 68 55 48 75 75 57 ns 57 63 66 44 47 68 83 48 59 98 105 83 60 275 48 48 490 69 48 68 57 405 70 68 340 48 39 12 54 280 55 ns 315 45 31 12 65 265 44 18 375 54 38 18 57 315 50 MAX 340 48 32 MIN 15 280 45 MAX 90 13 8 MIN UNIT HCT 69 ns 72 330 60 47 66 72 56 Submit Documentation Feedback Product Folder Link(s): CD/74HC4051, CD54/74HCT4051, CD54/74HC4052, pF 11 CD/74HC4051, CD54/74HCT4051, CD54/74HC4052, SCHS122J - NOVEMBER 1997 - REVISED FEBRUARY 2011 www.ti.com Analog Channel Specifications Typical values at TA = 25C PARAMETER CI TEST CONDITIONS Switch input capacitance CCOM Common output capacitance HC/HCT TYPES fMAX See Figure 3 (1) (2) VCC (V) 4052 12 4053 8 4051 145 -2.25 2.25 200 4051 180 -4.5 4.5 (1) (2) (3) 12 See Figure 7 (2) (3) MHz 185 200 All -2.25 2.25 0.035 All -4.5 4.5 0.018 4051 -2.25 2.25 -73 % -65 -64 4053 4051 pF 165 4053 4052 Switch OFF signal feedthrough (see Figures 13, 15, 17) pF 5 25 4053 See Figure 5 UNIT All 4052 Sine-wave distortion HC/HCT 4051 4052 Minimum switch frequency response at -3 dB (see Figures 12, 14, 16) VEE (V) -4.5 4.5 -75 4052 -67 4053 -66 dB Adjust input voltage to obtain 0 dBm at VOS for fIN = 1 MHz VIS is centered at (VCC - VEE)/2. Adjust input for 0 dBm Submit Documentation Feedback (c) 1997-2011, Texas Instruments Incorporated Product Folder Link(s): CD/74HC4051, CD54/74HCT4051, CD54/74HC4052, CD/74HC4051, CD54/74HCT4051, CD54/74HC4052, SCHS122J - NOVEMBER 1997 - REVISED FEBRUARY 2011 www.ti.com APPLICATION INFORMATION VCC VCC 0.1F VI = VIH VOS SWITCH ON VIS 10pF 50 SINE- WAVE VIS dB METER 10F VIS SWITCH ON VOS 10k 50pF VCC /2 VCC /2 fIS = 1kHz TO 10kHz Figure 3. Frequency Response Test Circuit DISTORTION METER Figure 5. Sine-Wave Distortion Test Circuit VCC VIS R 0.1F INPUT E SWITCH ON VOS1 R VCC C 600 fIS = 1MHz SINEWAVE R = 50 C = 10pF VCC /2 VCC /2 VCC R VCC /2 SWITCH OFF VOS2 R SWITCH ALTERNATING ON AND OFF tr, tf 6ns fCONT = 1MHz 50% DUTY CYCLE VOS 600 50pF SCOPE VCC /2 Figure 6. Control to Switch Feedthrough Noise Test Circuit dB METER C VP-P VOS VCC /2 Figure 4. Crosstalk Between Two Switches Test Circuit fIS 1MHz SINEWAVE R = 50 C = 10pF VCC VC = VIL 0.1F VOS SWITCH OFF VIS R R VCC /2 VCC /2 C dB METER Figure 7. Switch OFF Signal Feedthrough (c) 1997-2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): CD/74HC4051, CD54/74HCT4051, CD54/74HC4052, 13 CD/74HC4051, CD54/74HCT4051, CD54/74HC4052, SCHS122J - NOVEMBER 1997 - REVISED FEBRUARY 2011 www.ti.com APPLICATION INFORMATION VCC tr = 6ns tf = 6ns 90% 50% 10% SWITCH INPUT tPLH tPHL VEE 90% 50% 10% SWITCH OUTPUT FIGURE 8A. 6ns 6ns 90% E OR Sn tr 6ns 50% E OR Sn 10% tPLZ tPLZ 10% tPHZ OUTPUT LOW TO OFF tPZH OUTPUT HIGH TO OFF 50% SWITCH OFF SWITCH ON SWITCH ON FIGURE 8B. HC TYPES GND tPZL 50% 10% tPHZ 90% 3V 0.3 GND 50% 6ns 2.7 1.3 tPZL OUTPUT LOW TO OFF tf VCC tPZH 90% OUTPUT HIGH TO OFF 50% SWITCH OFF SWITCH ON SWITCH ON FIGURE 8C. HCT TYPES Figure 8. Switch Propagation Delay, Turn-On, Turn-Off Times VEE FOR tPLZ AND t PZL VCC FOR tPHZ AND t PZH RL = 1k VCC FOR tPLZ AND t PZL CL 50pF VEE FOR tPHZ AND t PZH TG IN OUT Figure 9. Switch ON/OFF Propagation Delay Test Circuit 14 Submit Documentation Feedback IN OUT TG 50pF Figure 10. Switch In to Switch Out Propagation Delay Test Circuit (c) 1997-2011, Texas Instruments Incorporated Product Folder Link(s): CD/74HC4051, CD54/74HCT4051, CD54/74HC4052, CD/74HC4051, CD54/74HCT4051, CD54/74HC4052, SCHS122J - NOVEMBER 1997 - REVISED FEBRUARY 2011 www.ti.com TYPICAL PERFORMANCE CURVES 120 0 VCC = 4.5V GND = -4.5V VEE = -4.5V RL = 50 PIN 4 TO 3 -2 80 VCC - VEE = 4.5V -4 60 VCC = 2.25V GND = -2.25V VEE = -2.25V RL = 50 PIN 4 TO 3 dB ON RESISTANCE () 100 VCC - VEE = 6V 40 -6 VCC - VEE = 9V 20 -8 1 2 3 4 5 6 INPUT SIGNAL VOLTAGE (V) 7 8 9 Figure 11. Typical ON Resistance vs Input Signal Voltage -10 10K 100K 1M FREQUENCY (Hz) 10M 100M Figure 14. Channel ON Bandwidth (HC/HCT4052) 0 0 VCC = 4.5V GND = -4.5V VEE = -4.5V RL = 50 PIN 12 TO 3 -2 VCC = 2.25V GND = -2.25V VEE = -2.25V RL = 50 PIN 4 TO 3 -20 -40 -4 -6 dB dB VCC = 2.25V GND = -2.25V VEE = -2.25V RL = 50 PIN 12 TO 3 -60 VCC = 4.5V GND = -4.5V VEE = -4.5V RL = 50 PIN 4 TO 3 -80 -8 -10 10K 100K 1M FREQUENCY (Hz) 10M 100M -100 10K 100K 1M FREQUENCY (Hz) 10M 100M Figure 15. Channel OFF Feedthrough (HC/HCT4052) Figure 12. Channel ON Bandwidth (HC/HCT4051) 0 0 -20 VCC = 2.25V GND = -2.25V VEE = -2.25V RL = 50 PIN 12 TO 3 -60 VCC = 4.5V GND = -4.5V VEE = -4.5V RL = 50 PIN 12 TO 3 -80 -100 10K VCC = 4.5V GND = -4.5V VEE = -4.5V RL = 50 PIN 5 TO 4 -1 dB dB -40 -2 VCC = 2.25V GND = -2.25V VEE = -2.25V RL = 50 PIN 5 TO 4 -3 -4 100K 1M 10M FREQUENCY (Hz) Figure 13. Channel OFF Feedthrough (HC/HCT4051) (c) 1997-2011, Texas Instruments Incorporated 100M 10K 100K 1M FREQUENCY (Hz) 10M 100M Figure 16. Channel ON Bandwidth (HC/HCT4053) Submit Documentation Feedback Product Folder Link(s): CD/74HC4051, CD54/74HCT4051, CD54/74HC4052, 15 CD/74HC4051, CD54/74HCT4051, CD54/74HC4052, SCHS122J - NOVEMBER 1997 - REVISED FEBRUARY 2011 www.ti.com TYPICAL PERFORMANCE CURVES 0 VCC = 2.25V GND = -2.25V VEE = -2.25V RL = 50 PIN 5 TO 4 -20 dB -40 VCC = 4.5V GND = -4.5V VEE = -4.5V RL = 50 PIN 5 TO 4 -60 -80 -100 10K 100K 1M FREQUENCY (Hz) 10M 100M Figure 17. Channel OFF Feedthrough (HC/HCT4053) 16 Submit Documentation Feedback (c) 1997-2011, Texas Instruments Incorporated Product Folder Link(s): CD/74HC4051, CD54/74HCT4051, CD54/74HC4052, PACKAGE OPTION ADDENDUM www.ti.com 18-Oct-2013 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (C) Device Marking (4/5) 5962-8775401EA ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type -55 to 125 5962-8775401EA CD54HC4053F3A 5962-8855601EA ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type -55 to 125 5962-8855601EA CD54HC4052F3A 5962-9065401MEA ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type -55 to 125 5962-9065401ME A CD54HCT4051F3A CD54HC4051F ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type -55 to 125 CD54HC4051F CD54HC4051F3A ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type -55 to 125 CD54HC4051F3A CD54HC4052F ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type -55 to 125 CD54HC4052F CD54HC4052F3A ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type -55 to 125 5962-8855601EA CD54HC4052F3A CD54HC4053F ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type -55 to 125 CD54HC4053F CD54HC4053F3A ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type -55 to 125 5962-8775401EA CD54HC4053F3A CD54HCT4051F3A ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type -55 to 125 5962-9065401ME A CD54HCT4051F3A CD74HC4051E ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type -55 to 125 CD74HC4051E CD74HC4051EE4 ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type -55 to 125 CD74HC4051E CD74HC4051M ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HC4051M CD74HC4051M96 ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU | CU SN Level-1-260C-UNLIM -55 to 125 HC4051M CD74HC4051M96E4 ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HC4051M CD74HC4051M96G3 ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -55 to 125 HC4051M CD74HC4051M96G4 ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HC4051M Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com Orderable Device 18-Oct-2013 Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (C) Device Marking (4/5) CD74HC4051ME4 ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HC4051M CD74HC4051MG4 ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HC4051M CD74HC4051MT ACTIVE SOIC D 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HC4051M CD74HC4051MTE4 ACTIVE SOIC D 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HC4051M CD74HC4051MTG4 ACTIVE SOIC D 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HC4051M CD74HC4051NSR ACTIVE SO NS 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HC4051M CD74HC4051NSRE4 ACTIVE SO NS 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HC4051M CD74HC4051NSRG4 ACTIVE SO NS 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HC4051M CD74HC4051PWR ACTIVE TSSOP PW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU | CU SN Level-1-260C-UNLIM -55 to 125 HJ4051 CD74HC4051PWRE4 ACTIVE TSSOP PW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HJ4051 CD74HC4051PWRG4 ACTIVE TSSOP PW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HJ4051 CD74HC4051PWT ACTIVE TSSOP PW 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HJ4051 CD74HC4051PWTE4 ACTIVE TSSOP PW 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HJ4051 CD74HC4051PWTG4 ACTIVE TSSOP PW 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HJ4051 CD74HC4052E ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type -55 to 125 CD74HC4052E CD74HC4052EE4 ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type -55 to 125 CD74HC4052E CD74HC4052M ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HC4052M CD74HC4052M96 ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU | CU SN Level-1-260C-UNLIM -55 to 125 HC4052M Addendum-Page 2 Samples PACKAGE OPTION ADDENDUM www.ti.com Orderable Device 18-Oct-2013 Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (C) Device Marking (4/5) CD74HC4052M96E4 ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HC4052M CD74HC4052M96G4 ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HC4052M CD74HC4052ME4 ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HC4052M CD74HC4052MG4 ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HC4052M CD74HC4052MT ACTIVE SOIC D 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HC4052M CD74HC4052MTE4 ACTIVE SOIC D 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HC4052M CD74HC4052MTG4 ACTIVE SOIC D 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HC4052M CD74HC4052NSR ACTIVE SO NS 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HC4052M CD74HC4052NSRE4 ACTIVE SO NS 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HC4052M CD74HC4052NSRG4 ACTIVE SO NS 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HC4052M CD74HC4052PW ACTIVE TSSOP PW 16 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HJ4052 CD74HC4052PWE4 ACTIVE TSSOP PW 16 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HJ4052 CD74HC4052PWG4 ACTIVE TSSOP PW 16 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HJ4052 CD74HC4052PWR ACTIVE TSSOP PW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU | CU SN Level-1-260C-UNLIM -55 to 125 HJ4052 CD74HC4052PWRE4 ACTIVE TSSOP PW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HJ4052 CD74HC4052PWRG4 ACTIVE TSSOP PW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HJ4052 CD74HC4052PWT ACTIVE TSSOP PW 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HJ4052 CD74HC4052PWTE4 ACTIVE TSSOP PW 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HJ4052 Addendum-Page 3 Samples PACKAGE OPTION ADDENDUM www.ti.com Orderable Device 18-Oct-2013 Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (C) Device Marking (4/5) CD74HC4052PWTG4 ACTIVE TSSOP PW 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HJ4052 CD74HC4053E ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type -55 to 125 CD74HC4053E CD74HC4053EE4 ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type -55 to 125 CD74HC4053E CD74HC4053M ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HC4053M CD74HC4053M96 ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU | CU SN Level-1-260C-UNLIM -55 to 125 HC4053M CD74HC4053M96E4 ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HC4053M CD74HC4053M96G3 ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -55 to 125 HC4053M CD74HC4053M96G4 ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HC4053M CD74HC4053ME4 ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HC4053M CD74HC4053MG4 ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HC4053M CD74HC4053MT ACTIVE SOIC D 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HC4053M CD74HC4053MTE4 ACTIVE SOIC D 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HC4053M CD74HC4053MTG4 ACTIVE SOIC D 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HC4053M CD74HC4053NSR ACTIVE SO NS 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HC4053M CD74HC4053NSRG4 ACTIVE SO NS 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HC4053M CD74HC4053PW ACTIVE TSSOP PW 16 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HJ4053 CD74HC4053PWE4 ACTIVE TSSOP PW 16 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HJ4053 CD74HC4053PWG4 ACTIVE TSSOP PW 16 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HJ4053 Addendum-Page 4 Samples PACKAGE OPTION ADDENDUM www.ti.com Orderable Device 18-Oct-2013 Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (C) Device Marking (4/5) CD74HC4053PWR ACTIVE TSSOP PW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU | CU SN Level-1-260C-UNLIM -55 to 125 HJ4053 CD74HC4053PWRE4 ACTIVE TSSOP PW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HJ4053 CD74HC4053PWRG4 ACTIVE TSSOP PW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HJ4053 CD74HC4053PWT ACTIVE TSSOP PW 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HJ4053 CD74HC4053PWTE4 ACTIVE TSSOP PW 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HJ4053 CD74HC4053PWTG4 ACTIVE TSSOP PW 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HJ4053 CD74HCT4051E ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type -55 to 125 CD74HCT4051E CD74HCT4051EE4 ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type -55 to 125 CD74HCT4051E CD74HCT4051M ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HCT4051M CD74HCT4051M96 ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HCT4051M CD74HCT4051M96E4 ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HCT4051M CD74HCT4051M96G4 ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HCT4051M CD74HCT4051ME4 ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HCT4051M CD74HCT4051MG4 ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HCT4051M CD74HCT4051MT ACTIVE SOIC D 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HCT4051M CD74HCT4051MTE4 ACTIVE SOIC D 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HCT4051M CD74HCT4051MTG4 ACTIVE SOIC D 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HCT4051M CD74HCT4052E ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type -55 to 125 CD74HCT4052E Addendum-Page 5 Samples PACKAGE OPTION ADDENDUM www.ti.com Orderable Device 18-Oct-2013 Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (C) Device Marking (4/5) CD74HCT4052EE4 ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type -55 to 125 CD74HCT4052E CD74HCT4052M ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HCT4052M CD74HCT4052M96 ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HCT4052M CD74HCT4052M96E4 ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HCT4052M CD74HCT4052M96G4 ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HCT4052M CD74HCT4052ME4 ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HCT4052M CD74HCT4052MG4 ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HCT4052M CD74HCT4052MT ACTIVE SOIC D 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HCT4052M CD74HCT4052MTE4 ACTIVE SOIC D 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HCT4052M CD74HCT4052MTG4 ACTIVE SOIC D 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HCT4052M CD74HCT4053E ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type -55 to 125 CD74HCT4053E CD74HCT4053EE4 ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type -55 to 125 CD74HCT4053E CD74HCT4053M ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HCT4053M CD74HCT4053M96 ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HCT4053M CD74HCT4053M96E4 ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HCT4053M CD74HCT4053M96G4 ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HCT4053M CD74HCT4053ME4 ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HCT4053M CD74HCT4053MG4 ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HCT4053M Addendum-Page 6 Samples PACKAGE OPTION ADDENDUM www.ti.com Orderable Device 18-Oct-2013 Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (C) Device Marking (4/5) CD74HCT4053MT ACTIVE SOIC D 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HCT4053M CD74HCT4053MTE4 ACTIVE SOIC D 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HCT4053M CD74HCT4053MTG4 ACTIVE SOIC D 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HCT4053M CD74HCT4053PWR ACTIVE TSSOP PW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU | CU SN Level-1-260C-UNLIM -55 to 125 HK4053 CD74HCT4053PWRE4 ACTIVE TSSOP PW 16 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HK4053 CD74HCT4053PWRG4 ACTIVE TSSOP PW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HK4053 CD74HCT4053PWT ACTIVE TSSOP PW 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HK4053 CD74HCT4053PWTE4 ACTIVE TSSOP PW 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HK4053 CD74HCT4053PWTG4 ACTIVE TSSOP PW 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HK4053 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Addendum-Page 7 Samples PACKAGE OPTION ADDENDUM www.ti.com (4) 18-Oct-2013 There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. 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OTHER QUALIFIED VERSIONS OF CD54HC4051, CD54HC4052, CD54HC4053, CD54HCT4051, CD74HC4051, CD74HC4052, CD74HC4053, CD74HCT4051 : * Catalog: CD74HC4051, CD74HC4052, CD74HC4053, CD74HCT4051 * Automotive: CD74HC4051-Q1, CD74HCT4051-Q1, CD74HC4051-Q1, CD74HCT4051-Q1 * Enhanced Product: CD74HC4051-EP, CD74HC4051-EP * Military: CD54HC4051, CD54HC4052, CD54HC4053, CD54HCT4051 NOTE: Qualified Version Definitions: * Catalog - TI's standard catalog product * Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects * Enhanced Product - Supports Defense, Aerospace and Medical Applications * Military - QML certified for Military and Defense Applications Addendum-Page 8 PACKAGE MATERIALS INFORMATION www.ti.com 11-Oct-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant CD74HC4051M96 SOIC D 16 2500 330.0 16.8 6.5 10.3 2.1 8.0 16.0 Q1 CD74HC4051M96G3 SOIC D 16 2500 330.0 16.8 6.5 10.3 2.1 8.0 16.0 Q1 CD74HC4051M96G4 SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1 CD74HC4051PWR TSSOP PW 16 2000 330.0 12.4 7.0 5.6 1.6 8.0 12.0 Q1 CD74HC4051PWRG4 TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 CD74HC4051PWT TSSOP PW 16 250 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 CD74HC4052M96 SOIC D 16 2500 330.0 16.8 6.5 10.3 2.1 8.0 16.0 Q1 CD74HC4052M96G4 SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1 CD74HC4052NSR SO NS 16 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1 CD74HC4052PWR TSSOP PW 16 2000 330.0 12.4 7.0 5.6 1.6 8.0 12.0 Q1 CD74HC4052PWRG4 TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 CD74HC4052PWT TSSOP PW 16 250 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 CD74HC4053M96 SOIC D 16 2500 330.0 16.8 6.5 10.3 2.1 8.0 16.0 Q1 CD74HC4053M96G3 SOIC D 16 2500 330.0 16.8 6.5 10.3 2.1 8.0 16.0 Q1 CD74HC4053M96G4 SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1 CD74HC4053PWR TSSOP PW 16 2000 330.0 12.4 7.0 5.6 1.6 8.0 12.0 Q1 CD74HC4053PWRG4 TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 CD74HC4053PWT TSSOP PW 16 250 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 11-Oct-2013 Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant CD74HCT4051M96 SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1 CD74HCT4052M96 SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1 CD74HCT4053M96 SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1 CD74HCT4053PWR TSSOP PW 16 2000 330.0 12.4 7.0 5.6 1.6 8.0 12.0 Q1 CD74HCT4053PWRG4 TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 CD74HCT4053PWT TSSOP PW 16 250 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) CD74HC4051M96 SOIC D 16 2500 364.0 364.0 27.0 CD74HC4051M96G3 SOIC D 16 2500 364.0 364.0 27.0 CD74HC4051M96G4 SOIC D 16 2500 333.2 345.9 28.6 CD74HC4051PWR TSSOP PW 16 2000 364.0 364.0 27.0 CD74HC4051PWRG4 TSSOP PW 16 2000 367.0 367.0 35.0 CD74HC4051PWT TSSOP PW 16 250 367.0 367.0 35.0 CD74HC4052M96 SOIC D 16 2500 364.0 364.0 27.0 CD74HC4052M96G4 SOIC D 16 2500 333.2 345.9 28.6 CD74HC4052NSR SO NS 16 2000 367.0 367.0 38.0 CD74HC4052PWR TSSOP PW 16 2000 364.0 364.0 27.0 CD74HC4052PWRG4 TSSOP PW 16 2000 367.0 367.0 35.0 Pack Materials-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 11-Oct-2013 Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) CD74HC4052PWT TSSOP PW 16 250 367.0 367.0 35.0 CD74HC4053M96 SOIC D 16 2500 364.0 364.0 27.0 CD74HC4053M96G3 SOIC D 16 2500 364.0 364.0 27.0 CD74HC4053M96G4 SOIC D 16 2500 333.2 345.9 28.6 CD74HC4053PWR TSSOP PW 16 2000 364.0 364.0 27.0 CD74HC4053PWRG4 TSSOP PW 16 2000 367.0 367.0 35.0 CD74HC4053PWT TSSOP PW 16 250 367.0 367.0 35.0 CD74HCT4051M96 SOIC D 16 2500 333.2 345.9 28.6 CD74HCT4052M96 SOIC D 16 2500 333.2 345.9 28.6 CD74HCT4053M96 SOIC D 16 2500 333.2 345.9 28.6 CD74HCT4053PWR TSSOP PW 16 2000 364.0 364.0 27.0 CD74HCT4053PWRG4 TSSOP PW 16 2000 367.0 367.0 35.0 CD74HCT4053PWT TSSOP PW 16 250 367.0 367.0 35.0 Pack Materials-Page 3 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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