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Am29DL642G
Data Sheet
PRELIMINARY
This Data Sheet st ates AMD’s curr ent tech nical spec ifications reg arding the Product s describ ed herein. This Data
Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. Publication# 26503 Rev: BAmendment/+1
Issue Date: Spetember 5, 2002
Refer to AMD
’
s Website (www.amd.com) for the latest information.
Am29DL642G
128 Megabit (8 M x 16-Bit) CMOS 3.0 Volt-only
Simultaneous Read/Write Flash Memory
DISTINCTIVE CHARACTERISTICS
■Two 64 Megabit (Am29DL640G ) in a single 63-ball 12
x 11 mm Fine-pitch BGA package (features are
described herein for each inte rnal Am29DL640G)
■Two Chip Ena ble inpu ts
— Two CE# inputs to control selection of each internal
Am29DL640G devices
■Single power supply operation
— 2.7 to 3.6 v olt read, erase, and program operations
■Simultaneous Read/Write op erations
— Data can be continuously read from one bank while
executing erase/program functions in another bank.
— Zero latency between read and write operations
■Flexible BankTM architecture
— Read may occur in any of the three banks not being
written or erased.
— Four banks may be grouped by customer to achieve
desired bank divisions.
■Boot Sectors
— Top and bottom boot sectors in the same device
— Any combination of s ectors can be erased
■SecSi™ (Secured Silicon) Sector SecSiTM (Secured
Silicon) Sector: Extra 256 Byte sector
—Factory locked and identifiable: 16 bytes available for
secure, random factory Electronic Serial Number;
verifiable as factory loc ked through autoselect
function. ExpressFlash option all o ws entire sector to
be available for factory-secured data
—Cus tomer lock able: One-time programmable only.
Once locked, data cannot be changed
■High performance
— 70 or 90 ns access time
■Manufactured on 0.17 µm process technol ogy
■CFI (Common Flash Interface) compliant
— Provides device-specific information to the system,
allowing host so ftware to easily reconfigure for
different Flash devices
■Ultra low power consumption (typical values at 3.0 V,
5 MHz) for the part
— 10 mA typical active read current
— 15 mA typical erase/program current
— 400 nA typical standby mode current
■Flexible sect or architec ture
— Two hundred fifty-six 32 Kword sectors
■Compatibility with JEDEC standards
— Except for the added CE2#, the Fine-pitch B GA is
pinout and software compatible w ith single-power
supply Flash
— Sup erio r inadvertent wr ite protection
■Minimum 1 m illion erase cycle guarantee per sector
■63-ball Fine-pitch BGA Package
SOFTWARE FEATURES
■Data Management Software (DMS)
— AMD-supplied software manages data programming,
enabling EEPROM emulation
— Eases historical sector erase flash limitations
■Suppo rts Commo n Flash Memory Interface (CFI)
■Erase Suspend/Erase Resume
— Suspends erase operations to allow reading from
other sectors in s ame bank
■Data# Polling and Toggle Bits
— Provides a software method of detecting the status of
program or erase cycles
■Unlock Bypass Program command
— Reduc es overall programming time when issuing
multiple program command sequences
HARDWARE FEATURES
■Ready/Busy# output (RY/BY#)
— Hardware method for detec ting program or erase
cycle completion
■Hardware reset pin (RESET#)
— Hardware method of resetting the internal state
machine to the read mode
■WP#/ACC input pin
— Write protect (WP#) function protects sectors 0, 1,
140, and 141, regardless of sector protect status
— Acceleration (ACC) function accelerates program
timing
■Sector protection
— Hardware method of locking a sector, either
in-system or using programming equipment, to
prevent any program or erase operation within that
sector
— Temporary Sector Unprotect allows changing data in
protected sectors in-system
2 Am29DL642G Spetember 5, 2002
PRELIMINARY
GENERAL DESCRIPTION
The Am29DL642G is a 128 Mbit, 3.0 Volt (2.7 V to 3.6 V)
that combines two Am29DL640G single power supply
fla sh mem ory devic es in a sin gle 63 -bal l Fo rtifi ed BG A
pac ka ge. Each Am 29 DL 64 0G i s a 64 Mbit , 3.0 Volt ( 2. 7 V
to 3.6 V) device organized as 4,194,304 words. Data ap-
pears on DQ15- DQ0. T he device is des igned t o be pr o-
grammed in-system with the standard system 3.0 volt
VCC supply. A 12.0 volt VPP is not required for p rogram or
erase operations. The Am29DL642G is equipped with
two CE# inputs for flexible selection between the two in-
ternal 64 Mb devices. The device can also be pro-
gra mmed in stan dard EPR OM pro gr amme rs.
The Am29DL642G offers an access time of 70 or 90 ns.
To eliminate bus contention the Am29DL642G device
has two separate chip enables (CE# and CE2#). Each
chip enable (CE# or CE2#) is connected to only one of
the tw o dice i n the Am 29DL642G package. To the sys-
tem, this device will be the same as tw o independent
Am29DL640G on the same board. The only difference
is that they are now packaged together to reduce
board spac e.
Each device requires only a single 3.0 Volt power sup-
ply (2.7 V to 3.6 V) for both read and write functions. In-
ter nally ge nerated and regu lated v oltage s are pro vided
for the progra m and erase oper ations.
Simul taneo us Read /Write Oper ations with
Zero Latency
The Simu ltaneou s Read/ Writ e archit ecture provide s si-
multaneous operati on by div i di ng the me mo ry sp ac e of
each Am29DL640G device into fou r banks , two 8 Mb
banks with small and large sectors, and two 24 Mb banks
of large sectors. Sector addresses are fixed, system soft-
ware can be used to form user-defined bank groups.
During an Erase/Prog ram operation, any of the three
non-busy banks may be read from. Note that only two
banks can operate simultaneously. The device can im-
prove overall system performance by allowing a host sys-
tem to pr ogram or erase i n one bank, the n immediate ly
and simu ltaneo usly read from the other ban k, with zero
latency. This releases the system from waiting for the
completion of program or erase operations.
Each Am29DL640G can be organized as both a top and
bottom boot sector configuration.
Am29DL642G Features
The S ecSi™ (Sec ured S ilicon) Se ctor is an extra 256
by te sec to r cap abl e of be in g per m an ently loc ked by AMD
or customers. The SecSi Indicator Bit (DQ7) is perma-
nently set to a 1 if the part is factory locked, and set to a
0 if customer l ocka ble. This way, customer lockable
parts can never be used to replace a factory locked part.
Factory locked parts provide several options. The SecSi
Sector may stor e a sec ure, random 16 byte ESN ( Elec-
tronic Serial Number), customer code (programmed
through AMD’s ExpressFlash service), or both. Customer
Lockable parts may utilize the SecSi Sector as bonus
space, reading and writing like any other flash sector, or
may permanently lock their own code there.
DMS (Data Ma nagemen t Softw are) allows systems to
eas ily tak e adva nta ge o f the a dvan c ed arch i tecture of the
simultaneous read/write product line by allowing removal
of EEPROM devices. DMS will also allow the system
software to be simplified, as it will perform all functions
necessary to modify data in file structures, as opposed to
single-byte modifications. To write or update a particular
piece of data (a phone number or configuration data, for
example), the user only needs to state which piece of
data is to be updated, and where the updated data is lo-
cat ed in the syste m. This is an ad vant age compar ed to
systems where user-written s oftware must keep track of
the ol d da ta locati o n, statu s, l o gical to p hysical tr an slati on
of the data on to the Flas h memor y device (or memory d e-
vices), and more. Using DMS, user-written software does
not need to interf ace with the Flash memory directly. In-
stea d, t he user 's s o ftwar e acces se s the F las h me mo ry b y
calling one of only six functions. AMD provides this soft-
ware t o si mplify s ystem de sign an d softwar e int egration
efforts.
The de vice offers comple te comp atibility wi th the JEDEC
single-power-supply Flash command set standard.
Commands are written to the command register using
standard microprocessor write timings. Reading data out
of the device is sim ilar t o reading from other Flash or
EPROM devices.
The host system can detect whether a program or erase
operation is complete by using the device status bits :
RY/BY# pin, DQ7 (D ata# Polling) and DQ6/DQ2 (toggl e
bits). After a program or erase cycle has been com-
plet ed, the device auto matically returns to the read mode.
The secto r e rase a rch it ec ture allows memory sectors to
be er ased and reprogrammed w ithout affecting the dat a
con ten ts of oth er sectors . T he de v ice is fu lly e ra sed w hen
shipped from the factory.
Ha rdware dat a prote ction measures include a low VCC
detec tor that auto matically inhi bits write operations dur-
ing power t ransitions. The har dware sector p rotection
feature disables both program and erase operations in
any comb inati on of the se ctors of me mory. This can b e
achieved in-system or via programming equipment.
The device offers two power-s aving features. When ad-
dresses have been stable for a specified amount of time,
the d evic e e nters the a utomati c sl eep m ode. Th e sy s-
tem can a lso pla ce the devi ce into t he standby mode.
Power consumption is greatly reduced in both modes.
Bank Megabits Sector Sizes
Bank 1 8 Mb Eight 4 Kword,
Fifteen 32 Kword
Bank 2 24 Mb Forty-eight 32 Kword
Bank 3 24 Mb Forty-eight 32 Kword
Bank 4 8 Mb Eight 4 Kword,
Fifteen 32 Kword
Spetember 5, 2002 Am29DL642G 3
PRELIMINARY
TABLE OF CONTENTS
Dis tinct i v e Ch a r a c t e r is tics . . . . . . . . . . . . . . . . . . 1
General Descrip tion . . . . . . . . . . . . . . . . . . . . . . . . 2
Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 4
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Connection Diagram . . . . . . . . . . . . . . . . . . . . . . . . 6
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 8
Device Bus Operations . . . . . . . . . . . . . . . . . . . . . . 9
Table 1. Am29DL642G Device Bus Operations ................................9
Requirements for Reading Array Data ..................................... 9
Writing Commands/Command Sequences .............................. 9
Accelerated Program Operation ............................................. 10
Autoselect Functions .............................................................. 10
Simultaneous Read/Write Operations with Zero Latency ....... 10
Standby Mode ........................................................................ 10
Automatic Sleep Mode ........................................................... 10
RESET#: Hardware Reset Pin ............................................... 10
Output Disable Mode .............................................................. 11
Table 2. Am29DL642G Sector Architecture ....................................11
Table 4. Bank Address ....................................................................17
SecSiTM Sector Addresses............................................................. 17
Autoselect Mode ..................................................................... 17
Table 6. Am29DL642G Autoselect Codes, (High Voltage Method) 18
Sector/Sector Block Protection and Unprotection .................. 19
Table 7. Am29DL642G Boot Sector/Sector Block Addresses for Pro-
tection/Unprotection ........................................................................19
Write Protect (WP#) ................................................................ 20
Table 8. WP#/ACC Modes ..............................................................20
Temporary Sector Unprotect .................................................. 20
Figure 1. Temporary Sector Unprotect Operation........................... 20
Figure 2. In-System Sector Protect/Unprotect Algorithms .............. 21
SecSi™ (Secured Silicon) Sector
Flash Memory Region ............................................................ 22
Hardware Data Protection ...................................................... 22
Low VCC Write Inhibit ............................................................ 22
Write Pulse “Glitch” Protection ............................................... 23
Logical Inhibit .......................................................................... 23
Power-Up Write Inhibit ............................................................ 23
Common Flash Memory Interface (CFI) . . . . . . .23
Table 9. CFI Query Identification String.......................................... 23
System Interface String................................................................... 24
Table 11. Device Geometry Definition ............................................ 24
Table 12. Primary Vendor-Specific Extended Query ...................... 25
Command Definitions . . . . . . . . . . . . . . . . . . . . . . 26
Reading Array Data ................................................................ 26
Reset Command ..................................................................... 26
Autoselect Command Sequence ............................................ 26
Enter SecSi™ Sector/Exit SecSi Sector
Command Sequence .............................................................. 26
Word Program Command Sequence ..................................... 27
Unlock Bypass Command Sequence ..................................... 27
Figure 3. Program Operation .......................................................... 28
Chip Erase Command Sequence ........................................... 28
Sector Erase Command Sequence ........................................ 28
Erase Suspend/Erase Resume Commands ........................... 29
Figure 4. Erase Operation.............................................................. 29
Table 13. Am29DL642G Command Definitions .............................. 30
Wr ite O pe r a tion S t a tus . . . . . . . . . . . . . . . . . . . . 3 1
DQ7: Data# Polling ................................................................. 31
Figure 5. Data# Polling Algorithm .................................................. 31
RY/BY#: Ready/Busy# ............................................................ 32
DQ6: Toggle Bit I .................................................................... 32
Figure 6. Toggle Bit Algorithm........................................................ 32
DQ2: Toggle Bit II ................................................................... 33
Reading Toggle Bits DQ6/DQ2 ............................................... 33
DQ5: Exceeded Timing Limits ................................................ 33
DQ3: Sector Erase Timer ....................................................... 33
Table 14. Write Operation Status ................................................... 34
Absolute Maximum R a tings . . . . . . . . . . . . . . . . 35
Figure 7. Maximum Negative Overshoot Waveform ...................... 35
Figure 8. Maximum Positive Overshoot Waveform........................ 35
DC Cha ra c teristic s . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 9. ICC1 Current vs. Time (Showing Active and
Automatic Sleep Currents) ............................................................. 37
Figure 10. Typical ICC1 vs. Frequency ............................................ 37
Test C onditions . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Figure 11. Test Setup.................................................................... 38
Figure 12. Input Waveforms and Measurement Levels ................. 38
AC Cha ra c teristic s . . . . . . . . . . . . . . . . . . . . . . . . 39
Read-Only Operations ........................................................... 39
Figure 13. Read Operation Timings ............................................... 39
Hardware Reset (RESET#) .................................................... 40
Figure 14. Reset Timings............................................................... 40
Erase and Program Operations .............................................. 41
Figure 15. Program Operation Timings.......................................... 42
Figure 16. Accelerated Program Timing Diagram.......................... 42
Figure 17. Chip/Sector Erase Operation Timings .......................... 43
Figure 18. Back-to-back Read/Write Cycle Timings ...................... 44
Figure 19. Data# Polling Timings (During Embedded Algorithms). 44
Figure 20. Toggle Bit Timings (During Embedded Algorithms)...... 45
Figure 21. DQ2 vs. DQ6................................................................. 45
Temporary Sector Unprotect .................................................. 46
Figure 22. Temporary Sector Unprotect Timing Diagram .............. 46
Figure 23. Sector/Sector Block Protect and
Unprotect Timing Diagram ............................................................. 47
Alternate CE# Controlled Erase and Program Operations ..... 48
Figure 24. Alternate CE# Controlled Write (Erase/Program)
Operation Timings.......................................................................... 49
Erase And Pro grammi ng Performance . . . . . . . 50
La t c h up Cha r a c t e r is tics. . . . . . . . . . . . . . . . . . . . 50
Dat a Ret e ntion. . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 51
FSD063—63-Ball Fine-Pitch Ball Grid Array (FBGA)
10.95 x 11.95 mm package .................................................... 51
Revis ion Summ a r y . . . . . . . . . . . . . . . . . . . . . . . . 52
4 Am29DL642G Spetember 5, 2002
PRELIMINARY
PRODUCT SELECTOR GUIDE
Note: See “AC Characteristics” for full specifications.
Part Number Am29DL642G
Sp eed Rating Regul ated Voltage Range : VCC = 2.7–3.6 V 70 90
Max Access Time (ns) 70 90
CE# Access Time (ns) 70 90
OE# Access Time (ns) 30 30
Spetember 5, 2002 Am29DL642G 5
PRELIMINARY
BLOCK DIAGRAM
Input/Output
Buffers
X-Decoder
Y-Decoder
Chi p Enable
Output Enable
Logic
Erase Voltage
Generator
PGM Voltage
Generator
Timer
VCC Detect or
State
Control
Command
Register
VCC
VSS
WE#
ACC
CE#
OE#
STB
STB
Sector Switches
RY/BY#
RESET#
Data
Latch
Y-Gating
Cell Matrix
Ad dress Latch
Input/Output
Buffers
X-Decoder
Y-Decoder
Chip Enable
Output Enabl e
Logic
Erase Voltage
Generator
PGM Voltage
Generator
Timer
VCC Detector
State
Control
Command
Register
STB
STB
DQ15
–
DQ0
Sector Switches
RY/BY#
Data
Latch
Y-Gating
Cell Matrix
Address Latch
A21–A0
A21–A0
A21–A0
CE#2
DQ15–DQ0
6 Am29DL642G Spetember 5, 2002
PRELIMINARY
CONNECTION DIAGRAM
Special Hand ling Ins truc tions for BGA
Package
Special handling is required f or Flash Memory pr oducts
in BGA packages.
Flash memory devices in BGA packages may be
damaged if exposed to ultrasonic cleaning methods.
The p ac kage an d /or da ta i nte gr i ty m ay be c omp ro mi sed
if the package body is exposed to temperatures above
150°C for prolonged pe r iods of time.
63-Ball Fine-pitch BG A
Top View, Balls Facing
Down
C2 D2 E2 F2 G2 H2 J2 K2
C3 D3 E3 F3 G3 H3 J3 K3
C4 D4 E4 F4 G4 H4 J4 K4
C5 D5 E5 F5 G5 H5 J5 K5
C6 D6 E6 F6 G6 H6 J6 K6
C7 D7A7 B7
A8 B8
A1 B1
A2
E7 F7 G7 H7 J7 K7 L7
L8
M7
M8
L1
L2
M1
M2
NC* NC*NC*
NC* NC* NC* NC*
NC* NC*
NC* NC*NC NC
NC NC DQ15 V
SS
CE2#A16A15A14A12A13
DQ13 DQ6DQ14DQ7A11A10A8A9
V
CC
DQ4DQ12DQ5A19A21RESET#WE#
DQ11 DQ3DQ10DQ2A20A18WP#/ACCRY/BY#
DQ9 DQ1DQ8DQ0A5A6A17A7
OE# V
SS
CE#A0A1A2A4A3
* Balls are shorted together via the substrate but not connected to the die.
Spetember 5, 2002 Am29DL642G 7
PRELIMINARY
PIN DESCRIPTION
A21–A0 = 22 Addresses inputs
DQ15–DQ0 = 16 Data inputs/outputs
CE# = Chip Enable input
CE2# = Chip Enable input for second die
OE# = Output Enable input
WE# = Write Enable input
WP#/ACC = Hardware W rite Protec t/ Acceler ation
Pin
RESET# = Hardware Reset Pin input
RY/BY# = Ready/Busy output
VCC = 3.0 volt-only single power supply
(see Product Selector Guide for
speed options and vol tage
supply tolerances)
VSS = Device Ground
NC = Pin Not Connected Internally
LOGIC SYMBOL
22 16
DQ15–DQ0
A21–A0
CE#
CE2#
OE#
WP#/ACC
RY/BY#
WE#
RESET#
8 Am29DL642G Spetember 5, 2002
PRELIMINARY
ORDERING INFORMATION
Standard Products
AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is
formed by a combination of the following:
Valid Combinations
Valid Combinations list configurations planned to be sup-
ported in volume for this device. Consult the local AMD sales
offic e to confirm availability of specific valid combinations and
to check on newly released combinations.
Am29DL642G 70 MD I
TEMPERATURE RANGE
I = Industrial (–40°C to +85°C)
PACKAGE TYPE
MD = 63-Ball Fine-pitch Ball Grid Array (FBGA)
0.8 mm pitch, 10.95 x 11.95 mm package (FSD063)
SPEED OPTION
See Product Selector Guide and Valid Combinations
DE VIC E NUMB ER/ DES CRI PT ION
Am29DL642G
128 Megabit (2 x 8 M x 16-Bit) CMOS Simultaneous Operation Flash Memory
3.0 Volt -onl y Read, Program, and Erase
Valid Combinations for
Fine-pitch BGA Packages
SpeedOrder Number Package
Marking
Am29DL642G70 MDI D642G70V I 70 ns
Am29DL642G90 D642G90V I 90 ns
Spetember 5, 2002 Am29DL642G 9
PRELIMINARY
DEVICE BUS OPERATIONS
This section describes the r equirement s and use of
the device bus operation s, which are initiated through
the internal command register. The command register
itself does not occupy any addressable m emory loca -
tion. The register is a latch used to store the com-
mands, along with the address and data information
needed to execute the command. The contents of the
regis ter serve as inputs to t he intern al state machine.
The state machine outputs dictate the function of the
device. Table 1 lists the device bus operations, the in-
puts an d cont rol levels they requir e, and the resulting
output. The following subsections describe each of
these operations in further detail.
Table 1. Am29DL642G Device Bus Operations
Legend: L = Logic Low = VIL, H = Logic High = VIH, VID = 11.5–12.5 V, VHH = 9.0 ± 0.5 V , X = Don’t Care, SA = Sector Address,
AIN = Address In, DIN = Data In, DOUT = Data Ou t
Notes:
1. Addresse s are A21:A0.
2. The sector protect and sector unprotect functions may also be implemented via programming equipment. See the “Sector/Sector
Block Protection and Unprotection” section.
3. CE# can be replaced with CE2# when referring to the second die in the package. CE# and CE2# must not both be driven at the
same time.
4. If WP#/ACC = V IL, sectors 0, 1, 140, and 141 remain protected. If WP#/ACC = VIH, protection on sector s 0, 1, 140, and 141
depends on whether they were last protected or unprotected using the method described in “Sector/Sector Block Protection
and Unprotection”. If WP#/ACC = VHH, all sec tors will be unprotected.
Requirements for Reading Array Data
To read array data f rom the o utputs, the s ystem must
driv e the C E# a nd OE# pins to VIL. C E # is the po wer
control and selects the device. OE# is the output con-
trol and gates array data to the output pins. WE#
should remain at VIH.
The inte rnal state machine is set fo r reading array data
upon device power-up, or after a hardware reset. This
ensures that no spurious alteration of the memory
content occurs during the power transition. No com-
mand is necessary in this mode to obtain array data.
Standard microprocessor read cycles that assert valid
addresses on the device address inputs produce valid
data on the device data outputs. Each bank remains
enabled for read access until the command register
contents are altered.
Refer to the AC Read-Only Operations table for timing
specifications and to Figure 13 for the timing diagram.
ICC1 in the DC Characteristics table represents the ac-
tive current specification for reading array data.
W r iting Commands/Command Sequences
To write a command or command sequence (which in-
cludes programming data to the device and erasing
sectors of memory), the system must drive WE# and
CE# (or CE2#) to VIL, and OE# to VIH.
Operation CE#
(Note 3) OE# WE# RESET# WP#/ACC Addresses
(Note 1) DQ15–
DQ0
Read L L H H L/H AIN DOUT
Write L H L H (Note 4) AIN DIN
Standby VCC ±
0.3 V XXVCC ±
0.3 V L/H X High-Z
Output Disable L H H H L/H X High-Z
Reset X X X L L/H X High-Z
Sector Protect (Note 2) L H L VID L/H SA , A6 = L,
A1 = H, A0 = L DIN
Sector Unprotect (Note 2) L H L V ID (Note 4) SA, A6 = H,
A1 = H, A0 = L DIN
Temporary Sector Unprotect X X X VID (Note 4) AIN DIN
10 Am29DL642G Spetember 5, 2002
PRELIMINARY
The device features an Unlock Bypass mode to facil-
itate faster programm ing. Once a bank enters the Un-
lock Byp ass mode, only two write c ycles are require d
to progra m a word, ins tead o f fou r. The “Word Pro-
gram Command Sequence” section has details on
programming data to the device using both standard
and Unlock Bypass command sequences.
An erase operation can erase one sector, multiple sec-
tors , or the entire device. Table 2 indic ates the addres s
space that each sector occupies. Similarly, a “sector
address” is the address bits r equired to uniquely select
a sec tor. The “ Co mmand De finitio ns” se ction has de-
tails on erasing a sec tor or the entire chip, or suspend-
ing/resum ing the erase operati on.
The device address space is divided into four banks. A
“bank address ” is the addres s bits r equir ed t o uniquely
select a bank.
ICC2 in the DC Characteristics table represents the ac-
tive current specification for the write mode. The AC
Characteristics section contains timing specification
tables and timing diagrams for write operations.
Accelerated Program Operation
The device offers accelerated program operations
through the ACC function. This is one of two functions
provided by the WP#/AC C pin. This function is prima-
rily intend ed to al low faster m anufactur ing through put
at the factory.
If the system ass erts VHH on this pin, th e device auto-
matically enters the aforementioned Unlock Bypass
mode, temporarily unprotects any protected sectors,
and us es the hi gher vo ltage on the pi n to red uce the
time required for program operations. The system
would use a two-cycle program command sequence
as required by the Unlock Bypass mode. Removing
VHH from the W P#/A CC pin retur ns the dev ice to nor -
mal operation. Note that VHH must not be assert ed on
WP#/ACC for operations other than accelerated pro-
gramming, or device damage may result. In addition,
the WP#/ACC pin must not be left floating or uncon-
nected; inconsistent behavi or of t he dev ice m ay result.
See “Write Protect (WP#)” on page 20. for related in-
formation.
Autoselect Functions
If the system writes the autoselect command se-
quence, the device enters the autoselect mode. The
system can then read autoselect codes from t he inter-
nal register (which is separate from the memory array)
on DQ15–DQ0. Standard read cycle timings apply in
this mode. Ref er to the Autoselect Mode and Autose-
lect Command Sequence sections for more informa-
tion.
Simultaneous Read/Write Operations with
Zero Latency
This dev ice is capa ble of r eading data f rom one ba nk
of mem ory w hile prog ramming or eras ing in the o ther
bank of memory. An erase operation may also be sus-
pended to read from or program to another location
within the same bank (except the sector being
erased). Figure 18 shows how read and write cycles
may be i nitia ted fo r simu ltane ous o perati on wit h ze ro
latency. ICC6 and ICC7 in the DC Chara cteris tics table
represent the current speci fications for read-while-pr o-
gram and read-while-erase, respect iv ely.
Standby Mode
When the system is not reading or writing to the de-
vice, it can place the device in the standby mode. In
this mode, current consumption is greatly reduced,
and the outputs are placed in the high impedance
state, independent of the OE# input.
The device enters the CMOS standby m ode when the
CE# or CE2# and RE S ET# pins ar e both held at VCC ±
0.3 V. (Note that this is a mor e res tric ted voltage r ange
than VIH.) If CE# and RESET# are held at VIH, but not
within VCC ± 0.3 V, the device will be in the standby
mode, but the standby current will be greater. The de-
vice requires standard access time (tCE) for read ac-
cess when the device is in either of these standby
modes, before it is ready to read data.
If the device is deselected during erasure or program-
ming, the device draws active current until the
operation is completed.
ICC3 in the DC Characteristics table represents the
standby current specification.
Automatic Sleep Mode
The automatic sleep mode minimi zes Flash device en-
ergy consumption. The device automatically enables
this m ode when addre sses remain sta ble for tACC +
30 ns. The automa tic sleep mode is indepe ndent of
the CE#, CE2# , WE#, an d OE# con trol signals. Stan-
dar d addre ss access timings pr ovide ne w data wh en
addr ess es a re chan ged . Wh ile in sleep mod e, o utput
data is latched and a lways availa ble to the system .
ICC5 in the DC Characteristics table represents the
automatic sleep mode current specification.
RESET#: Hardware Reset Pin
The RESET# pin provides a hardware method of re-
setting t he dev ice to reading array data. When the RE-
SE T# pin is dr iven l ow fo r at le ast a p eriod of t RP, the
device immediately terminates any operation in
progress, tristates all output pins, and ignores all
read/wr ite comm ands for the du ration of t he RESET#
pulse. The device also resets the internal state ma-
chine to reading array data. The operation that was in-
Spetember 5, 2002 Am29DL642G 11
PRELIMINARY
terrupted should be reinitiated once the device is
ready t o accept another command sequence, to en-
sure data integr ity.
Current is reduced for the duration of the RESET#
pulse. When RESET# is held at VSS±0.3 V, the device
draws CMOS standby current (ICC4). If RESET# is held
at VIL but not within V SS± 0.3 V, the standby current will
be greater.
The R ESET# p in may be t ied t o the sy stem reset cir-
cuitry. A system res et would thus also reset the Flas h
memory, enabling the system to read the boot-up firm-
ware from the Flash memory.
If RESE T# is as serted during a progr am or erase op -
eration, the RY/BY# p in remains a “0” (busy ) until the
internal reset o perat ion is complet e, whic h req uires a
time of tREADY (during Embedded Algorithms). The
system can thus monitor RY/BY# to determine
whether the reset operation is c omplete. If RESET# is
asserted when a program or eras e oper ation is not ex-
ecuting (R Y/BY# pin is “1”), the reset operat ion is com-
pleted within a time of tREADY (not during Embedded
Algorithms). The system can read data tRH after the
RESET# pin returns to VIH.
Refer to the AC Characteristic s tables for RESET# pa-
rameters and to Figure 14 for the timing diagram .
Output Disable Mode
When the OE# input is at VIH, output from t he device is
disabled. The output pins are placed in the high
impedance state.
Table 2. Am29DL642G Sector Architecture
Bank Sector Sector Address
A21–A12 Sector Size
(Kwords) (x16)
Address Range
Bank 1
SA0 0000000000 4 00000h–00FFFh
SA1 0000000001 4 01000h–01FFFh
SA2 0000000010 4 02000h–02FFFh
SA3 0000000011 4 03000h–03FFFh
SA4 0000000100 4 04000h–04FFFh
SA5 0000000101 4 05000h–05FFFh
SA6 0000000110 4 06000h–06FFFh
SA7 0000000111 4 07000h–07FFFh
SA8 0000001xxx 32 08000h–0FFFFh
SA9 0000010xxx 32 10000h–17FFFh
SA10 0000011xxx 32 18000h–1FFFFh
SA11 0000100xxx 32 20000h–27FFFh
SA12 0000101xxx 32 28000h–2FFFFh
SA13 0000110xxx 32 30000h–37FFFh
SA14 0000111xxx 32 38000h–3FFFFh
SA15 0001000xxx 32 40000h–47FFFh
SA16 0001001xxx 32 48000h–4FFFFh
SA17 0001010xxx 32 50000h–57FFFh
SA18 0001011xxx 32 58000h–5FFFFh
SA19 0001100xxx 32 60000h–67FFFh
SA20 0001101xxx 32 68000h–6FFFFh
SA21 0001101xxx 32 70000h–77FFFh
SA22 0001111xxx 32 78000h–7FFFFh
12 Am29DL642G Spetember 5, 2002
PRELIMINARY
Bank 2
SA23 0010000xxx 32 80000h–87FFFh
SA24 0010001xxx 32 88000h–8FFFFh
SA25 0010010xxx 32 90000h–97FFFh
SA26 0010011xxx 32 98000h–9FFFFh
SA27 0010100xxx 32 A0000h–A7FFFh
SA28 0010101xxx 32 A8000h–AFFFFh
SA29 0010110xxx 32 B0000h–B7FFFh
SA30 0010111xxx 32 B8000h–BFFFFh
SA31 0011000xxx 32 C0000h–C7FFFh
SA32 0011001xxx 32 C8000h–CFFFFh
SA33 0011010xxx 32 D0000h–D7FFFh
SA34 0011011xxx 32 D8000h–DFFFFh
SA35 0011000xxx 32 E0000h–E7FFFh
SA36 0011101xxx 32 E8000h–EFFFFh
SA37 0011110xxx 32 F0000h–F7FFFh
SA38 0011111xxx 32 F8000h–FFFFFh
SA39 0100000xxx 32 F9000h–107FFFh
SA40 0100001xxx 32 108000h–10FFFFh
SA41 0100010xxx 32 110000h–117FFFh
SA42 0101011xxx 32 118000h–11FFFFh
SA43 0100100xxx 32 120000h–127FFFh
SA44 0100101xxx 32 128000h–12FFFFh
SA45 0100110xxx 32 130000h–137FFFh
SA46 0100111xxx 32 138000h–13FFFFh
SA47 0101000xxx 32 140000h–147FFFh
SA48 0101001xxx 32 148000h–14FFFFh
SA49 0101010xxx 32 150000h–157FFFh
SA50 0101011xxx 32 158000h–15FFFFh
SA51 0101100xxx 32 160000h–167FFFh
SA52 0101101xxx 32 168000h–16FFFFh
SA53 0101110xxx 32 170000h–177FFFh
SA54 0101111xxx 32 178000h–17FFFFh
SA55 0110000xxx 32 180000h–187FFFh
SA56 0110001xxx 32 188000h–18FFFFh
SA57 0110010xxx 32 190000h–197FFFh
SA58 0110011xxx 32 198000h–19FFFFh
SA59 0100100xxx 32 1A0000h–1A7FFFh
SA60 0110101xxx 32 1A8000h–1AFFFFh
SA61 0110110xxx 32 1B0000h–1B7FFFh
SA62 0110111xxx 32 1B8000h–1BFFFFh
SA63 0111000xxx 32 1C0000h–1C7FFFh
SA64 0111001xxx 32 1C8000h–1CFFFFh
SA65 0111010xxx 32 1D0000h–1D7FFFh
SA66 0111011xxx 32 1D8000h–1DFFFFh
SA67 0111100xxx 32 1E0000h–1E7FFFh
SA68 0111101xxx 32 1E8000h–1EFFFFh
SA69 0111110xxx 32 1F0000h–1F7FFFh
SA70 0111111xxx 32 1F8000h–1FFFFFh
Table 2. Am29DL642G Sector Architecture (Continued)
Bank Sector Sector Address
A21–A12 Sector Size
(Kwords) (x16)
Address Range
Spetember 5, 2002 Am29DL642G 13
PRELIMINARY
Bank 3
SA71 1000000xxx 32 200000h–207FFFh
SA72 1000001xxx 32 208000h–20FFFFh
SA73 1000010xxx 32 210000h–217FFFh
SA74 1000011xxx 32 218000h–21FFFFh
SA75 1000100xxx 32 220000h–227FFFh
SA76 1000101xxx 32 228000h–22FFFFh
SA77 1000110xxx 32 230000h–237FFFh
SA78 1000111xxx 32 238000h–23FFFFh
SA79 1001000xxx 32 240000h–247FFFh
SA80 1001001xxx 32 248000h–24FFFFh
SA81 1001010xxx 32 250000h–257FFFh
SA82 1001011xxx 32 258000h–25FFFFh
SA83 1001100xxx 32 260000h–267FFFh
SA84 1001101xxx 32 268000h–26FFFFh
SA85 1001110xxx 32 270000h–277FFFh
SA86 1001111xxx 32 278000h–27FFFFh
SA87 1010000xxx 32 280000h–28FFFFh
SA88 1010001xxx 32 288000h–28FFFFh
SA89 1010010xxx 32 290000h–297FFFh
SA90 1010011xxx 32 298000h–29FFFFh
SA91 1010100xxx 32 2A0000h–2A7FFFh
SA92 1010101xxx 32 2A8000h–2AFFFFh
SA93 1010110xxx 32 2B0000h–2B7FFFh
SA94 1010111xxx 32 2B8000h–2BFFFFh
SA95 1011000xxx 32 2C0000h–2C7FFFh
SA96 1011001xxx 32 2C8000h–2CFFFFh
SA97 1011010xxx 32 2D0000h–2D7FFFh
SA98 1011011xxx 32 2D8000h–2DFFFFh
SA99 1011100xxx 32 2E0000h–2E7FFFh
SA100 1011101xxx 32 2E8000h–2EFFFFh
SA101 1011110xxx 32 2F0000h–2FFFFFh
SA102 1011111xxx 32 2F8000h–2FFFFFh
SA103 1100000xxx 32 300000h–307FFFh
SA104 1100001xxx 32 308000h–30FFFFh
SA105 1100010xxx 32 310000h–317FFFh
SA106 1100011xxx 32 318000h–31FFFFh
SA107 1100100xxx 32 320000h–327FFFh
SA108 1100101xxx 32 328000h–32FFFFh
SA109 1100110xxx 32 330000h–337FFFh
SA110 1100111xxx 32 338000h–33FFFFh
SA111 1101000xxx 32 340000h–347FFFh
SA112 1101001xxx 32 348000h–34FFFFh
SA113 1101010xxx 32 350000h–357FFFh
SA114 1101011xxx 32 358000h–35FFFFh
SA115 1101100xxx 32 360000h–367FFFh
SA116 1101101xxx 32 368000h–36FFFFh
SA117 1101110xxx 32 370000h–377FFFh
SA118 1101111xxx 32 378000h–37FFFFh
Table 2. Am29DL642G Sector Architecture (Continued)
Bank Sector Sector Address
A21–A12 Sector Size
(Kwords) (x16)
Address Range
14 Am29DL642G Spetember 5, 2002
PRELIMINARY
Bank 4
SA119 1110000xxx 32 380000h–387FFFh
SA120 1110001xxx 32 388000h–38FFFFh
SA121 1110010xxx 32 390000h–397FFFh
SA122 1110011xxx 32 398000h–39FFFFh
SA123 1110100xxx 32 3A0000h–3A7FFFh
SA124 1110101xxx 32 3A8000h–3AFFFFh
SA125 1110110xxx 32 3B0000h–3B7FFFh
SA126 1110111xxx 32 3B8000h–3BFFFFh
SA127 1111000xxx 32 3C0000h–3C7FFFh
SA128 1111001xxx 32 3C8000h–3CFFFFh
SA129 1111010xxx 32 3D0000h–3D7FFFh
SA130 1111011xxx 32 3D8000h–3DFFFFh
SA131 1111100xxx 32 3E0000h–3E7FFFh
SA132 1111101xxx 32 3E8000h–3EFFFFh
SA133 1111110xxx 32 3F0000h–3F7FFFh
SA134 1111111000 4 3F8000h–3F8FFFh
SA135 1111111001 4 3F9000h–3F9FFFh
SA136 1111111010 4 3FA000h–3FAFFFh
SA137 1111111011 4 3FB000h–3FBFFFh
SA138 1111111100 4 3FC000h–3FCFFFh
SA139 1111111101 4 3FD000h–3FDFFFh
SA140 1111111110 4 3FE000h–3FEFFFh
SA141 1111111111 4 3FF000h–3FFFFFh
Table 2. Am29DL642G Sector Architecture (Continued)
Bank Sector Sector Address
A21–A12 Sector Size
(Kwords) (x16)
Address Range
Table 3. Am29DL642G Sector Architecture for CE2#
Bank Sector Sector Address
A21–A12 Sector Size
(Kwords) (x16)
Address Range
Bank 1
SA0 0000000000 4 00000h–00FFFh
SA1 0000000001 4 01000h–01FFFh
SA2 0000000010 4 02000h–02FFFh
SA3 0000000011 4 03000h–03FFFh
SA4 0000000100 4 04000h–04FFFh
SA5 0000000101 4 05000h–05FFFh
SA6 0000000110 4 06000h–06FFFh
SA7 0000000111 4 07000h–07FFFh
SA8 0000001xxx 32 08000h–0FFFFh
SA9 0000010xxx 32 10000h–17FFFh
SA10 0000011xxx 32 18000h–1FFFFh
SA11 0000100xxx 32 20000h–27FFFh
SA12 0000101xxx 32 28000h–2FFFFh
SA13 0000110xxx 32 30000h–37FFFh
SA14 0000111xxx 32 38000h–3FFFFh
SA15 0001000xxx 32 40000h–47FFFh
SA16 0001001xxx 32 48000h–4FFFFh
SA17 0001010xxx 32 50000h–57FFFh
SA18 0001011xxx 32 58000h–5FFFFh
SA19 0001100xxx 32 60000h–67FFFh
SA20 0001101xxx 32 68000h–6FFFFh
SA21 0001101xxx 32 70000h–77FFFh
SA22 0001111xxx 32 78000h–7FFFFh
Spetember 5, 2002 Am29DL642G 15
PRELIMINARY
Bank 2
SA23 0010000xxx 32 80000h–87FFFh
SA24 0010001xxx 32 88000h–8FFFFh
SA25 0010010xxx 32 90000h–97FFFh
SA26 0010011xxx 32 98000h–9FFFFh
SA27 0010100xxx 32 A0000h–A7FFFh
SA28 0010101xxx 32 A8000h–AFFFFh
SA29 0010110xxx 32 B0000h–B7FFFh
SA30 0010111xxx 32 B8000h–BFFFFh
SA31 0011000xxx 32 C0000h–C7FFFh
SA32 0011001xxx 32 C8000h–CFFFFh
SA33 0011010xxx 32 D0000h–D7FFFh
SA34 0011011xxx 32 D8000h–DFFFFh
SA35 0011000xxx 32 E0000h–E7FFFh
SA36 0011101xxx 32 E8000h–EFFFFh
SA37 0011110xxx 32 F0000h–F7FFFh
SA38 0011111xxx 32 F8000h–FFFFFh
SA39 0100000xxx 32 F9000h–107FFFh
SA40 0100001xxx 32 108000h–10FFFFh
SA41 0100010xxx 32 110000h–117FFFh
SA42 0101011xxx 32 118000h–11FFFFh
SA43 0100100xxx 32 120000h–127FFFh
SA44 0100101xxx 32 128000h–12FFFFh
SA45 0100110xxx 32 130000h–137FFFh
SA46 0100111xxx 32 138000h–13FFFFh
SA47 0101000xxx 32 140000h–147FFFh
SA48 0101001xxx 32 148000h–14FFFFh
SA49 0101010xxx 32 150000h–157FFFh
SA50 0101011xxx 32 158000h–15FFFFh
SA51 0101100xxx 32 160000h–167FFFh
SA52 0101101xxx 32 168000h–16FFFFh
SA53 0101110xxx 32 170000h–177FFFh
SA54 0101111xxx 32 178000h–17FFFFh
SA55 0110000xxx 32 180000h–187FFFh
SA56 0110001xxx 32 188000h–18FFFFh
SA57 0110010xxx 32 190000h–197FFFh
SA58 0110011xxx 32 198000h–19FFFFh
SA59 0100100xxx 32 1A0000h–1A7FFFh
SA60 0110101xxx 32 1A8000h–1AFFFFh
SA61 0110110xxx 32 1B0000h–1B7FFFh
SA62 0110111xxx 32 1B8000h–1BFFFFh
SA63 0111000xxx 32 1C0000h–1C7FFFh
SA64 0111001xxx 32 1C8000h–1CFFFFh
SA65 0111010xxx 32 1D0000h–1D7FFFh
SA66 0111011xxx 32 1D8000h–1DFFFFh
SA67 0111100xxx 32 1E0000h–1E7FFFh
SA68 0111101xxx 32 1E8000h–1EFFFFh
SA69 0111110xxx 32 1F0000h–1F7FFFh
SA70 0111111xxx 32 1F8000h–1FFFFFh
Table 3. Am29DL642G Sector Architecture for CE2# (Continued)
Bank Sector Sector Address
A21–A12 Sector Size
(Kwords) (x16)
Address Range
16 Am29DL642G Spetember 5, 2002
PRELIMINARY
Bank 3
SA71 1000000xxx 32 200000h–207FFFh
SA72 1000001xxx 32 208000h–20FFFFh
SA73 1000010xxx 32 210000h–217FFFh
SA74 1000011xxx 32 218000h–21FFFFh
SA75 1000100xxx 32 220000h–227FFFh
SA76 1000101xxx 32 228000h–22FFFFh
SA77 1000110xxx 32 230000h–237FFFh
SA78 1000111xxx 32 238000h–23FFFFh
SA79 1001000xxx 32 240000h–247FFFh
SA80 1001001xxx 32 248000h–24FFFFh
SA81 1001010xxx 32 250000h–257FFFh
SA82 1001011xxx 32 258000h–25FFFFh
SA83 1001100xxx 32 260000h–267FFFh
SA84 1001101xxx 32 268000h–26FFFFh
SA85 1001110xxx 32 270000h–277FFFh
SA86 1001111xxx 32 278000h–27FFFFh
SA87 1010000xxx 32 280000h–28FFFFh
SA88 1010001xxx 32 288000h–28FFFFh
SA89 1010010xxx 32 290000h–297FFFh
SA90 1010011xxx 32 298000h–29FFFFh
SA91 1010100xxx 32 2A0000h–2A7FFFh
SA92 1010101xxx 32 2A8000h–2AFFFFh
SA93 1010110xxx 32 2B0000h–2B7FFFh
SA94 1010111xxx 32 2B8000h–2BFFFFh
SA95 1011000xxx 32 2C0000h–2C7FFFh
SA96 1011001xxx 32 2C8000h–2CFFFFh
SA97 1011010xxx 32 2D0000h–2D7FFFh
SA98 1011011xxx 32 2D8000h–2DFFFFh
SA99 1011100xxx 32 2E0000h–2E7FFFh
SA100 1011101xxx 32 2E8000h–2EFFFFh
SA101 1011110xxx 32 2F0000h–2FFFFFh
SA102 1011111xxx 32 2F8000h–2FFFFFh
SA103 1100000xxx 32 300000h–307FFFh
SA104 1100001xxx 32 308000h–30FFFFh
SA105 1100010xxx 32 310000h–317FFFh
SA106 1100011xxx 32 318000h–31FFFFh
SA107 1100100xxx 32 320000h–327FFFh
SA108 1100101xxx 32 328000h–32FFFFh
SA109 1100110xxx 32 330000h–337FFFh
SA110 1100111xxx 32 338000h–33FFFFh
SA111 1101000xxx 32 340000h–347FFFh
SA112 1101001xxx 32 348000h–34FFFFh
SA113 1101010xxx 32 350000h–357FFFh
SA114 1101011xxx 32 358000h–35FFFFh
SA115 1101100xxx 32 360000h–367FFFh
SA116 1101101xxx 32 368000h–36FFFFh
SA117 1101110xxx 32 370000h–377FFFh
SA118 1101111xxx 32 378000h–37FFFFh
Table 3. Am29DL642G Sector Architecture for CE2# (Continued)
Bank Sector Sector Address
A21–A12 Sector Size
(Kwords) (x16)
Address Range
Spetember 5, 2002 Am29DL642G 17
PRELIMINARY
Table 4. Bank Address
Table 5. SecSiTM Sector Addresses
Autoselect Mode
The autoselect mode provides manufacturer and de-
vice identification, and sector protection verification,
through identifier codes output on DQ7–DQ0. This
mode is primarily intended for programming equip-
ment to automatically match a device to be pro-
grammed with its corresponding programming
algorithm. However, the autoselect code s can also be
accessed in-system through the co mmand register.
When using programming equipment, the autoselect
mode requires VID on address pin A9. Address pins
must be as shown in Table 6. In addition, when verify-
ing sector protection, the sec tor address must appear
on the appropriate highest order address bits (see
Table 2) . Table 6 shows the remaining a ddress bits
that are don’t care. When all nec es s ar y bits have been
set as required, the progr am m ing equipm ent may t hen
read the corresponding identifier code on DQ7–DQ0.
Howev er, the autoselec t co des can als o be acc essed
in-system through the command regi ster, for ins tances
when the Am29DL642G is erased or programmed in a
sy stem witho ut a cce ss to high volta ge on the A9 pin .
The command sequence is illustrated in Table 13.
Note that if a Bank Address (BA) on address bits A21,
A20, and A19 is asserted during the third write cycle of
the autoselect comman d, the h ost system can read
aut os elec t dat a fr om th at bank and th en im me di ately
read array data from the other bank, without exiting
the autoselect mode.
Bank 4
SA119 1110000xxx 32 380000h–387FFFh
SA120 1110001xxx 32 388000h–38FFFFh
SA121 1110010xxx 32 390000h–397FFFh
SA122 1110011xxx 32 398000h–39FFFFh
SA123 1110100xxx 32 3A0000h–3A7FFFh
SA124 1110101xxx 32 3A8000h–3AFFFFh
SA125 1110110xxx 32 3B0000h–3B7FFFh
SA126 1110111xxx 32 3B8000h–3BFFFFh
SA127 1111000xxx 32 3C0000h–3C7FFFh
SA128 1111001xxx 32 3C8000h–3CFFFFh
SA129 1111010xxx 32 3D0000h–3D7FFFh
SA130 1111011xxx 32 3D8000h–3DFFFFh
SA131 1111100xxx 32 3E0000h–3E7FFFh
SA132 1111101xxx 32 3E8000h–3EFFFFh
SA133 1111110xxx 32 3F0000h–3F7FFFh
SA134 1111111000 4 3F8000h–3F8FFFh
SA135 1111111001 4 3F9000h–3F9FFFh
SA136 1111111010 4 3FA000h–3FAFFFh
SA137 1111111011 4 3FB000h–3FBFFFh
SA138 1111111100 4 3FC000h–3FCFFFh
SA139 1111111101 4 3FD000h–3FDFFFh
SA140 1111111110 4 3FE000h–3FEFFFh
SA141 1111111111 4 3FF000h–3FFFFFh
Table 3. Am29DL642G Sector Architecture for CE2# (Continued)
Bank Sector Sector Address
A21–A12 Sector Size
(Kwords) (x16)
Address Range
Bank A21–A19
1000
2 001, 010, 011
3 100, 101, 110
4 111
Dev ice Sect or Size (x16)
Address Range
Am29DL642G 128 words 00000h–0007Fh
18 Am29DL642G Spetember 5, 2002
PRELIMINARY
To ac cess the autosele ct codes in-system, the ho st
system can issue the autoselect command via the
command register, as shown in Table 13. This method
does not require VID. Refer to the Autoselect Com-
mand Sequence section for more info rmat i on .
Table 6. Am29DL642G Autoselect Codes, (High Voltage Method )
Legend:
L = Logic Low = V
IL
, H = Logic High = V
IH
, BA = Bank Address, SA = Sector Address, X = Don’t care
.
Description CE# OE# WE#
A21
to
A12
A11
to
A10 A9
A8
to
A7 A6
A5
to
A4 A3 A2 A1 A0 DQ15
to DQ 0
DQ7
to
DQ0
Manu f ac t urer ID :
AMD LLHBAX
VID XLXLLLL X 01h
De vi ce ID
Read Cycle 1
LLHBAX
VID X
L
X
LLLH22h 7Eh
Read Cycle 2 L H H H L 22h 02h
Read Cycle 3 L HHHH 22h 01h
Sector P r otect ion
Verification LLHSAX
VID XLX HL X 01h (protected),
00h (unprotected)
SecSi Indicator Bit
(DQ7) LLHBAX
VID XLXLLHH X 80h ( facto r y l ocke d) ,
00h ( not fact ory
locked)
Spetember 5, 2002 Am29DL642G 19
PRELIMINARY
Sector/Sector Block Protection and
Unprotection
(Not e: F or t he fol lowin g discu ssi on, the ter m “s ect or”
applies to both sectors and sector blocks. A sector
block consis ts of two or m or e adjacent sectors that are
protected o r unpro tected at the same time (see Table
7).
The hardw are sec tor pr otec tion f eature disab les bo th
program and erase operati ons in any sector . The hard-
ware sector unpro tection feature re- enables both pro -
gram and erase operations in previously protected
secto rs. S ector prote ction/ unpr otectio n can be imple -
mented via two methods.
Table 7. Am29DL642G Boot Sector/Sector Blo ck
Addresses for Protection/Unpro t ection
Th e pri mary m ethod requ ir es VID on the RESET# pin
only, and can be implemented either in-system or via
pro grammi ng eq uipme nt. Figu re 2 s hows th e al go-
rith ms and F igu re 23 sho ws t he timing d iagra m. Th is
meth od uses s tand ard mi cropr oces sor bu s cy cle tim-
ing. For sector unprotect, all unprotected sectors must
first be protected prior to the first sector unprotect writ e
cycle. N ote that the sec tor unprotect algor ithm unpro-
tects all sector s in parallel. All p reviously pro tected
sectors must be in dividually re-protected. To change
data in protected sectors efficiently, the temporary
sector unprotect function is available. See “Temporary
Sector Unprotect”.
Sector A21–A12 Sector/
Sect or Block Size
SA0 0000000000 4 Kwords
SA1 0000000001 4 Kwords
SA2 0000000010 4 Kwords
SA3 0000000011 4 Kwords
SA4 0000000100 4 Kwords
SA5 0000000101 4 Kwords
SA6 0000000110 4 Kwords
SA7 0000000111 4 Kwords
SA8–SA10 0000001XXX,
0000010XXX,
0000011XXX, 96 (3x32) Kwords
SA11–SA14 0 00 01 XXXXX 128 (4x 32 ) Kwords
SA15– SA18 000 10 XXXXX 128 (4x32 ) Kwords
SA19– SA22 00011XXXXX 128 (4x32) Kwor ds
SA23– SA26 001 00 XXXXX 128 (4x32 ) Kwords
SA27-SA3 0 00101 XXXXX 128 (4x32 ) Kwor ds
SA31-SA3 4 00110XXX XX 128 (4x32 ) Kwords
SA35-SA3 8 00111XXXXX 128 (4x 32 ) Kwor ds
SA39-SA4 2 01000 XXXXX 128 (4x32 ) Kwor ds
SA43-SA4 6 01001 XXXXX 128 (4x32 ) Kwor ds
SA47-SA5 0 01010 XXXXX 128 (4x32 ) Kwor ds
SA51-SA5 4 01011XXX XX 128 (4x32 ) Kwords
SA55– SA58 0110 0XXX XX 128 (4x32 ) Kwords
SA59– SA62 0110 1XXX XX 128 (4x32 ) Kwords
SA63–SA66 01110XXXXX 128 (4x32) Kwords
SA67–SA70 01111XXXXX 128 (4x32) Kwords
SA71–SA74 10000XXXXX 128 (4x32) Kwords
SA75–SA78 10001XXXXX 128 (4x32) Kwords
SA79–SA82 10010XXXXX 128 (4x32) Kwords
SA83–SA86 10011XXXXX 128 (4x32) Kwords
SA87–SA90 10100XXXXX 128 (4x32) Kwords
SA91–SA94 10101XXXXX 128 (4x32) Kwords
SA95–SA98 10110XXXXX 128 (4x32) Kwords
SA99–SA102 10111XXXXX 128 (4x32) Kwords
SA103–SA106 11 000XXXXX 128 (4x32) Kwords
SA107–SA110 11001XXXXX 128 (4x32) Kwords
SA111–SA114 11 010XXXXX 128 (4x32) Kwords
SA115–SA11 8 11011XXXXX 1 2 8 (4x32) Kwords
SA119–SA122 111 00XXXXX 128 (4x32) Kwords
SA123–SA126 111 01XXXXX 128 (4x32) Kwords
SA127–SA130 11110XXXXX 128 (4x32) Kwords
SA131–SA133 1111100XXX,
1111101XXX,
1111110XXX 96 (3x32) Kwords
SA134 1111111000 4 Kwords
SA135 1111111001 4 Kwords
SA136 1111111010 4 Kwords
SA137 1111111011 4 Kwords
SA138 1111111100 4 Kwords
SA139 1111111101 4 Kwords
SA140 1111111101 4 Kwords
SA141 1111111111 4 Kwords
Sector A21–A12 Sector/
Sector Block Size
20 Am29DL642G Spetember 5, 2002
PRELIMINARY
The alter nate meth od in tend ed on ly f or p rogram min g
equipment requires VID on address pin A9 and OE#.
This method is compatible with programmer routines
written for earlier 3.0 volt-only AMD flash devices.
The device i s shippe d with all sector s unpro tecte d.
AMD offers the op tion of prog ramming and protectin g
sectors at its factory prior to shipping the device
through AMD’s ExpressFlash™ Service. Contact an
AMD representative for details.
It is possible to determine whether a sector is pro-
tected or unprotected. Se e the Autoselect Mode sec-
tion for details .
Write Protect (WP#)
The Write Protect function provides a hardware
method of protecting wit hout using VID. T his function is
one of two provided by the WP#/ACC pin.
If the sy stem a ssert s VIL on the WP#/ACC pin, the de-
vice disa bles pro gram and eras e fun cti ons i n se ctors
0, 1, 140, and 141, independen tly of whether thos e
sectors were protected or unprotected using the
method described in “Sector/Sector Block Protection
and Unprotection”.
If the sys tem asserts V IH on the WP#/ACC pin, the de-
vice reverts to whether sectors 0, 1, 140, and 141
were last set to be protected or unprotected. That is,
sector protection or unprotection for these sectors de-
pends on whether they were last protected or unpro-
tected using the method described in “Sector/Sector
Block Protection and Unprotection”.
Note that the WP#/ACC pin must not be left floating or
unconnected; inconsistent behavior of the device may
result.
Table 8. WP#/ACC Modes
Temporary Sector Unprotect
(Note: For the following discussion, the term “sector”
applies to both sectors and sector blocks. A sector
block consists of two or more adjacent sectors that are
protec ted or unp rotect ed at the same tim e (see Ta ble
7).
This feature allows temporary unprotection of previ-
ously protected sectors to change data in-system. The
Sector Unprotect mode is activated by setting the RE-
SET# pin to VID. During this mode, formerly protected
sectors can be programmed or erased by selecting the
sector addresses. Once VID is removed from the RE-
SET# pin, all the previously protected sectors are
protec ted again. F igure 1 shows the algorit hm, an d
Figure 22 sh ows the timing diagram s, for this feature.
If the WP#/ACC pin is at V IL, sectors 0, 1, 140, and
141 will remain protected during the Temporary sector
Unprotect mode.
Figure 1. Temporary Sector Unprotect Operation
WP# Input
Voltage Device
Mode
VIL Disables programming and erasing in
SA0, SA1, SA140, and SA141
VIH Enables programming and erasing in
SA0, SA1, SA140, and SA141
VHH
Enables accelerated progamming (ACC).
See “Accelerated Program Operation” on
page 10..
START
Perfor m Erase or
Program Operations
RESET# = VIH
Temporary Sector
Unprotect Completed
(Note 2)
RESET# = VID
(Note 1)
Notes:
1. All protected sectors unprotected (If WP#/ACC = V IL,
sectors 0, 1, 140, and 141 will remain protected).
2. All previously prot ected sectors are protected once
again.
Spetember 5, 2002 Am29DL642G 21
PRELIMINARY
Figure 2. In-System Sector Protect/Unprotect Algorithms
Sector Group Protect:
Write 60h to sector
group address with
A6 = 0, A1 = 1,
A0 = 0
Set up sector
group address
Wait 150 µs
Verify Sector Group
Protect: Write 40h
to sector group
address twith A6 = 0,
A1 = 1, A0 = 0
Read from
sector group address
with A6 = 0,
A1 = 1, A0 = 0
START
PLSCNT = 1
RESET# = VID
Wait 1 µs
First Write
Cycle = 60h?
Data = 01h?
Remove VID
from RESET#
Write reset
command
Sector Group
Protect complete
Yes
Yes
No
PLSCNT
= 25?
Yes
Device failed
Increment
PLSCNT
Temporary Sector
Group Unprotect
Mode
No
Sector Group
Unprotect:
Write 60h to sector
group address with
A6 = 1, A1 = 1,
A0 = 0
Set up first sector
group address
Wait 15 ms
Verify Sector Group
Unprotect: Write
40h to sector group
address with
A6 = 1, A1 = 1,
A0 = 0
Read from
sector group
address with A6 = 1,
A1 = 1, A0 = 0
START
PLSCNT = 1
RESET# = VID
Wait 1 µs
Data = 00h?
Last sector
group
verified?
Remove VID
from RESET#
Write reset
command
Sector Group
Unprotect complete
Yes
No
PLSCNT
= 1000?
Yes
Device failed
Increment
PLSCNT
Temporary Sector
Group Unprotect
Mode
No All sector
groups
protected?
Yes
Protect all sector
groups: The indicated
portion of the sector
group protect algorithm
must be performed for all
unprotected sector
groups prior to issuing
the first sector group
unprotect address
Set up
next sector group
address
No
Yes
No
Yes
No
No
Yes
No
Sector Group
Protect
Algorithm
Sector Group
Unprotect
Algorithm
First Write
Cycle = 60h?
Protect
another
sector group?
Reset
PLSCNT = 1
22 Am29DL642G Spetember 5, 2002
PRELIMINARY
SecSi™ (Secured Silicon) Sector
Flash Memory Region
The SecSi (Secured Silicon) Sector feature provides a
Flash memory region that enables permanent part
identification through an Electronic Serial Number
(ESN). The SecSi Sector is 256 bytes in length, and
uses a SecSi Sec tor Indicat or Bit (DQ7) to indic ate
whether or not the SecSi Sector is locked when
shipped from the factory. This bit is permanently set at
the factory and cann ot be changed, which preve nts
cloning of a fact ory locked part. Thi s ensures the secu-
rity of the ES N onc e the product is shipped t o the field.
AMD offers the de vice with th e SecSi S ector e ither
factory locked or customer lockable. The fac-
tory-locked version is always protected when shipped
from the f actor y, a nd h as the S ecSi (Se cured Silic on)
Sector Indicator Bit permanently set to a “1.” The cus-
tomer-lockable version is shipped with the SecSi Sec-
tor unp rot ected, a llow ing cu stome rs to utilize the th at
sector in any manner they choose. The customer- lock-
able version has the SecSi (Secured Silicon) Sector
Indicator Bit permanently set to a “0.” Thus, the SecSi
Sector Indicator Bit prevents customer-lockable de -
vices from being used to replace devices that are fac-
tory locked.
The system accesses the SecSi Sector Secure
through a command sequence (see “Ent er SecSi™
Sector/Exit S ecSi S ector Command Sequence”). After
the system has written the Enter SecSi Se ctor com-
mand sequence, it may read the SecSi Sector by
using the addresses nor mally occupie d by the boot
sectors. This mode of operation continues until the
system issues the Exit SecSi Sector command se-
quence, or until power is removed from the device. On
power-up, or following a hardware reset, the device re-
verts to sending commands to the first 256 bytes of
Sector 0.
Factory Locked: SecSi Sector Programmed and
Protected At the Factory
In a fa ctor y locked de vice, the SecSi Sec tor is pro -
tected when the d evice is shipped f rom the factory.
The SecSi Sector cannot be modified in any way. The
device is preprogramm ed with both a random number
and a secur e E SN . Th e 8- w ord ran dom num ber is at
addresses 000000h–000007h. The secure ESN is pro-
grammed in the next 8 words at addresses
000 008h–00 000Fh . The devic e is available pr epro -
grammed with one of the following:
■A random, secure ESN only
■Custome r code through the ExpressFlash service
■Both a random, secure ESN and customer code
through the ExpressFlash se rvice.
Customers may opt to have their code programmed by
AMD throug h the AMD ExpressF lash service. AMD
programs the cus tomer’s code, with or without th e r an-
dom ESN. Th e de vices ar e then s hipped f rom AMD’s
factory with the SecSi Sector permanently locked.
Contact an AMD representative for details on using
AMD ’s Express Fla sh se rvice .
Customer Lockable: SecSi Sector NOT
Programmed or Protected At the Factory
If the security feature is not required, the SecSi Sector
can be treated a s an additiona l Flash mem ory space .
The SecSi Sector can be read any number of times,
but can be programmed and locked only once. Note
that the accelerated programming (ACC) and unlock
bypass functions are not available when programming
the SecSi Sector.
The SecSi Sector area can be pro tected using one of
the following procedures:
■Write the three-cycle Enter SecSi Sector Region
command sequence, and then follow the in-system
sector protect algorithm as shown in Figure 2, ex-
cept that RE SET# may be at either VIH or VID. Th is
allows in-sy stem protection of the SecSi Sector Re-
gion without raising any device pin to a high voltage.
Note that this method is only applicable to the SecSi
Sector.
■Write the three-cycle Enter SecSi Sector Secure
Region command sequence, and then use the alter-
nate method of sector protection described in the
“Sector/Sector Block Protection and Unprotection”
section.
Once the SecSi Sector is locked and verified, the sys-
tem must write the Exit SecSi Sector Region com-
mand sequence to return to reading and writing the
remainder of the array.
The SecSi Sector lock must be used with caution
since, once locked, there is no procedure available for
unlo cking the SecS i Sec tor ar ea an d none of the b its
in the SecSi Sector memory space can be modified in
any way.
Hardware Data Protection
The command sequence requirement of unlock cycles
for programming or erasing provides data protection
against inadvertent writes (refer to Table 13 for com-
man d def initio ns). I n ad ditio n, th e follow ing hard ware
dat a pr otec tion mea sur es pre vent ac ciden tal er asu re
or programming, which mi ght otherwise be caused by
spurious system level signals during VCC power-up
and power-down transitions, or from system noise.
Low VCC Write In hibi t
When VCC is less than VLKO, the dev ice do es not ac -
cept any write cycles. This protects data during VCC
Spetember 5, 2002 Am29DL642G 23
PRELIMINARY
power-up and power-down. The command register
and all internal program/erase circuits are disabled,
and t he devi ce r ese ts to the rea d mo de . Sub seq uent
writes are ig nored unti l VCC is greate r than VLKO. Th e
system m ust prov ide the pr oper sig nals to t he contr ol
pins to prevent unintentional writes when VCC is
greater than VLKO.
Write Pulse “ Glitc h” Prote c tion
Noise pulses of less than 5 ns (typical) on OE#, CE#
or WE# do not initiate a write cycle.
Logical Inhibit
Write cycles are inhibited by holding any one of OE# =
VIL, CE# = VIH or W E# = V IH. To initiat e a w rite cycle,
CE# and WE# must be a logical zero while OE# is a
logical one.
Power-U p Writ e Inhi bit
If WE# = CE# = VIL and OE# = VIH dur ing po wer up,
the device does not accept commands on the rising
edge of WE #. The internal state m achine is automat i-
call y reset to the read mode on power-up.
COMMON FLASH MEMORY INTERFACE
(CFI)
The Common Flash Interface (CFI) specification out-
lines device and host system software interrogation
handshake, which allows specific vendor-specified
software algorithms to be used for entire families of
devices. Software support can then be device-inde-
pendent, JEDEC ID-independent , and forward- and
bac kward-comp atible f or the s pecifie d flash devic e
familie s. Fla sh ven dors can standar dize the ir exis ting
interfaces for long-term compatibility.
This device enters the CFI Query mode when the sys-
tem writes the CFI Query command, 98h, to address
55h, any time the device is ready to read array data.
The system can read CFI information at the a ddresses
given in Tables 9–12. To terminate reading CFI data,
the system must write the reset command.The CFI
Query mode is not accessible when the device is exe-
cuting an Embedded Program or embedded Erase al-
gorithm.
The system can also write t he CFI query command
when the device is in the autoselect mode. The device
ent ers the CFI qu ery mode , and the syst em ca n read
CFI data at the addresses given in Tables 9–12. The
system must write the reset c ommand to return the de-
vice to reading array data.
For further information, pleas e refer to the CFI Specifi-
cation and CFI Publication 100, available via the
World Wide Web at http://www.amd.com/us-en/as-
sets/content_t ype/DownloadableAs sets/cfi100.pdf and
http://www.amd.com/us-en/assets/content_type/Down
loada bleAssets/cfiamd 1.pdf. Alternativel y, contact an
AMD representative for copies of these documents.
Table 9. CFI Query Identification String
Addresses Data Description
10h
11h
12h
0051h
0052h
0059h Query Unique ASCII string “QRY”
13h
14h 0002h
0000h Primary OEM Command Set
15h
16h 0040h
0000h Address for Primary Extended Table
17h
18h 0000h
0000h Alternate OEM Command Set (00h = none exists)
19h
1Ah 0000h
0000h Address for Alternate OEM Extended Table (00h = none exists)
24 Am29DL642G Spetember 5, 2002
PRELIMINARY
Table 10. S ystem Interface String
Table 11. Device Geomet ry Defini tion
Addresses Data Description
1Bh 0027h VCC Min. (write/erase)
D7–D4: volt, D3–D0: 100 millivolt
1Ch 0036h VCC Max. (write/erase)
D7–D4: volt, D3–D0: 100 millivolt
1Dh 0000h VPP Min. voltage (00h = no VPP pin present)
1Eh 0000h VPP Ma x. voltage (00h = no VPP pin present)
1Fh 0004h Typical timeout per single byte/word write 2N µs
20h 0000h Typical timeout for Mi n. size buffer write 2N µs (00h = not supported)
21h 000Ah Typical timeout per individual block erase 2N ms
22h 0000h Ty pical timeout for full chip erase 2N ms (00h = not supported)
23h 0005h Max. timeout for byte/word write 2N times typical
24h 0000h Max. timeout for buffer write 2N times typical
25h 0004h Max. timeout per individual block era se 2N times typical
26h 0000h Max. timeout for full chip erase 2N times typical (00h = no t supported)
Addresses Data Description
27h 0017h Device Size = 2N byte
28h
29h 0002h
0000h Flash Device Interface description (refer to CFI publication 100)
2Ah
2Bh 0000h
0000h Max. number of byte in multi-byte write = 2 N
(00h = not s upported)
2Ch 0003h Number of Erase Block Regions within device
2Dh
2Eh
2Fh
30h
0007h
0000h
0020h
0000h
Eras e Block Region 1 Information
(refer to the CFI specification or CFI publication 100)
31h
32h
33h
34h
007Dh
0000h
0000h
0001h
Eras e Block Region 2 Information
(refer to the CFI specification or CFI publication 100)
35h
36h
37h
38h
0007h
0000h
0020h
0000h
Eras e Block Region 3 Information
(refer to the CFI specification or CFI publication 100)
39h
3Ah
3Bh
3Ch
0000h
0000h
0000h
0000h
Eras e Block Region 4 Information
(refer to the CFI specification or CFI publication 100)
Spetember 5, 2002 Am29DL642G 25
PRELIMINARY
Table 12. Primary Vendor-Speci fic Extended Query
Addresses Data Description
40h
41h
42h
0050h
0052h
0049h Query-unique ASCII string “PRI”
43h 0031h Major version number, ASCII (reflects modifications to the silicon)
44h 0033h Minor version number, ASCII (reflects modifications to the CFI table)
45h 0004h Address Sensitive Unlock (Bits 1-0)
0 = Required, 1 = No t Required
Silicon Revision Number (Bits 7-2)
46h 0002h Erase Suspend
0 = Not Supported, 1 = To Read Only, 2 = To Read & Write
47h 0001h Sector Protect
0 = Not Supported, X = Number of sectors in per group
48h 0001h Sector Temporary Unprotect
00 = Not Supported, 01 = Supported
49h 0004h Sector Protect/Unprotect scheme
01 =29F040 mode, 02 = 29F016 mode, 03 = 29F400, 04 = 29LV800 mode
4Ah 0077h Simultaneous Operation
00 = Not Supported, X = Number of Sectors (excl uding Bank 1)
4Bh 0000h Burst Mode Type
00 = Not Supported, 01 = Supported
4Ch 0000h Page Mode Type
00 = Not Supported, 01 = 4 Word Page, 02 = 8 Word Page
4Dh 0085h ACC (Acceleration) Supply Minimum
00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV
4Eh 0095h ACC (Acceleration) Supply Maximum
00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV
4Fh 0004h
Top/Bottom Boot Sector Flag
00h = Uniform device, 01h = 8 x 8 Kbyte Sectors, Top And Bottom Boot with Write
Protec t, 02h = Bottom Boot Device, 03h = Top Boot Device, 04h = Both Top and
Bottom
50h 0001h Program Suspend
0 = Not supported, 1 = Supported
57h 0004h Bank Organization
00 = Data at 4Ah is zero, X = Number of Banks
58h 0017h Bank 1 Region Information
X = Number of Sectors in Bank 1
59h 0030h Bank 2 Region Information
X = Number of Sectors in Bank 2
5Ah 0030h B ank 3 Region Information
X = Number of Sectors in Bank 3
5Bh 0017h B ank 4 Region Information
X = Number of Sectors in Bank 4
26 Am29DL642G Spetember 5, 2002
PRELIMINARY
COMMAND DEFINITIONS
Writing specific address and data commands or se-
quences int o the command register initi ates device op-
erations. Table 13 defines the valid register command
sequenc es. Writing incorrect ad dress an d data v al-
ues or writing them in the improper sequence re sets
the device to reading array data.
All a ddre sses are l atc hed o n th e falli ng edge of WE#
or CE#, whichever happens later. All data is latched on
the rising edge of WE# or CE#, whichever happens
first. Refer to the AC Characteristics section for timing
diagrams.
Reading Array Data
The device is automatically set to reading array data
after device pow er-up. No co mma nds are requir ed t o
retrieve data. Each bank is ready to read array data
after completing an Embedded Program or Embedded
Erase algorithm.
After the device accepts an Erase Suspend co mmand,
the corresponding bank enters the erase-sus-
pend-read mode, after which the system can read
data from any no n-erase-suspended sector wit hin the
same bank. The system can read array data using the
stand ard rea d ti ming , e xcept tha t if it r ead s at an ad-
dress within erase-suspended sectors, the device out-
puts status data. After completing a programming
operation in the Erase Suspend mode, the system
may once again read array data with the same excep-
tion. See the Erase Suspend/Erase Resume Com-
mands section for more info rmat ion.
The system must issue the reset command to return a
bank to the read (or erase-suspend- read) mode if DQ5
goes high during an active program or erase opera-
tion, o r if the bank is in the autosele ct mod e. S ee the
next section, Res et Command, for more inform atio n.
See also Requirements for Reading A rray Data in the
Device Bus Operations section for more information.
The Read-Only Operat ions table provi des the read pa-
rameters, and Figu re 13 shows the timing diagram.
Reset Command
Writing the reset command resets the banks to the
read or erase-suspend-read mode. Address bits are
don’t cares for this command.
The reset command may be written between the se-
quence cycles in an erase command sequence before
erasing begins. This reset s the bank to which the sys-
tem was writing to the read mode. Once erasure be-
gins, however, the device ignores reset commands
until th e operation is complete.
The reset command may be written between the
seque nce cycles in a pro gram com ma nd seque nce
before programming begins. This resets the bank to
which the s ystem was writing t o the read mode. If the
progra m command sequen ce is writte n to a bank that
is in the Erase Suspend mode, writing the reset
command returns that bank to the erase-sus-
pend-read mode. Once programming begins, how-
ever, the device ignores reset commands until the
operation is complete.
The reset command may be written between the se-
quence cycles in an autoselect command sequence.
Once in the autoselect mode, the reset command
mus t be w ritten t o return t o the read m ode. If a b ank
entered the autoselect mode while in the Erase Sus-
pend mo de, writing the reset command returns th at
bank to the erase-suspend-read mode.
If DQ5 goes high during a program or er ase op eration,
writing t he reset comman d retur ns the banks to the
read mode (or eras e-sus pend-read mode if that bank
was in Erase Suspend).
Autoselect Command Sequence
The autoselect command sequence allows the hos t
system to access the manufacturer and device codes,
and determine whether or not a sector is protected.
The autoselect command sequence may be written to
an address within a bank that is either in the read or
eras e-sus pend-r ead m ode. The au tose lect c ommand
ma y not be wr itten wh ile the device is active ly pro-
gramming or erasing in the other bank.
The autoselect command sequence is initiated by first
writing two unlock cycles. Th is is followed b y a third
write cycle that contains the bank address and the au-
to select comma nd. Th e b ank the n ent ers t he autos e-
lect mode. The system may read any number of
autoselect codes without reinitiating the command se-
quence.
Table 13 shows the address and data requirements.
To determine sector protection information, the system
must write to the appropriate bank address (BA) and
sector address (SA). Table 2 shows the address r ange
and bank number associated with each sector.
The system must write the reset command to return to
the read mode (or erase-suspend-read mode if the
bank was p reviously in Erase Suspend).
Enter SecSi™ Sector/Exit SecSi Sector
Command Seque nce
The SecSi Sector regi on pr ovi des a secured dat a ar ea
containing a random, sixteen-byte electronic serial
number (ESN). The system can access the SecSi
Se ctor re gion by issuin g the th ree- cycle Ent er SecS i
Sector command sequence. The device continues to
access the S ecSi Sector region u ntil the system is-
sues the four-cycle Exit SecSi Sector command se-
Spetember 5, 2002 Am29DL642G 27
PRELIMINARY
quence. The Exit SecSi Sector command sequence
returns the device to normal operation. The SecSi
Sector is not acces sible when the dev ice is executing
an Embedded Progr am or embedded Erase al gorithm.
Table 13 shows the address and data requirements for
both comma nd seque nces. Se e also “Se cSi™ (S e-
cur ed S ilic on) Sect or Flash M em ory R egio n” fo r furth er
information.
Word Program Command Sequence
Programming is a four-bus-cycle operation. The pro-
gram comm and sequence is initiated by writing tw o
unlock write cycles, followed by the program set-up
command. The p rogram address and data are written
next, which in turn initiate t he Embedde d Progr am al-
gorithm. T he system is not required to p rovide further
controls or timings. The device automatically provides
internally generated program pulses and verifies the
programmed cell margin. Table 13 shows the address
and data requirements for the word program com-
mand sequence.
When the Em bedded P rogram algorit hm is co mplete,
that bank then returns to the read mode and ad-
dresses are no longer latched. The system can deter-
mine the status of the program operation by using
DQ7, DQ6, or RY/BY #. Refer to the Write Operation
Status section for information on these status bits.
Any commands written to the device during the Em-
bedded Program Algorithm are ignore d. Note that a
hardware reset immediately terminates the program
operation. The program command sequence should
be reinitiated o nce that bank has returned to the rea d
mode, to ensure data integrity.
Prog rammin g is a llowed in a ny sequ ence a nd across
sector boundaries. A bi t cannot b e pr ogramm ed
from “0” back to a “1.” Attempting to do so may
cause t hat bank to set DQ5 = 1, or c aus e the DQ7 and
DQ6 stat us bi ts to i ndic ate t he oper ation was success-
ful. However, a succeeding read will show that the
data is still “0.” Only erase operations can convert a
“0” to a “1.”
Unlock Bypass Command Sequence
The unlock bypass feature allows the system to pro-
gram words to a bank faster than using the standard
program command sequence. The unlock bypass
command sequence is initiated by first writing two un-
lock cycles. This is followed by a third write cycle con-
taining the unlock bypass command, 20h. That bank
the n enters the unloc k bypa ss mode. A two- cycle un-
lock bypass program command sequence is all that is
required to program in this mode. The first cycle in t his
sequence contains the unlock bypass program com-
man d, A0h; the s econd cycl e contains the program
address and data. Additional data is programmed in
the same manner. This mode dispenses with t he initial
two unlock c ycles requ ired in the standard program
command se quence, resulting in faster total program-
ming time. Table 13 shows the requirements for the
command sequence.
Dur ing th e un lo ck by pas s m ode , o nly the Un loc k By -
pass Progr am and Un lock Bypass Reset commands
are valid. To exit the unlock bypass mode, the system
must issue the two-cycle unlock bypass reset com-
mand sequence. The first cycle must contain the bank
address and the data 90h. The second cycle need
only contain the data 00h. The bank then returns to
the read mode.
The device offers accelerated program operations
through t he WP#/ACC pin. Whe n th e system as serts
VHH on the W P#/ACC pin, the device automatical ly en-
ters the Unlock Bypass mode. The system may then
write the two-cycle Unlock Bypass program command
sequ ence. T he device u ses the h igher voltage on the
WP#/ACC pin to accelerate the operation. No te that
the WP#/ACC pin must not be at VHH any operation
other tha n accelerate d programmin g, o r device da m-
age may result. In addition, the WP#/ACC pin must not
be l eft f loating or u nconn ec ted; incon siste nt beha vior
of the device may result.
Figure 3 illustrates the algorithm for the program oper-
ation. Refer to the Erase and Program Operations
table in the AC Characteristics section for parameters,
and Figure 15 for timing diagrams.
28 Am29DL642G Spetember 5, 2002
PRELIMINARY
Figure 3. Program Operation
Chip Erase Command Sequence
Chip erase is a six bus cycle operation. The chip erase
com man d se quen ce is in iti ated b y w rit ing tw o unlo ck
cycles, followed by a set-up command. Two additional
unlock write cycles are then followed by the chip erase
command, which in turn invokes the Embedded Erase
algor ithm. The d evic e doe s not require the s ystem to
preprogram pr ior to erase . T he E m bedded E r as e algo-
rithm automaticall y pr eprogr ams and verif ies the entire
memory fo r an all zero data pattern p rior to electrical
erase. The system is not required to provide any con-
trols or timings during these operations. Table 13
shows the address and data requirements for the chip
erase command sequence.
When the Embedded Erase algorithm is complete,
that bank returns to the read mode and addresses are
no longer latched. The system can det ermine the sta-
tus of the erase operation by using DQ7, DQ6, DQ2,
or RY/BY#. Re fer to the Write Operation Status sec-
tion for info rmation on these status bits.
Any commands written during t he chip erase operation
are ignored. However, note that a hardware reset im-
mediately terminates the erase operation. If that oc-
curs, the chip erase c ommand sequence should be
reinitiated once that bank has returned to reading
array data, to ensure data integrity.
Fi gure 4 illus trates the algori thm f or the eras e ope ra-
tion. Refer to the Erase and Program Operations ta-
bles in the AC Ch aracteristics section for para meters,
and Figure 17 section for tim ing diagrams.
Sector Erase Command Sequence
Sector erase is a six bus cycle operation. The sector
erase command sequence is initiated by writing two
unlock cycles, followed by a set-up command. T wo ad-
ditional unlock cycles are written, and are then fol-
lowe d by t he ad dres s of the secto r to be er ased, and
the sector erase command. Table 13 shows the ad-
dress and dat a r equir em ents for the sec tor erase com-
mand sequence.
The device does not require the system to preprogram
prior to erase. The Embedded Erase algorithm auto-
matically programs an d verifies the en tire memory for
an all zero data pattern prior to electrical erase. The
system is not required to provide any controls or tim-
ings during these operations.
After the command sequence is written, a sector erase
time-out of 80 µs occurs. During the time-out period,
additional sector addresses and sector erase com-
mands may be wri tten. Loading the sector erase buffer
may be done in any sequence, and the number of sec-
tors may be from one sector to all sectors. The time
between thes e additional cycles must be less than 80
µs, otherwise er asure may b egin. Any se ctor erase
address and command following the exceeded
time-out may or may not be accepted. It is recom-
mended that processor interrupts be disabled during
this t ime to ensu re al l com mand s ar e acce pted . The
interrupts can be re-enabled after the last Sector
Erase command is wri tten. Any command other t han
Sector Erase or Erase Suspend during the
time-out period resets that bank to the read mode.
The system mus t rewrite the command sequence and
any additional addresses and commands.
The system c an monitor DQ3 to determine if the sec-
tor erase timer has timed out (See the section on DQ3:
Sector Erase Tim er . ). The time-out begins from the ris-
ing edge of the final WE# pulse in the command
sequence.
When the Embedded Erase algorithm is complete, the
bank returns to reading arr ay data and addresses are
no longer latched. Note that while the Embedded
Erase operation is in progress, the system can read
data from the non-erasing bank. The system can de-
termine the status of the erase operation by reading
START
Write Program
Command Sequence
Data Poll
from System
Verify Data? No
Yes
Last Address?
No
Yes
Programming
Completed
Increment Address
Embedded
Program
algorithm
in progress
Note: See Table 13 for program command sequence.
Spetember 5, 2002 Am29DL642G 29
PRELIMINARY
DQ7, DQ6, DQ2, or RY/BY# in the erasing bank.
Refer to the Wri te Opera tion S tatus section for infor-
mation on these status bits.
Once the sector er ase operation has begu n, only the
Erase Suspend command is valid. All other com-
mands are ignored. However, note that a hardware
reset immediately terminates the erase operation. If
that occurs, the sector erase command sequence
should be reinitiated once that bank has r eturned to
reading array data, to ensure data integrity.
Figure 4 illus trates the algor ithm fo r th e era se op era-
tion. R efer to the Erase and Program Operations ta-
bles in the AC Charact eristics section for parameters,
and Figure 17 section for timing diagrams.
Erase Suspend/Erase Resume
Commands
The Erase Suspend command, B0h, allows the sys-
tem to int errupt a sector erase operat ion and then read
data from, or program data to, any sector not selected
for er asur e. The bank address is required when wri ting
this comman d. This c ommand is v alid only d uring the
sector erase operation, including the 80 µs time-out
period during the sector erase command sequence.
The Erase Suspend command is ignored if written dur -
ing the chip erase operation or Embedded Program
algorithm.
Whe n the E ras e S uspen d co mmand is w ritte n dur ing
the sector erase operation, the device requires a max-
imum of 20 µs to suspend the erase operation. How-
ever, whe n the Erase S uspend c ommand is writte n
during the sector erase time-out, the device immedi-
ately terminates the t ime-out period and suspends the
erase operation. Addr esses are “d on’t-cares” when
writing the Era se suspend command.
After th e erase operation has bee n suspended , the
bank en ters the erase -suspend-rea d mode. T he sys-
tem can read data from or program data to any sector
not selected for erasure. (The device “erase sus-
pends” all sectors selected for erasure.) Reading at
any address within erase-suspended sectors pro-
duces status information on DQ7–DQ0. The system
can use DQ7, or DQ6 and DQ2 together, to determine
if a sector is actively erasing or is erase-suspended.
Refer to the Wri te Opera tion S tatus section for infor-
mation on these status bits.
After an eras e-suspe nde d prog ram operatio n is c om-
plete, the bank returns to the erase-suspend-read
mode. The system can determine the status of the
progr am ope ration u sing the DQ7 or DQ6 status bits,
just as in the standard Word Program operation.
Refer to the Write Operation Status section for more
information.
In the erase-suspend-read mode, the system can also
issu e the autoselec t comm and seque nce. The device
allows reading autoselect codes ev en at addresses
within erasing sectors, since the code s are not stored
in the mem ory array. When the dev ice exits the au-
toselect mode, the device reverts to the Erase Sus-
pen d mode, and is rea dy for ano ther vali d operation .
Refer to the Autoselect Mode and Autoselect Com-
mand Sequence sections for details.
To resume the sector erase operation, the system
must write the Erase Resume command (address bits
are don’t care). The bank address of the erase-sus-
pend ed bank is req uired wh en wr iting t his comma nd.
Further writes of the Resume command are ignored.
Another Erase Suspend com mand can be written after
the chip has resumed erasing.
Figure 4. Erase Operation
START
Write Erase
Command Sequence
(Notes 1, 2)
Data Poll to Erasing
Bank from System
Data = FFh?
No
Yes
Erasure Completed
Embedded
Erase
algorithm
in progress
Notes:
1. See Table 13 for er ase command sequence.
2. See th e section on DQ3 for information on the sector
erase timer.
30 Am29DL642G Spetember 5, 2002
PRELIMINARY
Table 13. Am29DL642G Command Defini t io ns
Legend:
X = Don’t ca re
RA = Address of th e m em ory lo cation to be read.
RD = Data read from location RA during r ead op eration.
PA = Address of th e m em ory location to be programmed. Address es
latch on the falling edge of the WE# or CE# pulse, whichever happens
later.
PD = Data to be program med at locat ion PA. Data latc hes on the ri sing
edge of WE# or CE# pulse, whi chever happens first.
SA = Address of the sector to be v erif ied (i n autoselec t mode) or
erased. Addres s bits A21–A12 uniquely sele ct any sector. Ref er to
Table 2 for information on sector addresses.
BA = Address of the bank that is bei ng switched to aut oselect mode, is
in bypass mode, or is being erased. A21–A19 uniquely select a bank.
Notes:
1. See Table 1 for description of bus operations.
2. All values are in hexadecimal.
3. Except for the read cycle and the fourth cycle of the autoselect
command sequence, all bus cycles are write cycles.
4. Data bits DQ15–DQ8 are don’t care in command sequences,
except for RD and PD.
5. Unless otherwise noted, address bits A21–A11 are don’t cares for
unlock and command cycles, unless SA or PA is required.
6. No unlock or command cycles required when bank is reading
array data.
7. The Reset command is required to return to the read mode (or to
the erase-suspend-read mode if previously in Erase Suspend)
when a bank is in the autoselect mode, or if DQ5 goes high (while
the bank is providing status information).
8. The fourth cycle of the autoselect command sequence is a read
cycle. The system must provide the bank address to obtain the
manufacturer ID, device ID, or SecSi Sector factory protect
inform ation. Data bits DQ15–DQ8 are don’t care. See the
Autoselect Comm and Sequence section for mor e information.
9. The device ID must be read across the fourth, fifth, and sixth
cycles.
10. The data is 80h for factory locked and 00h for not factory locked.
11. The data is 00h for an unprotected sector/sector block and 01h
for a protected sector/sector block.
12. The Unlock Bypass command is required prior to the Unlock
Bypass Program command.
13. The Unloc k Bypass Reset command is required to return to the
read mode when the bank is in the unlock bypass mode.
14. The system may read and program in non-erasing sectors, or
enter the autoselect mode, when in the Er ase Suspend mode.
The Erase Suspend command is valid only during a s ector erase
operation, and requires the bank address.
15. The Erase Resume command is valid only during the Erase
Suspend mode, and requires the bank addr ess.
16. Command is valid when device is ready to read array data or when
device is in autoselect mode.
Command
Sequence
(Note 1)
Cycles
Bus Cycles (Notes 2–5)
First Second Third Fourth Fifth Sixth
Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data
Read (Note 6) 1 RA RD
Reset (Note 7) 1 XX X F0
Autoselect (Note 8)
Manufacturer ID 4 555 A A 2AA 55 (BA)555 90 (BA)X00 01
Device ID (Note 9) 6 555 A A 2AA 55 (BA)555 90 (BA)X01 7E (BA)X0E 02 (BA)X0F 01
SecSi Sector Factory Protect
(Note 10) 4 555 AA 2AA 55 (BA)555 90 (BA)X03 80/00
Sector/Sector Block Protect
Verify (Note 11) 4 555 AA 2AA 55 (BA)555 90 (SA)X02 00/01
Enter Sec Si Sector Region 3 555 AA 2AA 55 555 88
Exit SecSi Sector Region 4 555 AA 2AA 55 555 90 XXX 00
Program 4 555 AA 2AA 55 555 A0 PA PD
Unlock Bypass 3 555 AA 2AA 55 555 20
Unlock Bypass Program (Note 12) 2 XXX A0 PA PD
Unlock Bypass Reset (Note 13) 2 BA 90 XXX 00
Chip Erase 6 555 A A 2AA 55 555 80 555 AA 2AA 55 555 10
Sector Erase 6 555 AA 2AA 55 555 80 555 AA 2AA 55 SA 30
Erase Suspend (Note 14) 1 BA B0
Erase Resume (Note 15) 1 BA 30
CFI Query (Note 16) 1 55 98
Spetember 5, 2002 Am29DL642G 31
PRELIMINARY
WRITE OPERATION STATUS
The device provides several bits to determine the status of
a program or erase operation: DQ2, DQ3, DQ5, DQ6, and
DQ7. Tabl e 14 and the following subsec tions de s c rib e the
function of the s e bits. DQ 7 and DQ6 eac h offer a method
for determining whether a progr am or erase opera tion is
complete or in progress. The device also provides a hard-
war e-based out put signal, RY /BY#, to det er m ine whether
an Embedded Progr am or Erase operation is in progress or
has been completed.
DQ7: Data# Polling
The Data# Polling bit, DQ7, indicates to the host system
whether an Em bedded Prog ram or Erase alg orit hm is in
progress or completed, or whether a bank is in Erase Sus-
pend. Data# Polling is valid after the rising edge of the final
WE# pulse in the command sequence.
Dur ing the Embed ded Program algor ithm, the device out-
puts on DQ7 the complement of the datum pr ogrammed to
DQ7. This DQ7 status also applies to programming during
Erase Suspend. When the Embedded Program algor ithm is
comp lete, the devic e outputs the datum pr og ram m ed t o
DQ7 . T he sy s tem m us t pr ov ide th e p ro gr am addres s t o
read valid status information on DQ7. If a pr ogram address
falls within a protected sector, Data# Polling on DQ7 is ac-
tive for approximate ly 1 µs, then that ba nk retur ns to the
read mode.
During the Embe dded E rase al gorithm, D ata# P olling
produces a “0” on DQ7. When the Embedded Erase
algorithm is compl ete, or if the ba nk enter s the Er ase
Suspend mode, Data# Polling produces a “1” on DQ7.
The system must provide an address within any of the
sectors selected for er asure to read valid stat us infor-
mation on DQ7.
After an erase command sequence is written, if all
sectors selected for erasing are protected, Data# Poll-
ing on DQ7 is active for approximately 100 µs, then
the bank returns to th e read mo de. If not all selecte d
sectors are protected, the Embedded Erase algorithm
erases the unprotected sectors, and ignores the se-
lected sectors tha t are protected. However, if the sys -
tem reads DQ7 at an address within a protected
secto r, the st atu s may n ot be vali d.
When the system det ects DQ7 has cha nged from the
complement to true data, it can read valid data at
DQ15–DQ0 o n the following read cy cles. Just prior to
the completion of an Embedded Program or Erase op-
eration, DQ7 may change asynchronously with
DQ15–DQ8 w hile Ou tput Enable (OE#) is asserted
low. That is, the device ma y chan ge from prov iding
status information to valid data on DQ7. Depending on
when the sy stem samples the DQ 7 output , it may read
the status or valid data. Even if the device has com-
pleted the program or erase operation and DQ7 has
valid data, the data outputs on DQ15–DQ0 may be stil l
inv alid. Vali d d ata on D Q15–D Q0 will a pp ear o n su c-
cessi ve read cy cles.
Table 14 shows the outputs for Data# Polling on DQ7.
Figure 5 shows the Data# Polling algorithm. Figure 19
in the AC Characteristics section shows the Data#
Polling timing diagram.
Figure 5. Da ta # P o llin g A lg orit h m
DQ7 = Data? Yes
No
No
DQ5 = 1?
No
Yes
Yes
FAIL PASS
Read DQ7–DQ0
Addr = VA
Read DQ7–DQ0
Addr = VA
DQ7 = Data?
START
Notes:
1. VA = Valid address for programming. During a sector
erase operation , a valid address is any sector address
within the sector being erased. During chip erase, a
valid address is any non-protected sector address.
2. DQ7 should be rechecked even if DQ5 = “1” because
DQ7 may change simultaneously with DQ5.
32 Am29DL642G Spetember 5, 2002
PRELIMINARY
RY/BY#: Read y/Bu sy#
The RY/BY# is a dedicated, open-drain output pin
which indicates whether an Embedded Algorithm is in
progress or complet e. T he RY /BY# status is vali d aft er
the rising edge of the final WE# pulse in the command
sequence. Since RY/BY# is an open-drain output , sev-
eral RY/BY# pins c an be tied t ogether in parallel with a
pull-up resistor to VCC.
If the output is low (Bus y), the device is actively eras -
ing or program ming. (This includes programming in
the Erase Suspend mode.) If the output is high
(Rea dy) , th e dev ice is in the rea d mode , th e sta ndby
mode, or one of the banks is in the erase-sus-
pend-read mode.
Table 14 shows the outputs for RY/BY#.
DQ6: Toggle Bit I
To gg le B it I on D Q6 indi cates whe the r an Em bed ded
Program or Erase algorithm is in progress or com-
plete, or wheth er the device has entered t he Erase
Suspend mode. Toggle Bit I may be read at any ad-
dress, a nd is valid after the ris ing ed ge of the f inal
WE# pulse in the command sequence (prior to the
program or er ase oper ation), and during t he sector
erase time-out .
During an Embedded Program or Erase algo rithm op-
eration, successive r ead cycles to any address cause
DQ6 to toggle. The system may use either OE# or
CE# to control the read cycles. When the operation is
complet e, DQ6 stops toggling.
After an erase command sequence is written, if all
sectors selected for erasing are protected, DQ6 tog-
gles for approximately 100 µs, then returns to reading
array data. If not all selected sectors are protected, the
Embedded Erase algorithm er ases the unprotected
sectors, and ignores the selected sectors that are pro-
tected.
The system can use DQ 6 and DQ2 t ogether to det er-
mine whether a sector is actively erasing or is
erase-suspended. When the device is actively erasing
(that is, the Embedded Erase algorithm is in progress),
DQ6 togg les. Whe n the device enters the E rase Sus -
pend mode, DQ6 stops toggling. However, the system
must also use DQ2 to dete rmine w hich sector s are
erasing or erase-suspended. Alternatively, the system
can use DQ7 (see the subsection on DQ7: Data# Poll -
ing).
If a program address falls within a protected sector,
DQ6 toggles for approximately 1 µs af ter the program
command sequence is written, then returns to reading
array data.
DQ 6 al so to ggl es d urin g th e er ase-s usp end- prog ram
mod e, and stops toggling once the Embedde d Pro-
gram algorithm is complete.
Table 14 shows the outputs for Toggle Bit I on DQ6.
Figure 6 shows the toggle bit algorithm. Figu re 20 in
the “AC Characteristics” section shows the toggle bit
timing d iagrams . Figur e 21 sho ws th e d iffere nce s b e-
tween DQ2 and DQ6 in graphical form. See also the
subsection on DQ2: Toggle Bit II.
Figure 6. To ggle B it A lg orit h m
START
No
Yes
Yes
DQ5 = 1?
No
Yes
Toggle Bit
= Toggle? No
Program/Erase
Operation Not
Complete, Write
Reset Command
Program/Erase
Operation Complete
Read DQ7–DQ0
Toggle Bit
= Toggle?
Read DQ7–DQ0
Twice
Read DQ7–DQ0
Note: The system should recheck the toggle bit even if DQ5
= “1” because the toggle bit may stop toggling as DQ5
changes to “1.” See the subsections on DQ6 and DQ2 for
more information.
Spetember 5, 2002 Am29DL642G 33
PRELIMINARY
DQ2: Toggle Bit II
The “Toggle Bit II” on DQ2, when used with DQ6, indi-
cates whether a particular sector is actively erasing
(that is, the Embedded Erase algorithm is in progress),
or whether that sector is erase- suspended. Tog gle Bit
II is valid after the rising edge of t he final WE# pulse in
the command sequence.
DQ2 toggles when the system reads at addresses
within those sectors that have been selected for era-
sure. (The system may use either OE# or CE# to con-
trol the read cycles.) But DQ2 cannot distinguish
whether the sector is actively erasing or is er ase-sus-
pended. DQ6, by comparison, indicates whether the
device is actively erasing, or is in Erase Suspend, but
cannot distinguis h which se ctors are selected for era-
sure. Thus, both s tat us bits ar e r equired for sector and
mode information. Refer to Table 14 to compare out-
puts for DQ2 and DQ6.
Figur e 6 shows the toggle bit a lgorithm in flowchart
form, and the section “DQ2: Toggle Bit II” explains the
algorithm . See a lso th e DQ6: To ggle Bit I sub section.
Fig u re 2 0 shows the toggle bit timing diagra m. Figure
21 shows the differences between DQ2 and DQ6 in
graphical form.
Reading Toggle Bits DQ6/DQ2
Refer to Figur e 6 for t he follo wing disc ussio n. W hen -
ever the system init ially beg ins reading t oggle bit s ta-
tus, it must read DQ15–DQ0 at least twice in a row to
determine whether a toggle bit is toggling. Typically,
the system wo uld note and store the va lue of the tog-
gle bit after the first read. After the second read, the
system would compare the new value of the toggle bit
with the fir st. If the toggle bit is not tog gling, the device
has completed the program or erase operation. The
system can read array data on DQ15–DQ0 on the fol-
lowing read cycle.
However, if after the initial two read cycles, the system
determines that the toggle bit is still tog gling, the s ys-
tem also should note whether the value of DQ5 is high
(see the section on DQ5). If it is, the system should
then dete rmine again w hethe r the to ggle bit is t og-
gling , s ince the t oggl e bit ma y ha ve s toppe d to gglin g
just as DQ5 w ent high. If the t oggle bit is no longer
toggling, the device has successfully completed the
program or erase oper ation. If it is stil l toggling, t he de-
vice did not completed the operation successfully, and
the system must write the reset command to return to
reading array data.
The remain ing scenario is that the sy stem initially de -
termines that the toggle bit is toggling and DQ5 has
not gone high. The system may continue to monitor
the toggle bit and DQ5 through successive read cy-
cles, determining the status as described in the previ-
ous paragraph. Alternatively, it may choose to perform
other system tasks. In this case, the system must start
at the beginning of the algorit hm when it returns to de-
termine the status of the operation (top of Figure 6).
DQ5: Exceeded Timing Limits
DQ5 indicates whether the program or erase time h as
exceeded a specified internal pulse count limit. Under these
conditions DQ5 produces a “1,” indicating that the program
or erase cycle was not successfully completed.
The device may output a “1” on DQ5 if t he system tries
to program a “1” to a location that was previously pro-
grammed to “0.” Only an erase operation can
change a “0” back to a “1.” Under this condition, the
device halts the operation, and when the timing limit
has been exceeded, DQ5 prod uces a “1.”
Under both these conditions, the system must write
the reset command to return to the read mode (or to
the erase-suspend-read mode if a bank was previ-
ously in the erase-suspend-program mode).
DQ3: Sector Erase Timer
After writing a sector erase command sequence, the
system may read DQ3 to deter mine whe ther or no t
era sure has b egun. ( The secto r era se tim er do es no t
apply to the chip erase command.) If additional
sectors are selected for erasure, the entire time-out
also applies after each additional sector erase com-
mand. When the time-out period is complete, DQ3
switch es from a “0” to a “1.” I f the time b etween addi-
tional sector erase commands from the system can be
assumed to be less than 50 µs, the system need not
monitor DQ3. See also the Sec tor Erase Command
Sequence section.
After t he sector erase command is writ ten, the syst em
should read the status of DQ7 (Data# Polling) or DQ6
(Toggle Bit I) to ensure that the device has accepted
the command sequence, and then read DQ3. If DQ3 is
“1,” the Embedded Erase algorithm has begun; all fur-
ther com mand s (ex cept E rase Suspen d) are ig nored
until the erase operation is complete. If DQ3 is “0,” the
devic e will accept additional sec tor erase com mands.
To en sure the c ommand has bee n accepted , the sys-
tem software should check the status of DQ3 prior to
and following each subsequent sector erase com-
mand. I f DQ3 is high o n the s econd status check, the
last command might not have been accepted.
Table 14 shows the status of DQ3 relative to the other
status bits.
34 Am29DL642G Spetember 5, 2002
PRELIMINARY
Table 14. Writ e Operati on Status
Notes:
1. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits.
Refer to the section on DQ5 for more information.
2. DQ7 and DQ2 require a valid address when reading status infor mation. Refer to the appropriate subsection for further
details.
3. When reading write operation status bits, the system must always provide the bank address where the Embedded Algorithm
is in progress. The device outputs array data if the system addresses a non-busy bank.
Status DQ7
(Note 2) DQ6 DQ5
(N ote 1) D Q3 DQ2
(N ote 2) RY/BY#
Standard
Mode Embedded Program Algorithm DQ7# Toggle 0 N/A No toggle 0
Embedded Erase Algorithm 0 Toggle 0 1 Toggle 0
Erase
Suspend
Mode
Erase-Suspend-
Read
Erase
Suspended Sector 1 No toggle 0 N/A Toggle 1
Non-Erase
Suspended Sector Data Data Data Data Data 1
Erase-Suspend-Program DQ7# Toggle 0 N/A N/A 0
Spetember 5, 2002 Am29DL642G 35
PRELIMINARY
ABSOLUTE MAXIMUM RATINGS
Storage Temperature
Plast ic Packages . . . . . . . . . . . . . . . –65°C to +150°C
Ambient Temperature
with Power Appli e d . . . . . . . . . . . . . –65°C to +125°C
Voltage with Respect to Ground
VCC (Note 1) . . . . . . . . . . . . . . . . .–0.5 V to +4.0 V
A9, OE#, and RESET#
(No te 2). . . . . . . . . . . . . . . . . . . .–0.5 V to +12 .5 V
WP#/ACC . . . . . . . . . . . . . . . . . .–0.5 V to +10 .5 V
All other pins (Note 1). . . . . . –0.5 V to VCC +0.5 V
Output Short Circuit Current (Note 3) . . . . . . 200 mA
Notes:
1. Minimum DC voltage on input or I/O pins is –0.5 V.
During voltage transitions, input or I/O pins may
overshoot VSS to –2.0 V for periods of up to 20 ns.
Maximu m DC volta ge on input or I/O pins is VCC +0.5 V.
See Figure 7. During voltage transitions, input or I/O pins
may overshoot to VCC +2.0 V for periods up to 20 ns. See
Figure 8.
2. Minimum DC input voltage on pins A9, OE#, RESET#,
and W P#/A CC is –0.5 V. Du ring vo ltage tran sitio ns, A9,
OE#, WP#/ACC, and RESET# may overshoot VSS to
–2.0 V for periods of up to 20 ns. See Figure 7. Maximum
DC input voltage on pin A9 is +12.5 V which may
overshoot to +14.0 V for periods up to 20 ns. Maximum
DC input voltage on WP#/ACC is +9.5 V which may
overshoot to +12.0 V for periods up to 20 ns.
3. No more than o ne output may be shor ted to ground at a
time. Duration of the short circuit should not be greater
than one second.
Stresses above those listed under “Absolute M aximum
Rati ngs” m ay caus e perm anen t damage to the dev ice. Th is
is a stress rating only; functional operation of the device at
these or any other conditions above those indicated in the
operational sections of this data sheet is not implied.
Exposure of the device to absolute maximum rating
conditions for extended periods may affect device reliability.
Figure 7. Maximum Negative
Overshoot Waveform
Figure 8. Maximum Positive
Overshoot Waveform
OPERATING RANGES
Industri al (I) Devices
Ambient Temperature (TA) . . . . . . . . . –40°C to +85° C
Extended (E) Devices
Ambient Temperature (TA) . . . . . . . . –55°C to +125°C
VCC Supply Voltages
VCC for standard voltage r ange . . . . . . .2.7 V to 3.6 V
Operating ranges define those limits between which the
functionality of the device is guaranteed.
20 ns
20 ns
+0.8 V
–0.5 V
20 ns
–2.0 V
20 ns
20 ns
VCC
+2.0 V
VCC
+0.5 V
20 ns
2.0 V
36 Am29DL642G Spetember 5, 2002
PRELIMINARY
DC CHARACTERISTICS
CMOS Compatible
Notes:
1. The ICC current listed is typically less than 2 mA/MHz, with OE# at VIH, one die active at a time.
2. Maximum ICC specifications are tested with VCC = VCCmax.
3. ICC active while Embedded Erase or Embedded Program is in progress.
4. Automatic sleep mode enables the low power mode when addresses remain stable for tACC + 30 ns. T ypical sleep mode current is
200 nA.
5. Not 100% tested.
Parameter
Symbol Parameter Description Test Conditions Min Typ Max Unit
ILI Input Load Curr ent VIN = VSS to VCC,
VCC = VCC max ±1.0 µA
ILIT A9 Input Load Current VCC = VCC max; A9 = 12.5 V 35 µA
ILO Output Leakage Current VOUT = VSS to VCC,
VCC = VCC max ±1.0 µA
ICC1 VCC Active Read Current
(Notes 1, 2) CE# = VIL, OE# = VIH 5 MHz 10 16 mA
1 MHz 2 4
ICC2 VCC Active Write Cu rrent
(Notes 1, 2, 3) CE# = VIL, OE# = VIH, WE# = VIL 15 30 mA
ICC3 VCC Standby Current (Note 2) CE#, RESET# = VCC ± 0.3 V 0.2 10 µA
ICC4 VCC Reset Current (Note 2) RESET # = VSS ± 0.3 V 0.2 10 µA
ICC5 Auto matic Sleep Mode (Notes 2, 4) VIH = VCC ± 0.3 V;
VIL = VSS ± 0.3 V 0.2 10 µA
ICC6 VCC Active Read-While-Program
Current (Notes 1, 2) CE# = VIL, OE# = VIH 21 45 mA
ICC7 VCC Active Read-While-Erase
Curr ent (Notes 1, 2) CE# = VIL, OE# = VIH 21 45 mA
ICC8
VCC Active
Progra m-While-Erase-Suspended
Current (Notes 2, 5) CE# = VIL, OE# = VIH 17 35 mA
VIL Input Low Voltage –0.5 0.8 V
VIH Input High Voltag e 0.7 x VCC VCC + 0.3 V
VHH
Voltage for WP#/ACC Sector
Protect/Unprotect and Program
Acceleration VCC = 3.0 V ± 10% 8.5 9.5 V
VID Voltage for Autoselect and
Temporary Sector Unprotect VCC = 3.0 V ± 10% 11.5 12.5 V
VOL Output Low Voltage IOL = 4.0 mA, VCC = VCC min 0.45 V
VOH1 Output High Voltage IOH = –2.0 mA, VCC = VCC min 0.85 VCC V
VOH2 IOH = –100 µA, VCC = VCC min V
CC–0.4
VLKO Low VCC Lock-Out Voltage (N ote 5) 2.3 2.5 V
Spetember 5, 2002 Am29DL642G 37
PRELIMINARY
DC CHARACTERISTICS
Zero-Power Flash
Note: Addresses are switching at 1 MHz
Figure 9. ICC1 Current vs. Time (Showing Active and Automatic S leep Currents)
25
20
15
10
5
00 500 1000 1500 2000 2500 3000 3500 4000
Supply Current in mA
Time in ns
10
8
2
0
12345
Frequency in MHz
Supply Current in mA
Note: T = 25 °CFigure 10. Typical ICC1 vs. Frequency
2.7 V
3.6 V
4
6
12
38 Am29DL642G Spetember 5, 2002
PRELIMINARY
TEST CONDITIONS
Table 15. Test Specifications
KEY T O SWITCHING WAVEFORMS
2.7 kΩ
CL6.2 kΩ
3.3 V
Device
Under
Test
Note: Di odes are IN3064 or equivalent
Figure 11. Test Setup
Test Condition 70, 90 Unit
Output Load 1 TTL gate
Output Load Capacitance, CL
(including jig capacitance) 30 pF
Input Rise and Fall Times 5 ns
Input P u lse Levels 0.0–3.0 V
Input timing measurement
reference levels 1.5 V
Output timing measurement
reference levels 1.5 V
WAVEFORM INPUTS OUTPUTS
Steady
Changing from H to L
Changing from L to H
Don’t Care, Any Cha nge Permitted Changing, State Unknown
Does Not Apply Center Line is High Impedanc e State (High Z)
3.0 V
0.0 V 1.5 V 1.5 VIO OutputMeasurement LevelInput
Figure 12. Input Waveforms and Measurement Levels
Spetember 5, 2002 Am29DL642G 39
PRELIMINARY
AC CHARACTERISTICS
Read-Only Operations
Notes:
1. Not 100% tested.
2. See Figure 11 and Table 15 for test specifications
3. CE# and CE2# must not be driven low simultaneously .
4. Measurements performed by placing a 50 ohm termination on the data pin with a bias of VCC/2. The time from OE# high to
the data bus driven to VCC/2 is taken as tDF
.
Parameter
Descript ion Test Setup 70 90JEDEC Std. Unit
tAVAV tRC Read Cycle Time (Note 1) Min 70 90 ns
tAVQV tACC Address to Output Delay (Note 3) CE# or CE2#,
OE# = VIL Max 70 90 ns
tELQV tCE Chip Enable to Output Delay OE# = VIL Max 70 90 ns
tGLQV tOE Output Enable to Output Delay Max 30 35 ns
tEHQZ tDF Chip Enabl e to Output High Z (Notes 1, 4) Max 16 ns
tGHQZ tDF Output Enable to Output High Z (Notes 1, 4) Max 16 ns
tAXQX tOH Output Hold Time From Addresses, CE# or OE#,
Whichever Occurs First Min0ns
tOEH Output Enable Hold T ime (Note
1)
Read Min 0 ns
Toggle and
Data# Polling Min10ns
tOH
tCE
Outputs
WE#
Addresses
CE# or CE2#
OE#
HIGH Z
Output V alid
HIGH Z
Addresses Stable
tRC
tACC
tOEH
tRH
tOE
tRH
0 V
RY/BY#
RESET#
tDF
Figure 13. Read Operatio n T imi ngs
40 Am29DL642G Spetember 5, 2002
PRELIMINARY
AC CHARACTERISTICS
Hardware Reset (RESET#)
Note: Not 100% tested.
Parameter
Description 70, 90 UnitJEDEC Std
tReady RESET# Pin Low (During Embedded Algorithm s)
to Read Mode (See Note) Max 20 µs
tReady RESET# Pin Low (N OT During Embedded
Algorithms) to Read Mode (See Note) Max 500 ns
tRP RESET# Pulse Width Min 500 ns
tRH Reset High Time Before Read (See Note) Min 50 ns
tRPD RESET# Low to Standby Mode Min 20 µs
tRB RY/BY# Recovery Time Min 0 ns
RESET#
RY/BY#
RY/BY#
tRP
tReady
Reset Timings NOT during Embedded Algorithms
tReady
CE# or CE2#, OE#
tRH
CE# or CE2#, OE#
Reset Timings during Embedded Algorithms
RESET#
tRP
tRB
Figure 14. Reset Timings
Spetember 5, 2002 Am29DL642G 41
PRELIMINARY
AC CHARACTERISTICS
Erase and Program Operations
Notes:
1. Not 100% tested.
2. See the “Erase And Programming Performance” section for more information.
Parameter
70 90JEDEC Std Description Unit
tAVAV tWC Write Cycle Time (Note 1) Min 70 90 ns
tAVWL tAS Address Setup Time Min 0 ns
tASO Address Setup Time to OE# low during toggle bit polling Min 15 ns
tWLAX tAH Address Hold Time Min 40 45 ns
tAHT Address Hold Time From CE# or OE # high
during toggle bit polling Min 0 ns
tDVWH tDS Data Setup Time Min 40 45 ns
tWHDX tDH Data Hold Time Min 0 ns
tOEPH Output Enable High during toggle bit polling Min 20 ns
tGHWL tGHWL Read Recovery Time Before Write
(OE# High to WE# Low) Min 0 ns
tELWL tCS CE# or CE#2 Setup Time Min 0 ns
tWHEH tCH CE# or CE#2 Hold Time Min 0 ns
tWLWH tWP Write Pulse Width Min 30 35 ns
tWHDL tWPH Write Pulse Width Hi gh Min 30 ns
tSR/W Latency B etween Read and Write Operations Min 0 ns
tWHWH1 tWHWH1 Programming Operation (Note 2) Typ 7 µs
tWHWH1 tWHWH1 Accelerated Programming Operation (Note 2) Typ 4 µs
tWHWH2 tWHWH2 Sector Erase Operation (Note 2) Typ 0.4 sec
tVCS VCC Setup Time (Note 1) Min 50 µs
tRB Write Recovery Time from RY /BY# Min 0 ns
tBUSY Program/E rase Valid to RY/BY# Delay Max 90 ns
42 Am29DL642G Spetember 5, 2002
PRELIMINARY
AC CHARACTERISTICS
OE#
WE#
CE# or CE2#
VCC
Data
Addresses
t
DS
tAH
tDH
tWP
PD
tWHWH1
tWC tAS
tWPH
tVCS
555 h PA PA
Read Status Data (last two cycles)
A0h
tCS
Status DOUT
Program Command Sequence (last two cycles)
RY/BY#
t
RB
tBUSY
tCH
PA
N
ote: PA = program address, PD = program data, DOUT is the true data at the program address.
Figure 15. Program Operatio n T iming s
WP#/ACC tVHH
VHH
VIL or VIH VIL or VIH
tVHH
Figure 16. Accelerated Program Timing Diagram
Spetember 5, 2002 Am29DL642G 43
PRELIMINARY
AC CHARACTERISTICS
OE#
CE# or CE2#
Addresses
VCC
WE#
Data
2AAh SA
tAH
tWP
tWC tAS
tWPH
555 h for chip erase
10 for Chip Erase
30h
tDS
tVCS
tCS
tDH
55h
tCH
In
Progress Complete
tWHWH2
VA
VA
Erase Command Sequence (last two cycles) Read Status Data
RY/BY#
tRB
tBUSY
N
otes: SA = sector address (for Sector Erase), VA = Valid Address for reading status data (see “Write Operation Status”.)
Figure 17. Chip/ Secto r Erase Operation T imi ngs
44 Am29DL642G Spetember 5, 2002
PRELIMINARY
AC CHARACTERISTICS
OE#
CE# or
CE2#
WE#
Addresses
tOH
Data
Valid
In Valid
In
Valid PA Valid RA
tWC
tWPH
tAH
tWP
tDS tDH
tRC
tCE
Valid
Out
tOE
tACC
tOEH tGHWL
tDF
Valid
In
CE# or CE2# Controlled Write CyclesWE# Controlled Write Cycle
Valid PA Valid PA
tCP
tCPH
tWC tWC
Read Cycle
tSR/W
Figure 18. Back-to-back Read/Write Cycle Timings
WE#
CE# or CE2#
OE#
High Z
t
OE
High Z
DQ7
DQ0–DQ6
RY/BY#
t
BUSY
Complement True
Addresses VA
t
OEH
t
CE
t
CH
t
OH
t
DF
VA VA
Status Data
Complement
Status Data True
Valid Data
Valid Data
t
ACC
t
RC
Note: VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data
read cycle.
Figure 19. Data# Polling Timings (During Embedded Algorithms)
Spetember 5, 2002 Am29DL642G 45
PRELIMINARY
AC CHARACTERISTICS
OE#
CE# or CE2#
WE#
Addresses
tOEH
tDH
tAHT
tASO
tOEPH
tOE
Valid Data
(first read) (second read) (stops toggling)
tCEPH
tAHT
tAS
DQ6/DQ2 Valid Data
Valid
Status Valid
Status Valid
Status
RY/BY#
Note: VA = Valid address; not r equired for DQ6. Illustration shows first two status cycle after command sequence, last status
read cycle, and a rray data read cycle
Figure 20. Toggle Bit Timings (During Embedded Algorithms)
Note: DQ2 toggles only when read at an address wit hin an erase-suspended sector. The system may use OE# or CE# to toggle
DQ2 and DQ6.
Figure 21. DQ2 vs. DQ6
Enter
Erase
Erase
Erase
Enter Erase
Suspend Program
Erase Suspend
Read Erase Suspend
Read
Erase
WE#
DQ6
DQ2
Erase
Complete
Erase
Suspend
Suspend
Program
Resume
Embedded
Erasing
46 Am29DL642G Spetember 5, 2002
PRELIMINARY
AC CHARACTERISTICS
Temp orary Sector Unprote ct
Note: Not 100% tested.
Parameter
All S pe e d Op t ion sJEDEC Std Description Unit
tVIDR VID Rise and Fall Time (See Note) Min 500 ns
tVHH VHH Rise and Fal l Time (See Note) Min 250 ns
tRSP RESET# Setup Time for Temporary Sector
Unprotect Min 4 µs
tRRB RESET# Hold Time from RY/BY# High for
Temporary Sector Unprotect Min 4 µs
RESET#
tVIDR
VID
VSS, VIL,
or VIH
VID
VSS, VIL,
or VIH
CE# or CE2#
WE#
RY/BY#
tVIDR
tRSP
Program or Erase Command Sequence
tRRB
Figure 22. Tem porary Sector Unprotect Timing Diagram
Spetember 5, 2002 Am29DL642G 47
PRELIMINARY
AC CHARACTERISTICS
Sector Group Protect: 150 µs
Sector Group Unprotect: 15 ms
1 µs
RESET#
SA, A6,
A1, A0
Data
C
E# or CE2#
WE#
OE#
60h 60h 40h
Valid* Valid* Valid*
Status
Sector Group Protect/Unprotect Verify
VID
VIH
* For sector protect, A6 = 0, A1 = 1, A0 = 0. For sector unprotect, A6 = 1, A1 = 1, A0 = 0.
Figure 23. Sector/Sect or Bl ock Protect and
Unprotect Timi ng Diagram
48 Am29DL642G Spetember 5, 2002
PRELIMINARY
AC CHARACTERISTICS
Alternate CE# Controlled Erase and Program Operations
Notes:
1. Not 100% tested.
2. See the “Erase And Programming Performance” section for more information.
Parameter Speed Options
JEDEC Std. Description 70 90 Unit
tAVAV tWC Write Cycle Time (Note 1) Min 70 90 ns
tAVWL tAS Address Setup Tim e Min 0 ns
tELAX tAH Address Hold Time Min 40 45 ns
tDVEH tDS Dat a Setup Time Min 40 4 5 ns
tEHDX tDH Data Hold Time Min 0 ns
tGHEL tGHEL Read Recovery Time Before Write
(OE# High to WE# Low) Min 0 ns
tWLEL tWS WE# Setup Time Min 0 ns
tEHWH tWH WE# Hold Time Min 0 ns
tELEH tCP CE# Pulse Width Min 40 4 5 ns
tEHEL tCPH CE# Pulse Width High Min 30 ns
tWHWH1 tWHWH1 Programming Operation (Note 2) Typ 7 µs
tWHWH1 tWHWH1 Accelerated Programming Operation (Not e 2) Typ 4 µs
tWHWH2 tWHWH2 Se ctor Erase Operati on (Note 2) Typ 0.4 sec
Spetember 5, 2002 Am29DL642G 49
PRELIMINARY
AC CHARACTERISTICS
tGHEL
tWS
OE#
CE# or CE2#
WE#
RESET#
tDS
Data
tAH
Addresses
tDH
tCP
DQ7# D
OUT
tWC tAS
tCPH
PA
Data# Polling
A0 for program
55 for erase
tRH
tWHWH1 or 2
RY/BY#
tWH
PD for program
30 for sector erase
10 for chip erase
555 for program
2AA for erase PA for program
SA for sector erase
555 for chip erase
tBUSY
Notes:
1. Figure indicates last two bus cycles of a program or erase operation.
2. PA = prog ra m a dd r e ss , SA = s e c t or ad dress, PD = pro gram dat a.
3. DQ7# is the complement of the data written to the device. DOUT is the data written to the device..
Figure 24. Alternate CE# Controlled Writ e (Erase/ Program) Operation Timings
50 Am29DL642G Spetember 5, 2002
PRELIMINARY
ERASE AND PROGRAMMING PERFORMANCE
Notes:
1. Typical program and erase times assume the following conditions: 25 °C, 3.0 V VCC, 1,000 ,000 cycl es. Additiona lly,
programming typicals assume checkerboard pattern.
2. Under worst case conditio ns of 90°C, VCC = 2.7 V, 1,000,000 cycles.
3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes
program faster than the maximum program times listed.
4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure.
5. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. See Table
13 for further information on command definitions.
6. The device has a minimum erase and program cycle endurance of 1,000,000 cycles.
LATCHUP CHARACTERISTICS
Note: Includes all pins except VCC. Test conditions: V CC = 3.0 V, one pin at a time.
DATA RETENTION
Parameter Typ (Note 1) Max (Note 2) Unit Comments
Sector Erase Time 0.4 5 sec Excludes 00h programming
prior to erasure (Note 4)
Chip Erase Time 56 sec
Accelerated Word Program Time 4 120 µs Excludes system level
overhead (Note 5)
Word Program Ti me 7 210 µs
Chip Program Time (Note 3) 28 84 sec
Description Min Max
Input voltage with respect to VSS on all pins except I/O pins
(including A9, OE#, and RESET#) –1.0 V 12.5 V
Input voltage with respect to VSS on all I/O pins –1.0 V V CC + 1.0 V
VCC Current –100 mA +100 mA
Parameter Description Test Conditions Min Unit
Minimum Pattern Data Retention Time 150°C10Years
125°C20Years
Spetember 5, 2002 Am29DL642G 51
PRELIMINARY
PHYSICAL DIMENSIONS
FSD063—63-Ball Fine-Pitch Ball Grid Array (FBGA) 10.95 x 11.95 mm package
3224 \ 16-038.14b
NOTES:
1. DIMENSIONING AND TOLERANCING METHODS PER ASME
Y14.5M-1994.
2. ALL DIMENSIONS ARE IN MILLIMETERS.
3. BALL POSITION DESIGNATION PER JESD 95-1, SPP-010.
4. e REPRESENTS THE SOLDER BALL GRID PITCH.
5. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D"
DIRECTION.
SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE "E"
DIRECTION.
n IS THE NUMBER OF POPULATED
SOLDER BALL POSITIONS FOR MATRIX SIZE MD X ME.
6 DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL
DIAMETER IN A PLANE PARALLEL TO DATUM C.
7 SD AND SE ARE MEASURED WITH RESPECT TO DATUMS
A AND B AND DEFINE THE POSITION OF THE CENTER
SOLDER BALL IN THE OUTER ROW.
WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE
OUTER ROW, SD OR SE = 0.000.
WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE
OUTER ROW, SD OR SE = e/2
8. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED
BALLS.
9. NOT USED.
10. A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK
MARK, METALLIZED MARK INDENTATION OR OTHER MEANS.
PACKAGE FSD 063
JEDEC N/A
10.95 mm x 11.95 mm
PACKAGE
SYMBOL MIN NOM MAX NOTE
A --- --- 1.40 PROFILE
A1 0.25 --- --- BALL HEIGHT
A2 1.00 --- 1.10 BODY THICKNESS
D 11.95 BSC. BODY SIZE
E 10.95 BSC. BODY SIZE
D1 8.80 BSC. MATRIX FOOTPRINT
E1 5.60 BSC. MATRIX FOOTPRINT
MD 12 MATRIX SIZE D DIRECTION
ME 8 MATRIX SIZE E DIRECTION
n 63 BALL COUNT
φb 0.30 0.35 0.40 BALL DIAMETER
eE 0.80 BSC. BALL PITCH
eD 0.80 BSC. BALL PITCH
SD / SE 0.40 BSC. SOLDER BALL PLACEMENT
A3,A4,A5,A6,B2,B3,B4,B5,B6
C1,C8,D1,D8,E1,E8,F1,F8 DEPOPULATED SOLDER BALLS
G1,G8,H1,H8,J1,J8,K1,K8
L3,L4,L5,L6,M3,M4,M5,M6
63X 6b
0.20 C
C
0.15 BAC
C
M
M
0.08
C
SIDE VIEW
A2
A1
A
0.08
C
0.15
(2X)
(2X) C
0.15
B
A
D
E
TOP VIEW
10
INDEX MARK
CORNER
PIN A1
L
M
eD
CORNER
E1
7
SE
D1
ABDCEFHG
8
7
5
6
4
2
3
J
K
1
eE
SD
BOTTOM VIEW
PIN A1
7
52 Am29DL642G Spetember 5, 2002
PRELIMINARY
REVISION SUMMARY
Revision A (June 12, 2002)
Init ial r eleas e.
Revision B (August 27, 2002)
Global
Changed speed rating from 90 ns to 70 ns. Deleted
refer ences and data related to byte mode.
Ordering Information
Added FSD063 package drawing and part number
designator.
Common Flash Interface (CFI)
In 3rd paragraph, corrected last sentence to indicate
that after a re set command , devic e returns to readin g
array data, not autoselect mode.
DC Characteristics
Changed maximum current for ICC3, ICC4, ICC5 to 10
mA. In Note 1, indicated that specification is for one
die active at a time.
AC Characteristics
Read-only Operations: Changed tDF from 30 to 16 ns,
and tOE from 35 to 30 ns. Added note reference to
tACC.
Era se and Program Opera tions: Change d tAH and tDS
from 45 to 40 ns, and tWP from 35 to 30 ns.
Physical Dimensions
Added FSD063 package drawing.
Revision B+1 (September 5, 2002)
Global
Added 90 ns speed option.
DC Characteristics
Deleted IACC parameter from table.
Trademarks
Copyright © 2002 Advanced Micro Devices, Inc. All rights reserved.
AMD, the AMD logo, and combinations thereof are registered trademarks of Advanced Micro Devices, Inc.
ExpressFlash is a trademark of Advanced Micro Devices, Inc.
Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.
