LTC4355
1
4355f
, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
TYPICAL APPLICATION
FEATURES
APPLICATIONS
DESCRIPTION
Positive High Voltage
Ideal Diode-OR with Input Supply
and Fuse Monitors
The LTC
®
4355 is a positive voltage ideal diode-OR controller
that drives two external N-channel MOSFETs. Forming the
diode-OR with N-channel MOSFETs instead of Schottky
diodes reduces power consumption, heat dissipation and
PC board area.
With the LTC4355, power sources can easily be ORed
together to increase total system reliability. The LTC4355
can diode-OR two positive supplies or the return paths of
two negative supplies, such as in a –48V system.
In the forward direction the LTC4355 controls the voltage
drop across the MOSFET to ensure smooth current transfer
from one path to the other without oscillation. If a power
source fails or is shorted, fast turnoff minimizes reverse
current transients.
Power fault detection indicates if the input supplies are
not in regulation, the inline fuses are blown, or the
voltages across the MOSFETs are greater than the fault
threshold.
+48V Diode-OR
■ Replaces Power Schottky Diodes
■ Controls N-Channel MOSFETs
■ 0.5µs Turn-Off Time Limits Peak Fault Current
■ Wide Operating Voltage Range: 9V to 80V
■ Smooth Switchover without Oscillation
■ No Reverse DC Current
■ Monitors VIN, Fuse, and MOSFET Diode
■ Available in DFN-14 (4mm × 3mm) and
SSOP-16 Packages
■ High Availability Systems
■ AdvancedTCA
®
(ATCA) Systems
■ +48V and –48V Distributed Power Systems
■ Telecom Infrastructure
Power Dissipation vs Load Current
4355 TA01
LTC4355
GND
GATE1 GATE2IN1 OUTIN2
MON1
MON2
SET
12.7k
340k
12.7k
340k
7A
22k 22k 22k
22k 22k
GREEN LEDs
PANASONIC LN1351C
7A
GND
FDB3632
FDB3632
TO
LOAD
VIN1 = +48V
VIN2 = +48V
VDSFLT
FUSEFLT1
FUSEFLT2
PWRFLT1
PWRFLT2
CURRENT (A)
0
0
POWER DISSIPATION (W)
1
2
3
4
5
6
2468
4355 TA02
10
DIODE (MBR10100)
FET (FDB3632)
POWER
SAVED
LTC4355
2
4355f
ELECTRICAL CHARACTERISTICS
ABSOLUTE MAXIMUM RATINGS
Supply Voltages
IN1, IN2 ...............................................–0.3V to 100V
OUT ..................................................... –0.3V to 100V
Input Voltages
MON1, MON2, SET .................................. –0.3V to 7V
Output Voltages
GATE1 (Note 3) ................... VIN1 – 0.2V to VIN1 + 13V
GATE2 (Note 3) ................... VIN2 – 0.2V to VIN2 + 13V
⎯
P
⎯
W
⎯
R
⎯
F
⎯
L
⎯
T
⎯
1,
⎯
P
⎯
W
⎯
R
⎯
F
⎯
L
⎯
T2,
⎯
V
⎯
D
⎯
S
⎯
F
⎯
L
⎯
T,
⎯
F
⎯
U
⎯
S
⎯
E
⎯
F
⎯
L
⎯
T
⎯
1,
⎯
F
⎯
U
⎯
S
⎯
E
⎯
F
⎯
L
⎯
T
⎯
2 ..............................–0.3V to 8V
(Notes 1, 2)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VOUT Operating Supply Range ●980V
IOUT Supply Current ●23 mA
IINx INx Pin Input Current GATE High ●0.5 0.6 1.2 mA
1
2
3
4
5
6
7
14
13
12
11
10
9
8
15
MON1
PWRFLT1
FUSEFLT1
FUSEFLT2
PWRFLT2
MON2
SET
IN1
GATE1
OUT
GATE2
IN2
VDSFLT
GND
TOP VIEW
DE14 PACKAGE
14-LEAD (4mm × 3mm) PLASTIC DFN
TJMAX = 125°C, θJA = 43°C/W
EXPOSED PAD (PIN 15) PCB GND CONNECTION OPTIONAL
MON1
PWRFLT1
FUSEFLT1
FUSEFLT2
PWRFLT2
MON2
SET
GND
TOP VIEW
S PACKAGE
16-LEAD PLASTIC SO
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
IN1
GATE1
NC
OUT
NC
GATE2
IN2
NC
TJMAX = 125°C, θJA = 75°C/W
ORDER PART NUMBER DE PART MARKING* ORDER PART NUMBER S PART MARKING
LTC4355CDE
LTC4355IDE
4355 LTC4355CS
LTC4355IS
LTC4355CS
LTC4355IS
Order Options Tape and Reel: Add #TR
Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF
Lead Free Part Marking: http://www.linear.com/leadfree/
Consult LTC Marketing for parts specifi ed with wider operating temperature ranges. *The temperature grade is identifi ed by a label on the shipping container.
The ● denotes the specifi cations which apply over the full operating
temperature range, otherwise specifi cations are at TA = 25°C. 9V < VOUT < 80V unless otherwise noted.
Operating Temperature Range
LTC4355C ................................................ 0°C to 70°C
LTC4355I .............................................–40°C to 85°C
Storage Temperature Range
DFN Package ......................................–65°C to 125°C
SO Package ........................................–65°C to 150°C
Lead Temperature (Soldering, 10 sec)
SO Package ....................................................... 300°C
PACKAGE/ORDER INFORMATION
LTC4355
3
4355f
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
ΔVGATEx External N-Channel Gate Drive
(VGATEx – VINx)
VOUT = 20V to 80V
VOUT = 9V to 20V
●
●
10
4.5
14
6
18
18
V
V
IGATEx(UP) External N-Channel Gate Pull-Up Current Gate Drive On, VGATE = VINx,
ΔVSD = 100mV
●–14 –20 –26 µA
IGATEx(DN) External N-Channel Gate Pulldown in Fault
Condition
Gate Drive Off, VGATEx = VINx +5V ●12 A
tOFF Gate Turn-Off Time VINx – VOUT = 55mV –|
––1V
VGATEx – VINx < 1V
●0.3 0.4 µs
VMONx(TH) MONx Pin Threshold Voltage VMONx Rising ●1.209 1.227 1.245 V
VMONx(HYST) MONx Pin Hysteresis Voltage ●10 30 45 mV
IMONx(IN) MONx Pin Input Current VMONx = 1.23V ●0±1 µA
VINx(TH) INx Pin Threshold Voltage VINx Rising ●3 3.5 4 V
VINx(HYST) INx Pin Hysteresis Voltage ●25 75 150 mV
ΔVSD Source-Drain Regulation Voltage
(VINx – VOUT )
VGATEx – VINx = 2.5V ●10 25 55 mV
ΔVSD(FLT) Short-Circuit Fault Voltage
(VINx – VOUT) Rising
SET = 0V
SET = 100kΩ
SET = Hi-Z
●
●
●
0.2
0.4
1.3
0.25
0.5
1.5
0.3
0.6
1.6
V
V
V
ΔVSD(FLT)(HYST) Short-Circuit Fault Hysteresis Voltage 30 mV
V
⎯
F
⎯
L
⎯
T
⎯
P
⎯
W
⎯
R
⎯
F
⎯
L
⎯
T
⎯
x,
⎯
F
⎯
U
⎯
S
⎯
E
⎯
F
⎯
L
⎯
T
⎯
x,
⎯
V
⎯
D
⎯
S
⎯
F
⎯
L
⎯
T Pins
Output Low
I
⎯
P
⎯
W
⎯
R
⎯
FL
⎯
T
⎯
x, I
⎯
F
⎯
U
⎯
S
⎯
E
⎯
F
⎯
L
⎯
T
⎯
x, I
⎯
V
⎯
D
⎯
S
⎯
F
⎯
L
⎯
T = 5mA ●100 200 mV
I
⎯
F
⎯
L
⎯
T
⎯
P
⎯
W
⎯
R
⎯
F
⎯
L
⎯
T
⎯
x,
⎯
F
⎯
U
⎯
S
⎯
E
⎯
F
⎯
L
⎯
T
⎯
x,
⎯
V
⎯
D
⎯
S
⎯
F
⎯
L
⎯
T Pins
Leakage Current
V
⎯
P
⎯
W
⎯
R
⎯
F
⎯
L
⎯
T
⎯
x, V
⎯
F
⎯
U
⎯
S
⎯
E
⎯
F
⎯
L
⎯
T
⎯
x, V
⎯
V
⎯
D
⎯
S
⎯
F
⎯
L
⎯
T = 5V ●0±1 µA
RSET(L) SET Resistance Range for ΔVSD(FLT) = 0.25V ●05kΩ
RSET(M) SET Resistance Range for ΔVSD(FLT) = 0.5V ●50 150 kΩ
RSET(H) SET Resistance Range for ΔVSD(FLT) = 1.5V ●1MΩ
ELECTRICAL CHARACTERISTICS
The ● denotes the specifi cations which apply over the full operating
temperature range, otherwise specifi cations are at TA = 25°C. 9V < VOUT < 80V, unless otherwise noted.
Note 2: All currents into pins are positive, all voltages are referenced to
GND unless otherwise specifi ed.
Note 3: The GATEx pins are internally limited to a minimum of 13V above
INx. Driving these pins beyond the clamp may damage the part.
LTC4355
4
4355f
TEMPERATURE (°C)
–50
VFLT (V)
100
125
100
50 050
150
75
4355 G06
IFLT = 5mA
IFLT (mA)
0
VFLT (V)
0.1
0.2
15
0510
0.3
4355 G05
CGATE (nF)
0
tOFF (ns)
300
400
500
40
4355 G07
200
100
010 20 20 50
VGATE < VIN + 1V
∆VSD = 50mV –1V
VINITIAL (V)
0
tPD (ns)
300
400
500
0.8
4355 G08
200
100
00.2 0.4 0.6 1.0
VIN = 48V
∆VSD = VINITIAL –1V
VFINAL (V)
–1.0
tPD (ns)
1000
1500
2000
–0.2
4355 G09
500
0–0.8 –0.6 –0.4 0
VIN = 48V
∆VSD = 50mV VFINAL
VOUT (V)
0
IOUT (mA)
1.0
1.5
80
0.5
020 40 60
2.0
4355 G01
VOUT = VIN
VIN (V)
0
IIN (mA)
0.5
0.8
80
0.3
020 40 60
1.0
4355 G02
VIN = VOUT
TYPICAL PERFORMANCE CHARACTERISTICS
IOUT vs VOUT IIN vs VIN IGATE vs ΔVSD
ΔVGATE vs IGATE
Fault Output Low
vs Load Current
Fault Output Low
vs Temperature
FET Turn-Off Time
vs GATE Capacitance
FET Turn-Off Time
vs Initial Overdrive
FET Turn-Off Time
vs Final Overdrive
VSD (mV)
–50
IGATE (µA)
–20
0
150
–40
–60 050 100
20
4355 G03
VGATE = 2.5V
IGATE (µA)
0
0
∆VGATE (V)
5
10
15
5101520
25
4355 G04
VIN > 18V
VIN = 12V
VIN = 9V
LTC4355
5
4355f
PIN FUNCTIONS
EXPOSED PAD (Pin 15, DE Package Only): Exposed pad
may be left open or connected to GND.
⎯
F
⎯
U
⎯
S
⎯
E
⎯
F
⎯
L
⎯
T
⎯
x (Pins 11,12/13,14): Fuse Fault Outputs.
Open-drain output that pulls to GND when VINx < 3.5V,
indicating that the fuse has blown open. Otherwise, this
output is high-impedance. Connect to GND if unused.
GATEx (Pins 2,4/2,6): Gate Drive Outputs. The GATE
pins pull high, enhancing the N-channel MOSFET when
the load current creates more than 25mV of voltage drop
across the MOSFET. When the load current is small,
the gates are actively driven to maintain 25mV across
the MOSFET. If the reverse current develops more than
–25mV of voltage drop across a MOSFET, a fast pulldown
circuit quickly connects the GATE pin to the IN pin, turning
off the MOSFET. Limit the capacitance between the GATE
and IN pins to less than 0.1µF.
GND (7/9): Device Ground.
INx (Pins 1,5/1,7): Input Voltages and GATE Fast Pulldown
Returns. The IN pins are the anodes of the ideal diodes
and connect to the sources of the N-channel MOSFETs.
The voltages sensed at these pins are used to control the
source-drain voltages across the MOSFETs and are used
by the fault detection circuits that drive the
⎯
P
⎯
W
⎯
R
⎯
F
⎯
L
⎯
T,
⎯
F
⎯
U
⎯
S
⎯
E
⎯
F
⎯
L
⎯
T, and
⎯
V
⎯
D
⎯
S
⎯
F
⎯
L
⎯
T pins. The GATE fast pulldown cur-
rent is returned through the IN pins. Connect these pins
as close to the MOSFET sources as possible. Connect to
OUT if unused.
MONx (Pins 9,14/11,16): Input Supply Monitors. These
pins are used to sense the input supply voltages. Connect
these pins to external resistive dividers between the input
supplies and GND. If VMONx falls below 1.23V, the
⎯
P
⎯
W
⎯
R
⎯
F
⎯
L
⎯
T
⎯
x
pin pulls to GND. Connect to GND if unused.
OUT (Pin 3/4): Drain Voltage Sense and Positive Sup-
ply Input. OUT is the diode-OR output of IN1 and IN2. It
connects to the common drain connection of the N-chan-
nel MOSFETs. The voltage sensed at this pin is used to
control the source-drain voltages across the MOSFETs
and is used by the fault detection circuits that drive the
⎯
P
⎯
W
⎯
R
⎯
F
⎯
L
⎯
T and
⎯
V
⎯
D
⎯
S
⎯
F
⎯
L
⎯
T pins. The LTC4355 is powered from
the OUT pin.
⎯
P
⎯
W
⎯
R
⎯
F
⎯
L
⎯
T
⎯
x (Pins 10,13/12,15): Power Fault Outputs.
Open-drain output that pulls to GND when VMONx falls
below 1.23V or the forward voltage across the MOSFET
exceeds ΔVSD(FLT). When VMONx is above 1.23V and
the forward voltage across the MOSFET is less than
ΔVSD(FLT),
⎯
P
⎯
W
⎯
R
⎯
F
⎯
L
⎯
T
⎯
x is high-impedance. Connect to GND
if unused.
SET (Pin 8/10): ΔVSD(FLT) Threshold Confi guration Input.
Tying SET to GND, to a 100kΩ resistor connected to GND,
or leaving SET open confi gures the ΔVSD(FLT) forward volt-
age fault threshold to 250mV, 500mV, or 1.5V respectively.
When the voltage across a MOSFET exceeds ΔVSD(FLT),
the
⎯
V
⎯
S
⎯
D
⎯
F
⎯
L
⎯
T pin and at least one of the
⎯
P
⎯
W
⎯
R
⎯
F
⎯
L
⎯⎯
T pins pull
to GND.
⎯
V
⎯
D
⎯
S
⎯
F
⎯
L
⎯
T (Pin 6, DE Package Only): MOSFET Fault Output.
Open-drain output that pulls to GND when the forward volt-
age across either MOSFET exceeds ΔVSD(FLT).
⎯
P
⎯
W
⎯
R
⎯
F
⎯
L
⎯
T
⎯
1
or
⎯
P
⎯
W
⎯
R
⎯
F
⎯
L
⎯
T
⎯
2 also pulls low to indicate which MOSFET’s
forward voltage drop exceeds ΔVSD(FLT). Otherwise, this
pin is high-impedance. Connect to GND if unused.
(DE/S Packages)
LTC4355
6
4355f
BLOCK DIAGRAM
–
+
4355 BD
–
+
–
+
–
+
+
–
+
–
+
–
+
–
–
+
–
+
–
+
–
+
+
–
+
–
+
–
+
–
GATE1
AMP
GATE2
AMP
3.5V 3.5V
FUSE1
FAULT
∆VSD(FLT)
∆VSD1(FLT)
FAULT
∆VSD2(FLT)
FAULT
25mV 25mV
∆VSD(FLT)
∆VSD(FLT) =
0.25V, 0.5V OR 1.5V
GATE1 GATE2OUTIN1 IN2
VDSFLT
FUSEFLT1 FUSEFLT2
PWRFLT2
GND
1.23V 1.23V
SET
MON1
MON1
MON2
MON2
PWRFLT1
FUSE2
FAULT
LTC4355
7
4355f
OPERATION
High availability systems often employ parallel-connected
power supplies or battery feeds to achieve redundancy
and enhance system reliability. ORing diodes have been
a popular means of connecting these supplies at the point
of load. The disadvantage of this approach is the forward
voltage drop and resulting effi ciency loss. This drop reduces
the available supply voltage and dissipates signifi cant
power. Using N-channel MOSFETs to replace Schottky
diodes reduces the power dissipation and eliminates the
need for costly heat sinks or large thermal layouts in high
power applications.
The LTC4355 is a positive voltage diode-OR controller that
drives two external N-channel MOSFETs as pass transis-
tors to replace ORing diodes. The IN and OUT pins form
the anodes and cathodes of the ideal diodes. The source
pins of the external MOSFETs are connected to the IN pins.
The drains of the MOSFETs are connected together at the
OUT pin, which is the positive supply of the device. The
gates of the external MOSFETs are driven by the LTC4355
to regulate the voltage drop across the pass transistors.
At power-up, the initial load current fl ows through the
body diode of the MOSFET with the higher INx voltage.
The associated GATEx pin immediately ramps up and turns
on the MOSFET. The amplifi er tries to regulate the voltage
drop across the source and drain connections to 25mV.
If the load current causes more than 25mV of drop, the
MOSFET gate is driven fully on and the voltage drop is
equal to RDS(ON) • ILOAD.
When the power supply voltages are nearly equal, this
regulation technique ensures that the load current is
smoothly shared between the MOSFETs without oscil-
lation. The current fl owing through each pass trans-
istor depends on the RDS(ON) of each MOSFET and the
output impedances of the supplies.
In the event of a supply failure, such as if the supply that
is conducting most or all of the current is shorted to GND,
reverse current fl ows temporarily through the MOSFET that
is on. This current is sourced from any load capacitance
and from the second supply through the body diode of
the other MOSFET. The LTC4355 quickly responds to this
condition, turning off the MOSFET in about 500ns. This
fast turn-off prevents the reverse current from ramping
up to a damaging level.
In the case where the pass transistor is fully on but the
voltage drop across it exceeds the confi gurable fault
threshold, ΔVSD(FLT), the
⎯
V
⎯
D
⎯
S
⎯
F
⎯
L
⎯
T pin pulls low. Using this
pin to shunt current away from an LED or optocoupler
provides an indication that a pass transistor has either
failed or has excessive forward current. Additionally, in
this condition the
⎯
P
⎯
W
⎯
R
⎯
F
⎯
L
⎯
T
⎯
1 or
⎯
P
⎯
W
⎯
R
⎯
F
⎯
L
⎯
T
⎯
2 pin pulls low
to identify the faulting channel.
The
⎯
P
⎯
W
⎯
R
⎯
F
⎯
L
⎯
T pins also indicate if an input supply is within
regulation. When VMON1 < 1.23V or VMON2 < 1.23V, the
corresponding
⎯
P
⎯
W
⎯
R
⎯
F
⎯
L
⎯
T pin pulls low to indicate that
the input supply is low, turning off an optional LED or
optocoupler.
The
⎯
F
⎯
U
⎯
S
⎯
E
⎯
F
⎯
L
⎯
T pins indicate the status of input fuses. If
the voltage at one of the IN pins is less than 3.5V, the
corresponding
⎯
F
⎯
U
⎯
S
⎯
E
⎯
F
⎯
L
⎯
T pin pulls low. The IN pins sink
a minimum of 0.5mA to guarantee that the IN pin will
pull low when the input fuse is blown open. Note that the
⎯
F
⎯
U
⎯
S
⎯
E
⎯
F
⎯
L
⎯
T pin will activate if the input supply is less than
3.5V even if the fuse is intact.
LTC4355
8
4355f
APPLICATIONS INFORMATION
MOSFET Selection
The LTC4355 drives N-channel MOSFETs to conduct the
load current. The important features of the MOSFETs are
on-resistance RDS(ON), the maximum drain-source voltage
VDSS, and the threshold voltage.
The gate drive for the MOSFET is guaranteed to be greater
than 4.5V when the supply voltage at VOUT is between 9V
and 20V. When the supply voltage at VOUT is greater than
20V, the gate drive is guaranteed to be greater than 10V. The
gate drive is limited to less than 18V. This allows the use
of logic level threshold N-channel MOSFETs and standard
N-channel MOSFETs above 20V. An external zener diode
can be used to clamp the potential from the MOSFET’s
gate to source if the rated breakdown voltage is less than
18V. See the circuit in Figure 4 for an example.
The maximum allowable drain-source voltage, BVDSS,
must be higher than the supply voltages. If an input is
connected to GND, the full supply voltage will appear
across the MOSFET.
If the voltage drop across either MOSFET exceeds the
confi gurable ΔVSD(FLT) fault threshold, the
⎯
V
⎯
D
⎯
S
⎯
F
⎯
L
⎯
T
pin and the
⎯
P
⎯
W
⎯
R
⎯
F
⎯
L
⎯
T pin corresponding to the fault-
ing channel pull low. The RDS(ON) should be small
enough to conduct the maximum load current
while not triggering a fault, and to stay within the
MOSFET’s power rating at the maximum load current
(I2 • RDS(ON)).
Fault Conditions
The LTC4355 monitors fault conditions and shunts current
away from LEDs or optocouplers, turning each one off to
indicate a specifi c fault condition (see Table 1).
When the voltage drop across the pass transistor is higher
than the confi gurable ΔVSD(FLT) fault threshold, the internal
pulldown at the
⎯
V
⎯
D
⎯
S
⎯
F
⎯
L
⎯
T pin and the
⎯
P
⎯
W
⎯
R
⎯
F
⎯
L
⎯
T
⎯
1 or
⎯
P
⎯
W
⎯
R
⎯
F
⎯
L
⎯
T
⎯
2
pin corresponding to the faulting channel turns on. The
ΔVSD(FLT) threshold is confi gured by the SET pin. Tying
SET to GND, tying SET to a 100kΩ resistor connected
to GND, or fl oating SET confi gures ΔVSD(FLT) to 250mV,
500mV, or 1.5V respectively.
Conditions that may cause a high voltage across the pass
transistor include: a MOSFET open on the higher supply,
excessive MOSFET current due to overcurrent on the load
or a shorted MOSFET on the lower supply.
The
⎯
P
⎯
W
⎯
R
⎯
F
⎯
L
⎯
T pins are additionally used to indicate if either
input supply is below its normal regulation range. If the
voltage at the MON1 or MON2 pin is less than VMON(TH),
typically 1.23V, the corresponding
⎯
P
⎯
W
⎯
R
⎯
F
⎯
L
⎯
T
⎯
1 or
⎯
P
⎯
W
⎯
R
⎯
F
⎯
L
⎯
T
⎯
2
pin will pull low. A resistive divider connected to the input
supply drives the MON pin for the corresponding supply,
confi guring the
⎯
P
⎯
W
⎯
R
⎯
F
⎯
L
⎯
T threshold for that supply. Be sure
to account for the tolerance of the MON pin threshold, the
resistor tolerances, and the regulation range of the supply
being monitored. Also, ensure that the voltage on the MON
pin will not exceed 12V.
The
⎯
F
⎯
U
⎯
S
⎯
E
⎯
F
⎯
L
⎯
T pins are used to indicate the status of the
input fuses. If one of the IN pins falls below VINx(TH), typi-
cally 3.5V, the
⎯
F
⎯
U
⎯
S
⎯
E
⎯
F
⎯
L
⎯
T pin corresponding to that supply
will pull low. The IN pins each sink a minimum of 0.5mA,
enough to pull the pin low after an input fuse blows open.
If there is a possibility that the MOSFET leakage current
can be greater than 0.5mA, a resistor can be connected
between the IN pin and GND to sink more current. Note
that if the input supply voltage is less than VINx(TH) the
⎯
F
⎯
U
⎯
S
⎯
E
⎯
F
⎯
L
⎯
T pin will pull low.
Table 1. Fault Table
ΔVSD1
< ΔVSD(FLT)
VIN1
> 3.5V
VMON1
> 1.23V
⎯
V
⎯
D
⎯
S
⎯
F
⎯
L
⎯
T*
⎯
F
⎯
U
⎯
S
⎯
E
⎯
F
⎯
L
⎯
T
⎯
1
⎯
P
⎯
W
⎯
R
⎯
F
⎯
L
⎯
T
⎯
1
True True True Hi-Z Hi-Z Hi-Z
True True False Hi-Z Hi-Z Pulldown
True False True Hi-Z Pulldown Hi-Z
True False False Hi-Z Pulldown Pulldown
False True True Pulldown Hi-Z Pulldown
False True False Pulldown Hi-Z Pulldown
False False True Pulldown Pulldown Pulldown
False False False Pulldown Pulldown Pulldown
*ΔVSD2 < ΔVSD(FLT)
System Power Supply Failure
The LTC4355 automatically supplies load current from
the system input supply with the higher voltage. If this
supply shorts to ground, reverse current begins to fl ow
through the pass transistor temporarily and the transis-
tor begins to turn off. When this reverse current creates
LTC4355
9
4355f
APPLICATIONS INFORMATION
–25mV of voltage drop across the drain and source pins
of the pass transistor, a fast pulldown circuit engages to
drive the gate low faster.
The remaining system power supply delivers the load cur-
rent through the body diode of its pass transistor until the
channel turns on. The LTC4355 ramps the gate up with
20µA, turning on the N-channel MOSFET to reduce the
voltage drop across it.
When the capacitances at the inputs and output are very
small, large changes in current can cause inductive tran-
sients that exceed the 100V Absolute Maximum Ratings
of the pins. A surge suppressor (TransZorb) at the output
will minimize this ringing.
Loop Stability
The servo loop is compensated by the parasitic capaci-
tance of the power N-channel MOSFET. No further com-
pensation components are normally required. In the case
when a MOSFET with less than 1000pF gate capacitance
is chosen, a 1000pF compensation capacitor connected
across the gate and source pins might be required.
Design Example
The following design example demonstrates the calcula-
tions involved for selecting components in a 36V to 72V
system with 5A maximum load current (see Figure 1).
First, choose the N-channel MOSFET. The 100V,
FDS3672 in the SO-8 package with RDS(ON) = 22mΩ(max)
offers a good solution. The maximum voltage drop across
it is:
ΔV = 5A • 22mΩ = 110mV
The maximum power dissipation in the MOSFET is a mere:
P = 5A • 110mV = 0.55W
Next, select the resistive dividers that guarantee the
⎯
P
⎯
W
⎯
R
⎯
F
⎯
L
⎯
T pins willl not assert when the input supplies are
above 36V. The maximum VMONx(TH) is 1.245V and the
maximum IMONx(IN) is 1µA. Choose a 1% tolerance resistor
R1 = 12.7kΩ. Then,
IV
R MIN I
V
R
MONx TH
MONx TH MAX21
1 245
1
=+
=
()
()( )
()
.
227 1 1 100
.(%)kAA
Ω− +=µµ
Use IR2 to choose R2.
RVV
Ak2 36 1 245
100 348=−=
.
µΩ
Adjust R2 down by 1% to 344kΩ to account for its tolerance.
The next lower standard resistor value is R2 = 340kΩ.
The LED D1, a Panasonic Green LN1351C, requires at
least 1mA of current to fully turn on. Therefore, R5 is set
to 33kΩ to accommodate the lowest input supply voltage
of 36V.
4355 F01
LTC4355
GND
GATE1 GATE2IN1 OUTIN2
MON1
MON2
SET
R1
12.7k
R2
340k
R3
12.7k
R4
340k
R5
33k
R7
33k
R9
33k
R6
33k
R8
33k
D1 D3
D2 D4
D5
GND
M1
FDS3672
M2
FDS3672
TO
LOAD
VIN1 = +48V
VIN2 = +48V
VDSFLT
FUSEFLT1
FUSEFLT2
PWRFLT1
PWRFLT2
F1
7A
F2
7A
GREEN LEDs
PANASONIC LN1351C
Figure 1. 36V to 72V/5A Design Example
LTC4355
10
4355f
APPLICATIONS INFORMATION
Layout Considerations
The following advice should be considered when laying
out a printed circuit board for the LTC4355.
The inputs to the servo amplifi ers, IN1, IN2, and OUT
should be connected as closely as possible to the
MOSFETs’ terminals for good accuracy.
Keep the traces to the MOSFETs wide and short. The PCB
traces associated with the power path through the MOS-
FETs should have low resistance (see Figure 2).
Figure 2. Layout Considerations
4355 F02
IN1
GATE1
OUT
GATE2
IN2
S
S
S
G
D
D
D
D
D
D
D
D
G
S
S
S
LTC4355
FET FET
LTC4355
11
4355f
Figure 3. –36V to –72V/10A with Positive Supply and
Negative Supply Diode-ORing
4355 F03
LTC4355
LTC4354 FAULT
GND
GATE1 GATE2IN1 OUTIN2
MON1
MON2
SET
12.7k
340k
12.7k
1µF
340k
10A
33k
12k
33k
2k
33k 33k
33k 33k
GREEN LEDs
PANASONIC LN1351C
RED LED
PANASONIC
LN1251CLA
10A
15A
15A
IRF3710
IRF3710
IRF3710
IRF3710
RTNA
RTNB
VSS
VCC
GBGADBDA
VA = –48V
VB = –48V
2k
VDSFLT
FUSEFLT1
FUSEFLT2
PWRFLT1
PWRFLT2
LOAD
APPLICATIONS INFORMATION
LTC4355
12
4355f
Figure 4. 36V to 72V/10A with Positive Supply and Negative Supply Diode-ORing,
Combined Fault Outputs, and Zener Clamps on MOSFET Gates
4355 F04
LTC4355
LTC4354 FAULT
GND
GATE1 GATE2IN1 OUTIN2
MON1
MON2
SET
12.7k
340k
12.7k
1µF
340k
10A
12k
2k
33k
GREEN LEDs
PANASONIC
LN1351C
10A
15A
15A
IRLR3110ZPbF
IRLR3110ZPbF
IRLR3110ZPbF
IRLR3110ZPbF
VA = 48V
VB = 48V
VSS
VCC
GBGADBDA
GNDA
GNDB
2k
VDSFLT
FUSEFLT1
FUSEFLT2
PWRFLT1
PWRFLT2
LOAD
12V ZENER
CM4Z669-LTC
12V ZENER
CM4Z669-LTC
APPLICATIONS INFORMATION
LTC4355
13
4355f
TYPICAL APPLICATIONS
LTC4355
GND
GATE1 GATE2IN1 OUTIN2
MON1
MON2
SET
R2
12.7k
R1
86.6k
F1
15A
R3
10k
R4
10k
R5
10k
D1 D2 D3
TO LOAD
GREEN LEDs
PANASONIC
LN1351C
M1
HAT2165H
VIN = 12V
GND
VDSFLT
FUSEFLT1
FUSEFLT2
PWRFLT1
PWRFLT2
4355 TA03
Single 12V/15A Ideal Diode with Parallel Drivers
Single 36V to 72V/30A Ideal Diode Using Parallel MOSFETs
4355 TA04
LTC4355
GND
IN2 GATE2GATE1IN1 OUT
MON1
MON2
SET
R2
12.7k
R1
340k
F1
30A
R3
33k
R5
33k
R4
33k
D1 D3
D2
GREEN LEDs
PANASONIC
LN1351C
GND
M1
IRFS4710
M2
IRFS4710
TO
LOAD
VIN = +48V
VDSFLT
FUSEFLT1
PWRFLT1
FUSEFLT2
PWRFLT2
LTC4355
14
4355f
TYPICAL APPLICATIONS
MON2
SET
MON1
IN1 GATE1 IN2
GND
GATE2 OUT
LTC4355CS
SENSE
LTC4261CGN
VIN
VEE
TMR GATE DRAIN
IRF1310NS
330nF
47nF
1µF
1.1k
1.1k
1.1k
1.1k
1M
10nF
100V
33nF
–48VOUT
4355 TA05
–48VRTN(OUT)
1k
2.49k
8mΩ
10Ω
330nF
100nF
100nF100nF
SS
UVH
UVL
ADIN2
OV
ON
INTVCC
FLTIN
EN
ADR1
ADR0
PG
SCL
SDAI
SDAO
ALERT
PGIO
PGI
ADIN
RAMP
10.2k100k
D: 1N4148WS
HZS5C1
VSS
VSS
GB
FDS3672
2k
2k
LTC4354CS8
GA
VCC
10k
DBDA
137k 107k
1µF
22nF
100V
SMBT70A
91Ω
100k
D
DD
D
FDS3672
100k
7A
–48V_A
–48V_B
MEDIUM LONG
7A
MEDIUM SHORT
10A
LONG
SHORT
SHORT
VRTN_A
ENABLE_B
ENABLE_A
VDA–
10A
LONG
VRTN_B
VDA–
FDS3672
FDS3672
100k
1M1M
100k
FMMT5401
FMMT5401
100nF
AdvancedTCA with High-Side and Low-Side Ideal Diode-OR
and Hot Swap Controller with I2C Current and Voltage Monitor
LTC4355
15
4355f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
PACKAGE DESCRIPTION
.016 – .050
(0.406 – 1.270)
.010 – .020
(0.254 – 0.508)× 45°
0° – 8° TYP
.008 – .010
(0.203 – 0.254)
1
N
2345678
N/2
.150 – .157
(3.810 – 3.988)
NOTE 3
16 15 14 13
.386 – .394
(9.804 – 10.008)
NOTE 3
.228 – .244
(5.791 – 6.197)
12 11 10 9
S16 0502
.053 – .069
(1.346 – 1.752)
.014 – .019
(0.355 – 0.483)
TYP
.004 – .010
(0.101 – 0.254)
.050
(1.270)
BSC
.245
MIN
N
1 2 3 N/2
.160 ±.005
RECOMMENDED SOLDER PAD LAYOUT
.045 ±.005
.050 BSC
.030 ±.005
TYP
INCHES
(MILLIMETERS)
NOTE:
1. DIMENSIONS IN
2. DRAWING NOT TO SCALE
3. THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .006" (0.15mm)
DE Package
14-Lead Plastic DFN (4mm × 3mm)
(Reference LTC DWG # 05-08-1708 Rev A)
S Package
16-Lead Plastic Small Outline (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1610)
3.00 ±0.10
(2 SIDES)
4.00 ±0.10
(2 SIDES)
NOTE:
1. DRAWING PROPOSED TO BE MADE VARIATION OF
VERSION (WGED-3) IN JEDEC PACKAGE OUTLINE MO-229
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE
TOP AND BOTTOM OF PACKAGE
0.40 ± 0.10
BOTTOM VIEW—EXPOSED PAD
1.70 ± 0.05
(2 SIDES)
0.75 ±0.05
R = 0.115
TYP
R = 0.05
TYP
3.30 ±0.05
(2 SIDES)
17
148
(SEE NOTE 6)
PIN 1
TOP MARK
0.200 REF
0.00 – 0.05
(DE14) DFN 0905 REV A
0.25 ± 0.05
PIN 1
NOTCH
R = 0.20 OR
0.35 × 45°
CHAMFER
0.50 BSC
3.30 ±0.05
(2 SIDES)
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
1.70 ±0.05
(2 SIDES)
2.20
±0.05
0.50
BSC
0.70 ±0.05
3.60
±0.05
PACKAGE
OUTLINE
0.25 ± 0.05
LTC4355
16
4355f
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com
© LINEAR TECHNOLOGY CORPORATION 2007
LT 0307 • PRINTED IN USA
RELATED PARTS
TYPICAL APPLICATION
PART NUMBER DESCRIPTION COMMENTS
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Negative High Voltage Supplies From –10V to –80V
LT1641-1/LT1641-2 Positive High Voltage Hot Swap Controllers Active Current Limiting, Supplies From 9V to 80V
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–48V Hot Swap Controllers in SOT-23 Fast Active Current Limiting, Supplies From –15V
LTC4252-1/LTC4252-2/
LTC4252-1A/LTC4252-2A
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and Monitor
Controls Two N-Channel MOSFETs, 1µs Turn-Off, 80V Operation
Hot Swap is a trademark of Linear Technology Corporation.
4355 TA06
LTC4355
LTC4354
GND
GATE1 GATE2IN1 OUTIN2
1µF
10A
12k
2k
10A
7A
7A
FDS3672
FDS3672
FDS3672
FDS3672
RTNA
RTNB
VSS
VCC
GBGADBDA
VA = –48V
VB = –48V
2k
LOAD
200W AdvancedTCA Ideal Diode-OR
