General Description
The MAX9491 multipurpose clock generator is ideal for
communication applications. It offers a factory-program-
mable PLL output that can be set to almost any frequency,
ranging from 4MHz to 200MHz. The MAX9491 uses a
one-time-programmable (OTP) ROM to program the PLL
output. The MAX9491 also features an integrated volt-
age-controlled crystal oscillator (VCXO) that is tuned by a
DC voltage. The VCXO output is used as the PLL input.
The VCXO has a wide ±200ppm (typ) tuning range. The
OTP on the MAX9491 is factory preset, based upon the
customer request. Contact the factory for samples with
preferred frequencies.
The device operates from a 3.3V supply and is speci-
fied over the -40°C to +85°C extended temperature
range. The MAX9491 is available in 14-pin TSSOP and
20-pin TQFN (5mm x 5mm) packages.
Applications
Telecommunications
Data Networking Systems
Home Entertainment Centers
SOHO
Features
♦5MHz to 35MHz for Crystal-Clock Reference
♦5MHz to 50MHz for a Driver Clock Reference
♦One Fractional-N PLL with Buffered Output
♦4MHz to 200MHz Output Frequency Range
♦Low RMS Jitter PLL (< 13ps) at 197 MHz
♦Integrated VCXO with ±200ppm Tuning Range
♦Available in 14-Pin TSSOP and 20-Pin TQFN
Packages
♦+3.3V Supply
♦-40°C to +85°C Temperature Range
MAX9491
Factory-Programmable, Single PLL
Clock Generator
________________________________________________________________ Maxim Integrated Products 1
15 14 13 12
PD
I.C.
VDD
VDD
11
GND
8
7
6
9
10
I.C.
I.C.
I.C.
GND
I.C.
19
18
17
16
I.C.
X1
X2
VDD
20I.C.
1234
TUNE
VDDA
AGND
GND
5
CLK_OUT
MAX9491
TOP VIEW
TQFN (5mm x 5mm)
Pin Configurations
19-3942; Rev 0; 1/06
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
PART
TEMP RANGE
PIN-
PACKAGE
PKG
CODE
MAX9491ETP
-40°C to +85°C 20 TQFN-EP**
T2055-5
MAX9491EUD* -40°C to +85°C
14 TSSOP U14-2
Ordering Information
*Future product—contact factory for availability.
**EP = Exposed pad.
14
13
12
11
10
9
8
1
2
3
4
5
6
7
X2
VDD
GNDVDD
I.C.
I.C.
X1
TOP VIEW
I.C.
GND
I.C.
CLK_OUT
GND
TUNE
MAX9491
TSSOP
PD
MAX9491
Factory Programmable Single PLL
Clock Generator
2 _______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
DC ELECTRICAL CHARACTERISTICS
(VDD = VDDA = +3.0V to +3.6V and TA= -40°C to +85°C. Typical values at VDD = VDDA = 3.3V, TA= +25°C, unless otherwise noted.)
(Note 1)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
VDD to GND...........................................................-0.3V to +4.0V
VDDA to AGND ......................................................-0.3V to +4.0V
All Other Pins to GND ..................................-0.3V to VDD + 0.3V
Short-Circuit Duration
(all LVCMOS outputs)..............................................Continuous
ESD Protection (Human Body Model)..................................±2kV
Continuous Power Dissipation (TA= +70°C)
20-Lead TQFN (derate 21.3mW/°C above +70°C) ....2758mW
14-Pin TSSOP (derate 9.1mW/°C above +70°C) ......796.8mW
Storage Temperature Range .............................-65°C to +150°C
Maximum Junction Temperature .....................................+150°C
Operating Temperature Range ...........................-40°C to +85°C
Lead Temperature (soldering, 10s) .................................+300°C
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
LVCMOS INPUTS (PD, X1 as a reference INPUT CLK)
Input High Level VIH 2.0 VDD V
Input Low Level VIL 0 0.8 V
High-Level Input Current IIH VIN = VDD 20 µA
Low-Level Input Current IIL VIN = 0 -20 µA
CLOCK OUTPUT (CLK_OUT)
Output High Level VOH IOH = -4mA VDD -
0.6 V
Output Low Level VOL IOL = 4mA 0.4 V
POWER SUPPLIES
Digital Power-Supply Voltage VDD 3.0 3.6 V
Analog Power-Supply Voltage VDDA 3.0 3.6 V
Total Current for Digital and
Analog Supplies IDC fOUT = 45MHz, no load
fIN = 13MHz 10 mA
Power-Down Current IDC2PD = low 60 µA
MAX9491
Factory Programmable Single PLL
Clock Generator
_______________________________________________________________________________________ 3
AC ELECTRICAL CHARACTERISTICS
(VDD = VDDA = +3.0V to +3.6V, CL= 10pF and TA= -40°C to +85°C. Typical values are at VDD = VDDA = 3.3V, TA= +25°C, unless
otherwise noted.) (Note 2)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
OUTPUT CLOCK (CLK_OUT)
Minimum Frequency Range fIN = 5MHz to 50MHz 4
Maximum Frequency Range fOUT CL < 5pF 133 200 MHz
Clock Rise Time tR20% to 80% of VDD, fOUT = 80MHz,
fIN = 13MHz 1.5 ns
Clock Fall Time tF80% to 20% of VDD, fOUT = 80MHz,
fIN = 13MHz 1.3 ns
Duty Cycle fOUT = 45MHz, fIN = 13MHz 44 50 56 %
fOUT = 45MHz, fIN = 13MHz 14
fOUT = 80MHz, fIN = 13MHz 22Output Period Jitter JP
fOUT = 197MHz, fIN = 13MHz 13
ps
RMS
Soft Power-On Time tPO2
PD from low to high, fOUT = 45MHz,
fIN = 13MHz, see Figure 2 1ms
Hard Power-On Time tPO1 See Figure 2 15 ms
VCXO CLOCK
Crystal Frequency fXTL 27 MHz
Crystal Accuracy ±30 ppm
Tuning Voltage Range VTUNE 03V
VCXO Tuning Range VTUNE = 0 to 3V, C1 = C2 = 4pF ±150 ±200 ppm
TUNE Input Impedance ZTUNE 95 kΩ
Output CLK Accuracy VTUNE = 1.5V, C1 = C2 = 4pF ±50 ppm
Note 1: All parameters are tested at TA= +25°C. Specifications over temperature are guaranteed by design and characterization.
Note 2: Guaranteed by design and characterization; limits are set at ±6 sigma.
MAX9491
Factory Programmable Single PLL
Clock Generator
4 _______________________________________________________________________________________
8
9
11
10
12
13
-40 10-15 35 60 85
SUPPLY CURRENT vs. TEMPERATURE
MAX9491 toc01
TEMPERATURE (°C)
SUPPLY CURRENT (mA)
fIN = 13MHz
fOUT = 45MHz
0.2
0.6
1.4
1.0
1.8
2.2
-40 10-15 35 60 85
RISE TIME vs. TEMPERATURE
MAX9491 toc02
TEMPERATURE (°C)
RISE TIME (ns)
fIN = 13MHz
fOUT = 45MHz
0.2
0.6
1.4
1.0
1.8
2.2
-40 10-15 35 60 85
FALL TIME vs. TEMPERATURE
MAX9491 toc03
TEMPERATURE (°C)
FALL TIME (ns)
fIN = 13MHz
fOUT = 45MHz
0
30
25
20
15
10
5
35
40
-40 10-15 35 60 85
JITTER vs. TEMPERATURE
MAX9491 toc04
TEMPERATURE (°C)
JITTER (ps)
fIN = 13MHz
fOUT = 45MHz
0
8
24
16
32
40
-40 10-15 35 60 85
JITTER vs. TEMPERATURE
MAX9491 toc05
TEMPERATURE (°C)
JITTER (ps)
fIN = 13MHz
fOUT = 80MHz
0
10
30
20
40
-40 10-15 35 60 85
JITTER vs. TEMPERATURE
MAX9491 toc06
TEMPERATURE (°C)
JITTER (ps)
fIN = 27MHz
fOUT = 197MHz
TYPICAL CLK_OUT WAVEFORM AT 45MHz
MAX9491 toc07
4ns/div
CLK1
1V/div
VDD = VDDA = 3.0V
TYPICAL CLK_OUT WAVEFORM AT 80MHz
MAX9491 toc08
4ns/div
CLK1
1V/div
VDD = VDDA = 3.0V
TYPICAL CLK_OUT WAVEFORM AT 197MHz
MAX9491 toc09
4ns/div
CLK1
1V/div
VDD = VDDA = 3.0V
Typical Operating Characteristics
(VDD = VDDA = +3.3V, TA= +25°C, fIN = 13MHz clock, CL= 10pF, 27MHz, unless otherwise noted.)
MAX9491
Factory Programmable Single PLL
Clock Generator
_______________________________________________________________________________________ 5
-300
-100
-200
100
0
200
300
VCXO ACCURACY vs. VCXO TUNING RANGE
MAX9491 toc10
VCXO TUNING RANGE (V)
VCXO ACCURACY (PP/M)
0 1.0 1.50.5 2.0 2.5 3.0
fIN = 27MHz
fOUT = 45MHz 6pF
4pF
5pF
0
20
60
40
80
100
45 5550 60 65 70 75 80
DUTY CYCLE vs. OUTPUT FREQUENCY
MAX9491 toc11
FREQUENCY (MHz)
DUTY CYCLE (%)
fIN = 13MHz
45MHz OUTPUT
MAX9491 toc12
10dB/REF = 0dBm
RBW = 3kHz
VBW = 3kHz
ATN = 20dB
CENTER = 45MHz
SPAN = 2MHz
80MHz OUTPUT
MAX9491 toc13
10dB/REF = 0dBm
RBW = 3kHz
VBW = 3kHz
ATN = 20dB
CENTER = 80MHz
SPAN = 2MHz
Typical Operating Characteristics (continued)
(VDD = VDDA = +3.3V, TA= +25°C, fIN = 13MHz clock, CL= 10pF, 27MHz, unless otherwise noted.)
MAX9491
Factory Programmable Single PLL
Clock Generator
6 _______________________________________________________________________________________
Detailed Description
The MAX9491 features a programmable fractional-N
PLL, so frequencies between 4MHz to 200MHz can be
generated. The device provides a buffered PLL clock
output. The crystal input frequency can be between
5MHz and 35MHz, and the clock input between 5MHz
and 50MHz. The internal VCXO has a fine-tuning range
of ±200ppm.
Power-Down
Driving PD low places the MAX9491 in power-down
mode. PD then sets CLK_OUT to high impedance and
shuts down the PLL. CLK_OUT has an 80kΩ(typ) inter-
nal pulldown resistor.
Voltage-Controlled Crystal Oscillator
(VCXO)
The MAX9491’s internal VCXO produces a reference
clock for the PLL used to generate the CLK_OUT. The
oscillator uses a crystal as the base frequency refer-
ence and has a voltage-controlled tuning input for micro
adjustment in a ±200ppm range. The tuning voltage,
VTUNE, can vary from 0 to 3V as shown in Figure 1. The
crystal should be AT-cut and oscillate on its fundamen-
tal mode with ±30ppm. The crystal shunt capacitor
Pin Description
Typical Operating Circuit/Block Diagram
+3.3V
VDD
VDDA
VDD
VDD
0.1µF x 3
0.1µF
MAX9491
+3.3V
GND
AGND
TUNE
C1
C2
CLK_OUT
PLL
VCXO
X1
OR REFERENCE
INPUT
X2
OTP PD
PIN
TQFN TSSOP NAME FUNCTION
1 5 TUNE VCXO Tune Voltage Input. If using a reference clock input or VCXO is not used,
connect TUNE to VDD.
2—V
DDA Analog Power Supply. Bypass to GND with a 0.1µF capacitor.
3 — AGND Analog Ground
4, 10, 11 6, 9, 11 GND Ground
5 7 CLK_OUT Output Clock. Internally pulled down.
6–9, 14, 19, 20 2, 3, 8, 10 I.C. Internally Connected. Leave unconnected for normal operation.
12, 13, 16 4, 12 VDD Power Supply. Bypass to GND with a 0.1µF capacitor.
15 13 PD Active-Low Power-Down Input. Pull high for normal operation. Drive PD low to place
MAX9491 in power-down mode. Internally pulled down.
17 14 X2 Crystal Connection 2. Leave unconnected if using a reference clock.
18 1 X1 Crystal Connection 1 or Reference Clock Input
EP — EP Exposed Paddle (TQFN Only). Connect EP to GND or leave unconnected.
MAX9491
Factory Programmable Single PLL
Clock Generator
_______________________________________________________________________________________ 7
should be less than 10pF, including board parasitic
capacitance. To achieve up to ±200ppm pullability, make
sure the crystal-loading capacitance is less than 14pF.
The VCXO is a free-running oscillator. It starts oscillating
with an internal POR signal and can be disabled by PD.
When VCXO is not used, connect TUNE to VDD.
Applications Information
Using an Input Clock as the Reference
When an input clock is used as the reference, connect
the input clock to X1, leave X2 unconnected, and connect
TUNE to VDD.
Crystal Selection
When using a crystal with the MAX9491’s internal oscil-
lator, connect the crystal to X1 and X2. Choose an AT-
cut crystal that oscillates on its fundamental mode with
±30ppm and loading capacitance less than 14pF. To
achieve a wide VCXO tuning range, select a crystal
with motional capacitance greater than 7fF and con-
nect 6pF or less shunt capacitors at both X1 and X2 to
ground. When the VCXO is used as an oscillator, select
both shunt capacitors to approximately 13pF. The opti-
mal shunt capacitors for achieving minimum frequency
offset can be determined experimentally.
27.0405
26.99595
-150ppm
3V VTUNE
0
+150ppm
27.00
VCXO OUTPUT FREQUENCY
(MHz)
Figure 1. VCXO Tuning Range for a 27MHz Crystal
VDD
2.2V
CLK_OUT
t
CLK_IN
PD
tPO2
tPO1
Figure 2. PLL Settling Time
MAX9491
Factory Programmable Single PLL
Clock Generator
8 _______________________________________________________________________________________
Board Layout Considerations and
Bypassing
The MAX9491’s high-frequency oscillator requires
proper layout to ensure stability. For best performance,
place components as close as possible to the device.
Digital or AC transient signals on GND can create noise
at the clock output. Return GND to the highest quality
ground available. Bypass each VDD and VDDA with a
0.1µF capacitor, placed as close as possible to the
device. Careful PC board ground layout minimizes
crosstalk between the output and digital inputs.
Chip Information
PROCESS: CMOS
MAX9491
Factory Programmable Single PLL
Clock Generator
_______________________________________________________________________________________ 9
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
TSSOP4.40mm.EPS
PACKAGE OUTLINE, TSSOP 4.40mm BODY
21-0066 1
1
G
MAX9491
Factory Programmable Single PLL
Clock Generator
10 ______________________________________________________________________________________
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
QFN THIN.EPS
D2
(ND-1) X e
e
D
C
PIN # 1
I.D.
(NE-1) X e
E/2
E
0.08 C
0.10 C
A
A1 A3
DETAIL A
E2/2
E2
0.10 M C A B
PIN # 1 I.D.
b
0.35x45°
D/2 D2/2
L
C
L
C
e e
L
CC
L
k
L
L
DETAIL B
L
L1
e
AAAAA
MARKING
I
1
2
21-0140
PACKAGE OUTLINE,
16, 20, 28, 32, 40L THIN QFN, 5x5x0.8mm
-DRAWING NOT TO SCALE-
L
e/2
MAX9491
Factory Programmable Single PLL
Clock Generator
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 11
© 2006 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products, Inc.
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
COMMON DIMENSIONS
MAX.
EXPOSED PAD VARIATIONS
D2
NOM.MIN. MIN.
E2
NOM. MAX.
NE
ND
PKG.
CODES
1. DIMENSIONING & TOLERANCING CONFORM TO ASME Y14.5M-1994.
2. ALL DIMENSIONS ARE IN MILLIMETERS. ANGLES ARE IN DEGREES.
3. N IS THE TOTAL NUMBER OF TERMINALS.
4. THE TERMINAL #1 IDENTIFIER AND TERMINAL NUMBERING CONVENTION SHALL
CONFORM TO JESD 95-1 SPP-012. DETAILS OF TERMINAL #1 IDENTIFIER ARE
OPTIONAL, BUT MUST BE LOCATED WITHIN THE ZONE INDICATED. THE TERMINAL #1
IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE.
5. DIMENSION b APPLIES TO METALLIZED TERMINAL AND IS MEASURED BETWEEN
0.25 mm AND 0.30 mm FROM TERMINAL TIP.
6. ND AND NE REFER TO THE NUMBER OF TERMINALS ON EACH D AND E SIDE RESPECTIVELY.
7. DEPOPULATION IS POSSIBLE IN A SYMMETRICAL FASHION.
8. COPLANARITY APPLIES TO THE EXPOSED HEAT SINK SLUG AS WELL AS THE TERMINALS.
9. DRAWING CONFORMS TO JEDEC MO220, EXCEPT EXPOSED PAD DIMENSION FOR
T2855-3 AND T2855-6.
NOTES:
SYMBOL
PKG.
N
L1
e
E
D
b
A3
A
A1
k
10. WARPAGE SHALL NOT EXCEED 0.10 mm.
JEDEC
0.70 0.800.75
4.90
4.90
0.25
0.25
0
--
4
WHHB
4
16
0.350.30
5.10
5.105.00
0.80 BSC.
5.00
0.05
0.20 REF.
0.02
MIN. MAX.NOM.
16L 5x5
L0.30 0.500.40
------
WHHC
20
5
5
5.00
5.00
0.30
0.55
0.65 BSC.
0.45
0.25
4.90
4.90
0.25
0.65
--
5.10
5.10
0.35
20L 5x5
0.20 REF.
0.75
0.02
NOM.
0
0.70
MIN.
0.05
0.80
MAX.
---
WHHD-1
28
7
7
5.00
5.00
0.25
0.55
0.50 BSC.
0.45
0.25
4.90
4.90
0.20
0.65
--
5.10
5.10
0.30
28L 5x5
0.20 REF.
0.75
0.02
NOM.
0
0.70
MIN.
0.05
0.80
MAX.
---
WHHD-2
32
8
8
5.00
5.00
0.40
0.50 BSC.
0.30
0.25
4.90
4.90
0.50
--
5.10
5.10
32L 5x5
0.20 REF.
0.75
0.02
NOM.
0
0.70
MIN.
0.05
0.80
MAX.
0.20 0.25 0.30
DOWN
BONDS
ALLOWED
YES3.103.00 3.203.103.00 3.20T2055-3
3.103.00 3.203.103.00 3.20
T2055-4
T2855-3 3.15 3.25 3.35 3.15 3.25 3.35
T2855-6 3.15 3.25 3.35 3.15 3.25 3.35
T2855-4 2.60 2.70 2.80 2.60 2.70 2.80
T2855-5 2.60 2.70 2.80 2.60 2.70 2.80
T2855-7 2.60 2.70 2.80 2.60 2.70 2.80
3.20
3.00 3.10T3255-3 3 3.203.00 3.10
3.203.00 3.10T3255-4 3 3.203.00 3.10
NO
NO
NO
NO
YES
YES
YES
YES
3.203.00T1655-3 3.10 3.00 3.10 3.20 NO
NO3.203.103.003.10T1655N-1 3.00 3.20
3.353.15T2055-5 3.25 3.15 3.25 3.35 YES
3.35
3.15
T2855N-1 3.25 3.15 3.25 3.35 NO
3.353.15T2855-8 3.25 3.15 3.25 3.35 YES
3.203.10T3255N-1 3.00 NO
3.203.103.00
L
0.40
0.40
**
**
**
**
**
**
**
**
**
**
**
**
**
**
SEE COMMON DIMENSIONS TABLE
±0.15
11. MARKING IS FOR PACKAGE ORIENTATION REFERENCE ONLY.
I
2
2
21-0140
PACKAGE OUTLINE,
16, 20, 28, 32, 40L THIN QFN, 5x5x0.8mm
-DRAWING NOT TO SCALE-
12. NUMBER OF LEADS SHOWN ARE FOR REFERENCE ONLY.
3.30T4055-1 3.20 3.40 3.20 3.30 3.40 ** YES
0.050 0.02
0.600.40 0.50
10
-----
0.30
40
10
0.40 0.50
5.10
4.90 5.00
0.25 0.35 0.45
0.40 BSC.
0.15
4.90
0.250.20
5.00 5.10
0.20 REF.
0.70
MIN.
0.75 0.80
NOM.
40L 5x5
MAX.
13. LEAD CENTERLINES TO BE AT TRUE POSITION AS DEFINED BY BASIC DIMENSION "e", ±0.05.
T1655-2 ** YES3.203.103.003.103.00 3.20
T3255-5 YES3.003.103.00 3.20 3.203.10 **
exceptions
Springer
