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10/02/06
IRLR7821PbF
IRLU7821PbF
HEXFET® Power MOSFET
Notes through are on page 11
PD - 95091B
Applications
Benefits
lVery Low RDS(on) at 4.5V VGS
lUltra-Low Gate Impedance
lFully Characterized Avalanche Voltage
and Current
lHigh Frequency Synchronous Buck
Converters for Computer Processor Power
lHigh Frequency Isolated DC-DC
Converters with Synchronous Rectification
for Telecom and Industrial Use
lLead-Free
D-Pak
IRLR7821PbF
I-Pak
IRLU7821PbF
VDSS RDS(on) max Qg
30V 10m
:
10nC
Absolute Maximum Ratings
Parameter Units
VDS Drain-to-Source Voltage V
VGS Gate-to-Source Voltage
ID @ TC = 25°C Continuous Drain Current, VGS @ 10V
ID @ TC = 100°C Continuous Drain Current, VGS @ 10V A
IDM Pulsed Drain Current
c
PD @TC = 25°C Maximum Power Dissipation
PD @TC = 100°C Maximum Power Dissipation
Linear Derating Factor W/°C
TJ Operating Junction and °C
TSTG Storage Temperature Range
Thermal Resistance
Parameter Typ. Max. Units
RθJC Junction-to-Case ––– 2.0
RθJA Junction-to-Ambient (PCB Mount)
g
––– 50 °C/W
RθJA Junction-to-Ambient ––– 110
W
-55 to + 175
75
0.50
37.5
Max.
65
f
47
f
260
± 20
30
IRLR/U7821PbF
2www.irf.com
S
D
G
Static @ TJ = 25°C (unless otherwise specified)
Parameter Min. Typ. Max. Units
BVDSS Drain-to-Source Breakdown Voltage 30 ––– ––– V
∆ΒVDSS
/
∆TJ Breakdown Voltage Temp. Coefficient ––– 23 ––– mV/°C
RDS(on) Static Drain-to-Source On-Resistance ––– 7.5 10 mΩ
––– 9.5 12.5
VGS(th) Gate Threshold Voltage 1.0 ––– ––– V
∆VGS(th) Gate Threshold Voltage Coefficient ––– -5.3 ––– mV/°C
IDSS Drain-to-Source Leakage Current ––– ––– 1.0 µA
––– ––– 150
IGSS Gate-to-Source Forward Leakage ––– ––– 100 nA
Gate-to-Source Reverse Leakage ––– ––– -100
gfs Forward Transconductance 46 ––– ––– S
QgTotal Gate Charge ––– 10 14
Qgs1 Pre-Vth Gate-to-Source Charge ––– 2.0 –––
Qgs2 Post-Vth Gate-to-Source Charge ––– 1.2 ––– nC
Qgd Gate-to-Drain Charge ––– 2.5 –––
Qgodr Gate Charge Overdrive ––– 4.3 ––– See Fig. 16
Qsw Switch Char
g
e (Qgs2 + Qgd)––– 3.7 –––
Qoss Output Charge ––– 8.5 ––– nC
td(on) Turn-On Delay Time ––– 11 –––
trRise Time ––– 4.2 –––
td(off) Turn-Off Delay Time ––– 10 ––– ns
tfFall Time ––– 3.2 –––
Ciss Input Capacitance ––– 1030 –––
Coss Output Capacitance ––– 360 ––– pF
Crss Reverse Transfer Capacitance ––– 120 –––
Avalanche Characteristics
Parameter Units
EAS Sin
g
le Pulse Avalanche Ener
gy
dh
mJ
IAR Avalanche Current
c
A
EAR Repetitive Avalanche Ener
gy
c
mJ
Diode Characteristics
Parameter Min. Typ. Max. Units
ISContinuous Source Current ––– ––– 65
f
(Body Diode) A
ISM Pulsed Source Current ––– ––– 260
(
Bod
y
Diode
)
ch
VSD Diode Forward Voltage ––– ––– 1.0 V
trr Reverse Recovery Time ––– 26 38 ns
Qrr Reverse Recovery Charge ––– 15 23 nC
ton Forward Turn-On Time Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
MOSFET symbol
VGS = 4.5V, ID = 12A
f
–––
VGS = 4.5V
Typ.
–––
–––
ID = 12A
VGS = 0V
VDS = 15V
TJ = 25°C, IF = 12A, VDD = 15V
di/dt = 100A/µs
f
TJ = 25°C, IS = 12A, VGS = 0V
f
showing the
integral reverse
p-n junction diode.
VDS = VGS, ID = 250µA
VDS = 24V, VGS = 0V
VDS = 24V, VGS = 0V, TJ = 125°C
Clamped Inductive Load
VDS = 15V, ID = 12A
Conditions
VGS = 0V, ID = 250µA
Reference to 25°C, ID = 1mA
VGS = 10V, ID = 15A
f
Conditions
7.5
Max.
230
12
ƒ = 1.0MHz
VDS = 16V, VGS = 0V
VDD = 15V, VGS = 4.5V
f
ID = 12A
VDS = 16V
VGS = 20V
VGS = -20V
IRLR/U7821PbF
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Fig 4. Normalized On-Resistance
Vs. Temperature
Fig 2. Typical Output CharacteristicsFig 1. Typical Output Characteristics
Fig 3. Typical Transfer Characteristics
1
10
100
1000
2.0 4.0 6.0 8.0 10.0
V = 15V
20µs PULSE WIDTH
DS
V , Gate-to-Source Voltage (V)
I , Drain-to-Source Current (A)
GS
D
T = 175 C
J°
T = 25 C
J°
-60 -40 -20 020 40 60 80 100 120 140 160 180
0.0
0.5
1.0
1.5
2.0
R , Drain-to-Source On Resistance
(Normalized)
DS(on)
V =
I =
GS
D
10V
65A
0.1 110 100
VDS, Drain-to-Source Voltage (V)
0.1
1
10
100
1000
10000
ID, Drain-to-Source Current (A)
2.5V
20µs PULSE WIDTH
Tj = 25°C
VGS
TOP 10V
4.5V
3.7V
3.5V
3.3V
3.0V
2.7V
BOTTOM 2.5V
0.1 110 100
VDS, Drain-to-Source Voltage (V)
1
10
100
1000
ID, Drain-to-Source Current (A)
2.5V
20µs PULSE WIDTH
Tj = 175°C
VGS
TOP 10V
4.5V
3.7V
3.5V
3.3V
3.0V
2.7V
BOTTOM 2.5V
TJ, Junction Temperature (°C)
IRLR/U7821PbF
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Fig 8. Maximum Safe Operating Area
Fig 6. Typical Gate Charge Vs.
Gate-to-Source Voltage
Fig 5. Typical Capacitance Vs.
Drain-to-Source Voltage
Fig 7. Typical Source-Drain Diode
Forward Voltage
110 100
VDS, Drain-to-Source Voltage (V)
10
100
1000
10000
C, Capacitance(pF)
VGS
= 0V, f = 1 MHZ
Ciss
= C
gs
+ C
gd, C
ds
SHORTED
Crss
= C
gd
Coss
= C
ds
+ C
gd
Coss
Crss
Ciss
0.1
1
10
100
1000
0.0 0.5 1.0 1.5 2.0
V ,Source-to-Drain Voltage (V)
I , Reverse Drain Current (A)
SD
SD
V = 0 V
GS
T = 175 C
J°
T = 25 C
J°
1 10 100
VDS, Drain-to-Source Voltage (V)
0.1
1
10
100
1000
ID, Drain-to-Source Current (A)
Tc = 25°C
Tj = 175°C
Single Pulse
1msec
10msec
OPERATION IN THIS AREA
LIMITED BY R DS(on)
100µsec
024681012
QG Total Gate Charge (nC)
0
1
2
3
4
5
6
VGS, Gate-to-Source Voltage (V)
VDS= 24V
VDS= 16V
ID= 12A
IRLR/U7821PbF
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Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
Fig 9. Maximum Drain Current Vs.
Case Temperature
25 50 75 100 125 150 175
0
10
20
30
40
50
60
70
T , Case Temperature ( C)
I , Drain Current (A)
°
C
D
LIMITED BY PACKAGE
0.01
0.1
1
10
0.00001 0.0001 0.001 0.01 0.1 1
Notes:
1. Duty factor D = t / t
2. Peak T = P x Z + T
1 2
JDM thJC C
P
t
t
DM
1
2
t , Rectangular Pulse Duration (sec)
Thermal Response (Z )
1
thJC
0.01
0.02
0.05
0.10
0.20
D = 0.50
SINGLE PULSE
(THERMAL RESPONSE)
-75 -50 -25 025 50 75 100 125 150 175 200
TJ , Temperature ( °C )
0.5
1.0
1.5
2.0
2.5
VGS(th) Gate threshold Voltage (V)
ID = 250µA
Fig 10. Threshold Voltage Vs. Temperature
IRLR/U7821PbF
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25 50 75 100 125 150 175
0
200
400
600
800
1000
Starting Tj, Junction Temperature ( C)
E , Single Pulse Avalanche Energy (mJ)
AS
°
ID
TOP
BOTTOM
4.9A
8.5A
12A
D.U.T. V
DS
I
D
I
G
3mA
V
GS
.3µF
50KΩ
.2µF
12V
Current Regulator
Same Type as D.U.T.
Current Sampling Resistors
+
-
Fig 13. Gate Charge Test Circuit
Fig 12b. Unclamped Inductive Waveforms
Fig 12a. Unclamped Inductive Test Circuit
tp
V
(BR)DSS
I
AS
Fig 12c. Maximum Avalanche Energy
Vs. Drain Current
R
G
I
AS
0.01
Ω
t
p
D.U.T
L
VDS
+
-V
DD
DRIVER
A
15V
20V
VGS
Fig 14a. Switching Time Test Circuit
V
DS
90%
10%
V
GS
t
d(on)
t
r
t
d(off)
t
f
Fig 14b. Switching Time Waveforms
VDS
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %
RD
VGS
RG
D.U.T.
VGS
+
-
VDD
IRLR/U7821PbF
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Fig 15. Peak Diode Recovery dv/dt Test Circuit for N-Channel
HEXFET® Power MOSFETs
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
P.W. Period
di/dt
Diode Recovery
dv/dt
Ripple ≤5%
Body Diode Forward Drop
Re-Applied
Voltage
Reverse
Recovery
Current
Body Diode Forward
Current
V
GS
=10V
V
DD
I
SD
Driver Gate Drive
D.U.T. I
SD
Waveform
D.U.T. V
DS
Waveform
Inductor Curent
D = P. W .
Period
* VGS = 5V for Logic Level Devices
*
+
-
+
+
+
-
-
-
RGVDD
• dv/dt controlled by RG
• Driver same type as D.U.T.
• ISD controlled by Duty Factor "D"
• D.U.T. - Device Under Test
D.U.T
Fig 16. Gate Charge Waveform
Vds
Vgs
Id
Vgs(th)
Qgs1 Qgs2 Qgd Qgodr
IRLR/U7821PbF
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Control FET
Special attention has been given to the power losses
in the switching elements of the circuit - Q1 and Q2.
Power losses in the high side switch Q1, also called
the Control FET, are impacted by the Rds(on) of the
MOSFET, but these conduction losses are only about
one half of the total losses.
Power losses in the control switch Q1 are given
by;
Ploss = Pconduction+ Pswitching+ Pdrive+ Poutput
This can be expanded and approximated by;
P
loss =Irms
2×Rds(on )
()
+I×Qgd
ig
×Vin ×f
⎛
⎝
⎜ ⎞
⎠
⎟ +I×Qgs 2
ig
×V
in ×f
⎛
⎝
⎜ ⎞
⎠
⎟
+Qg×Vg×f
()
+Qoss
2×Vin ×f
⎛
⎝ ⎞
⎠
This simplified loss equation includes the terms Qgs2
and Qoss which are new to Power MOSFET data sheets.
Qgs2 is a sub element of traditional gate-source
charge that is included in all MOSFET data sheets.
The importance of splitting this gate-source charge
into two sub elements, Qgs1 and Qgs2, can be seen from
Fig 16.
Qgs2 indicates the charge that must be supplied by
the gate driver between the time that the threshold
voltage has been reached and the time the drain cur-
rent rises to Idmax at which time the drain voltage be-
gins to change. Minimizing Qgs2 is a critical factor in
reducing switching losses in Q1.
Qoss is the charge that must be supplied to the out-
put capacitance of the MOSFET during every switch-
ing cycle. Figure A shows how Qoss is formed by the
parallel combination of the voltage dependant (non-
linear) capacitances Cds and Cdg when multiplied by
the power supply input buss voltage.
Synchronous FET
The power loss equation for Q2 is approximated
by;
P
loss =P
conduction +P
drive +P
output
*
P
loss =Irms
2×Rds(on)()
+Qg×Vg×f
()
+Qoss
2×Vin ×f
⎛
⎝
⎜ ⎞
⎠ +Qrr ×Vin ×f
(
)
*dissipated primarily in Q1.
For the synchronous MOSFET Q2, Rds(on) is an im-
portant characteristic; however, once again the im-
portance of gate charge must not be overlooked since
it impacts three critical areas. Under light load the
MOSFET must still be turned on and off by the con-
trol IC so the gate drive losses become much more
significant. Secondly, the output charge Qoss and re-
verse recovery charge Qrr both generate losses that
are transfered to Q1 and increase the dissipation in
that device. Thirdly, gate charge will impact the
MOSFETs’ susceptibility to Cdv/dt turn on.
The drain of Q2 is connected to the switching node
of the converter and therefore sees transitions be-
tween ground and Vin. As Q1 turns on and off there is
a rate of change of drain voltage dV/dt which is ca-
pacitively coupled to the gate of Q2 and can induce
a voltage spike on the gate that is sufficient to turn
the MOSFET on, resulting in shoot-through current .
The ratio of Qgd/Qgs1 must be minimized to reduce the
potential for Cdv/dt turn on.
Power MOSFET Selection for Non-Isolated DC/DC Converters
Figure A: Qoss Characteristic
IRLR/U7821PbF
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D-Pak (TO-252AA) Part Marking Information
D-Pak (TO-252AA) Package Outline
LINE A
34
RECTIFIER
LOGO
IRF R120
12
ASSEMBLY
LOT CODE
YEAR 1 = 2001
DAT E CODE
PART NUMBER
WEEK 16
116A
INT ERNAT IONAL
AS S EMB LED ON WW 16, 2001
IN THE ASSEMBLY LINE "A"
OR
Note: "P" in as s embly line pos ition
EXAMPLE:
LOT CODE 1234
THIS IS AN IRFR120
WITH ASSEMBLY
indicates "L ead- F r ee"
PRODUCT (OPTIONAL)
P = DE S IGN AT E S L E AD-F R E E
A = ASSEMBLY SITE CODE
PART NUMBER
WEEK 16
DAT E CODE
YEAR 1 = 2001
RECTIFIER
INT ERNAT IONAL
LOGO
LOT CODE
ASSEMBLY
3412
IRFR120
IRLR/U7821PbF
10 www.irf.com
I-Pak (TO-251AA) Part Marking Information
I-Pak (TO-251AA) Package Outline
Dimensions are shown in millimeters (inches)
78
LINE A
LOGO
INTERNATIONAL
RECTIFIER
OR
PRODUCT (OPTIONAL)
P = DE S I GNAT E S L E AD- F R E E
A = ASSEMBLY SITE CODE
IRFU120
119A
DAT E CODE
PART NUMBER
LOT CODE
ASSEMBLY
56 78
YEAR 1 = 2001
WEE K 19
i ndi cates L ead-F ree"
AS S EMB L ED ON WW 19, 2001
IN THE ASSEMBLY LINE "A"
Note: "P" in ass embly line position
EXAMPLE:
WIT H AS S E MB L Y
THIS IS AN IRF U120
LOT CODE 5678 RECTIFIER
INTERNATIONAL
LOGO
ASSEMBLY
LOT CODE
IRFU120
56
PART NUMBER
WEE K 19
DAT E CODE
YEAR 1 = 2001
IRLR/U7821PbF
www.irf.com 11
Repetitive rating; pulse width limited by
max. junction temperature.
Starting TJ = 25°C, L = 3.2mH
RG = 25Ω, IAS = 12A.
Pulse width ≤ 400µs; duty cycle ≤ 2%.
Notes:
Calculated continuous current based on maximum allowable
junction temperature. Package limitation current is 30A.
When mounted on 1" square PCB (FR-4 or G-10 Material).
For recommended footprint and soldering techniques refer to
application note #AN-994.
Data and specifications subject to change without notice.
This product has been designed and qualified for the Industrial market.
Qualification Standards can be found on IR’s Web site.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information.10/2006
D-Pak (TO-252AA) Tape & Reel Information
Dimensions are shown in millimeters (inches)
TR
16.3 ( .641 )
15.7 ( .619 )
8.1 ( .318 )
7.9 ( .312 )
12.1 ( .476 )
11.9 ( .469 ) FEED DIRECTION FEED DIRECTION
16.3 ( .641 )
15.7 ( .619 )
TRR TRL
NOTES :
1. CONTROLLING DIMENSION : MILLIMETER.
2. ALL DIMENSIONS ARE SHOWN IN MILLIMETERS ( INCHES ).
3. OUTLINE CONFORMS TO EIA-481 & EIA-541.
NOTES :
1. OUTLINE CONFORMS TO EIA-481.
16 mm
13 INCH
Note: For the most current drawings please refer to the IR website at:
http://www.irf.com/package/