1
File Number 1893.3
CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures.
http://www.intersil.com or 407-727-9207 |Copyright © Intersil Corporation 1999
IRFF330
3.5A, 400V, 1.000 Ohm, N-Channel
Power MOSFET
This N-Channel enhancement mode silicon gate power field
effect transistor is an advanced power MOSFET designed,
tested, and guaranteed to withstand a specified level of
energy in the breakdown avalanche mode of operation. All of
these power MOSFETs are designed for applications such
as switching regulators, switching convertors, motor drivers,
relay drivers, and drivers for high power bipolar switching
transistors requiring high speed and low gate drive power.
These types can be operated directly from integrated
circuits.
Formerly developmental type TA17414.
Features
3.5A, 400V
•r
DS(ON) = 1.000
Single Pulse Avalanche Energy Rated
SOA is Power Dissipation Limited
Nanosecond Switching Speeds
Linear Transfer Characteristics
High Input Impedance
Related Literature
- TB334 “Guidelines for Soldering Surface Mount
Components to PC Boards”
Symbol
Packaging
JEDEC TO-205AF
Ordering Information
PART NUMBER PACKAGE BRAND
IRFF330 TO-205AF IRFF330
NOTE: When ordering, include the entire part number.
D
G
S
SOURCE
GATE
DRAIN
(CASE)
Data Sheet March 1999
2
Absolute Maximum Ratings TC = 25oC, Unless Otherwise Specified
IRFF330 UNITS
Drain to Source Voltage (Note 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .VDS 400 V
Drain to Gate Voltage (RGS = 20k) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR 400 V
Continuous Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID3.5 A
Pulsed Drain Current (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDM 14 A
Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .VGS ±20 V
Maximum Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .PD25 W
Linear Derating Factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.2 W/oC
Single Pulse Avalanche Energy Rating (Note 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .EAS 300 mJ
Operating and Storage Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ,T
STG -55 to 150 oC
Maximum Temperature for Soldering
Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TL
Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tpkg 300
260
oC
oC
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. TJ= 25oC to 125oC.
Electrical Specifications TC = 25oC, Unless Otherwise Specified
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
Drain to Source Breakdown Voltage BVDSS VGS = 0V, ID = 250µA (Figure 10) 400 - - V
Gate to Threshold Voltage VGS(TH) VGS = VDS, ID = 250µA 2.0 - 4.0 V
Zero-Gate Voltage Drain Current IDSS VDS = Rated BVDSS, VGS = 0V - - 25 µA
VDS = 0.8 x Rated BVDSS, VGS = 0V, TJ = 125oC - - 250 µA
On-State Drain Current (Note 2) ID(ON) VDS > ID(ON) x rDS(ON)MAX,V
GS = 10V (Figure 7) 3.5 - - A
Gate to Source Leakage Forward IGSS VGS = ±20V - - ±100 nA
DraintoSourceOnResistance(Note2) rDS(ON) VGS = 10V, ID = 2.0A (Figures 8, 9) - 0.8 1.000
Forward Transconductance (Note 2) gfs VDS = 10V, ID = 3.3A (Figure 12) 2.9 3.5 - S
Turn-On Delay Time td(ON) ID 3.5A, RG = 9.1, VGS = 10V, RL = 49
VDD = 175V (Figures 17, 18) MOSFET Switching
Times are Essentially Independent of Operating
Temperature
- - 30 ns
Rise Time tr- - 35 ns
Turn-Off Delay Time td(OFF) - - 55 ns
Fall Time tf- - 35 ns
Total Gate Charge
(Gate to Source + Gate to Drain) Qg(TOT) VGS = 10V, ID = 3.5A, IG(REF) = 1.5mA,
VDS = 0.8V x Rated BVDSS (Figures 14, 19, 20)
Gate Charge is Essentially Independent of
Operating Temperature
-1830nC
Gate to Source Charge Qgs -11 - nC
Gate to Drain “Miller” Charge Qgd - 7.0 - nC
Input Capacitance CISS VGS = 0V, VDS = 25V, f = 1.0MHz (Figure 11) - 700 - pF
Output Capacitance COSS - 150 - pF
Reverse Transfer Capacitance CRSS -40 - pF
Internal Drain Inductance LDMeasuredfromtheDrain
Lead, 5mm (0.2in) from
header to Center of Die
Modified MOSFET
Symbol Showing the
Internal Device
Inductances
- 5.0 - nH
Internal Source Inductance LSMeasured from the
Source Lead, 5mm
(0.2in) from Header to
Source Bonding Pad
-15 - nH
Junction to Case RθJC - - 5.0 oC/W
Junction to Ambient RθJA Free Air Operation - - 175 oC/W
LS
LD
G
D
S
IRFF330
3
Source to Drain Diode Specifications
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
Continuous Source to Drain Current ISD Modified MOSFET
Symbol Showing the
Integral Reverse P-N
Junction Rectifier.
- - 3.5 A
Pulse Source to Drain Current (Note 3) ISDM - - 14 A
Source to Drain Diode Voltage (Note 2) VSD TJ = 25oC, ISD = 3.5A, VGS = 0V (Figure 13) - - 1.6 V
Reverse Recovery Time trr TJ = 150oC, ISD = 3.5A, dISD/dt = 100A/µs - 600 - ns
Reverse Recovered Charge QRR TJ = 150oC, ISD = 3.5A, dISD/dt = 100A/µs - 4.0 - µC
NOTES:
2. Pulse test: pulse width 300µs, duty cycle 2%.
3. Repetitive Rating: pulse width limited by Max junction temperature. See Transient Thermal Impedance curve (Figure 3).
4. VDD = 50V, start TJ = 25oC, L = 42.85mH, RG = 25, peak IAS = 3.5A (Figures 14,15).
Typical Performance Curves Unless Otherwise Specified
FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE
TEMPERATURE FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs
CASE TEMPERATURE
FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE
D
G
S
0 50 100 150
0
TC, CASE TEMPERATURE (oC)
POWER DISSIPATION MULTIPLIER
0.2
0.4
0.6
0.8
1.0
1.2
TC, CASE TEMPERATURE (oC)
50 75 10025 150
4
0
ID, DRAIN CURRENT (A)
125
3
2
1
ZθJC, NORMALIZED
1.0
0.1
0.01 10-2
10-5 10-4 10-3 0.1 1 10
T1, RECTANGULAR PULSE DURATION (LC)
NOTES:
DUTY FACTOR: D = t1/t2
PDM
t1t2
SINGLE PULSE TJ= PDM x ZθJC(t) x RθJC + TC
THERMAL IMPEDANCE
0.01
0.5
0.2
0.05
0.02
0.1
IRFF330
4
FIGURE 4. FORWARD BIAS SAFE OPERATING AREA FIGURE 5. OUTPUT CHARACTERISTICS
FIGURE 6. SATURATION CHARACTERISTICS FIGURE 7. TRANSFER CHARACTERISTICS
NOTE: Heating effect of 2µs pulse is minimal.
FIGURE 8. DRAIN TO SOURCE ON RESISTANCE vs GATE
VOLTAGE AND DRAIN CURRENT FIGURE 9. NORMALIZED DRAIN TO SOURCE ON
RESISTANCE vs JUNCTION TEMPERATURE
Typical Performance Curves Unless Otherwise Specified (Continued)
103
110
102
0.1
ID, DRAIN CURRENT (A)
1.0
10
0.01
TC = 25oC
TJ = MAX RATED
SINGLE PULSE
OPERATION IN THIS
AREA IS LIMITED
BY rDS(ON)
DC
10µs
100µs
1ms
100ms
10ms
VDS, DRAIN TO SOURCE VOLTAGE (V) VDS, DRAIN TO SOURCE VOLTAGE (V)
500 100
0
8
ID, DRAIN CURRENT (A)
4
7
6
5
3
2
1
150 200 250 300
80µs PULSE TEST
VGS = 5.5V
VGS = 4.5V
VGS = 5V
VGS = 4V
VGS = 10V
VDS, DRAIN TO SOURCE VOLTAGE (V)
2468010
5
4
3
0
2
ID, DRAIN CURRENT (A)
80µs PULSE TEST
1VGS = 4V
VGS = 5V
VGS = 4.5V
VGS = 10V VGS = 6V VDS > ID(ON) x rDS(ON)MAX
80µs PULSE TEST
TJ = 125oC
ID(ON), DRAIN TO SOURCE CURRENT (A)
VGS, GATE TO SOURCE VOLTAGE (V)
3
1
0024615
2
4
TJ = -55oC
TJ = 25oC
5
37
ID, DRAIN CURRENT (A)
20 30010
3
2
0
rDS(ON), DRAIN TO SOURCE
VGS = 10V
VGS = 20V
15 255
1
ON RESISTANCE ()
2µs PULSE TEST 2.2
1.4
0.6
0 160
TJ, JUNCTION TEMPERATURE (oC)
NORMALIZED ON RESISTANCE
1.8
1.0
0.2 -40 40 80 120
VGS = 10V
ID = 2A
IRFF330
5
FIGURE 10. NORMALIZED DRAIN TO SOURCE BREAKDOWN
VOLTAGE vs JUNCTION TEMPERATURE FIGURE 11. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
FIGURE 12. TRANSCONDUCTANCE vs DRAIN CURRENT FIGURE 13. SOURCE TO DRAIN DIODE VOLTAGE
FIGURE 14. GATE TO SOURCE VOLTAGE vs GATE CHARGE
Typical Performance Curves Unless Otherwise Specified (Continued)
1.25
1.05
0.85
0 160
TJ, JUNCTION TEMPERATURE (oC)
NORMALIZED DRAIN TO SOURCE
1.15
0.95
0.75-40 40 80 120
BREAKDOWN VOLTAGE
ID = 250µA
VDS, DRAIN TO SOURCE VOLTAGE (V)
C, CAPACITANCE (pF)
2000
1600
1200
800
400
0
VGS = 0V, f = 1MHz
CISS = CGS + CGD
CRSS = CGD
COSS CDS + CGS
CISS
COSS
CRSS
0203010 40 50
ID, DRAIN CURRENT (A)
481002
10
4
6
0
2
gfs, TRANSCONDUCTANCE (S)
80µs PULSE TEST
8
6
TJ = -55oC
TJ = 125oC
TJ = 25oC
TJ = 150oC
TJ = 25oC
ISD, SOURCE TO DRAIN CURRENT (A)
VSD, SOURCE TO DRAIN VOLTAGE (V)
100
10
101234
TJ = 25oC
TJ = 150oC
Qg(TOT), TOTAL GATE CHARGE (nC)
81624320
20
15
0
10
VGS, GATE TO SOURCE VOLTAGE (V)
5
ID = 3.5A
VDS = 80V
VDS = 200V
VDS = 320V
40
IRFF330
6
Test Circuits and Waveforms
FIGURE 15. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 16. UNCLAMPED ENERGY WAVEFORMS
FIGURE 17. SWITCHING TIME TEST CIRCUIT FIGURE 18. RESISTIVE SWITCHING WAVEFORMS
FIGURE 19. GATE CHARGE TEST CIRCUIT FIGURE 20. GATE CHARGE WAVEFORMS
tP
0.01
L
IAS
+
-
VDS
VDD
RG
DUT
VARY tP TO OBTAIN
REQUIRED PEAK IAS
0V
VGS
VDD
VDS
BVDSS
tP
IAS
tAV
0
VGS
RL
RG
DUT
+
-VDD
tON
td(ON)
tr
90%
10%
VDS 90%
10%
tf
td(OFF)
tOFF
90%
50%
50%
10% PULSE WIDTH
VGS
0
0
0.3µF
12V
BATTERY 50k
VDS
S
DUT
D
G
IG(REF)
0
(ISOLATED
VDS
0.2µF
CURRENT
REGULATOR
ID CURRENT
SAMPLING
IG CURRENT
SAMPLING
SUPPLY)
RESISTOR RESISTOR
SAME TYPE
AS DUT Qg(TOT)
Qgd
Qgs
VDS
0
VGS
VDD
IG(REF)
0
IRFF330
7
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with-
out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see w eb site http://www.intersil.com
Sales Office Headquarters
NORTH AMERICA
Intersil Corporation
P. O. Box 883, Mail Stop 53-204
Melbourne, FL 32902
TEL: (407) 724-7000
FAX: (407) 724-7240
EUROPE
Intersil SA
Mercure Center
100, Rue de la Fusee
1130 Brussels, Belgium
TEL: (32) 2.724.2111
FAX: (32) 2.724.22.05
ASIA
Intersil (Taiwan) Ltd.
7F-6, No. 101 Fu Hsing North Road
Taipei, Taiwan
Republic of China
TEL: (886) 2 2716 9310
FAX: (886) 2 2715 3029
IRFF330