"MOTOROLA . 654 C00 EE wi SEMICONDUCTOR TECHNICAL DATA Mc6802 Microprocessor With Clock and Optional RAM The MC6802 is a monolithic 8-bit microprocessor that contains all the registers and accumulators of the present MC6800 plus an internal clock oscillator and driver on the same chip. tn addition, the MC6802 has 128 bytes of on-board RAM located at hex addresses $0000 to $007F. The first 32 bytes of RAM, at hex addresses $0000 to $001F, may be retained in a low power mode by utilizing Vcc standby; thus, facilitating memory retention during a power-down situation. The MC6802 is completely software compatible with the MC6800 as well as the entire M6800 family of parts. Hence, the MC6802 is expandable to 64K words. @ On-Chip Clock Circuit 1288 Bit On-Chip RAM . @ 32 Bytes of RAM are Retainable Software-Compatible with the MC6300 Expandable to 64K Words Standard TTL-Compatible Inputs and Outputs 8-Bit Word Size 16-Bit Memory Addressing @ Interrupt Capability TYPICAL MICROCOMPUTER Vec Vcc Vcc Vcc ~_] - oumer MC6846 IRQ RESET las | This block diagram shows a typical cost ef- e ei ROM, I/O, Timer MA tL fective microcomputer The MPU is the RESET e cso be MA VMA HALT + T center of the microcomputer system and 1s + Clock E = shown in a minimum system interfacing with =e} 2 Bytes ROM aia _ RE P+ a ROM combination chip. It 1s not intended we; = 10 1/0 Lines FW ceaa2 Nui that this system be limited to this funcuian Parallel | ~+m{ 3 Lines Timer MPU but that it be expandable with other parts in V0 | ~_~ D0-D7 (aa > 00-07 BAP the M6800 Microcomputer family ~~ EXTAL J p- ~~} CJ ~--ar4 CP2 AO0-A10, en Contrat { cp, cst A0-A15 AO-AIS = XTAL L This document contains information on a new product. Specifications and information herein are subject to change without notice. MOTOROLA MICROPROCESSOR DATA 3-256MC6802 MAXIMUM RATINGS Rating Symbol Value Unit This input contains circuitry to protect the inputs against damage due to high static volt- Supply Voltage Vec_|-0.3to +70) V ages or electric fields; however, it is advised Input Voltage Vin | -0.3to +7.0| V that normal precautions be taken to avoid Operating Temperature Range Ta C application of any voltage higher than max- MC6802, MC680A02, MC680B02 Oto +70 imum rated voltages to this high-impedance MC6802C, MC680A02C ~40 to +85 circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (e.g., either Vss or Vcc). Storage Temperature Range Tstg | 55 to +150 C THERMAL CHARACTERISTICS Characteristic Symboi Value Unit Average Thermal Resistance (Junction to Ambient) Plastic BJA 100 CW POWER CONSIDERATIONS The average chip-junction temperature, Ty, in C can be obtained from: Ty=TatlPp 6a) (1) where: Ta = Ambient Temperature, C BJA = Package Thermal Resistance, Junction-to-Ambient, C/W PD = Pint+ Pport PINT =!ccx Veo Watts Chip Internal Power Peort = Port Power Dissipation, Watts User Determined For most applications PegorT<Pint and can be neglected. PPoRT may become significant if the device is configured to drive Darlington bases or sink LED loads. An approximate relationship between Pp and Ty {if Ppgrt is neglected) is: Pop =K+(Ty+273C) (2) Solving equations (1) and (2) for K gives: K=Pp + (Ta + 273C) +85a"Pp* (3) where K is a constant pertaining to the particular part. K can be determined from equation (3) by measuring Pp [at equilibrium) for a known Ta. Using this value of K, the values of Pp and Ty can be obtained by solving equations (1} and (2) iteratively for any value of Ta. MOTOROLA MICROPROCESSOR DATA 0CT7Mc6802 DC ELECTRICAL CHARACTERISTICS (Vo = +5.0 Vde=0.5%, Vsg =0, Ta =0 to 70C, unless otherwise noted) Characteristic Symbol Min Typ Max Unit input High Voltage Logic, EXTAL ViH Vsgt+2.0 _ Vcc V RESET Vsg+4.0 _ Vcc Input Low Voltage Logic, EXTAL, RESET ViL Vss-0.3 ~ Vsgt+08}] V Input Leakage Current (Vjp, =0 to 5.25 V, Vop = max) Logic lin _ 1.0 2.5 pA Output High Voltage VOH Vv (Load = - 205 pA, Voc =min) _ DO-D7 Vsg+24| (ILgad= ~145 pA, Voc = min) A0-A15, RAW, VMA, E Vgs+2.4 _ (Load = 100 pA, Vec=min) BA Vgg+2.4 _ Output Low Voltage (ILoaq=1.6 mA, Vcc = min} Vor _ Vsgt04] V Internal Power Dissipation (Measured at Ta =0C) PINT _ 0.750 1.0 Vop Standby Power Down VspB 4.0 _ 5.25 Vv Power Up Vsp 4.75 _- 5.25 Standby Current ISBB = _ 8.0 mA Capacitance # D0-07 Cin = 10 12.5 pF (Vin =0, Ta = 25C, f= 1.0 MHz) Logic Inputs, EXTAL 6.5 10 A0-A15, R/W, VMA Cout 12 *in power-down mode, maximum power dissipation is less than 42 mW. #Capacitances are periodically sampled rather than 100% tested. CONTROL TIMING (Vcc=5.0 V +5%, Vsg =0, Ta=TL to Ty), unless otherwise noted) oo MC6802 MC&8A02 MC68B02 , Characteristic Symbol ~ ~ Unit Min Max Min Max Min Max Frequency of Operation fo 0,1 1.0 0.1 1.5 0.1 2.0 MHz Crystal Frequency IXTAL 1.0 4.0 1.0 6.0 1.0 8.0 MHz External Oscillator Frequency 4xfy 0.4 4.0 0.4 6.0 0.4 8.0 MHz Crystal Oscillator Start Up Time tre 100 _ 100 _ 100 _ ms Processor Controls (HALT, MR, RE, RESET, RG NMI) Processor Control Setup Time tpcs 200 _ 140 _ 110 _ ns Processor Controi Rise_and Fall Time tpcr. (Does Not Apply to RESET} tec 100 _ 100 100 MOTOROLA MICROPROCESSOR DATA 3-258MC6802 BUS TIMING CHARACTERISTICS Ident. . MC6802 MC68A02 MC68H02 Number Characteristic Symbol Min Max Min Max Min Max Unit 1 Cycle Time teye 1.0 10 | 0.667) 10 0.5 10 Bs 2 Pulse Width, E Low PWe_ | 450 | 5000 | 280 | SQQ0 | 210 | 5000 ns 3 Pulse Width, E High PWeH | 450 | 9500 | 280 | 9700 | 220 | 9700 ns 4 Clock Rise and Fall Time tr, tf _ 25 _ 25 _ 25 ns 9 Address Hold Time* tAH 20 _ 20 _ 20 ns 12 Non-Muxed Address Valid Time to E (see Note 4) | tayi 160 _ 100 _ 50 ns tayv2 _ 270 _ _ _ _ 17 Read Data Setup Time toSR 100 - 70 _ 60 _ ns 18 Read Data Hold Time tOHR 10 _ 10 _ 10 _ ns 19 Write Data Delay Time toow _ 225 _ 170 _ 160 ns 21 Write Data Hold Time* toHWw 30 _ 20 _ 20 _ ns 29 Usable Access Time (see Note 4) tacc | 535 335 _ 235 _ ns *Address and data hold times are periodicaily tested rather than 100% tested. R/W, Address {Non-Muxed) Read Data Non-Muxed Write Data Non-Muxed NOTES: 1. Voltage levels shown are V_<0.4 V, V}4=2.4 V, unless otherwise specified. FIGURE 2 - BUS TIMING 12 MPU Read Oata Non Muxed 29 . Measurement points shown are 0.8 V and 2.0 V, unless otherwise noted. 2 3. Usable access time is computed by: 12+3+4-17. 4. If programs are not executed from an-board RA RAM, TAV2 applies. For normal data storage in t executed fram on-board RAM when using A and with all parts. 5. All electrical and contrai characteristics are referenced from: TL =0C minimum and Ty =70C maximum. MOTOROLA MICROPROCESSOR DATA M, TAV1 applies. .o7c0 If programs are to be stored and executed from on-board he on-board RAM, this extended delay does not apply. Programs cannot be B parts (MC68A02, MC68B802). On-board RAM can be used for data storageMC6802 FIGURE 3 BUS TIMING TEST LOAD 4.75 V Ay = 2.2 kO C= 130 pF for 00-07, __ Test Point MM Fao = 90 pF for AO-A15, B/W, and VMA =O pF for BA Cc R R=11.7kQ for 00-07, MMD7000 = 16 kQ for AO-A15, R/W, and VMA or Equiv. = 24 kO for BA FIGURE 4 TYPICAL DATA BUS OUTPUT DELAY versus CAPACITIVE LOADING 600 Igk 2-205 pA max @24V lol = 16mA max BO04V Veco+50V Ta=28C 500 400 300 DELAY TIME (as} DELAY TIME ins) 200 FIGURE 5 TYPICAL READ/WRITE, VMA AND ADDRESS OUTPUT DELAY versus CAPACITIVE LOADING 600 1OH =-145 pA max @24V loL = 16 mA max@Odv Veco =S0V Ta = 29C 500 400 Address VMA 300 200 400 100 0 CL includes Stray capacitance Cy includes stray Capacitance Q 400 200 300 400 500 600 9 400 Cy, LOAD CAPACITANCE (pF) Ci, LOAD CAPACITANCE (pF) FIGURE 6 EXPANDED BLOCK DIAGRAM AIS Al4 A13 Al2 All AIO AQ AS A7 AB AS A4 AZ A2 AI AO Ourput Cutout Buffers Bufters 7 1 RAM i Contral <- RAM Enable I I (ToT | \ 32 Bytes E+ Vcc Standby - 1 1 Memory Ready > | % Bytes ; Enable |~- Ce TTT 4 RESET 4 Program Program Non-Maskabie Interrupt NMI} 3m Clock Counter H Counter, HALT ~ py Instrucnion Interrupt Request (IRQ) p4 Decode piace Stack an inte P EXTAL > Control a ot XTAL PY Index Index Bus Available ~~ Register |, Register Valid Memory Address - Read/Wnite (R/ Wi Accumulator LI : Instruction Accumulator Register 8 Condition Code Register al Voc =Pin 8 Data Yss=Pins 1, 21 Butter ALU peered ed 0? O06 OS D4 03 02 DI MOTOROLA MICROPROCESSOR DATA 3-260MC6802 MPU REGISTERS A general block diagram of the MC6802 is shown in Figure 1. As shown, the number and configuration of the registers are the same as for the MC6800. The 128 x 8- bit RAM* has been added to the basic MPU. The first 32 bytes can be retained during powerup and power- down conditions via the RE signal. The MPU has three 16-bit registers and three 38-bit registers available for use by the programmer (Figure 7). PROGRAM COUNTER The program conter is a two byte (16-bit) register that points to the current program address. STACK POINTER The stack pointer is a two byte register that contains the address of the next available location in an externa! pushdown/pop-up stack. This stack is normally a ran- dom access read/write memory that may have any lo- cation (address) that is convenient. in those applications that require storage of information in the stack when power is lost, the stack must be non-volatile. INDEX REGISTER The index register is a two byte register that is used to store data or a 16-bit memory address for the indexed mode of memory addressing. ACCUMULATORS The MPU contains two 8-bit accumulators that are used to hold operands and results from an arithmetic logic unit (ALU). CONDITION CODE REGISTER The condition code register indicates the results of an Arithmetic Logic Unit operation: Negative {N), Zero (Z), Overflow (V), Carry from bit 7 (C), and Half Carry from bit 3 (H). These bits of the Condition Code Register are used as testable conditions for the conditional branch instructions. Bit 4 is the interrupt mask bit (1). The un- used bits of the Condition Code Register {b6 and b7) are ones. Figure 8 shows the order of saving the microproces- sor status within the stack. *If programs are not executed from on-board RAM, TAV1 applies. If programs are to be stored and executed from on-board RAM, TAV2 applies. For normal data storage in the on-board RAM, this extended delay does nat apply. Programs cannot be executed from on-board RAM when using A and B parts (MC68A02 and MC68802). On-board RAM can be used for data storage with all parts. FIGURE 7 PROGRAMMING MODEL OF THE MICROPROCESSING UNIT ACCA Accumulator & ~ ~ 15 Oo Q 9 Ix index Register PC Program Counter oOL_ oO Stack Pointer ~ lo Canditian Cades Register | L Carry (From Sit 7) Overflow Zero Negative interrupt Half Carry (From it 3) MOTOROLA MICROPROCESSOR DATA 3-261~ MC6802 FIGURE 8 SAVING THE STATUS OF THE MICROPROCESSOR IN THE STACK SP = Stack Pointer CC = Candition Codes (Also called the Processor Status By ACCE = Accumulator B ACCA = Accumulator A IXH = tndex Register, Higher Order & Sits IXL * Index Register, Lower Order 8 Bits PCH = Program Counter, Higher Order 8 Bits PCL = Program Counter, Lower Order 8 Bits m-9 m - m - tel m-6 m- m-4 m-3 m-2 m-2 m1 m- 1 m m me mei m+ 2 m+2 | i : i \ i Before After MPU SIGNAL DESCRIPTION Proper operation of the MPU requires that certain control and timing signals be provided to accomplish specific func- uons and that other signal lines be monitored to determine the state of the processor. These control and uming signals are similar to those of the MC6800 except that TSC, DBE, $1, $2 input, and two unused pins have been eliminated, and the following signal and timing lines have been added: RAM Enable (RE) Crystal Connections EXTAL and XTAL Memory Ready (MR} Vcc Standby Enable 2 Output (E) The following is a summary of the MPU signals: ADDRESS BUS (A0-A15) Sixteen pins are used for the address bus. The outputs are capable of driving one standard TTL load and 90 pF. These lines do not have three-state capability DATA BUS (00-D7) Eight pins are used for the data bus It is bidirectional, transferring data to and from the memory and peripheral devices. It also has three-state output buffers capable of driving one standard TTL toad and 130 pF. Data bus will be in the output mode when the internal RAM 1s accessed and RE will be high. This prohibits external data entering the MPU it should be noted that the internal RAM 1s fully decoded from $0000 to $007F. External RAM at $0000 to $007F must be disabled when internal RAM is ac- cessed. HALT When this input is in the low state, all activity in the machine will be halted. This input 1s level Sensitive. In the HALT mode, the machine will stop at the end of an instruc- tion, bus available will be at a high state, valid memory ad- dress will be at a low state. The address bus will display the address of the next instruction. To ensure single instruction operation, transition of the HALT line must occur tpcs before the rising edge of E and the HALT line must go high for one clock cycle. HALT should be wed high if not used. This is good engineering design practice in general and necessary to en- sure proper operation of the part. READ/WRITE (R/W) This TTL-compatble output signals the peripherals and memory devices whether the MPU is in a read (high! or write (low) state. The normal standby state of this signal 1s read (high). When the processor 's halted, it will be in the read state. This output is capable of driving one standard TTL load and 90 pF. VALID MEMORY ADDRESS (VMA) This output indicates to peripheral devices that there ts a valid address on the address bus. In normal operation, this signal should be utlized for enabling peripheral interfaces such as the PIA and ACIA. This signal is not three-state One standard TTL load and 90 pF may be directly driven by this active high signal. BUS AVAILABLE (BA) The bus available signal will nor- matly be in the low state, when activated, it will go to the high state indicating that the microprocessor has stopped and that the address bus is available (but not in a three-state condition). This will occur if the HALT line is in the low state or the processor is in the WAIT state as a result of the execu- uon of a WAIT instruction At such time, all three-state out- put drivers will go to their off-stare and other outputs to their normally inactive level The processor is removed from the MOTOROLA MICROPROCESSOR DATA 3-262MC6802 WAIT state by the occurrence of a maskable (mask bit | =0) tion of a routine to intualize the processor from its reset con- or nonmaskable interrupt This output 1s capable of driving dition All the higher order address lines wil be forced high one standard TTL load and 30 pF For the restart, the last two (SFFFE, SFFFF) locanons in __ memory will be used to load the program that is addressed INTERRUPT REQUEST (IRQ) by the program counter. Dunng the restart routine, the inter- A low level on this input requests that an interrupt se- rupt mask bit is set and musi be reset before the MPU can be quence be generated within the machine The processor will interrupted by IRQ. Power-up and reset timing and power- wait untl it completes the current instruction that ts being down sequences are shown in Figures 9 and 10, respecuvely axcuted before it recognizes the request At that ume, if the RESET, when brought law, must be held iow at least three interrupt mask bit in the condition code register 1s not set, clock cycles This allows adequate time to respond internally the machine will begin an interrupt sequence. The index to the reset This is independent of the trc power-up reset register, program counter, accumulators, and condition that 1s required code register are stored away on the stack Next the MPU When RESET ts released 11 must go through the low-to- will respond to the interrupt request by setting the interrupt high threshold wihout bouncing, oscillating, of otherwise mask bit high so that no further interrupts may occur At the Causing an erroneous reset (less than three clock cycles) end of the cycle, a 16-bit vectaring address which s located This may cause improper MPU operation untl the next valid in memory locations $FFF8 and $FFF9 1s loaded which reset causes the MPU to branch to an interrupt routine in memory __ Tne HALT line must be in the high state for interrupts to NON-MASKABLE INTERRUPT (NMI) be serviced. Interrupts will be latched internally while HALT A low-going edge on this input requests that a non- Is low maskabie interrupt sequence be generated within the oro- A norninal 3 kQ pullup resistor to Vcc should be used for cessor As with the interrupt request signal, the processor wire-OR and optimum control of interrupts 1RQ may be ted will complete the current instruction that 1s being executed directly to Vcc if not used before it recognizes the NMI signal The interrupt mask bit in the condition code register has no effect on NMI RESET The index register, program counter, accumulators, and This input is used to reset and start the MPU from a condition code registers are stored away on the stack At the power-down condition, resulting from a power failure or an end of the cycie, a 16-bit vectoring address which 1s located Initial start-up of the processor When this line 's low, the in memory locations $FFFC and SFFFO is loaded causing the MPU is inactive and the information in the registers will be MPU to branch to an interrupt service routine in memory lost. If a high Jevel is detected on the input, this will signal A nominal 3 pullup resistor to Cc should be used for the MPU to begin the restart sequence This will start execu- wire-OR and optimum contro! of interrupts NMI may de ted FIGURE 9 POWER-UP AND RESET TIMING an) jus _ 475V mn Vcc -_t LJ bee IPCS re + - Vin RESET vit Option 1 (See Note Below! to > RESET i Opuon 2 (See Figure 10 for Power-dawn Condition) RE Le tees (Rr NOTE If aptian 1 1s chosen, RESET and RE pins can be ved together MOTOROLA MICROPROCESSOR DATA 3-263Do ay MC6802 directly to Vcc if not used Inputs IRQ and NMI are hardware interrupt lines that are sampled when ts high and will start the interrupt routine on a low E following the compieuon of an instruction. Figure 11 1S a flowchart describing the major decision paths and interrupt vectors of the microprocessor Table 1 gives the memory map for interrupt vectors TABLE 1 MEMORY MAP FOR INTERRUPT VECTORS Vector Description MS Ls SFFFE SFFFF Restart SFFFC SFFFD Non-Maskable Interrupt SFFFA | SFFFB Software Interrupt SFFFS SFFF9 Interrupt Request Vcc RE FIGURE 11 MPU FLOWCHART Start Sequence SFFFE, $FFFF Machine on Halt FIGURE 10 POWER-DOWN SEQUENCE a. KA 78 ne bet-3 Cycles ig Y Y Fetch | Execute eten instruction Interrupt Routine v Execute j Instruction NMI TRO SFFFC SFFF8 SFFFO SFFF9 Y } MOTOROLA MICROPROCESSOR DATA 3-264MC6802 FIGURE 12 CRYSTAL SPECIFICATIONS Yi Cin Cout 3.58 MHz 27 oF 27 pF 4 MHz 27 pF 27 pF 8 38 6 MHz 20 pF 20 pF 1 cou7 Y T Cin 8 MHz 18 pF 18 pF Crystal Loading 10 TW v1 at See eae e_ co iZ W Nominal Crystal Pararneters* 3.58 MHz 4.0 MHz 6.0 MHz 8.0 MHz Rs 600 502 W-50 2 20-40 2 co 3.5 pF 6.5 pF 4-6 pF 4-6 pF C1 0.015 pF 0.025 pF 0.01-0 02 pF 0.01-0.02 pF Q > 40K > WK > 20K > 20K *These are representative AT-cut parallel resonance crystal parameters only Crystals of ather types of cuts may also be used. Figura 13 SUGGESTED PC BOARD LAYOUT Example of Board Design Using the Crystal Oscillator ft mm max 4 woo Signals are Not Wired in this Area 77 LL CL Wi. rysta cL 3 E Signal is Wired Apart from 38 Pin 34 and 39 Pin 37 m \ 20 mm max > MOTOROLA MICROPROCESSOR DATA accMC6802 FIGURE 14 MEMORY READY SYNCHRONIZATION 4xty Oscillator EXTAL XTAL ni @ MC6802 MR Qa 4 Memory Ready Of Generated from CSaLogic SN74LS74 FIGURE 15 MR NEGATIVE SETUP TIME REQUIREMENT E Clock Stretch -IPCS rtPCS + 0.8 V O08V The E clock will be stretched at end of E high of the cycle during which MA negative meets the tpcs setup ume The tpcs setup time is referenced to the fail of E. If the tpcs setup time is not met, E will be stretched at the end of the next E-high 4 cycle E will be stretched in in- tegral multiples of A cycles Resuming E Clocking fe tiecs He ttecs he tiecs et tec I T | | Stretched E I \ | " Ul! The E clock will resume normal operauon at the end of the % cycle during which MA asseruon meets the tpcs setup time The tpcs setup time IS referenced to transitians of E were it not stretched If PCS setup time is not met, E will fall at the second possible transition time after MR is asserted There is no direct means of determining when the tpcs references accur, unless the synchronizing circuit of Figure 14 1s used MOTOROLA MICROPROCESSOR DATA 3-266MC6802 RAM ENABLE (RE) A TTL-compatible RAM enable input controls the on- chip RAM of the MC6802. When placed in the high state, the on-chip memory is enabled to respond to the MPU controls. In the low state, RAM is disabled. This pin may also be utilized to disable reading and writing the on- chip RAM during a powerdown situation. RAM Enable must be low three cycles before Vcc goes below 4.75 V during powerdown. RE should be tied to the correct high or low state if not used. EXTAL AND XTAL These inputs are used far the internal oscillator that may be crystal controlled. These connections are for a parallel resonant fundamental crystal (see Figure 12) ({AT-cut) A divide-by-four circuit has been added so a 4 MHz crystal may be used in lieu of a 1 MHz crystal for a more cost-effective system. An example of the crystal circurt layout 1s shown in Figure 13. Pin 39 may be driven externally by a TTL input signal four times the required E clock frequency Pin 38 1s to be grounded. An RC network is not directly usable as a frequency source on pins 38 and 39. An RC network type TTL or CMOS oscillator will work well as long as the TTL or CMOS output drives the on-chip oscillator. LC networks are not recommended to be used in place of the crystal If an external clock is used, it may not be halted for more than tpwoL. The MC6802 is a dynamic part except for the internal RAM, and requires the external clock to retain information. MEMORY READY (MR) MR 1s a TTL-compatible input signal controlling the stret- ching of . Use of MA requires synchronization with the 4xfg signal, as shown in Figure 14 When MR ts high, E will be in normal operation. When MR is low, E will be stretched in- tegral numbers of half periods, thus allowing interface to slow memories. Memory Ready timing 1s shown in Figure 15. MR should be tied high (connected directly to Vcc) !f not used. This is necessary to ensure proper operation of the part. A maximum stretch IS tcyc. ENABLE () This pin supphes the clock for the MPU and the rest of the system. This 1s a single-phase, TTL-compatible clock. This clock may be conditioned by a memory read signal. This 1s equivalent to #2 on the MC6800. This output is capable af driving one standard TTL load and 190 pF. Voc STANDBY This pin supplies the dc voltage to the first 32 bytes of RAM as well as the RAM Enable (RE) control logic. Thus, retention of data in this portion of the RAM on a power-up, power-down, or standby condition is guar- anteed. Maximum current drain at V$g maximum is IsBe- MPU INSTRUCTION SET The instruction set has 72 different instructions. Included are binary and decimal arithmetic, lagical, shift, rotate, load, store, canditional or unconditional branch, interrupt and stack manipulation instructions (Tables 2 through 6) The in- struction set is the same as that for the MC68C0. MPU ADDRESSING MODES There are seven address modes that can be used by a pro- grammer, with the addressing mode a function of both the type of instruction and the coding within the instruction A summary of the addressing modes far a particular instruction can be found in Table 7 along with the associated instruction execution time that 1s given in machine cycles. With a bus frequency of 1 MHz, these umes would be microseconds ACCUMULATOR (ACCX) ADDRESSING In accumulator only addressing, either accumulator A or accumulator 8 1s specified. These are one-byte instructions IMMEDIATE ADDRESSING In immediate addressing, the operand is contained In the second byte af the instruction except LDS and LDX which have the operand in the second and third bytes of the in- struction. The MPU addresses this lacation when it fetches the immediate instruction for execution. These are two- or three-byte instructions. DIRECT ADDRESSING In direct addressing, the address of the operand is contain- ed in the second byte of the instruction Oirect addressing allows the user to directly address the lowest 256 bytes in the machine, 1 e., locations zero through 255. Enhanced execu- ulon umes are achieved by storing data in these locations. In most configurations, it should be a random-access memory. These are two-byte instructions. EXTENDED ADDRESSING In extended addressing, the address contained in the se- cond byte of the instruction ts used as the higher eight bits of the address of the operand. The third byte of the instruction 1s used as the lower erght bits of the address for the operand. This 1s an absolute address in memory. These are three-byte INSTFUCTIONS. INDEXED ADDRESSING In indexed addressing, the address contained in the se- cond byte af the instruction is added to the index register's lowest eight bits in the MPU. The carry is then added to the higher order etght dits of the index register. This result 1s then used to address memory The modified address is held in a temporary address register so there is no change to the index register These are two-byte instructions. MOTOROLA MICROPROCESSOR DATA 3-267MC6802 IMPLIED ADDRESSING byte of the instruction 1s added to the program counters in the implied addressing mode, the instruction gives the lowest eight bits plus two. The carry or borrow is then added address (i.e., stack pointer, index register, etc.). These are to the high eight bits. This allaws the user to address data one-byte instructions. within a range of 125 to + 129 bytes of the present instruc- tion. These are two-byte instructions. RELATIVE ADDRESSING In relative addressing, the address contained in the second TABLE 2 MICROPROCESSOR INSTRUCTION SET ALPHABETIC SEQUENCE ABA Add Accumulators CLR Clear PUL Pull Data ADC Add with Carry CLY Clear Overflow ROL Rotate Lett ADO Add CMP Compare ROR Rotate Right AND Logical And COM Complement ATI Return from Interrupt ASL Anthmetic Shit Left CPX Compare Index Register . RATS Return from Subroutine ASA Arithmetic Shit Right DAA Decimal Adjust SBA Subtract Accumulator Bcc Branch if Carry Clear DEC Decrement sBc Subtract with C BCS Branch it Carry Set DES. Decrement Stack Pointer SEC Set Car wn Varry > BEQ Branch f Equal to Zero DEX Decrement Index Register ry BGE Branch if Greater or Equal Z SE! Set Interrupt Mask ) qua <ero FOR Exclusive OR SEV _ Set Overflow BGT Branch @ Greater than Zero STA St A | BHI Branch if Higher INC Increment ore Accumulator : STS Store Stack Register BIT Bit Test INS Increment Stack Pointer STX Store Index Register BLE Branch if Less or Equal INX Increment index Register = Su Subtract BLS Sranch if Lower or Same Swi Soft BLT Branch it Less than Zero JMP Jump oftware Interrupt BMI Branch if Minus JSR dump to Subroutine TAB Transter Accumutators BNE Branch it Nat Equal to Zero LDA Load Accumulator TAP Transfer Accumulators to Condition Code Reg BPL Branch if Plus LOS Load Stack Pointer TBA Transter Accumulators BRA Branch Always LDX Load Index Register TPA Transfer Condition Code Reg. to Accumulator BSR Sranch to Subroutine LSR Logical Shift Right TST Test BVC Branch it Overtiow Ciear NEG Negate TSX Transfer Stack Pointer to Index Register BVS Branch if Overflow Set NOP No Operation TXS Transter Index Register to Stack Pointer CBA Compare Accumulators ORA Inclusive OR Accumulator wal Wait for Interrupt CLe Clear Carry cul Clear Interrupt Mask PSH Push Data MOTOROLA MICROPROCESSOR DATA 3-268MC6802 TABLE 3 ACCUMULATOR AND MEMORY INSTRUCTIONS AQOAESSING MOOES BOGLEAN/AAITHMETIC OPERATION CONO COOE AEG IMME OIRECT INDEX EXTNO IMPLIED LAN ergttor tobels Si[(iiziife OPERATIONS mnemonic] op ~ =/oe ~ =|ar ~ =|or ~ sor ~ = cater te contents) my rpmyzyyye Add AOODA sa2 2; 98 J 2/48 S$ 2/88 4&4 J AM -A treiritpihe acoa cB 2 =62<40B 3 627 ee 8 2) Fa A] Bem +8 theyryrpsde Add Acmitirs ABA 1 2 i Ard ca ppepryrp eit Add wih Carty AQCA eg 2 2/399 3 2/A9 $ 2) 89 4 3 A>M->C -& treyrpipedt . acce co 2 27/09 3 2)9 S$ 2] F9 4 2 BeM+C -8 treltyipeye And ANOA a4 2 2194 3 2] sa 8 2) BA 4 3 AM -Aa ejelt| tyre ANOB ca 2 2) 04 3 2) 6&4 5 @PFe & 3 a:m -a8 @periy clAle Gar Tess BITA a6 2 2198 3 214s 5 71865 4& J AcoM wfeliitiyase BiTe ch 2 2405 3 2ykS S B@LFS 4 3 a-M elestitiale Cleae CLR 6F 7 2) 7F 6 3 ag -M e{eojals;Ala CLRA 4-2 1 aq A @y;e(;A;s| aja CURE seo2 1 | OO 8 e@peyays| aya Camoare CMPa gr 2 2] 3t 2 2@fatr $s 2) ar 4 3 A-M e@lerritpedt CMPB ct 2 2; or F 2pet & 2, Fr 4 J 3 0M epelrirpiyt Cammpare Acmitrs CBA woz A 4@ ereliiiytyt Complement Is com $1 7? 2/73 6 3 Mc elealii lias COMA 43 2 Tt ahca elerci tials come $3 2 1 | 6-8 epelr pcp as Compiement 2's NEG so 7 2/70 6 4 oo M MW efel IO INegate? NEGA 40 2 1 | oo AA efel HO NEGB 502 1 | 08 8-8 ef el iM Decimal Adjust A OAA go62 C+ Caaverts Senary Add of BCD Characters | Of eo] {| t} D> ta BCD Farmat Oecrement oec 6A 7 2,74 6 FY Mo o1cM ejel: Oo e OeCA 4a 2 1) A 1A alelt):G@e oecB SA 2 1] e-1 -8 elelritGye Excluswe OR ERA g8o2 62/98 63 24 aa S$ 2] BB ls BS AQM -A ejeliitjaye EORB cs 2 2,|08 3 2) &8 S$ 2] Fe & J 8M -9 eject ty ale Increment INC 6c 7 2) 70 & YF Mel -M elelili Gye INCA aC 2 Fy] wet od elelritge INCB gc 2 2] Bet cg efetritGe Load Acmitr LOAA ag 2 2196 3 2] a6 S 2186 4 27 MA ele!) fr} Ris LOAB cs 20 2/06 3 2) 6 & 21 FE & J M8 efeltitiale O+ Inclusive ORAA 8A 2 7} 9A 3 2] AA 4 718A 4 3 AM -A e@jelr tT Rte ORAg CA 2 2L10A 3 21/&A & TFZIFA 4 3 Bem +3 @leolliti Rie Push Data PSHA i 4 1 A -Mgp SPT SP elelel alee PSHB 7040 oN | BO Mgp SPOT SP elefelelele Pull Qara PULA W204 ~~Ct SP +1 -SP Msp -A elelele/ ele PULa 3304 01 SP > 1 -SP Mcp 4 elaleleleles Aatate Lett Rot 8 7? 2)79 6 3 M efelt igi ROLA 4924 *} Co gaa elelt ii Gli ROLE s9 2 ti] 4 c b7 ~ 00 elorritage Rotate Right ROR 66) 42/7 6 3 M efelr lig: AQAA 46201 | ST eee efelt) tieyt ROAB 56 2 ~1'4/ 8 c a7 80 ejerry 1G Shot Lett Acthmenc ASL 68 7 2/78 6 4 M _ efoirh og ASLA 48 2 T]a Q- aqom-o efelriti@y: Agua soot 1d 8 c oT bo efels|tkgrt Shift Right, Aniamenc ASR 6 7 2) ar & 3 ) _ efol fay: cm a ASAA a7o20dL | ADMIT - a efeliy ras ASAB 67 2 1/8 b? bd On Shvit Aight Loge USA 64 7? 2] 74 6 3 _ eleial :Keyt (SRA 442 FL A 9-Cotom - a ofeoral iGye LSR8 sa2 tifa b? bo efelai tit Store Acinise STaa q7o4 62] ar 6B oO] BF OS 3 A cM e@eleltiilaje STAB o7 4 2/ 6 2) FF 3 acM esels[tiaje Subtract SuBA ga 2 2/90 3 2) 40 5 2/80 4 3 A MOA @lettirthaie suas cg 2 2)00 3 2) fo Ss 2; Fo 4 J &-M -8 eperryiy ryt Subtract Acmirs 38a lo 2 7 A 8 -s elepilcsdt Suatr woth Carry S8CA 82 2 2} 92 2 2] a2 4 TEB2 4 9 A M-C CA eyevit iy iy: sacs cz2 2 zg)a2 3 2)e&2 4 2] F2 4 2 8-M-C 6 eleripiy tts Transter Acmitry TaAg we 2 1 a8 ele/I/ttApe Taa wo? 4 B-a eye; [ii Rrte Test Zero o Minus TST 60 7? 2}70 3 M- 00 elelt] if ale TSTA 40 2 1 | A- Oe elerilt ala TSTe so 2 1 a - 00 ejpeyiy ip Rysa MPL 2 vie LEGENO- CONOITION CODE SYMBOLS OP = Operatian Cade (Hexadecimal) Baalean inctusve OF ~ Number af MPY Cycles Q Boalean Exciunve OA 4 Malt carry trom bal J 2 Muinder ol Progeam Oy tes a Campiement of M ' ialerruat math , Asunmetic Plus, - Tramter Into N Negative (1gn Bil? - Antimetic Menus, 0 Git Zero, z Zero (byle) Boolean ANO 00 Bytn = Zero v Qvertlaw 2: complement Msp Contents of memary tocation gointed ta be Stach Poenter c Carey tram bet ? R Rewt Always Nole - Accumulater addressing mode sastructions we inctuded 19 the column tor IMPLIED addretung s Set Always : Teal and set st true cleared orterwise e Nat Atlected MOTOROLA MICROPROCESSOR DATA 3-269- 4 : MC6802 TABLE 4 INDEX REGISTER AND STACK MANIPULATION INSTRUCTIONS CONG. CODE REG. [men DIRECT INDEX EXTNO IMPLIED |4) 3 |2/1]90 POINTER ORERATIONS MNEMONIC; OP} ~| =; OP) ~| =} OP) ~} =| OP; ~ | =| OP, ~ |] = BOOLEAN/ARITHMETIC OPERATION | Hit; NIZ/ VIC Compare index Heg CPx aci}3] 3f9c|4a]2jacj6!/2zfaec)sj3 XH MXL- IMD o/s! : Qe Decrement index Reg QEX og] 4) X-1-X ele elilele Decrement Stack Pnir oes 3a, 441 SP 1 -+SP e\e; ejele;e Increment Index Aeg INX og; 4] Xo1 X ere ea; i ele tacrement Stack Pnitr INS wpa] SP +1 -SP ee ejelele Load Index Req LOX ce) 3} 3 /oe; 4] 2;eel se] 2]re}s | 3 Mo XyIM 1) XL ee@ tale Load Stack Pntr Los ge; 3} 3}9e} 4! 2taeis6|] 2]/ ee] 5/3 M -SPu. (Mel) = SPy : 0@]:\R\ Stare index Reg STX of) S|] 2];eF{ 7) 2] FF] 6} 3 Xo oMOXp cIMe tT 2) e@ i | Rie Store Stack Pris sts 9F1 5] 2}aF1 7] 2, BF1 613 SPy -M, SPL (Me 1) el el@l:| Rie anda Reg + Stack Pntr TXS | 36] 4 1 x 1 SP ee e;eieie Stack Pir > ind Aeg TSX ' | 3054 |) SP+1 -X eo elelele ~~ TABLE 5 JUMP AND BRANCH INSTRUCTIONS COND. COOE AEG. RELATIVE INDEX EXTND IMPLIED S$} 4] 3] 2) 1] 6 OPERATIONS MNEMONIC OP; ~ | =/OP; ~| =| or; ~{ =|; OF) ~ | = SRANCH TEST Hj) dp Nw] zywyie Branch Always BRA 20] 4 42 None e;@e/e;e!;le|le Branch It Carry Clear Bcc 24] 442 C=0 e}|e|/e/ejele Branch If Carry Set BCS 25/4 | 2 Cz) e) e|e;)elel/e Branch If = Zero BEG 27,442 z*} , ele] elele Branch If > Zero BGE 20], 4 2 N@vV=0 @; o!|e/ ee] ale Branch if > Zero 6GT 2E1 48 [| 2 Z+(N@V)=0 o|e]e; eo] ele Branch It Higher BHI 22) 4 | 2 C+Z=0 | e@e/]e; ee) eje Branch If Zero BLE 2F i 4] 2 Z+(IN@vel el elel el ele Sranch If Lower Or Sarme BLS 23) 4 | 2 C+221 . | oe; ee} oe) ele Bcanch If < Zero BLT 20; 4} 2 N@vel o| e|e| | ele Branch It Minus BMI 28 | 4 | 2 N=] *#, ee); e!}elete Branch If Not Equal Zero BNE 26/4 4 2 Z=0 o|/ @efelelej;e Branch If Overttow Clear 8VC 28; 432 veo ele; e, ej, e;e Branch tt Overtlow Set BYS 29; 4/2 vel @;, ofa! e!lefe Branch It Plus Bet 2A] 4 | 2 N=0 el elel| ej ele Branch To Sudsoutine BSR 30; 8 | 2 el elele|ele Jump JMP 6E| 4; 2] 76] 3] 3 See Special Ooerations el ej] oe} ee} ele Jump Ta Subroutine JSR Ao| 8 | 2] 80) 9) 3 (Figure 16) o| e' eo) | ele No Operation nop or} 241 Advances Prog Cntr Only ole e| | e|e Return From Interrupt ATI 36} 10} 1 10; Return From Subroutme ATS 39 } ole | eo; e| ele Software Interrupt Swi SFL t2 41 See Special Operations @|e,e|ele/;e Wart tor Interrupt WA) 3 1 (Figure 16) @| ej elele a MOTOROLA MICROPROCESSOR DATA 3-270SPECIAL OPERATIONS JSA, JUMP TO SUBROUTINE: MC6802 FIGURE 16 SPECIAL OPERATIONS PC _ Main Program SP Stack PC Subroutine a AD: JSA SP-? NX + K Tat Subs Instr INOXO ned | K2 Ofteer* c> gp-1 | lae2i x n+? | Next Main instr. sp fj ine2le *K = 8-Bit Unsigned Value [n+ 2] y and [a 2 Formas 2 pc __Main Program SP Stack PC Subeoutine n { BO= JSR SP-2 S | tse Suar Inser n+t | SH Sube Adde - H EXTNO ae2 | SL =Sube Adds > oe ate ~ SP Line dit (S Formed From Sy and Sy) a+3 | Next Main Instr = Stack Pointer Alter Execution BSR, BRANCH TO SUBROUTINE PC Main Program $e Stack PE Subroutine mn | 80 = 8SR $P-2 ore Ist Subr Instr a+ | 2 K= Oftser > sp-i | Ine 2) 4 n+2 Next Main Instr SP {ne 2] eb *K = 7 Bor Signed Value, n+ 2 Farmed From [a+ 21 y and [n> eh JMP, JUMP: PC Main Pragram PC Main Program n | GE = IMP fn 7 = IMP not | Ks Offser nod [Ry 2 Next Address INOXO : EXTENDED w+? [Ky = Neat Adaress K RTS, RETURN FROM SUBROUTINE. PC Subrounne SP Stack PC Main Program | 39+ ATS c> sP Next Main instr SP +1 Ny sPe2{ Ny ATI, RETURN FROM INTERRUPT. pC _Interrunt Program 5p Stack Pc Main Program S 3B: ATI > SP a Neat Main Instr gp ed Condition Code SP +2 Acmitt 8 SP +3 Acmltr A SP ed Index Reqster [XH) SP + Index Register (X 1) SP +6 PCy SP+7 PEL TABLE 6 CONDITION CODE REGISTER MANIPULATION INSTRUCTIONS CONGO COOE REG. imPLieg $y, 4} 14244} a OPERATIONS mnemonic [or | ~ | =| SOOLEAN OPERATION | H pinizi{vic Clear Carry cue oc; 2) 4 qa-c e; | elele'aA Clear Interrupt Mask Cl oe; 2] 5 Ot e/a eleleie Clear Overtlow clv OA; 2] 1 o-Vv ele | ele;|A;e@ Set Carry Sec oo; 24) 1- e ep ejejels Set Interrugt Mask Set or} 2] 1-l ei sjelele | e Set Overitow SEV 08} 2]! lev eleleleisle Acmite A -CCR TAP 06 | 2 1 A -CCR oo COR ~Acmitr A TPA or {2 [1 cca -A slelerele! . CONDITION CODE REGISTER NOTES. (Bit sets) test 1s true and cteared arherwise) (Qe V) = Test Result + 100000007 7 (Bot N) Test Sige bet of most signiticant (MS) byte = 17 (Git Cl Test Aesult # 000000007 8 (But V) Test 2s complement overtlow fram subtraction of MS bytes? (Bie C) Test, Gecmal value of most signiticant CO Character greater than nine? g (Bit N) Test Aesult less than cera? (Bet t4 = (Not cleared +! previgusly set} 10. (AN Load Condition Code Register Iram Stack (See Special Operations) (BV) Test Operand = [0000000 prior to execution? WW (Qu I) Set when interruat occurs. if previously set, a Nan Maskable (Bit V) Test Operand = QUITIIET priors to execution? Intersupt required lo exit the vail state (Bet V) Test Set equat to result af NGC alter shitt nas occucred 12 (AN) Set according ta (he contents of Accumulator A MOTOROLA MICROPROCESSOR DATA 3-271\ e MC6802 TABLE 7 INSTRUCTION ADDRESSING MODES AND ASSOCIATED EXECUTION TIMES (Times in Machine Cycie) Padus) pexaput papuaxg yang aeipawuy| xI3V (Ppursedg jeng) aanelay pajdwy paxapuy pepuaixg bag slerpaurnsy KOOV {(puesedo eng) INC INS INX JMP JSA LOA LDS LDX LSR NEG NOP ORA PSH PUL ABA ADC ACO ANO ASL ASR BCC BCS BEA BGE BGT BH BIT x x AOL ROR ATI ATS SBA BLE BLS BLT BMI BNE BPL BRA 8SR BvC BYS x SBC SEC SE! SEV STA STS STX CBA CLC CL! CLR CLY x SUB SWI TAB CMP x TAP TBA TPA TST TSX TSX WAI COM CPx OAA DEC DES DEX EOR ine x Interrupt tume 1s 12 cyctes from the end of NOTE the instruction being executed, except following a WAL instruction Then itis 4 cycies MOTOROLA MICROPROCESSOR DATA 3-272MC6802 SUMMARY OF CYCLE-BY-CYCLE OPERATION Table 8 provides a detailed description of the information present on the address bus, data bus, valid memory address line (VMA), and the read/write line (R/W) during each cycle for each instruction This information is useful in comparing actual with ex- pected results during debug of both software and hardware as the control program is executed The information is categorized in groups according to addressing modes and number of cycles per instruction. (In general, instructions with the same addressing mode and number of cycles ex- ecute in the same manner; exceptions are indicated in the table.) TABLE 8 OPERATIONS SUMMARY Address Made Cycle | VMA RIW and Instructions Cycles = Line Address Bus Line Data Sus IMMEDIATE AOC EOR 1 1 Op Code Address 1 Op Cade ts One 2 2 1 Op Code Address + 1 1 Operand Data BIT sac CMP SUB CPX 1 1 Op Code Address 1 Op Code tbe 3 1 Op Cade Address + 1 1 Operand Oata (High Order Byte) 1 Op Cade Address + 2 1 Operand Oata (Low Order Byte) OIRECT ADC EOR 1 1 Op Code Address j Op Code AND Ona 3 2 1 | Op Code Address + 1 1 | Address of Operand BIT ssc 3 1 Address of Operand 1 Operand Oata CMP SUB CPX 1 1 Op Code Address 1 Op Code tox 4 2 1 Op Code Address + 1 1 Address of Operand 3 1 Adaress of Operand 1 Operand Data (High Order Byte) 4 1 Operand Address + 1 1 Operand Data {Low Order Byte} STA 1 1 Op Cade Address 1 Op Code 4 2 1 Op Code Address + 1 1 Oestinatian Address 3 0 Destination Address 1 Irrelevant Oata (Note 1) 4 1 Destination Address 0 Data from Accumulator STS 1 1 Op Code Address 1 Op Code STX 2 1 Op Code Address + 1 1 Address of Operand 5 3 0 Address af Operand 1 irrelevant Oata (Note 1) 4 1 Address of Operand 0 Register Oata (High Order Byte) 5 1 Address of Operand +1 Q Register Cata (Low Order Byte) INDEXED JMP 1 1 Op Code Address 1 Op Code 4 2 1 Op Code Address * 1 1 Offset 34 0 Index Register 1 Irrelevant Data (Note 1} 4 Qa Index Register Plus Offser (w/a Carry} 1 Irrelevant Data (Note 1} Aogc EOR 1 1 Oo Code Address 1 Op Code ts Ona 2 1 Op Code Address + 1 1 Offset siT ssc 5 3 0 Index Register 1 Irrelevant Data (Note 1) CMP SUB 4 0 Index Register Plus Offset (w/o Carry) 1 Irrelevant Data (Nate 1) 5 1 Index Register Plus Offset 1 Operand Oata CPX 1 1 Op Cade Address 1 Op Code tox 2 1 Op Code Address + 1 1 Offset 6 3 Q Index Register 1 Irrelevant Oata {Note 1) 4 0 Index Register Plus Offset (w/o Carry) 1 trrelevant Oata (Note 1) 5 1 Index Register Plus Offset 1 Operand Data (High Order Syte) 6 1 Index Register Ptus Offset + 1 1 Operand Oata {Low Order Byte} MOTOROLA MICROPROCESSOR DATA 3-273MC6802 TABLE 8 OPERATIONS SUMMARY (CONTINUED) Address Mode Cycte |VMA R/W and Instructions Cycles # Line Address Bus Line Data Bus INDEXED (Continued) STA 1 1 Op Code Address 1 Op Code 2 1 Op Cade Address + 1 1 Offset 6 3 0 index Register 1 Irrelevant Oata (Note 1) 4 Q Index Register Plus Offset (w/o Carry) 1 Irrelevant Data (Note 1) 5 0 Index Register Pius Offset 1 Irrelevant Data (Note 1) 6 1 Index Register Plus Offset 0 Operand Data ASL LSR 1 1 Op Code Address 1 Op Code asa Noe 2 1 Op Code Address + 1 1 Offset com AOR 7 3 0 Index Register 1 irrelevant Data (Note 1} INC 4 0 Index Register Plus Offset (w/o Carry) 1 Irrelevant Data (Note 1) 5 : tndex Register Plus Offset 1 Current Operand Data 6 0 Index Register Plus Offset 1 Irrelevant Data (Note 1) 7 1/0 Index Register Plus Offset a New Operand Data (Note 3) (Note 3} STS 1 1 Op Code Address 1 Op Code STX 2 1 Op Cade Address + 1 1 Offset ? 3 0 Index Register 1 Irrelevant Oata (Note 1) 4 0 index Register Plus Offset (w/o Carry) 1 Irrelevant Data (Note 1) 5 0 Index Register Plus Offset 1 Irrelevant Data (Note 1) 6 1 Index Register Plus Offset 0 Operand Data (High Order 8yte) 7 1 Index Register Plus Offset + 1 Q Operand Data [Low Order Byte) JSR 1 1 Op Cade Address 1 Op Code 2 1 Op Code Address + 1 1 Offset 3 0 Index Register 1 Irrelevant Data (Note 1) 8 4 1 Stack Pointer 0 Return Address (Low Order Byte) 5 1 Stack Pointer 1 0 Return Address (High Order Byte) 6 0 Stack Pointer 2 1 irrelevant Data (Note 1) 7 0 Index Register 1 Irrelevant Data (Nate 1) 8 0 Index Register Plus Offset (w/o Carry) 1 irrelevant Data (Note 1) EXTENDED JMP 1 1 Op Code Address 1 Op Code 3 2 1 Op Code Address + 1 1 Jump Address {High Order Byte) 3 1 Op Code Address + 2 1 Jump Address (Low Order Byte) AOC EOR 1 1 Op Cade Address 1 Op Code AND Onn 4 2 1 Op Code Address + 1 1 Address of Operand (High Order Byte) BIT sBC 3 4 Op Code Address + 2 1 Address of Operand (Low Order Byte) CMP SUB 4 1 Address ot Operand 1 Operand Data CPX 1 1 Op Code Address 1 Op Code OE 2 1 Op Code Address + 1 1 Address of Qperand (High Order Byte) 5 3 1 Op Code Address + 2 1 Address of Operand (Low Order Ayte} 4 1 Address of Operand 1 Operand Data (High Order Byte) 5 1 Address of Operand + 1 1 Operand Data (Low Order Syte) STA A 1 1 Op Code Address 1 Op Code STAB 2 1 Op Code Address + 1 1 Destination Address (High Order Syte) 5 3 1 Op Cade Address + 2 1 Destination Address (Low Order Byte) 4 0 Operand Destination Address 1 Irrelevant Data (Note 1) 5 1 Operand Destination Address 0 Data from Accumulator ASL LSA 1 1 Op Code Address 1 Op Code ASA NEG CLR ROL 2 1: Op Code Address + 1 1 Address of Operand (High Order Byte) bee non 6 3 1 Op Code Addrass + 2 1 Address of Operand (Low Order Byte) INC 4 1 Address of Operand 1 Current Operand Data 5 0 Address of Operand 1 Irrelevant Data (Note 1) 6 1/0 Address of Operand Q New Operand Data (Note 3) incre MOTOROLA MICROPROCESSOR DATA 3-274TABLE 8 OPERATIONS SUMMARY (CONTINUED) MC6802 Address Mode Cycle | VMA RAV and Instructions Cycles i Line Address Bus Line Data Bus EXTENDED (Continued) STS 1 1 Op Code Addrass 1 Op Code STX 2 1 Op Code Address + 1 1 Address of Operand {High Order Byte) 6 3 1 Op Code Address + 2 1 Address of Operand (Low Order Byte) 4 a Address af Operand 1 leralevant Data (Nate 1) 5 1 Address of Operand Q Operand Data (High Order Byte) 6 1 Address of Operand + 1 Q Operand Data (Low Order Byta) JSR 1 1 Op Code Address 1 Op Code 2 1 Op Code Address + 1 1 Address of Subroutine (High Order Syte) 3 1 Op Code Address + 2 1 Address of Subroutine (Low Order Byte) 4 1 Subroutine Starting Address 1 Op Code of Next Instruction 9 5 1 Stack Pointer Q Return Address (Low Order Syte) 6 1 Stack Pointer 1 0 Return Address (High Order Byte) 7 0 Stack Pointer - 2 1 trrelevant Data (Note 1) 8 0 Op Code Address + 2 1 Irrelevant Data (Nore 1) 9 1 Op Code Address + 2 1 Address af Subroutine [Low Order Byte} INHERENT ABA DAA SEC 1 3 Op Code Address 1 Op Code ASL DEC SEI 2 ASR INC SEV 2 1 Op Code Address + 1 1 Op Cade of Next Instruction CBA LtSR TAB CLC NEG TAP CLI NOP TBA CLR ROL TPA CLV ROR TST COM SBA OES 1 1 Op Cade Address 1 Op Code oe 4 2 1 Op Code Address + 1 1 Op Code of Next Instruction INX 3 0 Previous Register Contents 1 Irrelevant Oata (Nore 1) 4 0 New Register Contents 1 Irrelevant Data (Note 1) PSH 1 1 Op Code Address 1 Op Code 4 2 1 Op Code Address + 1 1 Op Cade of Next Instruction 3 1 Stack Pointer 0 Accumulator Data 4 Q Stack Pointer 1 1 Accumulator Data PUL 1 1 Op Code Address 1 Op Code 4 2 1 Op Cade Address + 1 1 Op Cade of Next Instruction 3 0 Stack Pointer 1 Irrelevant Data {Note 1} 4 1 Stack Pointer + 1 1 Operand Data from Stack TSX 1 1 Op Code Address 1 Op Code 4 2 1 Op Code Address + 1 1 Op Code of Next Instruction 3.,| 0 Srack Pointer 1 Irrelevant Data (Nore 1) 4 0 New Index Register 1 Irrelevant Data (Note 1) TXS 1 1 Op Code Address 1 Op Code 4 2 1 Op Cade Address + 1 1 Op Code of Next Instruction 3 0 Index Register 1 Irrelevant Oata 4 Qa New Stack Pointer 1 Irralevant Data PTS 1 1 Op Code Address 1 Op Code 2 1 Op Code Address + 1 1 trrelevant Oata (Note 2) 5 3 0 Stack Pointer 1 Irrelevant Data (Note 1) 4 1 Stack Pointer + 1 1 Address of Next Instruction (High Order Byte) 5 1 Stack Pointer + 2 1 Address of Next Instruction (Low Order Byte) MOTOROLA MICROPROCESSOR DATA 3-275MC6802 TABLE 8 OPERATIONS SUMMARY (CONCLUDED) Address Mode Cycle| VMA R/V and Instructions Cycles # Line Address Bus Line Data Bus INHERENT (Continued) WAI 1 1 |Op Code Address 1 | Op Code 2 1 | Op Code Address + 1 1 | Op Cade of Next instruction 3 1 {Stack Pointer Q j Return Address (Low Order Syte) 4 1 {Stack Pointer 1 Q | Return Address (High Order Byte} 9 5 1 {Stack Pointer 2 Q | Index Register (Low Order Byte) 6 1 {Stack Pointer ~ 3 Q | Index Register (High Order Byte) 7 1 [Stack Pointer 4 O | Contents of Accumulator A 8 1 |Stack Pointer 5 Q | Contents of Accumulator 8 9 1 {Stack Pointer 6 1 | Contents of Cand. Code Register ATt 1 1 |Op Code Address 1 | Oo Cade 2 1 |Op Code Address +1 1 | irretevant Data (Note 2) 3 O |Stack Pointer 1 | trretevant Data (Note 1) 4 1 |Stack Pointer + 1 1 | Contents of Cond. Code Register from Stack 10 5 1 | Stack Pointer + 2 1 {Contents of Accumulator B from Stack 6 1 | Stack Pointer + 3 1 | Contents of Accumulator A from Stack 7 1 |Stack Pointer + 4 1 | Index Register from Strack (High Order Byte) 8 1 | Stack Pointer +5 1. | Index Register fram Stack (Low Order Byte) 9 1 | Stack Pointer + 6 1 | Next Instruction Address from Stack (High Order Byte) 10 1 [Stack Pointer +7 1 | Next Instruction Address from Stack (Low Order Byte} swi 1 1 | Op Code Address 1 | Op Code 2 1 |Op Code Address + 1 1 | Irrelevant Data (Note 1) 3 1 | Stack Pointer O | Return Address (Low Order Syte) 4 1 | Stack Pointer 1 QO | Return Address (High Order Byte) 5 1 | Stack Pointer 2 O | Index Register (Low Order Syte) 12 6 1 | Stack Pomter 3 QO | tndex Register (High Order Byte) ? 1 | Stack Pointer 4 O | Contents of Accumulator A 8 1 | Stack Pointer 5 O | Contents of Accumulator B 9 1 | Stack Pointer 6 0 | Cantents of Cond. Code Register 10 O | Stack Pointer 7 1 | Irretevant Data (Note 1) 11 1 | Vector Address FFFA (Hex) 1 | Address of Subroutine (High Order Byte} 12 1 | Vector Address FFFB (Hex) 1 | Address of Subroutine (Low Order Byte) RELATIVE BCC 8H! BNE 1 1 | Op Code Address 1 | Op Cade BED ats ora 4 2 1 | Op Code Address + 1 1 | Branch Offset BGE BLT 8VC 3 O | Op Code Address + 2 1 | Irrelevant Oata (Note 1) BGT 8M! BVvS 4 O | Branch Address 1 | Irrelevant Oata (Note 1) BSR 1 1 | Op Code Address 1 | Op Code 2 1 | Op Cade Address + 1 1 | Branch Offser 3 O | Return Address of Main Program 1 | Srrelevant Data (Note 1) 8 4 1 | Stack Pointer O | Return Address (Low Order Byte) 5 1 | Stack Pointer 1 O | Return Address (High Order Bytal 6 O | Stack Pointer 2 1 | Irrelevant Oata (Note 1) ? O | Return Address of Main Program 1 | trrelevant Data (Note 1) 8 0 | Subroutine Address (Note 4) 1 | Irrelevant Osta (Note 1} NOTES . 1 Jf device which 1s addressed during this cycle uses VMA, then the Data Bus will go to the high-impedance three-state candition Depending on bus capacitance, data trom the previous cycle may be retained on the Data Bus 2 Data is ignored by the MPU w For TST, VMA=0 and Operand data does not change 4 MS Byte of Address Bus=MS Byte of Address of ASR instruction and LS Byte of Address Bus=LS Byte of Sub-Routine Address MOTOROLA MICROPROCESSOR DATA 3-276ORDERING INFORMATION MECHANICAL DATA AND ORDERING INFORMATION MC6802 Package Type Frequency MHz Temperature Order Number Plastic 1.0 0C ta 70C MC6802P P Suffix 1.0 40C ta +85C MC6802CP 1.5 Oc to 70C MC68A02P 1.5 40C to +85C MC&8A02CP 2.0 arc to 70C MC68802P Cerdip 1.0 OC to 70C MC68025 S Suffix 1.0 40C to +85C MC6802CS 1.5 0C to 70C MC68A02S 1.5 40C to +85C MC68A02CS 2.0 orc ta 70C MC68B02S PIN ASSIGNMENT Vss Jie NA 40 RESET HALT Qj 2 39) EXTAL MR 3 38 | XTAL iRa 4 ve VMA 05 36 [1 RE NMi 06 35 1 Vcc Standby BA 7 340 Aw Vcc 08 33 1 Do Ao U9 32 0 pt Al (10 31] 02 A2 111 30 1 D3 A3 12 290 D4 A4 13 28 1] Ds A5 [14 27 1) 06 A6 015 260 07 A? 16 25 9 AIS . A8 (117 240 Ai4 AS [} 18 230 a13 A1l0 G19 22 0 At2 All {)20 219 Vss MOTOROLA MICROPROCESSOR DATA 3-277