AK5367 - AKM Semiconductor, Inc. - Datasheet.Directory

[AK5367]

AK5367

96kHz 24-Bit

Δ

Σ

ADC with 0V Bias Selector

GENERAL DESCRIPTION

AK5367 is a high-performance 24-bit, 96kHz sampling ADC for consumer audio and digital recording

applications. The AK5367 uses an Enhanced Dual-Bit modulator architecture, this analog-to-digital

converter has an impressive dynamic range of 102dB with a high level of integration. The AK5367 has a

4-channel stereo input selector, an input Programmable Gain Amplifier with resistance. All this integration

with high-performance makes the AK5367 well suited for CD and DVD recording systems. The integrated

charge pump circuit can generate the negative power supply and remove the output coupling capacitor.

FEATURES

1. 24bit Stereo ADC

• 4:1 0V Bias Stereo input Selector

• Digital HPF for offset cancellation (fc=1.0Hz@fs=48kHz)

• Decimation LPF: -0.2dB@ 20kHz, -3.0dB@23kHz (fs=48kHz)

• Soft Mute

• Single-end Inputs

• S/(N+D): 90dB

• DR, S/N: 102dB

• Audio I/F Format: 24bit MSB justified, I2S

2. Control Interface: I2C-Bus

3. Master Mode / Slave Mode

4. Master Clock:

• 256fs/384fs (32kHz ∼ 96kHz)

• 512fs/768fs (32kHz ∼ 48kHz)

5. Sampling Rate: 32kHz to 96kHz

6. Pow er Supply

• Analog Supply: 4.5 ∼ 5.5V

• Digital Supply: 3.0 ∼ 3.6V

7. Ta = −20 ∼ 85°C

8. Package: 30pin VSOP

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[AK5367]

■ Block Diagram

ROUT

ADC

Audio

I/F

ADC

HPF

ADC

RIN1

RIN2

RIN3

RIN4

LOPIN LISEL

RISELROPIN

HPF

PDN AVDD VSS1

LRCK

BICK

SDTO

MCLK

DVDD

VSS2 CVDD

SDA

LIN1

LIN2

LIN3

LIN4

LOUT

2Vrms

0V

47K

24K

47K

24K

Vcom=0V

0V

1Vrms

CP CN CVEE

SCL

Charge

Pump

VCOM

0.1μ 1μ

10μ

47K

+

47K

Figure 1. AK5367 Block Diagram

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[AK5367]

■ Ordering Guide

AK5367EF −20 ∼ +85°C 30pin VSOP (0.65mm pitch)

AKD5367 Evaluation Board for AK5367

■ Pin Layout

6

5

4

3

2

1 VCOM

LIN1

LIN2

RIN2

LIN3

7

LIN4 8

AVDD

VSS1

DVDD

LRCK

MCLK

BICK

SDTO

AK5367EF

Top View

10

9 RIN4

RISEL

ROUT 11

ROPIN 12

SCL

SDA

PDN

CP

25

26

27

28

29

30

24

23

21

22

20

19

RIN3

LOPIN 13

LOUT 14

CN

CVDD

18

17

LISEL 15 CVEE 16

VSS2

RIN1

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[AK5367]

PIN/FUNCTION

No. Pin Name I/O Function

Common Voltage Output Pin, AVDD/2

1 VCOM O Bias voltage of ADC input.

2 LIN1 I Lch Analog Input 1 Pin

3 RIN1 I Rch Analog Input 1 Pin

4 LIN2 I Lch Analog Input 2 Pin

5 RIN2 I Rch Analog Input 2 Pin

6 LIN3 I Lch Analog Input 3 Pin

7 RIN3 I Rch Analog Input 3 Pin

8 LIN4 I Lch Analog Input 4 Pin

9 RIN4 I Rch Analog Input 4 Pin

10 RISEL I Rch Analog Input Pin

ROUT O Rch Feedback Resistor Output Pin

11 ROPIN O Rch Feedback Resistor Input Pin

12 LOPIN O Lch Feedback Resistor Intput Pin

13 LOUT O Lch Feedback Resistor Output Pin

14

15 LISEL I Lch Analog Input Pin

Negative Voltage Output Pin

Connect to VSS2 with a 1.0μF capacitor that should have the low ESR

(Equivalent Series Resistance) over all temperature range. When this capacitor

has the polarity, the positive polarity pin should be connected to the VSS2 pin.

Non polarity capacitors can also be used.

16 CVEE O

Charge Pump Ground Pin, 0V

17 VSS2 -

Connect to CVEE with a 1.0μF capacitor that should have the low ESR

(Equivalent Series Resistance) over all temperature range. When this capacitor

has the polarity, the positive polarity pin should be connected to the VSS2 pin.

Non polarity capacitors can also be used.

CVDD -

Charge Pump Power Supply Pin, 3.0V∼3.6V

18 Negative Charge Pump Capacitor Terminal Pin

19 CN I

Connect to CP with a 0. 1μF capacitor that should have the low ESR (Equivalent

Series Resistance) over all temperature range. When this capacitor has the

polarity, the positive polarity pin should be connected to the CP pin. Non polarity

capacitors can also be used.

Positive Charge Pump Capacitor Terminal Pin

20 CP O

Connect to CN with a 0. 1μF capacitor that should have the low ESR (Equivalent

Series Resistance) over all temperature range. When this capacitor has the

polarity, the positive polarity pin should be connected to the CP pin. Non polarity

capacitors can also be used.

Power Down Mode & Reset Pin

21 PDN I “H”: Power up, “L”: Power down & Reset

The AK5367 must be reset once upon power-up.

Control Data Input / Output Pin in I2C Control

SDA I/O

22 Control Data Clock Pin in I2C Control

SCL I

23 Audio Serial Data Output Pin

24 SDTO O “L” Output at Power-down mode.

Audio Serial Data Clock Pin

25 BICK I/O “L” Output in Master Mode at PWN bit= “0”.

26 MCLK I Master Clock Input Pin

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[AK5367]

No. Pin Name I/O Function

Channel Clock Pin

27 LRCK I/O “L” Output in Master Mode at PWN bit= “0”.

28 DVDD - Digital Power Supply Pin, 3.0∼ 3.6V

29 VSS1 - Analog Ground Pin

30 AVDD - Analog Power Supply Pin, 4.5 ∼ 5.5V

Note: All input pins except analog input pins (RISEL, LISEL, LIN1-4, RIN1-4) should not be left floating.

■ Handling of Unused Pin

The unused input pins should be processed appropriately as below.

Classification Pin Name Setting

LIN1-4,RIN1-4,LISEL,RISEL

Analog These pins should be open.

LOPIN,LOUT,ROPIN,ROUT

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[AK5367]

ABSOLUTE MAXIMUM RATINGS

(VSS1=VSS2=0V; Note 1, Note 2)

Parameter Symbol min max Units

Power Supplies: Analog AVDD −0.3 6.0 V

Digital DVDD −0.3 6.0 V

Charge Pump CVDD −0.3 4.0 V

Input Current, Any Pin Except Supplies IIN - ±10 mA

Analog Input Voltage(LISEL,RISEL,LIN1-4, R IN1-4 pins) VINA −0.3 AVDD+0.3 V

Digital Input Voltage (Note 3) VIND −0.3 DVDD+0.3 V

Ambient Temperature (Powered applied) Ta −20 85 °C

Storage Temperature Tstg −65 150 °C

Note 1. All voltages with respect to ground.

Note 2. VSS1 and VSS2 must be connected to the same analog ground plane.

Note 3. PDN,SCL,SDA,MCLK,BICK,LRCK pins

WARNING: Operation at or beyond these limits may result in permanent damage to the device.

Normal operation is not guaranteed at these extremes.

RECOMMENDED OPERATING CONDITIONS

(VSS1=VSS2=0V;Note 1)

Parameter Symbol min typ max Units

Analog AVDD 4.5 5.0 5.5 V

Power Supplies Digital DVDD 3.0 3.3 3.6 V

(Note 4) Charge Pump CVDD 3.0 3.3 3.6 V

DVDD-CVDD ΔVDD -0.3 0 +0.3 V

Note 4. The power up sequence between AVDD, DVDD and CVDD is not critical.

In slave mode, the AK5367 must be power up at the PDN pin = “L”.

In master mode, the AK5367 must be power up at the PDN pin = “L”, or when DVDD is powered up, MCLK

clock must input and the AK5367 must be reset by the PDN pin=“L”. The internal register data is unknown until

PDN pin=“L”. The power on/off sequence between AVDD, DVDD and CVDD is not critical, however when

DVDD is powered off, all digital input pins must be left floating or held to VSS.

The power off is means that AVDD, CVDD and DVDD are floating or short to VSS.

WARNING: AKEMD assumes no responsibility for the usage beyond the conditions in this datasheet.

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[AK5367]

ANALOG CHARACTERISTICS

(Ta=25°C; AVDD=5.0V, DVDD=CVDD=3.3V; VSS1=VSS2=0V; fs=48kHz,96kHz; BICK=64fs;

Signal Frequency=1kHz; 24bit Data; Measurement frequency=20Hz ∼ 20kHz at fs=48kHz, 40Hz ∼ 40kHz at fs=96kHz;

unless otherwise specified)

Parameter min typ max Units

Pre-Amp Characteristics:

Feedback Resistance 10 50 kΩ

S/(N+D) (Note 5)- 100 dB

S/N (A-weighted) (Note 5)- 108 dB

Load Resistance RL (Note 6)15 kΩ

Load Capacitance CL (Note 6) 20 pF

ADC Analog Input Characteristics: ( ) Note 7

Resolution 24 Bits

Input Voltage (Note 8)2.7 3.0 3.3 Vpp

−1dBFS 82 90 dB fs=48kHz

BW=20kHz −60dBFS - 39 dB

S/(N+D)

−1dBFS - 90 dB

fs=96kHz

BW=40kHz −60dBFS - 37 dB

DR (−60dBFS, A-weighted) 94 102 dB

S/N (A-weighted) 94 102 dB

Interchannel Isolation (fs=48kHz) (Note 9) 85 96 dB

Interchannel Gain Mismatch 0.1 0.5 dB

Gain Drift 100 - ppm/°C

Power Supply Rejection (Note 10) - 50 dB

Power Supplies

Power Supply Current

Normal Operation (PDN pin = “H”) mA

23

15.5

AVDD mA

4

2.5

CVDD mA

3

2

DVDD (fs=48kHz) mA

6

4

DVDD (fs=96kHz)

Power down mode (PDN pin = “L”) (Note 11) μA

100

10

AVDD+DVDD

Note 5. This value is measured at LOUT and ROUT pins using Ri= 47kΩ, Rf= 24 kΩ when the input signal voltage is

2Vrms.

Note 6. This value of RL and CL are load resistance and capacitance that the LOUT and ROUT pins can drive. R L does not

include the feedback resistor (Rf) and the i nput impedance of t he LISEL/RISEL pins. The value of CL does not

include the internal impedance of the AK5367.

Note 7. This value is measured via the followin g path. Pre-Amp → ADC.(Ri= 47kΩ, Rf= 24 kΩ)

Note 8. Input voltage to LISEL and RISEL pins is proportional to AVDD voltage. typ. Vin = 0.6 x AVDD (Vpp)

Note 9. 93dB(typ.) at fs=96kHz.

Note 10. PSR is applied to AVDD and DVDD with 1kHz, 50mVpp Sine wave.

Note 11. All digital input pins are held DVDD or VSS2.

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[AK5367]

ADC

LOPIN LISEL

LIN1

LOUT

0V

R i

R f

R i

0V

C1=10μF

R i

LIN2

LIN3

LIN4

AK5367

RLCL

-

+

Figure 2. Pre-Amp Circuit

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[AK5367]

FILTER CHARACTERISTICS (fs=48kHz)

(Ta=−20 ∼ 85°C; AVDD=4.5 ∼ 5.5V; DVDD=CVDD=3.0 ∼ 3.6V)

Parameter Symbol min typ max Units

ADC Digital Filter (Decimation LPF):

Passband (Note 12) ±0.1dB PB 0 18.9 kHz

−0.2dB - 20.0 - kHz

−3.0dB - 23.0 - kHz

Stopband SB 28 kHz

Passband Ripple PR ±0.04 dB

Stopband Attenuation SA 68 dB

Group Delay Distortion ΔGD 0 μs

Group Delay (Note 13) GD 20 1/fs

ADC Digital Filter (HPF):

Frequency Response (Note 12) −3dB FR 1.0 Hz

−0.1dB 6.5 Hz

FILTER CHARACTERISTICS (fs=96kHz)

(Ta=−20 ∼ 85°C; AVDD=4.5 ∼ 5.5V; DVDD=CVDD=3.0 ∼ 3.6V)

Parameter Symbol min typ max Units

ADC Digital Filter (Decimation LPF):

Passband (Note 12) ±0.1dB PB 0 37.8 kHz

−0.2dB - 40.0 - kHz

−3.0dB - 46.0 - kHz

Stopband SB 56 kHz

Passband Ripple PR ±0.04 dB

Stopband Attenuation SA 68 dB

Group Delay Distortion ΔGD 0 μs

Group Delay (Note 13) GD 20 1/fs

ADC Digital Filter (HPF):

Frequency Response (Note 12) −3dB FR 2.0 Hz

−0.1dB 13.0 Hz

Note 12. The passband and stopband frequencies scale with fs. For example, PB= 18.9kHz@±0.1dB is 0.39375 x fs,

(fs=48kHz).

Note 13. The calculated delay time induced by digital filtering. This time is from the input of an analog signal

to the setting of 24bit data both channels to the ADC output register for ADC.

DC CHARACTERISTICS

(Ta=-20°C ∼ 85°C; AVDD=4.5 ∼ 5.5V; DVDD=CVDD=3.0 ∼ 3.6V)

Parameter Symbol min typ max Units

High-Level Input Voltage VIH 70%DVDD - - V

Low-Level Input Voltage VIL - - 30%DVDD V

High-Level Output Voltage (Iout=−1mA) VOH DVDD−0.5 - - V

Low-Level Output Voltage

(Except SDA pin: Iout=1mA) VOL - - 0.5 V

(SDA pin: Iout=3mA) VOL - - 0.4 V

Input Leakage Current Iin - - ±10 μA

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[AK5367]

SWITCHING CHARACTERISTICS

(Ta=-20°C ∼ 85°C; AVDD=4.5 ∼ 5.5V; DVDD=CVDD=3.0 ∼ 3.6V; CL=20pF)

Parameter Symbol min typ max Units

Master Clock Timing

MHz

24.576

8.192

fCLK

512fs, 256fs Frequency ns

16

tCLKL

Pulse Width Low ns

16

tCLKH

Pulse Width High MHz

36.864

12.288

fCLK

768fs, 384fs Frequency ns

10.5

tCLKL

Pulse Width Low ns

10.5

tCLKH

Pulse Width High

LRCK Frequency fs 32 96 kHz

Duty Cycle Slave mode 45 55 %

Master mode 50 %

Audio Interface Timing

Slave mode

ns

160

tSCK

BICK Period ns

65

tSCKL

BICK Pulse Width Low ns

65

tSCKH

Pulse Width High ns

30

tLRSH

LRCK Edge to BICK “↑” (Note 14)ns

30

tSHLR

BICK “↑” to LRCK Edge (Note 14)

LRCK to SDTO (MSB) (Except I2S mode)

BICK “↓” to SDTO

tLRS

tSSD

35

35 ns

ns

Master mode

BICK Frequency fSCK 64fs Hz

BICK Duty dSCK 50 %

BICK “↓” to LRCK tMSLR −20 20 ns

BICK “↓” to SDTO tSSD −20 35 ns

Control Interface Timing (I2C Bus mode):

SCL Clock Frequency - 400 kHz

fSCL

Bus Free Time Between Transmissions 1.3 - μs

tBUF

Start Condition Hold Time 0.6 - μs

tHD:STA

(prior to first clock pulse)

Clock Low Time 1.3 - μs

tLOW

Clock High Time 0.6 - μs

tHIGH

Setup Time for Repeated Start Condition 0.6 - μs

tSU:STA

SDA Hold Time from SCL Falling (Note 15)0 - μs

tHD:DAT

SDA Setup Time from SCL Rising 0.1 - μs

tSU:DAT

Rise Time of Both SDA and SCL Lines - 0.3 μs

tR

Fall Time of Both SDA and SCL Lines - 0.3 μs

tF

Setup Time for Stop Condition 0.6 - μs

tSU:STO

Pulse Width of Spike Noise 0 50 ns

tSP

Suppressed by Input Filter

Cb

Capacitive load on bus - 400 pF

Note 14. BICK rising edge must not occur at the same time as LRCK edge.

Note 15. Data must be held long enough to bridge the 300ns-transition time of SCL.

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Parameter Symbol min typ max Units

Reset Timing

tPD 150 ns

PDN Pulse Width (Note 16)tPDV 4388 1/fs

PDN “↑” to SDTO valid at Slave Mode (Note 17)tPDV 4385 1/fs

PDN “↑” to SDTO valid at Master Mode (Note 17)

Note 16. The AK5367 can be reset by bringing the PDN pin = “L”.

Note 17. This cycle is the number of LRCK rising edges from the PDN pin = “H”.

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[AK5367]

■ Timing Diagram

1/fCLK

MCLK

tCLKH tCLKL

VIH

VIL

1/fs

LRCK

VIH

VIL

tSCK

BICK

tSCKH tSCKL

VIH

VIL

Figure 3. Clock Timing

LRCK

VIH

VIL

tSHLR

BICK

VIH

VIL

tLRS

SDTO 50%DVDD

tLRSH

tSSD

Figure 4. Audio Interface Timing (Slave mode)

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[AK5367]

LRCK

BICK 50%DVDD

SDTO 50%DVDD

tSSD

tMSLR dSCK

50%DVDD

Figure 5. Audio Interface Timing (Master mode)

tHIGH

SCL

SDA

VIH

tLOW

tBUF

tHD:STA

tR tF

tHD:DAT tSU:DAT tSU:STA

Stop Start Start Stop

tSU:STO

VIL

VIH

VIL

tSP

Figure 6. I2C Bus mode Timing

tPD

PDN

VIL

PDN

VIH

VIL

tPDV

SDTO 50%DVDD

Figure 7. Power Down & Reset Timing

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[AK5367]

OPERATION OVERVIEW

■ System Clock

MCLK, BICK and LRCK clocks are required. The LRCK clock input must be synchronized with MCLK, however the

phase is not critical. Table 1 shows the relationship of typical sampling frequency and the system clock frequency. The

MCLK, BICK and master/slave mode setting are selected by CKS2-0 bits(Table 2).

In slave mode, all external clocks (MCLK, BICK and LRCK) must be present unless PDN pin = “L”. If these clocks are

not provided, the AK5367 may draw excess current due to its use of internal dynamically refreshed logic. If the external

clocks are not present, place the AK5367 in power-down mode (PDN pin = “L”). In master mode, the master clock

(MCLK) must be provided unless PDN pin = “L”. It is not necessary to reset by bringing PDN pin “L” when clocks and

fs are changed. They should be changed after soft mute (SMUTE bit = “1”) to avoids the switching noise.

MCLK

fs 256fs 384fs 512fs 768fs

32kHz 8.192MHz 12.288MHz 16.384MHz 24.576MHz

44.1kHz 11.2896MHz 16.9344MHz 22.5792MHz 33.8688MHz

48kHz 12.288MHz 18.432MHz 24.576MHz 36.864MHz

96kHz 24.576MHz 36.864MHz N/A N/A

Table 1. System Clock Example (N/A: Not available)

Mode CKS2 CKS1 CKS0 Master/Slave MCLK BICK

256/384fs (32k≤fs≤96k) ≥ 48fs or 32fs

0 0 0 0 Slave 512/768fs (32k≤fs≤48k) (Note 18) (default)

1 0 0 1 Reserved

2 0 1 0 Master 256fs (32k≤fs≤96k) 64fs

3 0 1 1 Master 512fs (32k≤fs≤48k) 64fs

4 1 0 0 Reserved

5 1 0 1 Reserved

6 1 1 0 Master 384fs (32k≤fs≤96k) 64fs

7 1 1 1 Master 768fs (32k≤fs≤48k) 64fs

Table 2. Operation Mode Select

Note 18. The SDTO output is 16bit when BICK=32fs input.

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[AK5367]

■ Audio Interface Format

Table 3

Two kinds of data formats can be chosen with the DIF bit ( ). In both modes, the serial data is in MSB first, 2’s

compliment format. The SDTO is clocked out on the falling edge of BICK. The audio interface supports both m aster and

slave modes. In master mode, BICK and LRCK are output with the BICK frequency fixed to 64fs and the LRCK

frequency fixed to 1fs.

Mode DIF bit SDTO LRCK BICK(Slave) BICK(Master) Figure

64fs

0 0 24bit, MSB justified H/L ≥ 48fs or 32fs Figure 8 (default)

1 1 24bit, I2S Compatible 64fs

L/H ≥ 48fs or 32fs Figure 9

Table 3. Audio Interface Format

LRCK

BICK(64fs)

SDTO(o)

0

23 22

12

4 0

20 21 24 31 0 12

23 22 0

10

23

2220 21 31

23:MSB, 0:LSB

Lch Data Rch Data

24

321

22 23 23

1234

Figure 8. Mode 0 Timing

LRCK

BICK(64fs)

SDTO(o)

0

23 22

12

4 0

2521 24 0 12

23 22 0

1022 2521 24

321

22 23 23

1234

3

23:MSB, 0:LSB

Lch Data Rch Data

Figure 9. Mode 1 Timing

■ Master Mode and Slave Mode

The AK5367 becomes slave mode when it is in the power-down mode (PDN pin = “L”) or exiting power-down. After

exiting the power-down mode, master mode should be set by CKS0-2 bits.

In master mode, LRCK and BICK pins are floating until CKS0-2 bits fixed. Therefore BICK and LRCK pins must be

connected with 100 kΩ pull-up or pull-down resistance.

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[AK5367]

■ Digital High Pass Filter

The ADC has a digital high pass filter for DC offset cancellation. The cut-off frequency of the HPF is 1.0Hz

(@fs=48kHz) and scales with sampling rate (fs).

■ Power-dow n

The AK5367 is placed in the power-down mode by bringing PDN pin = “L” and the digital filter is also reset at the sam e

time. This reset should always be done after power-up. At the power-down mode, the VCOM voltage is become VSS1.

After exiting the power-down m ode, the Charge pump circuit is powered up, and then Pre-Amp circuit is auto powered up

and an analog initialization cycle starts(Figure 10). Therefore, the output data SDTO becomes available after 4388 x

LRCK cycles at slave mode, and 4385 x LRCK cycles at master mode. In the initialization, the both channel of ADC

output is “0” of 2’s complement. After the initialization, the ADC output is settled to the data equal to analog input

signal.(the setting time is same as group delay)

A

DC

Internal State

PDN

Pre-amp In

(Analog)

A

DC OUT

(Digital)

Clock In

MCLK,LRCK,BICK

Charge Pump

Internal State

CVEE Pin

Power-down Initialize Normal Operation

(1)

Idle Noise

GD GD

“0”data

(2)

(3)

(4)

Idle Noise

Power-down Normal Operation

0V

-CVDD

(5)

power-up

Power-down Initialize Normal Operation

GD

(3)

“0”data Idle Noise

Power-down Normal Operation

0V

-CVDD

(

5

)

power-up

(1)

Power Supply

(AVDD, DVDD, CVDD)

(2)

power-up power-up

(2)

Notes:

(1) 4388/fs at slave mode, 4385/fs at master mode.

(2) Analog output corresponding to digital input has group delay (GD).

(3) ADC output is “0” data at the power-down mode.

(4) Place the AK5367 in power-down mode if MCLK, BICK and LRCK are not present.

(5) Power-up time of Charge Pump Circuit. 260/fs (slave mode), 257/fs (master mode).

Figure 10. Power-down/up sequence example

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[AK5367]

■ System Reset

The AK5367 should be reset once by bringing PDN pi n “L” after power-up. At the slave m ode, the internal tim i ng starts

clocking by the rising edge (falling edge at Mode 1) of LRCK after exiting from reset and power down state by MCLK.

The AK5367 is in power-down states until the LRCK is input. At the master mode, bringing PDN pin “H” and exiting

from reset and power down state by MCLK input.

■ Soft Mute Operation

Soft mute operation is performed in the digital domain of the ADC output. When SMUTE bit goes “1”, the ADC output

data is attenuated to −∞ within 1024 LRCK cycles. When the SMUTE bit returned “0”, the mute is cancelled and the

output attenuation gradually changes to 0dB within 1024 LRCK cycles. If the soft mute is cancelled before mute state

after starting of the operat ion, the attenuation is disconti nued and returned to 0dB. The soft mute is effective for changing

the signal source without stopping the signal transmission.

SMUTE bit

Attenuation

1024/fs

0dB

-∞

1024/fs

(1)

(2)

SDTO Output Data “0” data

Figure 11. Soft Mute Function

Notes:

(1) The output signal is attenuated by −∞ within 1024 LRCK cycles (1024/fs).

(2) If the soft mute is cancelled before the mute, the attenuation is discontinued and returned to 0dB by the same cycle.

■ Input Selector

The AK5367 includes 4ch stereo input selectors. The input selector is 4 to 1 selector and set by SEL2-0 bits (Table 4).

SEL2 bit SEL1 bit SEL0 bit Input Selector

0 0 0 LIN1 / RIN1

0 0 1 LIN2 / RIN2

0 1 0 LIN3 / RIN3

0 1 1 LIN4 / RIN4

1 0 0 All off (Note) (default)

Table 4. Input Selector

Note: The LOUT, ROUT pin are 0V.

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[AK5367]

[Input selector switching sequence]

The input selector should be changed after soft mute to avoid the switching noise of the input selector (Figure 12).

1. Enable the soft mute before changing channel.

2. Change channel.

3. Disable the soft mute.

SMUTE bit

A

ttenuation

Channel

0dB

-∞

(1)

(2)

LIN1/RIN1 LIN2/RIN2

(1)

Figure 12. Input channel switching sequence example

Note:

(1) The output signal is attenuated by −∞ within 1024 LRCK cycles (1024/fs).

(2) When changing channels, the input channel should be changed during (2). The period of (2) should be around

200ms because there is some DC difference between the channels.

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[AK5367]

■ Pre-Amp and Input Attenuator

The input ATTs are constructed by adding the input resistor (Ri) for LIN1-4/RIN1-4 pins and the feedback resistor (Rf)

between LOPIN/ROPIN pin and LOUT/ROUT pin (Figure 13). The input voltage range of the LISEL/RISEL pin is

typically 0.6 x AVDD (Vpp). If the input voltage of the input selector exceeds typ. 0.6 x AVDD, the input voltage of the

LISEL/RISEL pins must be attenuated to 0.6 x AVDD by the input ATTs. Table 5 shows the example of Ri and Rf.

LIN1

LIN2

LIN3

LIN4

RIN1

RIN2

RIN3

RIN4

LISEL

ROPIN ROUT RISEL

LOPIN LOUT

Pre-Amp

Ri

Rf

C1=10μF

ADC

C1=10μF

Figure 13. Pre-Amp and Input ATT

• Example for input range

Input Range ATT Gain [dB] LISEL/RISEL pin

Ri [kΩ] Rf [kΩ]

4Vrms 47 12 1.02Vrms

−11.86

2Vrms 47 24 1.02Vrms

−5.84

1Vrms 47 47 0 1Vrms

Table 5. Input ATT example

Note: The value of Ri is over 10kΩ.

MS0694-E-00 2007/12

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[AK5367]

■ Charge Pump Circuit

The internal charge pump circuit generates negative voltage(CVEE) from CVDD voltage. The generated voltage is used

for Pre-Amp.

VSS2

CP CN

AK5367

Charge

Pump

Cp=0.1μF Cout=1μF

CVDD

CVEE

Negative Voltage

To Pre-Amp

Figure 14. Charge Pump Circuit

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[AK5367]

■ Serial Control Interface

The AK5367 supports the first-mode I2C-bus system (max: 400kHz).

The pull-up resistance of SDA,SCL pins should be connected below the voltage of DVDD+0.3V.

1. WRITE Operations

Figure 15 shows the data transfer sequence for the I2C-bus mode. All commands are preceded by a START condition. A

HIGH to LOW transition on the SDA line while SCL is HIGH indicates a START condition (Figure 21). After the

START condition, a slave address is sent. This address is 7 bits long followed by the eight h bit t hat is a data di rection bi t

(R/W). The most significant 7 bits of the slave address are fixed as “0110001”. If the slave address matches that of the

AK5367, the AK5367 generates an acknowledge and the operation is executed. The master must generate the

acknowledge-related clock pulse and release the SDA line (HIGH) during the acknowledge clock pulse (Figure 22). A

R/W bit value of “1” indicates that the read op eration is to be ex ecuted. A “0” in dicates that the write op eration is to be

executed.

The second byte consists of the control register address of the AK5367. The format is MSB first, and those most

significant 6-bits are fixed to zeros (Figure 17). The data after the second byte contains control data. The format is MSB

first, 8bits (Figure 18). The AK5367 generates an acknowledge after each byte is received. A data transfer is always

terminated by a STOP condition generated by the master. A LOW to HIGH transition on the SDA line while SCL is

HIGH defines a STOP condition (Figure 21).

The AK5367 can perform m ore than one by t e wri t e operat i on per sequence. The master can transmit more than one byte

instead of terminating the write cycle after the first data byte is transferred. After receiving each data packet the internal

2-bit address counter is incremented by one, and the next data i s automatically t aken i nt o the next address. If the address

exceeds 02H prior to generating the stop condition, the address counter will “roll over” to 00H and the previous data will

be overwritten.

The data on the SDA line must remain stable during the HIGH period of the clock. The HIGH or LOW state of the data

line can only change when the clock signal on the SCL lin e is LOW (Figure 23) except for the START and STOP

conditions.

SDA Slave

Address

S

T

A

R

T

R/W="0"

A

C

K

Sub

Address(n)

A

C

K

Data(n)

A

C

K

Data(n+1)

A

C

K

A

C

K

Data(n+x)

A

C

K

P

S

T

O

P

Figure 15. Data Transfer Sequence at the I2C-Bus Mode

0 1 1 0 0 0 1 R/W

Figure 16. The First Byte

0 0 0 0 0 0 A1 A0

Figure 17. The Second Byte

D7 D6 D5 D4 D3 D2 D1 D0

Figure 18. Byte Structure after the second byte

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[AK5367]

2. READ Operations

Set the R/W bit = “1” for the READ operation of the AK5367. After transmission of data, the master can read the next

address’s data by generating an acknowledge instead of term inating the write cycle after the receipt of the first data word.

After receiving each data packet the internal 2-bit address counter is incremented by one, and the next data is

automatically taken into the next address. If the address exceeds 02H prior to generating a stop condition, the address

counter will “roll over” to 00H and the previous data will be overwritten.

The AK5367 supports two basic read operations: CURRENT ADDRESS READ and RANDOM ADDRESS READ.

2-1. CURRENT ADDRESS READ

The AK5367 contains an internal address counter that maintains the address of the last word accessed, incremented by

one. Therefore, if the last access (either a read or write) were to address n, the next CURRENT READ operation would

access data from the address n+1. After receipt of the slave address with R/W bit set to “1”, the AK5367 generates an

acknowledge, transmits 1-byte of data to the address set by the internal address counter and increments the internal

address counter by 1. If the master does not generate an acknowledge to the data but generates a stop condition, the

AK5367 ceases transmission.

SDA Slave

Address

S

T

A

R

T

R/W="1"

A

C

K

A

C

K

Data(n+1)

A

C

K

Data(n+2)

A

C

K

A

C

K

Data(n+x)

A

C

K

P

S

T

O

P

Data(n)

Figure 19. CURRENT ADDRESS READ

2-2. RANDOM ADDRESS READ

The random read operation allows the ma ster to access any memory location at random. Prior to issuing the slave address

with the R/W bit “1”, the master must first perform a “dum m y” write operation. The m aster issues a start request, a slave

address (R/W bit = “0”) and then the register address to read. After the register address is acknowledged, the master

immediately reissues the start request and the slave address with the R/W bit “1”. The AK5367 then generates an

acknowledge, 1 byte of data and increments the internal address counter by 1. If the master does not generate an

acknowledge to the data but generates a stop condition, the AK5367 ceases transmission.

SDA Slave

Address

S

T

A

R

T

R/W="0"

A

C

K

A

C

K

A

C

K

Data(n)

A

C

K

Data(n+x)

A

C

K

P

S

T

O

P

Sub

Address(n) SSlave

Address

R/W="1"

S

T

A

R

T

Data(n+1)

A

C

K

A

C

K

Figure 20. RANDOM ADDRESS READ

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[AK5367]

SCL

SDA

stop conditionstart condition

SP

Figure 21. START and STOP Conditions

SCL FROM

MASTER

acknowledge

DATA

OUTPUT BY

TRANSMITTER

DATA

OUTPUT BY

RECEIVER

1 98

START

CONDITION

not acknowledge

clock pulse for

acknowledgement

S

2

Figure 22. Acknowledge on the I2C-Bus

SCL

SDA

data line

stable;

data valid

change

of data

allowed

Figure 23. Bit Transfer on the I2C-Bus

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[AK5367]

■ Register Map

Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0

00H Power Down Control 0 0 0 0 0 0 0 PWN

01H Input Selector Control 0 0 0 0 0 SEL2 SEL1 SEL0

02H Clock & Format Control 0 0 0 DIF CKS2 CKS1 CKS0 SMUTE

PDN pin = “L” resets the registers to their default valu es.

Note: Unused bits must contain a “0” value.

Only write to address 00H to 02H.

■ Register Definitions

Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0

00H Power Down Control 0 0 0 0 0 0 0 PWN

R/W RD RD RD RD RD RD RD R/W

Default 0 0 0 0 0 0 0 1

PWN: Power down control

0 : Po wer down. All registers are not initialized.

1: Normal Operation (default)

“0” powers down all sections and then ADC do not operate. The contents of all register are not initialized

and enabled to write to the registers.

Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0

01H Input Selector Control 0 0 0 0 0 SEL2 SEL1 SEL0

R/W RD RD RD RD RD RD R/W R/W

Default 0 0 0 0 0 1 0 0

Table 4)

SEL2-0: Input selector (

Initial values are “100”.

Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0

02H Clock & Format Control 0 0 0 DIF CKS2 CKS1 CKS0 SMUTE

R/W RD RD RD R/W R/W R/W R/W R/W

Default 0 0 0 0 0 0 0 0

SMUTE: Soft Mute control

0: Normal Operation (default)

1: SDTO outputs soft-muted.

CKS2-0: Operation mode select (Table 2)

Initial values are “000”.

DIF: Audio interface format (Table 3)

Initial values are “0” (24bit, MSB justified).

MS0694-E-00 2007/12

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[AK5367]

SYSTEM DESIGN

Figure 24 shows the system connect ion diagram. The evaluation board (AKD5367) demonstrates appli cation circuits, the

optimum layout, power supply arrangements and measurement results.

LIN1

2

RIN1

3

LIN2

4

RIN2

5

LIN3

6

RIN3

7

LIN4

8

RIN4

9

LISEL

10 RISEL

11 ROUT

12 ROPIN

13

VSS1 29

DVDD 28

LRCK 27

MCLK 26

BICK 25

SDTO 24

SCL 23

SDA 22

PDN 21

CP 20

CN 19

CVDD 18

AK5367

14

15

17

16

LOPIN

LOUT VSS2

CVEE

Analog

VCOM

1 AVDD 30 +

0.1u 10u

A

nalog 5V

+

0.1u

DSP or μP

Digital 3.3V

+

0.1u 10u

Digital 3.3V

0.1u

+10u

+1u

10u

+

24K

Ground

Digital

Ground

Analog In

47K

0.1u 2.2u

+

24K

+ 10u

Figure 24. Typical Connection Diagram

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[AK5367]

1. Grounding and Power Supply Decoupling

The AK5367 requires careful attention to power supply and grounding arrangements. AVDD, DVDD and CVDD are

usually supplied from the analog supply in the system. Alternatively if AVDD, DVDD and CVDD are supplied

separately, the power up sequence is not critical. VSS1 and VSS2 of the AK5367 must be connected to analog ground

plane. System analog ground and digital ground should be connected together near to where the suppl ies are brought onto

the printed circuit board. Decoupling capacitors should be as near to the AK5367 as possible, with the small value

ceramic capacitor being the closest.

2. Voltage Reference Inputs

The differential voltage between AVDD and VSS1 sets the analog input range. VCOM is a signal common of this chip.

An electrolytic capacitor 2.2µF parallel with a 0.1µF ceramic capacitor attached to VCOM pin eliminates the effects of

high frequency noise. No load current may be drawn from the VCOM pin. All signals, especially clocks, should be kept

away from VCOM pins in order to avoid unwanted coupling into the AK5367.

3. Analog Inputs

An analog input of AK5367 is single-ended input to Pre-Am p through the exte rnal resistor. For input si gnal range, adjust

feedback resistor so that Pre-Amp output may become the input range (typ. 0.6 x AVDD Vpp) of ADC (LISEL,RISEL

pin). Between the Pre-Amp output (LOUT, ROUT pin) and the ADC input (LISEL,RISEL pin) is AC coupled with

capacitor. When the impedance of LISEL/RISEL pins is “R” and the capacitor of between the Pre-Amp output and the

ADC input is “C”, the cut-off frequency is fc = 1/(2πRC). The ADC output data format is 2’s compliment. The internal

HPF removes the DC offset. The AK5367 samples the analog inputs at 64fs. The digital filter rejects noise above the stop

band except for multiples of 64fs. The AK5367 includes an anti-aliasing filter (RC filter) to attenuate a noise around 64fs.

4. Attention to the PCB Wiring

LIN1-4 and RIN1-4 pins are the summ ing nodes of t he Pre-Amp. At tenti on should be given t o avoid coupling wit h other

signals on those nodes. This can be accomplished by making the wire lengt h of the input resistors as short as possible. The

same theory also applies to the LOPIN/ROPIN pins and feedback resistors; keep the wire length to a minimum. Unused

input pins am ong LIN1-4 and RIN1-4 pins should be left open. When external devices are connected to LOUT and ROUT

pin, the input impedance is min. 15kΩ.

4. I2C bus Connection

SCL and SDA pins should be connected to DVDD through the resistor based on I2C standard. As there is a protection

between each pin and DVDD, the pulled up voltage mast be DVDD or lower(Figure 25).

VSS2

DVDD

AK5367

+3.3V

SDA pin

Figure 25. SDA pin output

MS0694-E-00 2007/12

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[AK5367]

PACKAGE

Detail A

NOTE: Dimension "*" does not include mold flash.

0.22±0.1 0.65

*9.7±0.1 1.5MAX

A

115

16

30

30pin VSOP (Unit: mm)

5.6±0.1

7.6±0.2

0.45±0.2

-0.05

+0.10

0.3

0.15

0.12 M

0.08

1.2±0.10

0.10 +0.10

-0.05

■ Material & Lead finish

Package molding compound: Epoxy

Lead frame material: Cu

Lead frame surface treatment: Solder (Pb free) plate

MS0694-E-00 2007/12

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[AK5367]

MARKING

AKM

AK5367EF

XXXBYYYYC

XXXBYYYYC Date code identifier

XXXB : Lot number (X : Digit number, B : Alpha character)

YYYYC : Assembly date (Y : Digit number, C : Alpha character)

REVISION HISTORY

Date (YY/MM/DD) Revision Reason Page Contents

07/12/27 00 First Edition

MPORTANT NOTICE

z These products and their specifications are subject to change without notice.

When you consider any use or application of these products, please make inquiries the sales office of Asahi Kasei

EMD Corporation (AKEMD) or authorized distributors as to current status of the products.

z AKEMD assumes no liability for infringement of any patent, intellectual property, or other rights in the application or

use of any information contained herein.

z Any export of these products, or devices or systems containing them, may require an export license or other official

approval under the law and regulati ons of the country of e xport pertaini ng to custom s and tariffs, currency exchange,

or strategic materials.

z AKEMD products are neither intended nor authorized for use as critical componentsNote1) in any safety, l ife support, or

other hazard related device or systemNote2), and AKEMD assumes no responsibility for such use, except for the use

approved with the express written consent by Representative Director of AKEMD. As used here:

Note1) A critical component is one whose failure to function or perform may reasonably be expected to result,

whether directly or indi rectl y, in t he loss of the safety or effecti veness of the device or system containing it, and

which must therefore meet very high standards of performance and reliability.

Note2) A hazard related device or system is one designed or intended for life support or maintenance of safety or

for applications in medicine, aerospace, nuclear energy, or other fi elds, in which its failure to function or perform

may reasonably be expected to result in loss of life or in significant injury or damage to person or property.

z It is the responsibility of the buyer or distributor of AKEMD products, who distributes, disposes of, or otherwise

places the product with a third party, to notify such third party in advance of the above content and conditions, and the

buyer or distributor agrees to assume any and all responsibility and liability for and hold AKEMD harm less from any

and all claims arising from the use of said product in the absence of such notification.

MS0694-E-00 2007/12

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