List of figures
Figure 1. Pin connections for each package (top view) ...............................................2
Figure 2. Supply current vs. supply voltage .......................................................8
Figure 3. Input offset voltage distribution at VCC = 5 V................................................8
Figure 4. Input offset voltage distribution at VCC = 3.3 V ..............................................8
Figure 5. Input offset voltage distribution at VCC = 1.8 V ..............................................8
Figure 6. Vio temperature co-efficient distribution (-40 °C to 25 °C) .......................................8
Figure 7. Vio temperature co-efficient distribution (25 °C to 125 °C) ......................................8
Figure 8. Input offset voltage vs. supply voltage ....................................................9
Figure 9. Input offset voltage vs. input common-mode at VCC = 1.8 V .....................................9
Figure 10. Input offset voltage vs. input common-mode at VCC = 2.7 V .....................................9
Figure 11. Input offset voltage vs. input common-mode at VCC = 5.5 V .....................................9
Figure 12. Input offset voltage vs. temperature......................................................9
Figure 13. VOH vs. supply voltage ..............................................................9
Figure 14. VOL vs. supply voltage..............................................................10
Figure 15. Output current vs. output voltage at VCC = 1.8 V ............................................ 10
Figure 16. Output current vs. output voltage at VCC = 5.5 V ............................................ 10
Figure 17. Input bias current vs. common mode at VCC = 5 V........................................... 10
Figure 18. Input bias current vs. common mode at VCC = 1.8 V ......................................... 10
Figure 19. Input bias current vs. temperature at VCC = 5 V ............................................10
Figure 20. Bode diagram at VCC = 1.8 V ......................................................... 11
Figure 21. Bode diagram at VCC = 2.7 V ......................................................... 11
Figure 22. Bode diagram at VCC = 5.5 V ......................................................... 11
Figure 23. Open loop gain vs. frequency ......................................................... 11
Figure 24. Positive slew rate vs. supply voltage .................................................... 11
Figure 25. Negative slew rate vs. supply voltage ................................................... 11
Figure 26. 0.1 Hz to 10 Hz noise ..............................................................12
Figure 27. Noise vs. frequency................................................................ 12
Figure 28. Noise vs. frequency and temperature ...................................................12
Figure 29. Output overshoot vs. load capacitance .................................................. 12
Figure 30. Small signal .....................................................................12
Figure 31. Large signal ..................................................................... 12
Figure 32. Positive overvoltage recovery at VCC = 1.8 V ..............................................13
Figure 33. Positive overvoltage recovery at VCC = 5 V ...............................................13
Figure 34. Negative overvoltage recovery at VCC = 1.8 V ............................................. 13
Figure 35. Negative overvoltage recovery at VCC = 5 V ............................................... 13
Figure 36. PSRR vs. frequency ...............................................................13
Figure 37. Output impedance vs. frequency....................................................... 13
Figure 38. Block diagram in the time domain (step 1) ................................................14
Figure 39. Block diagram in the time domain (step 2) ................................................14
Figure 40. Vio cancellation principle ............................................................ 15
Figure 41. Block diagram in the frequency domain .................................................. 15
Figure 42. Input current limitation ..............................................................16
Figure 43. Stability criteria with a serial resistor at VDD = 5 V ........................................... 17
Figure 44. Stability criteria with a serial resistor at VDD = 1.8 V.......................................... 17
Figure 45. Test configuration for Riso ........................................................... 17
Figure 46. EMIRR on IN+ pin................................................................. 18
Figure 47. Oxygen sensor principle schematic .....................................................18
Figure 48. Precision instrumentation amplifier schematic.............................................. 19
Figure 49. Low-side current sensing schematic .................................................... 19
TSZ121, TSZ122, TSZ124
List of figures
DS9216 - Rev 10 page 36/38