1
2
3
4
5
6
7
14
13
12
11
10
9
8
1CLR
1D
1CLK
1PRE
1Q
1Q
GND
VCC
2CLR
2D
2CLK
2PRE
2Q
2Q
SN54LVC74A . . . J OR W PACKAGE
SN74LVC74A . . . D, DB, NS, OR PW PACKAGE
(TOP VIEW)
3 2 1 20 19
9 10 11 12 13
4
5
6
7
8
18
17
16
15
14
2D
NC
2CLK
NC
2PRE
1CLK
NC
1PRE
NC
1Q
1D
1CLR
NC
2Q
2Q V
2CLR
1Q
GND
NC
SN54LVC74A . . . FK PACKAGE
(TOP VIEW)
CC
NC - No internal connection
SN74LVC74A . . . RGY PACKAGE
(TOP VIEW)
1 14
7 8
2
3
4
5
6
13
12
11
10
9
2CLR
2D
2CLK
2PRE
2Q
1D
1CLK
1PRE
1Q
1Q
1CLR
2Q V
GND
CC
SN54LVC74A, SN74LVC74A
www.ti.com
SCAS287T JANUARY 1993REVISED JULY 2013
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH CLEAR AND PRESET
Check for Samples: SN54LVC74A,SN74LVC74A
1FEATURES DESCRIPTION
The SN54LVC74A dual positive-edge-triggered D-
Operate From 1.65 V to 3.6 V type flip-flop is designed for 2.7-V to 3.6-V VCC
Inputs Accept Voltages to 5.5 V operation, and the SN74LVC74A dual positive-edge-
Max tpd of 5.2 ns at 3.3 V triggered D-type flip-flop is designed for 1.65-V to 3.6-
V VCC operation.
Typical VOLP (Output Ground Bounce)
<0.8 V at VCC = 3.3 V, TA= 25°C A low level at the preset (PRE) or clear (CLR) inputs
sets or resets the outputs, regardless of the levels of
Typical VOHV (Output VOH Undershoot) the other inputs. When PRE and CLR are inactive
>2 V at VCC = 3.3 V, TA= 25°C (high), data at the data (D) input meeting the setup
Latch-Up Performance Exceeds 250 mA Per time requirements is transferred to the outputs on the
JESD 17 positive-going edge of the clock pulse. Clock
ESD Protection Exceeds JESD 22 triggering occurs at a voltage level and is not directly
related to the rise time of the clock pulse. Following
2000-V Human-Body Model (A114-A) the hold-time interval, data at the D input can be
200-V Machine Model (A115-A) changed without affecting the levels at the outputs.
1000-V Charged-Device Model (C101) The data I/Os and control inputs are overvoltage
tolerant. This feature allows the use of these devices
for down-translation in a mixed-voltage environment.
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Copyright © 1993–2013, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas On products compliant to MIL-PRF-38535, all parameters are
Instruments standard warranty. Production processing does not tested unless otherwise noted. On all other products, production
necessarily include testing of all parameters. processing does not necessarily include testing of all parameters.
TG
C
C
TG
C
C
TG
C
C
C
TG
C
C
PRE
CLK
D
CLR
Q
Q
C
SN54LVC74A, SN74LVC74A
SCAS287T JANUARY 1993REVISED JULY 2013
www.ti.com
FUNCTION TABLE
INPUTS OUTPUTS
PRE CLR CLK D Q Q
L H X X H L
H L X X L H
L L X X H(1) H(1)
H H H H L
H H L L H
H H L X Q0Q0
(1) This configuration is nonstable; that is, it does not persist when PRE
or CLR returns to its inactive (high) level.
LOGIC DIAGRAM, EACH FLIP-FLOP
(POSITIVE LOGIC)
2Submit Documentation Feedback Copyright © 1993–2013, Texas Instruments Incorporated
Product Folder Links: SN54LVC74A SN74LVC74A
SN54LVC74A, SN74LVC74A
www.ti.com
SCAS287T JANUARY 1993REVISED JULY 2013
Absolute Maximum Ratings(1)
over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT
VCC Supply voltage range –0.5 6.5 V
VIInput voltage range(2) –0.5 6.5 V
VOOutput voltage range(2) (3) –0.5 VCC + 0.5 V
IIK Input clamp current VI< 0 –50 mA
IOK Output clamp current VO< 0 –50 mA
IOContinuous output current ±50 mA
Continuous current through VCC or GND ±100 mA
D package(4) 86
DB package(4) 96
θJA Package thermal impedance NS package(4) 76 °C/W
PW package(4) 113
RGY package(5) 47
Tstg Storage temperature range –65 150 °C
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
(3) The value of VCC is provided in the recommended operating conditions table.
(4) The package thermal impedance is calculated in accordance with JESD 51-7.
(5) The package thermal impedance is calculated in accordance with JESD 51-5.
Recommended Operating Conditions(1)
SN54LVC74A SN74LVC74A UNIT
MIN MAX MIN MAX
Operating 2 3.6 1.65 3.6
VCC Supply voltage V
Data retention only 1.5 1.5
VCC = 1.65 V to 1.95 V 0.65 × VCC
VIH High-level input voltage VCC = 2.3 V to 2.7 V 1.7 V
VCC = 2.7 V to 3.6 V 2 2
VCC = 1.65 V to 1.95 V 0.35 × VCC
VIL Low-level input voltage VCC = 2.3 V to 2.7 V 0.7 V
VCC = 2.7 V to 3.6 V 0.8 0.8
VIInput voltage 0 5.5 0 5.5 V
VOOutput voltage 0 VCC 0 VCC V
VCC = 1.65 V –4
VCC = 2.3 V –8
IOH High-level output current mA
VCC = 2.7 V –12 –12
VCC = 3 V –24 –24
VCC = 1.65 V 4
VCC = 2.3 V 8
IOL Low-level output current mA
VCC = 2.7 V 12 12
VCC = 3 V 24 24
Δt/Δv Input transition rise or fall rate 10 10 ns/V
TAOperating free-air temperature –55 125 –40 125 °C
(1) All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
Copyright © 1993–2013, Texas Instruments Incorporated Submit Documentation Feedback 3
Product Folder Links: SN54LVC74A SN74LVC74A
SN54LVC74A, SN74LVC74A
SCAS287T JANUARY 1993REVISED JULY 2013
www.ti.com
Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted) –40°C TO 125°C
–55°C TO 125°C(1) –40°C TO 85°C(1) SN74LVC74A
PARAMETER TEST CONDITIONS VCC UNIT
SN54LVC74A SN74LVC74A Recommended
MIN TYP MAX MIN TYP MAX MIN TYP MAX
1.65 V to 3.6 VCC VCC
V 0.2 0.2
IOH = –100 μAVCC
2.7 V to 3.6 V 0.2
IOH = –4 mA 1.65 V 1.2 1.2
VOH V
IOH = –8 mA 2.3 V 1.7 1.7
2.7 V 2.2 2.2 2.2
IOH = –12 mA 3 V 2.4 2.4 2.4
IOH = –24 mA 3 V 2.2 2.2 2.2
1.65 V to 3.6 0.2 0.2
V
IOL = 100 μA2.7 V to 3.6 V 0.2
IOL = 4 mA 1.65 V 0.45 0.45
VOL V
IOL = 8 mA 2.3 V 0.7 0.7
IOL = 12 mA 2.7 V 0.4 0.4 0.4
IOL = 24 mA 3 V 0.55 0.55 0.55
IIVI= 5.5 V or GND 3.6 V ±5 ±5 ±5 μA
ICC VI= VCC or GND, IO= 0 3.6 V 10 10 10 μA
One input at VCC 0.6 V,
ΔICC 2.7 V to 3.6 V 500 500 500 μA
Other inputs at VCC or GND
CiVI= VCC or GND 3.3 V 5 5 5 pF
(1) All typical values are at VCC = 3.3 V, TA= 25°C.
Timing Requirements
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1)SN54LVC74A
VCC = 3.3 V
VCC = 2.7 V UNIT
± 0.3 V
MIN MAX MIN MAX
fclock Clock frequency 83 100 MHz
PRE or CLR low 3.3 3.3
twPulse duration ns
CLK high or low 3.3 3.3
Data 3.4 3
tsu Setup time before CLKns
PRE or CLR inactive 2.2 2
thHold time, data after CLK1 1 ns
4Submit Documentation Feedback Copyright © 1993–2013, Texas Instruments Incorporated
Product Folder Links: SN54LVC74A SN74LVC74A
SN54LVC74A, SN74LVC74A
www.ti.com
SCAS287T JANUARY 1993REVISED JULY 2013
Timing Requirements
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1)
SN74LVC74A
–40°C to 125°C –40°C to 125°C
–40°C to 85°C –40°C to 85°C
Recommended Recommended UNIT
VCC = 1.8 V VCC = 1.8 V VCC = 2.5 V VCC = 2.5 V
± 0.15 V ± 0.15 V ± 0.2 V ± 0.2 V
MIN MAX MIN MAX MIN MAX MIN MAX
fclock Clock frequency 83 83 83 83 MHz
PRE or CLR low 4.1 4.1 3.3 3.3
twPulse duration ns
CLK high or low 4.1 4.1 3.3 3.3
Data 3.6 3.6 2.3 2.3
tsu Setup time before CLKns
PRE or CLR inactive 2.7 2.7 1.9 1.9
thHold time, data after CLK1 1 1 1 ns
Timing Requirements
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1)
SN74LVC74A
–40°C to 125°C –40°C to 125°C
–40°C to 85°C –40°C to 85°C
Recommended Recommended UNIT
VCC = 3.3 V VCC = 3.3 V
VCC = 2.7 V VCC = 2.7 V ± 0.3 V ± 0.3 V
MIN MAX MIN MAX MIN MAX MIN MAX
fclock Clock frequency 83 83 150 100 MHz
PRE or CLR low 3.3 3.3 3.3 3.3
twPulse duration ns
CLK high or low 3.3 3.3 3.3 3.3
Data 3.4 3.4 3 3
tsu Setup time before CLKns
PRE or CLR inactive 2.2 2.2 2 2
thHold time, data after CLK1 1 0 1 ns
Switching Characteristics
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1)
SN54LVC74A
FROM TO VCC = 3.3 V
PARAMETER VCC = 2.7 V UNIT
(INPUT) (OUTPUT) ± 0.3 V
MIN MAX MIN MAX
fmax 83 100 MHz
CLK 6 1 5.2
tpd Q or Q ns
PRE or CLR 6.4 1 5.4
Switching Characteristics
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1)
SN74LVC74A
–40°C to 125°C –40°C to 125°C
–40°C to 85°C –40°C to 85°C
FROM TO Recommended Recommended
PARAMETER UNIT
(INPUT) (OUTPUT) VCC = 1.8 V VCC = 1.8 V VCC = 2.5 V VCC = 2.5 V
± 0.15 V ± 0.15 V ± 0.2 V ± 0.2 V
MIN MAX MIN MAX MIN MAX MIN MAX
fmax 83 83 83 83 MHz
CLK 1 7.1 1 7.1 1 4.4 1 4.4
tpd Q or Q ns
PRE or CLR 1 6.9 1 6.9 1 4.6 1 4.6
tsk(o) ns
Copyright © 1993–2013, Texas Instruments Incorporated Submit Documentation Feedback 5
Product Folder Links: SN54LVC74A SN74LVC74A
SN54LVC74A, SN74LVC74A
SCAS287T JANUARY 1993REVISED JULY 2013
www.ti.com
Switching Characteristics
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1)
SN74LVC74A
–40°C to 125°C –40°C to 125°C
–40°C to 85°C –40°C to 85°C
FROM TO Recommended Recommended
PARAMETER UNIT
(INPUT) (OUTPUT) VCC = 3.3 V VCC = 3.3 V
VCC = 2.7 V VCC = 2.7 V ± 0.3 V ± 0.3 V
MIN MAX MIN MAX MIN MAX MIN MAX
fmax 83 83 150 100 MHz
CLK 1 6 6 1 5.2 5.2
tpd Q or Q ns
PRE or CLR 1 6.4 6.4 1 5.4 5.4
tsk(o) 1 ns
Operating Characteristics
TA= 25°C VCC = 1.8 V VCC = 2.5 V VCC = 3.3 V
TEST
PARAMETER UNIT
CONDITIONS TYP TYP TYP
Cpd Power dissipation capacitance per flip-flop f = 10 MHz 24 24 26 pF
6Submit Documentation Feedback Copyright © 1993–2013, Texas Instruments Incorporated
Product Folder Links: SN54LVC74A SN74LVC74A
VM
th
tsu
From Output
Under Test
CL
(see Note A)
LOAD CIRCUIT
S1 VLOAD
Open
GND
RL
RL
Data Input
Timing Input VI
0 V
VI
0 V
0 V
tw
Input
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
PULSE DURATION
tPLH
tPHL
tPHL
tPLH
VOH
VOH
VOL
VOL
VI
0 V
Input
Output
Waveform 1
S1 at VLOAD
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
VOL
VOH
tPZL
tPZH
tPLZ
tPHZ
VLOAD/2
0 V
VOL + V
VOH - V0 V
VI
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
Output
Output
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
VLOAD
GND
TEST S1
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 .
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.
Output
Control
VMVM
VMVM
VMVM
VM
VMVM
VM
VM
VM
VI
VM
VM
1.8 V ± 0.15 V
2.5 V ± 0.2 V
2.7 V
3.3 V ± 0.3 V
1 k
500
500
500
VCC RL
2 × VCC
2 × VCC
6 V
6 V
VLOAD CL
30 pF
30 pF
50 pF
50 pF
0.15 V
0.15 V
0.3 V
0.3 V
V
VCC
VCC
2.7 V
2.7 V
VI
VCC/2
VCC/2
1.5 V
1.5 V
VM
tr/tf
2 ns
2 ns
2.5 ns
2.5 ns
INPUTS
SN54LVC74A, SN74LVC74A
www.ti.com
SCAS287T JANUARY 1993REVISED JULY 2013
PARAMETER MEASUREMENT INFORMATION
Figure 1. Load Circuit and Voltage Waveforms
Copyright © 1993–2013, Texas Instruments Incorporated Submit Documentation Feedback 7
Product Folder Links: SN54LVC74A SN74LVC74A
SN54LVC74A, SN74LVC74A
SCAS287T JANUARY 1993REVISED JULY 2013
www.ti.com
REVISION HISTORY
Changes from Revision S (May 2005) to Revision T Page
Extended maximum temperature operating range from 85°C to 125°C. .............................................................................. 3
8Submit Documentation Feedback Copyright © 1993–2013, Texas Instruments Incorporated
Product Folder Links: SN54LVC74A SN74LVC74A
PACKAGE OPTION ADDENDUM
www.ti.com 18-Oct-2013
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
5962-9761601Q2A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 5962-
9761601Q2A
SNJ54LVC
74AFK
5962-9761601QCA ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 5962-9761601QC
A
SNJ54LVC74AJ
5962-9761601QDA ACTIVE CFP W 14 1 TBD A42 N / A for Pkg Type -55 to 125 5962-9761601QD
A
SNJ54LVC74AW
5962-9761601V2A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 5962-
9761601V2A
SNV54LVC
74AFK
5962-9761601VCA ACTIVE CDIP J 14 25 TBD A42 N / A for Pkg Type -55 to 125 5962-9761601VC
A
SNV54LVC74AJ
5962-9761601VDA ACTIVE CFP W 14 1 TBD A42 N / A for Pkg Type -55 to 125 5962-9761601VD
A
SNV54LVC74AW
SN74LVC74AD ACTIVE SOIC D 14 50 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 LVC74A
SN74LVC74ADBLE OBSOLETE SSOP DB 14 TBD Call TI Call TI -40 to 125
SN74LVC74ADBR ACTIVE SSOP DB 14 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 LC74A
SN74LVC74ADBRG4 ACTIVE SSOP DB 14 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 LC74A
SN74LVC74ADE4 ACTIVE SOIC D 14 50 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 LVC74A
SN74LVC74ADG4 ACTIVE SOIC D 14 50 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 LVC74A
SN74LVC74ADR ACTIVE SOIC D 14 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 LVC74A
SN74LVC74ADRE4 ACTIVE SOIC D 14 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 LVC74A
PACKAGE OPTION ADDENDUM
www.ti.com 18-Oct-2013
Addendum-Page 2
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
SN74LVC74ADRG4 ACTIVE SOIC D 14 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 LVC74A
SN74LVC74ADT ACTIVE SOIC D 14 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 LVC74A
SN74LVC74ADTE4 ACTIVE SOIC D 14 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 LVC74A
SN74LVC74ADTG4 ACTIVE SOIC D 14 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 LVC74A
SN74LVC74ANSR ACTIVE SO NS 14 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 LVC74A
SN74LVC74ANSRG4 ACTIVE SO NS 14 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 LVC74A
SN74LVC74APW ACTIVE TSSOP PW 14 90 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 LC74A
SN74LVC74APWE4 ACTIVE TSSOP PW 14 90 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 LC74A
SN74LVC74APWG4 ACTIVE TSSOP PW 14 90 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 LC74A
SN74LVC74APWLE OBSOLETE TSSOP PW 14 TBD Call TI Call TI -40 to 125
SN74LVC74APWR ACTIVE TSSOP PW 14 2000 Green (RoHS
& no Sb/Br) CU NIPDAU | CU SN Level-1-260C-UNLIM -40 to 125 LC74A
SN74LVC74APWRE4 ACTIVE TSSOP PW 14 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 LC74A
SN74LVC74APWRG4 ACTIVE TSSOP PW 14 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 LC74A
SN74LVC74APWT ACTIVE TSSOP PW 14 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 LC74A
SN74LVC74APWTE4 ACTIVE TSSOP PW 14 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 LC74A
SN74LVC74APWTG4 ACTIVE TSSOP PW 14 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 LC74A
SN74LVC74ARGYR ACTIVE VQFN RGY 14 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 LC74A
SN74LVC74ARGYRG4 ACTIVE VQFN RGY 14 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 LC74A
PACKAGE OPTION ADDENDUM
www.ti.com 18-Oct-2013
Addendum-Page 3
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
SNJ54LVC74AFK ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 5962-
9761601Q2A
SNJ54LVC
74AFK
SNJ54LVC74AJ ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 5962-9761601QC
A
SNJ54LVC74AJ
SNJ54LVC74AW ACTIVE CFP W 14 1 TBD A42 N / A for Pkg Type -55 to 125 5962-9761601QD
A
SNJ54LVC74AW
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
PACKAGE OPTION ADDENDUM
www.ti.com 18-Oct-2013
Addendum-Page 4
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN54LVC74A, SN54LVC74A-SP, SN74LVC74A :
Catalog: SN74LVC74A, SN54LVC74A
Automotive: SN74LVC74A-Q1, SN74LVC74A-Q1
Enhanced Product: SN74LVC74A-EP, SN74LVC74A-EP
Military: SN54LVC74A
Space: SN54LVC74A-SP
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
Enhanced Product - Supports Defense, Aerospace and Medical Applications
Military - QML certified for Military and Defense Applications
Space - Radiation tolerant, ceramic packaging and qualified for use in Space-based application
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
SN74LVC74ADBR SSOP DB 14 2000 330.0 16.4 8.2 6.6 2.5 12.0 16.0 Q1
SN74LVC74ADR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
SN74LVC74ADT SOIC D 14 250 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
SN74LVC74ANSR SO NS 14 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1
SN74LVC74APWR TSSOP PW 14 2000 330.0 12.4 7.0 5.6 1.6 8.0 12.0 Q1
SN74LVC74APWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
SN74LVC74APWRG4 TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
SN74LVC74APWT TSSOP PW 14 250 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
SN74LVC74ARGYR VQFN RGY 14 3000 330.0 12.4 3.75 3.75 1.15 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 29-Jul-2013
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN74LVC74ADBR SSOP DB 14 2000 367.0 367.0 38.0
SN74LVC74ADR SOIC D 14 2500 367.0 367.0 38.0
SN74LVC74ADT SOIC D 14 250 367.0 367.0 38.0
SN74LVC74ANSR SO NS 14 2000 367.0 367.0 38.0
SN74LVC74APWR TSSOP PW 14 2000 364.0 364.0 27.0
SN74LVC74APWR TSSOP PW 14 2000 367.0 367.0 35.0
SN74LVC74APWRG4 TSSOP PW 14 2000 367.0 367.0 35.0
SN74LVC74APWT TSSOP PW 14 250 367.0 367.0 35.0
SN74LVC74ARGYR VQFN RGY 14 3000 367.0 367.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 29-Jul-2013
Pack Materials-Page 2