ANALOG DACPORT Low Cost, Complete DEVICES y.P-Compatible 8-Bit DAC AD558 1.1 Scope. This specification covers the detail requirements for a 8-bit resolution D/A converter (DACPORT) complete with output amplifier, full microprocessor interface, precision reference and requiring only +5V. 1.2 Part Number. The complete part number per Table 1 of this specification is as follows: Device Part Number! -1 ADS5S58S(X)/883B -2 ADS5S8T(X)/883B NOTE See paragraph 1.2.3 for package identifier. 1.2.3 Case Outline. See Appendix 1 of General Specification ADI-M-1000: package outline: (&%) Package Description D D-16 16-Pin DIP (TO-116 Style) E E-20A 20-Terminal Leadless Chip Carrier 1.3 Absolute Maximum Ratings. (T,= + 25C unless otherwise noted) VectoGround .. 0... 0... ee ee Digital Inputs (Pins 1-10) .. 2... 2. ee es Vout a Power Dissipation... 0.0... ee et es Storage Temperature Range... . 2... ee es Lead Temperature Range (Soldering 10sec)... 2.2... 2.220000 ae 1.5 Thermal Characteristics. Thermal Resistance @;, = 30C/W 8ya = 100C/W DACPORT is a registered trademark of Analog Devices, Inc. DIGITAL-TO-ANALOG CONVERTERS 8-19 se ee eee Oto +18V Ce ee 0to +7.0V Indefinite Short to Ground Momentary Short to Vcc Ce ee ee 450mW tt eee 300C DIGITAL-TO-ANALOG CONVERTERS a AD558 SPECIFICATIONS Table 1. Design Sub Sub Sub Limit Group | Group | Group Test Symbol | Device @+25C }1 2,3 4 Test Condition! Units Relative Accuracy RA -1 1/2 1/2 3/4 All Bits with Positive + LSB max ~2 V4 v2 | 38 1/4 _ | Errors Onand All Bits with Negative Errors On Differential Nonlinearity DNL |-1,2 1 1 1 All Major Carriers + LSB max Zero Error Vos ~1 1 1 2 1 All Bits Off + LSB max -2 V2 1 1 V2 Gain Error Ag -1 1.5 1.5 2.5 1.5 No Load and 5mA Load + LSB max -2 0.5 1.5 1.0 0.5 All Bits On Output Voltage Settling Time ~1,2 3.0 Oto 10V Range ys max 15 Oto 2.56V Range Power Supply Rejection Ratio PSRR | -1,2 0.03 0.03 0.03 Note 3 %l% max Power Supply Current Ico -1,2 25 25 25 All Bits On +mA max Power Dissipation PD ~1,2 125 125 125 Voc= +5V All BitsOn mW max 375 375 375 Voc = + 15V All Bits On Digital Input High Voltage Vin -1,2 2.0 2.0 2.0 +Vmin Digital Input Low Voltage Vit ~-1,2 0.8 0.8 0.8 + Vmax Digital Input High Current ln -1,2 100 100 100 Vin =7V + pA max Digital Input Low Current I -1,2 100 100 100 ViL=0V + pA max Write Pulse Width* twr -1,2 200 270 ns min Data Setup Time* tps -1,2 200 270 ns min Data Hold Time* tou -1,2 10 10 ns min NOTES 'V,= +5V for 0to2.56V range, V5 = + 15 for 0 to 10V range (unless otherwise noted). *Settling time is specified for a positive full scale step to + 1/2LSB. Veg = 4.5V 10 5.5V for 0 to 2.56V range, Vcc = 11.4V to 16.5V for 0 to LOV range. Timing per Figure 1. 820 DIGITAL-TO-ANALOG CONVERTERS REV. C AD558 REV. C 3.2.1 Functional Block Diagram and Terminal Assignments. DIGITAL INPUT DATA CONTROL INPUTS LsB MSB cs | GE 0B0 DB1 DB2 DB3 DB4 DBS DBS DB7 PL CONTROL #L LATCHES v | LOGIC vu BAND. GAP 8-BIT VOLTAGE-SWITCHING REFERENCE D-TO.A CONVERTER u CONTROL AMP D Package (DIP) NY {LSB) OBO [ 1}, @ 6} Vout DBI [ 2 15 | Vour SENSE DB2 [ 3 14] Vout SELECT [ } DB2 4 DB3 | 4 AD558 13] GND ToP VIEW DB3 5 DB4 E] (Not to Scale) 2] GND NC 6 oes [Ee | 11} vce _ DB4 7 DEG [ 7 10| CS DBS 8 {MS8) DB? [ 8 9| cE 3.2.4 Microcircuit Technology Group. This microcircuit is covered by technology group (56). 4.2.1 Life Test/Burn-In Circuit. +Vec GND GND Yoo OUTPUT AMP Vout co Vout SENSE : 5 aans Vour SELECT < 2 < V E Package (LCC) g saat oo oO ago2> 7% 3.2 1 20 19 18 Vour SELECT 17 GND TOP VIEW 16 NC (Not to Scale) 15 GND 14 +Vec 1112-13 218 8 DBE (MSB) 087 3 Steady state life test is per MIL-STD-883 Method 1005. Burn-in is per MIL-STD-883 Method 1015 test condition (B). NY *38V0eT7Jicss) 080 Vour{ 16 Te pen sense L's 10k + 10% TE] eter t [4 | oss GND | 13 = Gl DB4 Gnp [12 $[E joes Nec [11]? +89 $-Z] ves Ss +l (MSB) DB? CE DIGITAL-TO-ANALOG CONVERTERS 8-21 DIGITAL-TO-ANALOG CONVERTERS a AD538 DATA on t_ tp, ____> mont KY tf, ____ ml Me ton Figure 1. AD558 Timing Diagram Table 2. AD558 Control Logic Truth Table Latch Input Data | CE cs DAC Data | Condition 0 oO 0 0 transparent 1 0 0 1 transparent 0 f 0 0 latching 1 J 0 1 latching 0 0 f 0 latching 1 0 f 1 latching X 1 xX previous data | latched xX X 1 previous data | latched Notes: X = Does not matter = Logic Threshold at Positive-Going Transition Og 8-22 DIGITAL-TO-ANALOG CONVERTERS REV. C