0S1204U DALLAS SEMICONDUCTOR DS1204U Electronic Key FEATURES * Cannot be deciphered by reverse engineering @ Partitioned memory thwarts pirating @ User-insertable packaging allows personal! posses- sion Exclusive blank keys on request Appropriate identification can be made with a 64-bit reprogrammable memory e Unreadable 64-bit security match code virtually pre- vents deciphering by exhaustive search with over 1019 possibilities 128 bits of secure read/write memory create addition- al barriers by permitting data changes as often as needed @ Rapid erasure of identification security match code and secure read/write memory can occur if tampering is datected Over 10 years of data retention with no limitations or restrictions on write cycle @ Low-power CMOS circuitry @ Four million bps data rate Durable and rugged Applications include software authorization, gray market software protection, proprietary data, financial transactions, secure personnel areas, and system ac- cess control DESCRIPTION The DS1204U Electronic Key is a miniature security system that stores 64 bits of user-definable identifica- tion code and a 64-bit security match code that protects 128 bits of read/write nonvolatile memory. The 64-bit identification code and the security match code are pro- grammed into the key via a special program mode oper- ation. After programming, the key follows a procedure with a serial format to retrieve or update data. Interface costto a microprocessor is minimized by on-chip circuit- PIN ASSIGNMENT DALLAS DS1204U ELECTRONIC KEY SIDE BOTTOM: PIN VIEW | LOIN SS See Mech. Drawing Sect. 16, Pg. 12 PIN DESCRIPTION Pin 1-Voc +5 Volts Pin 2- RST Reset Pin3 - DQ Data Input/Output Pin 4 - CLK Clock Pin - GND Ground ry that permits data transfer with only three signals: Clock (CLK), Reset (RST), and Data Input/Output (DQ). Low pin count and a guided entry for mating receptacle overcome mechanical problems normally encountered with conventional integrated circuit packaging, making the device transportable and user-insertable. &1 120391 1/9DS1204U OPERATION - NORMAL MODE The Electronic Key has two modes of operation: normal and program. The block diagram (see Figure 1) illus- trates the main elements of the key when used in the normal mode. To initiate data transfer with the key, RST is taken high and 24 bits are loaded into the command register on each low-to-high transition of the CLK input. The command register must match the exact bit pattern that defines normal operation for read or write, or com- munications are ignored. If the command register is loaded properly, communications are allowed to contin- ue. The next 64 cycles to the key are reads. Data is BLOCK DIAGRAM - NORMAL MODE Figure 1 clocked out of the key on the high-to-low transition of the clock from the identification memory. Next, 64 write cycles must be written to the compare register. These 64 bits must match the exact pattern stored in the secu- rity match memory. If a match is not found, access to ad- ditional information is denied. Instead, random data is output for the next 128 cycles when reading data. If write cycles are being executed, the write cycles are ignored. if a match is found, access is permitted to a 128-bit read/ write nonvolatile memory. Figure 2 is a summary of nor- mal mode operation and Figure 3 is a flow chart of the normal mode sequence. D/Q < Bit a rege. fdenttication - rst of 64-Bit t i Security Match Y Compare Register Le P| 128-Bit Command Register > Secure Memory << 4 Random Data i SEQUENCE - NORMAL MODE Figure 2 Protocol Identification Security Match Command Word 64 Read Cycles 64 Write Cycles Match Secure Memory 128 Reads or Writes 120391 2/8DS1204U FLOW CHART - NORMAL MODE Figure 3 Reset High Write Command| Protocol Read 64 Bits | Identification Write 64 Bits | Security Match Output Garbled Read or Write 128 Bits Based Secure NV RAM on Prot Stop t Reset Low Output in High Z PROGRAM MODE The block diagram in Figure 4 illustrates the main ele- ments of the key when used in the program mode. Toini- tiate the program mode, RST is driven high and 24 bits are loaded into the command register on each low-to-high transition of the CLK input. The command register must match the exact pattern that defines pro- gram operation. If an exact match is not found, the re- mainder of the program cycle is ignored. Ifthe command register is properly loaded, then the 128 bits that follow are written to the identification memory and the security match memory. Figure 5 is a summary of program mode operation and Figure 6 is a flow chart of program mode operation. 120391 39DS1204U BLOCK DIAGRAM - PROGRAM MODE Figure 4 D/Q < CLK Control Logic 64-Bit Identification _ 64-Bit K Security Match Command Register | SEQUENCE - PROGRAM MODE Figure 5 Protocol Identification Security Match Command Word | 64 Write Cycles 64 Write Cycles COMMAND WORD Each data transfer for the norma! and program mode begins with a three-byte command word as shown in Figure 7. As defined, the first byte of the command word specifies whether the 128-bit nonvolatile memory willbe written into or read. If any one of the bits of the first byte of the command word fails to meet the exact pattern of read or write, the data transfer will be aborted. The 8-bit pattern for read is 01100010. The pattern for write is 10011101. The first two bits of the second byte of the command word specify whether the data transfer to follow is a program or normal cycle. The bit pattern for program is 0 in bit 0 and 1 in bit 1. The program mode can be selected only when the first byte of the command word specifies a write. If the program mode is specified and the first byte of the command word does not specify awrite, data transfer willbe aborted. The bit pattern that selects the normal mode of operationis 1 in bit 0 and 0 in bit 1. The other two possible combinations for the first two bits of byte 2 will cause data transfer to abort. The remaining six bits of byte 2 and the first seven bits of byte 3 form unique patterns that allow multiple keys to teside on a common bus. As such, each respective code pattern must be written exactly for a given device or data transfer will abort. Dallas Semiconductor has five patterns available as standard products per the chartin Figure 7. Each pattern corresponds to a specific part number. Under special contract with Dallas Semi- conductor, the user can specify any bit pattern other than those specified as unavailable. The bit pattern as defined by the user must be written exactly or data transfer will abort. The last bit of byte 3 of the command word mustbe written to logic 1 or data transfer will abort. NOTE: Contact the Dallas Semiconductor sales office for a spe- cial command word code assignment that makes possi- ble an exclusive blank key. 120301 4/90S1204U FLOW CHART - PROGRAM MODE Figure 6 RESET High Write Command Protocol Write 64 Bits Identification t Write 64 Bits Security Match ne Stop t RESET Low Output in High Z RESET AND CLOCK CONTROL __ All data transfers are initiated by driving the RST input high. The RST input serves three functions. First, itturns on control logic, which allows access to the command register for the command sequence. Second, the RST signal provides a power source for the cycle to follow. To meat this requirement, a drive source for RST of 2mA @ 3.0 volts is required. However, if the Voc pin is con- nacted to a 5-volt source within nominal limits, the RST is not used as a source of power and input levels revert to normal Vjq and Vy inputs with a drive current require- ment of 500 pA. Third, the RST signal provides a meth- od of terminating data transfer. Aclock cycle is a sequence of a falling edge followed by a rising edge. For data inputs, the data must be valid during the rising edge of a clock cycle. Command bits and data bits are input on the rising edge of the clock and data bits are output on the falling edge of the clock. The rising edge of the clock returns the DQ pin to a high im- pedance state, All data transfer terminates if the RST pin is low and the DQ pin goes to a high impedance state. When data transfer to the key is terminated using RST, the transition of RST must occur while the clock is ata high level to avoid disturbing the last bit of data. Data transfer is illustrated in Figure 8 for normal mode and Figure 9 for program mode. 8-5 120391 5/9DS1204U COMMAND WORD Figure 7 Rw Aw Rw Rw Rw Rw Rw Rye Byte 1 x} xi xix x] x ip | P lg Byte 2 23 1/x}]x {x} x] x |x | X lag t Byte 3 0 0 o|; 0] 0 0 P|P Byte 2 DS1204U-G01 1 0 1/0] 0 0} 0 0 | Byte 3 0] o}]o]of{o|1]|P|FP | Byte2 DS1204UG02 1/o/1]o]0] 0] 0 | 0 | Byes 0 0 o|;o | 1 0 P |P | Byte2 DS1204U-G03 1 0 1 0; 0] 0 0 0 | Byte 3 0 0 0 | 0 1 1 P |P Byte 2 DS1204U-G04 1 0 1/0 ;]0)] 0 0 0 | Byte 3 o/ofo|{1]o]o|]|pe | P |Byte2 DS1204U~-G05 1 0 1 0 | oO 0 0 0 | Byte 3 KEY CONNECTIONS tions, contact to the key pins can be determined to en- The key is designed to be plugged into a standard 5-pin, sure connection integrity before data transfer begins. 0.1-inch center SIP receptacle. A guide is providedto | CLK, RST, and DQ all have internal 20K ohm pulldown prevent the key from being plugged in backwards and resistors to ground that can be sensed by a reading de- aid in alignment of the receptacle. For portable applica- vice. 120391 6/9DS1204U DATA TRANSFER - NORMAL MODE Figure 8 aa ULL LL | | CLOCK - SS S Joy | RESET o 1 . 23 ~ ~ < of a od ve ~<Raw| RW | . [| 1 | Do 5 | 063] a0] 5 63 | Dao] , [Da126] pater > \ ogni aE _/ DATA TRANSFER - PROGRAM MODE Figure 9 OCK fT * | RESET 0 12 23 x. &. <x, RW _ | 1 | ao ail ~ | a62| aes ao | at | | a62 aes > 5 5 $ COMMAND WRITE WRITE \ WORD \ 64 BITS A 64 BITS ABSOLUTE MAXIMUM RATINGS* Voltage on any Pin Relative to Ground -1.0V to +7.0V Operating Temperature 0C to 70C Storage Temperature -40C to +70C * This is a stress rating only and functional operation of the device at these or any other corditions outside those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability. RECOMMENDED DC OPERATING CONDITIONS (0C to 70C) PARAMETER SYMBOL MIN TYP MAX | UNITS | NOTES Logic 1 Vin 2.0 V 1, 8,10 Logic 0 Ve 03 +0.8 v 1 RESET Logic 1 Vine 3.0 Vv 1,9, 11 Supply Voc 4.5 5.0 5.5 Vv 1 120391 7/9 8-7DS1204U DC ELECTRICAL CHARACTERISTICS (0C to 70C; Voc = 5V + 10%) PARAMETER SYMBOL MIN TYP MAX UNITS NOTES Input Leakage ln +500 pA 4 Output Leakage ILo +500 pA Output Current @2.4V lou -1 mA Output Current @0.4V lo. +2 mA RST Input Resistance Zast 10 60 K ohms D/Q Input Resistance Zpaq 10 60 K ohms CLK Input Resistance Zeik 10 60 K ohms RST Current @3.0V 'RsT 2 mA 6, 9,13 Active Current lect 6 mA 6 Standby Current loce 2.5 mA 6 CAPACITANCE (ta = 25C) PARAMETER SYMBOL MIN TYP MAX UNITS | NOTES Input Capacitance Cw ) pF Output Capacitance Cour 7 pF AC ELECTRICAL CHARACTERISTICS {0C to 70C, Veg = SV + 10%) PARAMETER SYMBOL MIN TYP MAX UNITS | NOTES Data to CLK Setup toc 35 ns 2,7 CLK to Data Hold tepy 40 ns 2,7 CLK to Data Delay tepp 100 ns 2,3, 5,7 CLK Low Time to 125 ns 2,7 CLK High Time tou 125 ns 2,7 CLK Frequency fork DC 4.0 MHz 2,7 CLK Rise & Fall tp, te 500 ns 2,7 RST to CLK Setup tec 1 ps 2,7 CLK to RST Hold tocH 40 ns 2,7 RST Inactive Time towH 125 ns 2,7,14 RST to VO HighZ tepz 50 ns 2,7 120391 8/90S1204U TIMING DIAGRAM - WRITE DATA + tcWH 4. 4%. RESET CO toh et _ [-tccH CLOCK /| Pr | \ " \ DATA vo CDH wt TCH fe tt INPUTIOUTPUT/ / x Raw X///)X RA /// WX MLSS LX TIMING DIAGRAM - READ DATA t tt *| tcWH RESET oF tcc CLOCK toc e VM we NOTES: 1. All voltages are referenced to GND. 2. Measured at Viy = 2.0 or Vy_ = .8V and 10ns maximum rise and fall time. 3. Measured at Voy = 2.4 volts and Voy = 0.4 volts. 4. For CLK, D/Q, and RST. 5. Load capacitance = 50 pF. 6. Measured with outputs open. 7. Measured at Vj, of RST > 3.0V when RST supplies power. 8. Logic 1 maximum is Voc + 0.3 volts if the Voc pin supplies power and RST + 0.3 volts if the RST pin supplies power. 9. Applies to RST when Voc < 3.0V. 10. Input levels apply to CLK, DQ, and RST while Voc is within nominal limits. When Vg is not connected to the key, then RST input reverts to Vine. 11. RST logic 1 maximum is Vcc + 0.3 volts if the Voc pin supplies power and 5.5 volts maximum if RST supplies power. 12, Each DS1204U is marked with a 4-digit code AABB. AA designates the year of manufacture. BB designates the week of manufacture. The expected tpr is defined as starting at the date of manufacture. 13. Average AC RST current can be determined using the following formula: hrotat = 2 + lLoap pc + (4x 10-9) (CL + 140)f lrota and ILoap are in mA; C;, is in pF; fis in MHz. Applying the above formula, a load capacitance of 50 pF running at a frequency of 4.0 MHz gives an lroraz of 5 mA. 14. When RST is supplying power towy must be increased to100 ms average. 120391 9/8 8-9