STD110N02RT4G - ON Semiconductor L.L.C.

August, 2011 − Rev. 10

1Publication Order Number:

NTD110N02R/D

NTD110N02R, STD110N02R

Power MOSFET

24 V, 110 A, N−Channel DPAK

Features

•Planar HD3e Process for Fast Switching Performance

•Low RDS(on) to Minimize Conduction Loss

•Low Ciss to Minimize Driver Loss

•Low Gate Charge

•Optimized for High Side Switching Requirements in

High−Efficiency DC−DC Converters

•AEC Q101 Qualified − STD110N02R

•These Devices are Pb−Free and are RoHS Compliant

MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)

Rating Symbol Value Unit

Drain−to−Source Voltage VDSS 24 V

Gate−to−Source Voltage − Continuous VGS ±20 V

Thermal Resistance − Junction−to−Case

Total Power Dissipation @ TC = 25°C

Drain Current

− Continuous @ TC = 25°C, Chip

− Continuous @ TC = 25°C

Limited by Package

− Continuous @ TA = 25°C

Limited by Wires

− Single Pulse (tp = 10 ms)

RqJC

1.35

110

°C/W

Thermal Resistance

− Junction−to−Ambient (Note 1)

− Total Power Dissipation @ TA = 25°C

− Drain Current − Continuous @ TA = 25°C

RqJA

2.88

17.5

°C/W

Thermal Resistance

− Junction−to−Ambient (Note 2)

− Total Power Dissipation @ TA = 25°C

− Drain Current − Continuous @ TA = 25°C

RqJA

100

1.5

12.5

°C/W

Operating and Storage Temperature Range TJ, Tstg −55 to

175

°C

Single Pulse Drain−to−Source Avalanche

Energy − Starting TJ = 25°C

(VDD = 50 Vdc, VGS = 10 Vdc,

IL = 15.5 Apk, L = 1.0 mH, RG = 25 W)

EAS 120 mJ

Maximum Lead Temperature for Soldering

Purposes, (1/8″ from case for 10 s)

TL260 °C

Stresses exceeding Maximum Ratings may damage the device. Maximum

Ratings are stress ratings only. Functional operation above the Recommended

Operating Conditions is not implied. Extended exposure to stresses above the

Recommended Operating Conditions may affect device reliability.

1. When surface mounted to an FR4 board using 0.5 sq in drain pad size.

2. When surface mounted to an FR4 board using the minimum recommended

pad size.

http://onsemi.com

24 V 4.1 mW @ 10 V

RDS(on) TYP

110 A

ID MAXV(BR)DSS

N−Channel

CASE 369AA

DPAK

(Surface Mount)

STYLE 2

CASE 369D

DPAK

(Straight Lead)

STYLE 2

123

MARKING DIAGRAM

& PIN ASSIGNMENTS

YWW

110N2G

Gate

Source

Drain

Gate

Source

Drain

YWW

110N2G

Y = Year

WW = Work Week

T110N2 = Device Code

G = Pb−Free Package

See detailed ordering and shipping information in the package

dimensions section on page 5 of this data sheet.

ORDERING INFORMATION

NTD110N02R, STD110N02R

http://onsemi.com

ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted)

Characteristic Symbol Min Typ Max Unit

OFF CHARACTERISTICS

Drain−to−Source Breakdown Voltage (Note 3)

(VGS = 0 V, ID = 250 mA)

Positive Temperature Coefficient

V(BR)DSS

24 28

mV/°C

Zero Gate Voltage Drain Current

(VDS = 20 V, VGS = 0 V)

(VDS = 20 V, VGS = 0 V, TJ = 125°C)

IDSS

1.5

Gate−Body Leakage Current (VGS = ±20 V, VDS = 0 V) IGSS ±100 nA

ON CHARACTERISTICS (Note 3)

Gate Threshold Voltage (Note 3)

(VDS = VGS, ID = 250 mA)

Negative Threshold Temperature Coefficient

VGS(th)

1.0 1.5

5.0

2.0

mV/°C

Static Drain−to−Source On−Resistance (Note 3)

(VGS = 10 V, ID = 110 A)

(VGS = 4.5 V, ID = 55 A)

(VGS = 10 V, ID = 20 A)

(VGS = 4.5 V, ID = 20 A)

RDS(on)

4.1

5.5

3.9

5.5

4.6

6.2

Forward Transconductance (VDS = 10 V, ID = 15 A) (Note 3) gFS 44 Mhos

DYNAMIC CHARACTERISTICS

Input Capacitance

(VDS = 20 V, VGS = 0 V, f = 1.0 MHz)

Ciss 2710 3440 pF

Output Capacitance Coss 1105 1670

Transfer Capacitance Crss 450 640

SWITCHING CHARACTERISTICS (Note 4)

Turn−On Delay Time

(VGS = 10 V, VDD = 10 V,

ID = 40 A, RG = 3.0 W)

td(on) 11 22 ns

Rise Time tr39 80

Turn−Off Delay Time td(off) 27 40

Fall Time tf21 40

Gate Charge

(VGS = 4.5 V, ID = 40 A,

VDS = 10 V) (Note 3)

QT23.6 28 nC

QGS 5.1

QGD 11

SOURCE−DRAIN DIODE CHARACTERISTICS

Forward On−Voltage (IS = 20 A, VGS = 0 V) (Note 3)

(IS = 55 A, VGS = 0 V)

(IS = 20 A, VGS = 0 V, TJ = 125°C)

VSD 0.82

0.99

0.65

1.2 V

Reverse Recovery Time

(IS = 30 A, VGS = 0 V,

dIS/dt = 100 A/ms) (Note 3)

trr 36.5 ns

ta30

tb25

Reverse Recovery Stored Charge Qrr 0.048 mC

3. Pulse Test: Pulse Width ≤ 300 ms, Duty Cycle ≤ 2%.

4. Switching characteristics are independent of operating junction temperatures.

NTD110N02R, STD110N02R

http://onsemi.com

4.2 V

2.0

1.6

1.2

1.4

1.0

0.8

0.6 10

1000

100,000

010

100

VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)

ID, DRAIN CURRENT (AMPS)

VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)

Figure 1. On−Region Characteristics Figure 2. Transfer Characteristics

ID, DRAIN CURRENT (AMPS)

0.02

1086

0.01

Figure 3. On−Resistance versus

Gate−to−Source Voltage

VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)

Figure 4. On−Resistance versus Drain Current

and Gate Voltage

ID, DRAIN CURRENT (AMPS)

RDS(on), DRAIN−TO−SOURCE RESISTANCE (W)

Figure 5. On−Resistance Variation with

Temperature

TJ, JUNCTION TEMPERATURE (°C)

Figure 6. Drain−to−Source Leakage Current

versus Voltage

VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)

RDS(on), DRAIN−TO−SOURCE RESISTANCE

(NORMALIZED)

IDSS, LEAKAGE (nA)

175

−50 50250−25 75 125100

042

01510 255.0

150

VDS ≥ 10 V

TJ = 25°C

TJ = −55°C

TJ = 175°C

VGS = 4.5 V

175

VGS = 0 V

ID = 55 A

VGS = 10 V

0.03

0.008

0.006

0.014

TJ = 175°C

TJ = 100°C

120

210

180

0.004

20 1601208040 240

TJ = 25°C

100

10 V

3.8 V

4.5 V

5 V

6 V

8 V

10,000

ID = 110 A

TJ = 25°C

0.002

0.01

0.012

60 100 220200140 180

VGS = 10 V

1.8

150

125

TJ = 25°C

4 V

3.6 V

3.4 V

3.2 V

2.6 V

2.8 V

3 V

2.4 V

150

NTD110N02R, STD110N02R

http://onsemi.com

RDS(on) Limit

Thermal Limit

Package Limit

VGS

1000

100

1.0

1000

120

100

10 10

5000

155020

GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS)

C, CAPACITANCE (pF)

4000

3000

2000

1000

Qg, TOTAL GATE CHARGE (nC)

Figure 7. Capacitance Variation Figure 8. Gate−to−Source and

Drain−to−Source Voltage versus Total Charge

VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)

Figure 9. Resistive Switching Time Variation

versus Gate Resistance

RG, GATE RESISTANCE (W)

Figure 10. Diode Forward Voltage versus

Current

VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS)

IS, SOURCE CURRENT (AMPS)

t, TIME (ns)

Figure 11. Maximum Rated Forward Biased

Safe Operating Area

VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)

ID, DRAIN CURRENT (AMPS)

01520105

1 10 100 0.4 0.8 1.21.0

0.1 10 1001.0

ID = 40 A

TJ = 25°C

VGS

VGS = 0 V

VDS = 0 V TJ = 25°C

Crss

Ciss

Coss

Crss

0.6

Ciss

VGS = 20 V

SINGLE PULSE

TC = 25°C

VDS = 10 V

ID = 55 A

VGS = 10 V

VGS = 0 V

TJ = 25°C

10 ms

1 ms

td(off)

td(on)

VDS

QDS

100

VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)

VDS

QGS

NTD110N02R, STD110N02R

http://onsemi.com

0.2

1.0

0.1

0.01

t, TIME (s)

D = 0.5

0.1

0.05

0.02

0.01 Single Pulse

Figure 12. Thermal Response

r(t), EFFECTIVE TRANSIENT THERMAL

RESISTANCE (NORMALIZED)

0.00001 0.0001 0.001 0.01 0.1 1.0 10

ORDERING INFORMATION

Device Package Shipping†

NTD110N02RT4G DPAK

(Pb−Free)

2500 / Tape & Reel

STD110N02RT4G DPAK

(Pb−Free)

2500 / Tape & Reel

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging

Specifications Brochure, BRD8011/D.

NTD110N02R, STD110N02R

http://onsemi.com

PACKAGE DIMENSIONS

DPAK (SINGLE GUAGE)

CASE 369AA−01

ISSUE B

STYLE 2:

PIN 1. GATE

2. DRAIN

3. SOURCE

4. DRAIN

5.80

0.228

2.58

0.101

1.6

0.063

6.20

0.244

3.0

0.118

6.172

0.243

ǒmm

inchesǓ

SCALE 3:1

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and

Mounting Techniques Reference Manual, SOLDERRM/D.

SOLDERING FOOTPRINT*

0.005 (0.13) C

DIM MIN MAX MIN MAX

MILLIMETERSINCHES

D0.235 0.245 5.97 6.22

E0.250 0.265 6.35 6.73

A0.086 0.094 2.18 2.38

b0.025 0.035 0.63 0.89

c2 0.018 0.024 0.46 0.61

b2 0.030 0.045 0.76 1.14

c0.018 0.024 0.46 0.61

e0.090 BSC 2.29 BSC

b3 0.180 0.215 4.57 5.46

L4 −−− 0.040 −−− 1.01

L0.055 0.070 1.40 1.78

L3 0.035 0.050 0.89 1.27

Z0.155 −−− 3.93 −−−

NOTES:

1. DIMENSIONING AND TOLERANCING PER ASME

Y14.5M, 1994.

2. CONTROLLING DIMENSION: INCHES.

3. THERMAL PAD CONTOUR OPTIONAL WITHIN DI-

MENSIONS b3, L3 and Z.

4. DIMENSIONS D AND E DO NOT INCLUDE MOLD

FLASH, PROTRUSIONS, OR BURRS. MOLD

FLASH, PROTRUSIONS, OR GATE BURRS SHALL

NOT EXCEED 0.006 INCHES PER SIDE.

5. DIMENSIONS D AND E ARE DETERMINED AT THE

OUTERMOST EXTREMES OF THE PLASTIC BODY.

6. DATUMS A AND B ARE DETERMINED AT DATUM

PLANE H.

12 3

H0.370 0.410 9.40 10.41

A1 0.000 0.005 0.00 0.13

L1 0.108 REF 2.74 REF

L2 0.020 BSC 0.51 BSC

DETAIL A

SEATING

PLANE

L2 GAUGE

PLANE

DETAIL A

ROTATED 90 CW5

NTD110N02R, STD110N02R

http://onsemi.com

PACKAGE DIMENSIONS

IPAK

CASE 369D−01

ISSUE C

STYLE 2:

PIN 1. GATE

2. DRAIN

3. SOURCE

4. DRAIN

123

−T−

SEATING

PLANE

D3 PL

0.13 (0.005) T

DIM MIN MAX MIN MAX

MILLIMETERSINCHES

A0.235 0.245 5.97 6.35

B0.250 0.265 6.35 6.73

C0.086 0.094 2.19 2.38

D0.027 0.035 0.69 0.88

E0.018 0.023 0.46 0.58

F0.037 0.045 0.94 1.14

G0.090 BSC 2.29 BSC

H0.034 0.040 0.87 1.01

J0.018 0.023 0.46 0.58

K0.350 0.380 8.89 9.65

R0.180 0.215 4.45 5.45

S0.025 0.040 0.63 1.01

V0.035 0.050 0.89 1.27

NOTES:

1. DIMENSIONING AND TOLERANCING PER

ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

Z0.155 −−− 3.93 −−−

ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice

to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability

arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.

“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All

operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights

nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications

intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should

Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,

and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death

associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal

Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.

PUBLICATION ORDERING INFORMATION

N. American Technical Support: 800−282−9855 Toll Free

USA/Canada

Europe, Middle East and Africa Technical Support:

Phone: 421 33 790 2910

Japan Customer Focus Center

Phone: 81−3−5773−3850

NTD110N02R/D

LITERATURE FULFILLMENT:

Literature Distribution Center for ON Semiconductor

P.O. Box 5163, Denver, Colorado 80217 USA

Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada

Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada

Email: orderlit@onsemi.com

ON Semiconductor Website: www.onsemi.com

Order Literature: http://www.onsemi.com/orderlit

For additional information, please contact your local

Sales Representative