HDMI Transceiver with
Fast Port Switching
Data Sheet
ADV7623
Rev. D Document Feedback
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FEATURES
4-input, 1-output multiplexed HDMI transceiver
Xpressview fast switching on all HDMI input ports
Character- and icon-based on-screen display (OSD)
High-Bandwidth Digital Content Protection (HDCP 1.4)
HDCP repeater support
225 MHz HDMI Rx and Tx support 36-/30-/24-bit Deep Color
Supports DVI RGB graphics up to 1600 × 1200 at 60 Hz
Ultralow jitter digital PLL (100% deskew)
Quad HDMI Rx input
Format details available on all unselected ports
Adaptive equalizer for cable lengths up to 30 meters
Internal extended display identification data (EDID) RAM
EDID replication (512 bytes per port)
EDID with HDMI cable 5 V power support
5 V detect inputs
Hot plug assertion control pins
Single HDMI Tx output
EDID data extraction
Hot plug detect (HPD) input
Audio support
HDMI-compatible audio interface
Dedicated flexible audio input/output port
S/PDIF (IEC 60958-compatible) digital audio input/output
Super audio CD (SACD) with DSD input/output interface
High bit rate (HBR) audio
Dolby® TrueHD
DTS-HD Master Audio™
Full audio input and output support
General
Interrupt controller with 3 interrupt outputs
STDI (standard identification circuit)
Software libraries, driver, and application available
2-layer PCB design supported
APPLICATIONS
AVRs
HTiB
Sound bar with HDMI repeater support
HBR enabled TVs
Other repeater applications
GENERAL DESCRIPTION
The ADV7623 is a high performance, four-input, one-output,
High-Definition Multimedia Interface (HDMI®) transceiver
that integrates HDMI receiver and transmitter functions with
digital audio I/Os onto one chip. It supports all HDCP repeater
functions through fully tested Analog Devices, Inc., repeater
software libraries and drivers.
The ADV7623 incorporates Xpressview™ fast switching on all
input HDMI ports. Using an Analog Devices hardware-based
HDCP engine that minimizes software overhead, Xpressview
technology allows fast switching between any HDMI input
ports in less than 1 second.
The ADV7623 supports all mandatory HDMI 3D TV formats in
addition to all HDTV formats up to 1080p 36-bit Deep Color. The
ADV7623 also features an integrated HDMI CEC controller that
supports capability, discovery, and control (CDC).
The ADV7623 has an integrated on-screen display (OSD) feature
that allows generation and control of high quality character- and
icon-based system status and control displays. Customers interested
in using OSD are provided with Analog Devices OSD SDK.
The ADV7623 offers a dedicated flexible audio output port and
a dedicated audio input port to allow for easy extraction and
insertion of audio data into and out of the HDMI stream. HDMI
audio formats, including SACD via DSD and compressed high
bit rate audio via HBR, are supported. The ADV7623 also features
an audio return channel (ARC) receiver. ARC simplifies cabling
by combining upstream audio capability in a conventional
HDMI cable.
Fabricated in an advanced CMOS process, the ADV7623 is
provided in a 144-lead, 20 mm × 20 mm, Pb-free LQFP and is
specified over the 0°C to 70°C temperature range.
ADV7623 Data Sheet
Rev. D | Page 2 of 16
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Functional Block Diagram .............................................................. 3
Specifications ..................................................................................... 4
Digital, HDMI, and AC Specifications ...................................... 4
Data and I2C Timing Characteristics ......................................... 5
Power Specifications .................................................................... 7
Absolute Maximum Ratings ............................................................ 8
Package Thermal Performance ....................................................8
ESD Caution...................................................................................8
Pin Configuration and Function Descriptions ..............................9
Functional Overview...................................................................... 13
HDMI Receiver ........................................................................... 13
HDMI Transmitter ..................................................................... 13
I2C Interface ................................................................................ 13
Other Features ............................................................................ 13
Outline Dimensions ....................................................................... 14
Ordering Guide .......................................................................... 14
REVISION HISTORY
3/13—Revision D: Initial Version
Data Sheet ADV7623
Rev. D | Page 3 of 16
FUNCTIONAL BLOCK DIAGRAM
CH0
CH1
CH2
VIDE O DATA
DE
VS
HS
AUDIO DATA
VIDE O DATA
DE
VS
HS
AUDIO DATA
VIDE O DATA
DE
VS
HS
AUDIO DATA
VIDE O DATA
DE
VS
HS
AUDIO DATA
08302-001
XTAL
XTAL1
RXA_C
RXB_C
RXC_C
RXD_C
RXA_0
RXA_1
RXA_2
VIDEO/AUDIO
CLOCK
GENERATION
RX
PLL
CEC
TXC
TX0
TX1
TX2
5V DETECT
COMPONENT
PROCESSOR
SCL
SDATA
ALSB
CS
I
2
C
CONTROLLER
PWRDN
RESET
GLOBAL
CONTROLS
DDCA_SDA
DDCA_SCL
DDCB_SDA
DDCB_SCL
DDCC_SDA
DDCC_SCL
DDCD_SDA
DDCD_SCL
AP0_IN
AP1_IN
AP2_IN
AP3_IN
AP4_IN
AP5_IN
SCLK_IN
MCLK_IN
AP0_OUT
AP1_OUT
AP2_OUT
AP3_OUT
AP4_OUT
AP5_OUT
SCLK_OUT
MCLK_OUT
ARC+
RX EDI D/
REPEATER
CONTROLLER
RX HPD
CONTROLLER
EP_MISO
EP_MOSI
EP_CS
EP_SCK
SPI MASTER/
SLAVE
EQUALIZER
RXB_0
RXB_1
RXB_2 EQUALIZER
SAMPLER
SAMPLER
RXC_0
RXC_1
RXC_2 EQUALIZER SAMPLER
RXD_0
RXD_1
RXD_2 EQUALIZER
CEC
CONTROLLER
EDID
RAM
SAMPLER
HDMI RECEIVER
PROCESSOR
TRANSMITTER
PACKET BUI L DER
HDCP
ENCRYPTION
ENGINE
HDMI
ENCODER
SERIALIZER
TM DS DRIVERS
INT1
INT2
INT_TX
INTERRUPT
CONTROLLER
TXDDC_SDA
TXDDC_SCL
TX
EDID/HDCP
CONTROLLER
EDID/HDCP
BUFFER
HPD_ARC–
TX HPD
CONTROLLER
HDCP
DECRYPTION
ENGINE
SYNC
MEASUREMENT PACKET
PROCESSOR
INFOFRAME
PACKET
MEMORY
AUDIO
PROCESSOR
ARC
RECEIVER
AUDIO
CAPTURE
HDCP KEYS
TX
PLL
ADV7623
5V_DETA
5V_DETB
5V_DETC
5V_DETD
HP_CTRLA
HP_CTRLB
HP_CTRLC
HP_CTRLD
OSD
Figure 1.
ADV7623 Data Sheet
Rev. D | Page 4 of 16
SPECIFICATIONS
CVDD = 1.8 V ± 5%, DVDD = 1.8 V ± 5%, DVDDIO = 3.3 V ± 5%, PVDD = 1.8 V ± 5%, TVDD = 3.3 V ± 5%, TXAVDD = 1.8 V ± 5%,
TXPVDD = 1.8 V ± 5%, TXPLVDD = 1.8 V ± 5%, TMIN to TMAX = 0°C to 70°C.
DIGITAL, HDMI, AND AC SPECIFICATIONS
Table 1.
Parameter Test Conditions/Comments Min Typ Max Unit
DIGITAL INPUTS
Input High Voltage (VIH) 2 V
Input Low Voltage (VIL) 0.8 V
Input Current (IIN) RESET, EP_MISO, ALSB and CS pins −60 +60 µA
Other digital inputs −10 +10 µA
Input Capacitance (CIN) 10 pF
DIGITAL INPUTS (5 V TOLERANT)1
Input High Voltage (VIH) 2.6 V
Input Low Voltage (VIL) 0.8 V
Input Current (IIN) −82 +82 µA
DIGITAL OUTPUTS
Output High Voltage (VOH) 2.4 V
Output Low Voltage (VOL) 0.4 V
High Impedance Leakage Current (I
LEAK
)
10
µA
Output Capacitance (COUT) 20 pF
HDMI
TMDS Differential Pin Capacitance
0.3
pF
AC SPECIFICATIONS
Input Specifications
Intrapair (+ to −) Differential Input Skew for
TMDS Clock Rates up to 222.75 MHz
0.4 tBIT ps
Intrapair (+ to −) Differential Input Skew for
TMDS Clock Rates Above 222.75 MHz
0.15 tBIT + 112 ps
Channel-to-Channel Differential Input Skew 0.2 tPIXEL + 1.78 ns
TMDS Input Clock Range 25 225 MHz
TMDS Input Clock Jitter Tolerance 0.5 0.25 tBIT
Output Specifications
TMDS Output Clock Frequency 20 225 MHz
TMDS Output Clock Duty Cycle 48 52 %
TMDS Output Differential Swing 900 1100 1200 mV
Differential Output Timing
Low-to-High Transition Time 75 175 ps
High-to-Low Transition Time 75 175 ps
1 The following pins are 5 V tolerant: DDCA_SCL, DDCA_SDA, DDCB_SCL, DDCB_SDA, DDCC_SCL, DDCC_SDA, DDCD_SCL, DDCD_SDA, TXDDC_SDA, TXDDC_SCL,
HP_CTRLA, HP_CTRLB, HP_CTRLC, HP_CTRLD, HPD_ARC−, 5V_DETA, 5V_DETB, 5V_DETC, 5V_DETD, PWRDN, CEC, ARC+.
Data Sheet ADV7623
Rev. D | Page 5 of 16
DATA AND I2C TIMING CHARACTERISTICS
Table 2.
Parameter Symbol Test Conditions/Comments Min Typ Max Unit
VIDEO SYSTEM CLOCK AND XTAL
Crystal Nominal Frequency 28.63636 MHz
Crystal Frequency Stability ±50 ppm
External Clock Source1 External crystal must operate at 1.8 V
Input High Voltage VIH XTAL driven with external clock source 1.2 V
Input Low Voltage VIL XTAL driven with external clock source 0.4 V
RESET FEATURE
Reset Pulse Width 5 ms
I2C PORTS (FAST MODE)
xCL Frequency2 400 kHz
xCL Minimum Pulse Width High2 t1 600 ns
xCL Minimum Pulse Width Low
2
t
2
1.3
µs
Hold Time (Start Condition) t3 600 ns
Setup Time (Start Condition) t4 600 ns
xDA Setup Time2 t5 100 ns
xCL and xDA Rise Time2 t6 300 ns
xCL and xDA Fall Time2 t7 300 ns
Setup Time (Stop Condition) t8 0.6 µs
I2C PORTS (NORMAL MODE)
xCL Frequency2 100 kHz
xCL Minimum Pulse Width High2 t1 4.0 µs
xCL Minimum Pulse Width Low2 t2 4.7 µs
Hold Time (Start Condition) t3 4.0 µs
Setup Time (Start Condition) t4 4.7 µs
xDA Setup Time2 t5 250 ns
xCL and xDA Rise Time
2
t
6
1000
ns
xCL and xDA Fall Time2 t7 300 ns
Setup Time (Stop Condition) t8 4.0 µs
AUDIO OUTPUT PORT (MASTER MODE)
SCLK Mark Space Ratio t13:t14 45:55 55:45 % duty
cycle
APx_OUT Data Transition Time (LRCLK)3 t15 End of valid data to negative SCLK edge 10 ns
APx_OUT Data Transition Time (LRCLK)3 t16 Negative SCLK edge to start of valid data 10 ns
APx_OUT Data Transition Time (I2S Data)3 t17 End of valid data to negative SCLK edge 5 ns
APx_OUT Data Transition Time (I2S Data)3 t18 Negative SCLK edge to start of valid data 5 ns
AUDIO INPUT PORT
APx_IN Setup Time (I
2
S Data)
3
t
19
2
ns
APx_IN Hold Time (I2S Data)3 t20 2 ns
APx_IN Setup Time (LRCLK)3 t19 2 ns
APx_IN Hold Time (LRCLK)3 t20 2 ns
1 This part must be configured for external oscillator operation. A 1.8 V oscillator must be used.
2 The prefix x refers to S, DDCA_S, DDCB_S, DDCC_S, and DDCD_S.
3 The suffix x refers to 0, 1, 2, 3, 4, and 5.
ADV7623 Data Sheet
Rev. D | Page 6 of 16
Timing Diagrams
xDA
xCL
t
5
t
3
t
4
t
8
t
6
t
7
t
2
t
1
t
3
NOTES
1. x REFERS TO S, DDCA_S , DDCB_S, DDCC_S , DDCD_S.
08302-002
Figure 2. I2C Timing
0
8302-004
SCLK
LRCLK
I2S[3:0]
LEFT-JUSTIFIED
MODE
I2S[3:0]
RIGHT-JUSTIFIED
MODE
I2S[3:0]
I
2
S MODE
MSB MSB – 1
t
13
t
14
t
15
t
17
t
18
t
16
MSB MSB – 1
LSBMSB
t
17
t
18
t
17
t
18
Figure 3. I2S Output Timing
08302-007
VALID DAT A
VALID DATA
I2S[3:0],
LRCLK
SCLK
RISING EDGE
R0x0B[6] = 0
SCLK
FALLING EDGE
R0x0B[6] = 1
I2S[3:0]
LRCLK
t
19
t
20
t
19
t
20
Figure 4. I2S Input Timing
Data Sheet ADV7623
Rev. D | Page 7 of 16
POWER SPECIFICATIONS
Table 3.
Parameter Min Typ Max Unit Test Conditions/Comments
POWER SUPPLIES
Comparator Power Supply (CVDD) 1.71 1.8 1.89 V
Digital Core Power Supply (DVDD) 1.71 1.8 1.89 V
Digital I/O Power Supply (DVDDIO) 3.14 3.3 3.46 V
PLL Power Supply (PVDD) 1.71 1.8 1.89 V
Termination Power Supply (TVDD) 3.14 3.3 3.46 V
TX TMDS Output Power Supply (TXAVDD) 1.71 1.8 1.89 V
TX Power Supply (TXPVDD) 1.71 1.8 1.89 V
TX PLL Power Supply (TXPLVDD) 1.71 1.8 1.89 V
CURRENT CONSUMPTION1, 2, 3, 4
Comparator Power Supply (ICVDD) 481 545 mA Four ports with 1080p 12-bit, Xpressview and OSD enabled
1.0 mA Power-Down Mode 1
1.0 mA Power-Down Mode 0
Digital Core Power Supply (IDVDD) 301 350 mA Four ports with 1080p 12-bit, Xpressview and OSD enabled
9.0
mA
Power-Down Mode 1
6.7 mA Power-Down Mode 0
Digital I/O Power Supply (IDVDDIO) 1.0 2.0 mA Four ports with 1080p 12-bit, Xpressview and OSD enabled
3.4 mA Power-Down Mode 1
3.3 mA Power-Down Mode 0
PLL Power Supply (IPVDD) 34.0 39.6 mA Four ports with 1080p 12-bit, Xpressview and OSD enabled
1.7 mA Power-Down Mode 1
1.6 mA Power-Down Mode 0
Termination Power Supply (ITVDD) 283 312 mA Four ports with 1080p 12-bit, Xpressview and OSD enabled
0.4 mA Power-Down Mode 1
0.4 mA Power-Down Mode 0
TX TMDS Output Power Supply (ITXAVDD) 13.0 14.3 mA Four ports with 1080p 12-bit, Xpressview and OSD enabled
0.5 mA Power-Down Mode 1
0.3 mA Power-Down Mode 0
TX Power Supply (ITXPVDD) 5.0 6.6 mA Four ports with 1080p 12-bit, Xpressview and OSD enabled
2.8 mA Power-Down Mode 1
2.8 mA Power-Down Mode 0
TX PLL Power Supply (I
TXPLVDD
)
23.0
26.4
mA
Four ports with 1080p 12-bit, Xpressview and OSD enabled
1.6 mA Power-Down Mode 1
1.6 mA Power-Down Mode 0
1 All maximum current values are guaranteed by characterization to assist in power supply design.
2 Typical current consumption values are recorded with nominal voltage supply levels and at room temperature.
3 Maximum current consumption values are recorded with maximum rated voltage supply levels and at room temperature.
4 Termination power supply includes TVDD current consumed off chip.
ADV7623 Data Sheet
Rev. D | Page 8 of 16
ABSOLUTE MAXIMUM RATINGS
Table 4.
Parameter Rating
CVDD to GND 2.2 V
DVDD to GND 2.2 V
PVDD to GND 2.2 V
DVDDIO to GND 4.0 V
TVDD to GND 4.0 V
TXAVDD to GND 2.2 V
TXPVDD to GND 2.2 V
TXPLVDD to GND
2.2 V
Digital Inputs Voltage to GND GND − 0.3 V to DVDDIO + 0.3 V
up to a maximum of 4.0 V
5 V Tolerant Digital Inputs to GND1 5.5 V
Digital Output Voltage to GND GND − 0.3 V to DVDDIO + 0.3 V
up to a maximum of 4.0 V
XTAL, XTAL1 Pins −0.3 V to PVDD to +0.3 V
Maximum Junction Temperature
(TJ MAX)
125°C
Storage Temperature 150°C
Infrared Reflow, Soldering (20 sec) 260°C
1 The following inputs are 3.3 V inputs but are 5 V tolerant: DDCA_SCL,
DDCA_SDA, DDCB_SCL, DDCB_SDA, DDCC_SCL, DDCC_SDA, DDCD_SCL,
DDCD_SDA, TXDDC_SDA, TXDDC_SCL, HP_CTRLA, HP_CTRLB, HP_CTRLC,
HP_CTRLD, HPD_ARC−, 5V_DETA, 5V_DETB, 5V_DETC, 5V_DETD, PWRDN,
CEC, ARC+.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
PACKAGE THERMAL PERFORMANCE
To reduce power consumption when using the ADV7623, turn
off the unused sections of the part.
Due to printed circuit board (PCB) metal variation and, thus,
variation in PCB heat conductivity, the value of θJA may differ
for various PCBs.
The most efficient measurement solution is obtained using the
package surface temperature to estimate the die temperature
because this eliminates the variance associated with the θJA value.
The maximum junction temperature (TJ MAX) of 125°C must not
be exceeded. The following equation calculates the junction
temperature using the measured package surface temperature
and applies only when no heat sink is used on the DUT:
TJ = TS + (ΨJT × WTOTAL)
where:
TS = the package surface temperature (°C).
ΨJT = 0.6°C/W for a 144-lead LQFP.
WTOTAL = ((CVDD × ICVDD) + (DVDD × IDVDD) +
(PVDD × IPVDD) + (DVDDIO × IDVDDIO) +
(0.7 × TVDD × ITVDD) + (TXAVDD × IT XAVDD) +
(TXPVDD × ITXPVDD) + (TXPLVDD × IT XP LVDD ))
Note that for WTOTAL, 5% of TVDD power is dissipated on the
part itself.
ESD CAUTION
Data Sheet ADV7623
Rev. D | Page 9 of 16
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
ADV7623
TOP VIEW
(No t t o Scal e)
PIN 1
08302-005
1
DDCC_SCL
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36 73
DVDDIO
74
AP3_IN
75
AP2_IN
76
AP1_IN
77
AP0_IN
78
SDATA
79
SCL
80
DGND
81
DVDD
82
INT1
83
INT2
84
INT_TX
85
DGNDIO
86
DVDDIO
87
AP0_OUT
88
AP1_OUT
89
AP2_OUT
90
AP3_OUT
91
AP4_OUT
92
DGND
93
DVDD
94
AP5_OUT
95
SCLK_OUT
96
MCLK_OUT
97
RESET
98
PWRDN
99
PGND
100
PVDD
101
XTAL
102
XTAL1
103
PVDD
104
PGND
105
HP_CTRLA
106
5V_DETA
107
RTERM
108
DDCA_SDA
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
DDCC_SDA
37
TXPLVDD
38
TXGND
39
TXPGND
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
EXT_SWING
HPD_ARC–
ARC+
TXDDC_SDA
TXDDC_SCL
TXAVDD
TXGND
TXC–
TXC+
TXGND
TX0–
TX0+
TXGND
TX1–
TX1+
TXAVDD
TX2–
TX2+
TXGND
CEC
DGND
DVDD
ALSB
CS
EP_SCK
EP_CS
EP_MOSI
EP_MISO
MCLK_IN
SCLK_IN
AP5_IN
AP4_IN
DGNDIO
5V_DETC
HP_CTRLC
RXB_2+
RXB_2–
TVDD
RXB_1+
RXB_1–
CGND
RXB_0+
RXB_0–
TVDD
RXB_C+
RXB_C–
CGND
CVDD
DDCB_SCL
DDCB_SDA
DVDD
DGND
5V_DETB
HP_CTRLB
RXA_2+
RXA_2–
TVDD
RXA_1+
RXA_1–
CGND
RXA_0+
RXA_0–
TVDD
RXA_C+
RXA_C–
CGND
CVDD
DDCA_SCL
CVDD
CGND
RXC_C–
RXC_C+
TVDD
RXC_0–
RXC_0+
CGND
RXC_1–
RXC_1+
TVDD
RXC_2–
RXC_2+
HP_CTRLD
5V_DETD
DGND
DVDD
DDCD_SDA
DDCD_SCL
CVDD
CGND
RXD_C–
RXD_C+
TVDD
RXD_0–
RXD_0+
CGND
RXD_1–
RXD_1+
TVDD
RXD_2–
RXD_2+
CVDD
CGND
TXPVDD
Figure 5. Pin Configuration
Table 5. Pin Function Descriptions
Pin No.
Mnemonic
Type
Description
1 DDCC_SCL Digital input HDCP Slave Serial Clock Port C. DDCC_SCL is a 3.3 V input that is 5 V tolerant.
2 CVDD Power Receiver Comparator Supply Voltage (1.8 V).
3 CGND Ground TVDD and CVDD Ground.
4 RXC_C− HDMI input Digital Input Clock Complement of Port C in the HDMI Interface.
5 RXC_C+ HDMI input Digital Input Clock True of Port C in the HDMI Interface.
6 TVDD Power Receiver Terminator Supply Voltage (3.3 V).
7 RXC_0− HDMI input Digital Input Channel 0 Complement of Port C in the HDMI Interface.
8
RXC_0+
HDMI input
Digital Input Channel 0 True of Port C in the HDMI Interface.
9 CGND Ground TVDD and CVDD Ground.
10 RXC_1− HDMI input Digital Input Channel 1 Complement of Port C in the HDMI Interface.
11 RXC_1+ HDMI input Digital Input Channel 1 True of Port C in the HDMI Interface.
12 TVDD Power Receiver Terminator Supply Voltage (3.3 V).
ADV7623 Data Sheet
Rev. D | Page 10 of 16
Pin No. Mnemonic Type Description
13 RXC_2− HDMI input Digital Input Channel 2 Complement of Port C in the HDMI Interface.
14 RXC_2+ HDMI input Digital Input Channel 2 True of Port C in the HDMI Interface.
15 HP_CTRLD Digital output Hot Plug Detect for Port D.
16 5V_DETD Digital input 5 V Detect Pin for Port D in the HDMI Interface.
17
DGND
Ground
DVDD Ground.
18 DVDD Power Digital Supply Voltage (1.8 V).
19 DDCD_SDA Digital I/O HDCP Slave Serial Data Port D. DDCD_SDA is a 3.3 V input/output that is 5 V tolerant.
20 DDCD_SCL Digital input HDCP Slave Serial Clock Port D. DDCD_SCL is a 3.3 V input that is 5 V tolerant.
21 CVDD Power Receiver Comparator Supply Voltage (1.8 V).
22 CGND Ground TVDD and CVDD Ground.
23 RXD_C− HDMI input Digital Input Clock Complement of Port D in the HDMI Interface.
24 RXD_C+ HDMI input Digital Input Clock True of Port D in the HDMI Interface.
25 TVDD Power Receiver Terminator Supply Voltage (3.3 V).
26 RXD_0− HDMI input Digital Input Channel 0 Complement of Port D in the HDMI Interface.
27 RXD_0+ HDMI input Digital Input Channel 0 True of Port D in the HDMI Interface.
28 CGND Ground TVDD and CVDD Ground.
29 RXD_1− HDMI input Digital Input Channel 1 Complement of Port D in the HDMI Interface.
30 RXD_1+ HDMI input Digital Input Channel 1 True of Port D in the HDMI Interface.
31 TVDD Power Receiver Terminator Supply Voltage (3.3 V).
32 RXD_2− HDMI input Digital Input Channel 2 Complement of Port D in the HDMI Interface.
33 RXD_2+ HDMI input Digital Input Channel 2 True of Port D in the HDMI Interface.
34
CVDD
Power
Receiver Comparator Supply Voltage (1.8 V).
35 CGND Ground TVDD and CVDD Ground.
36 TXPVDD Power 1.8 V Power Supply for Digital and I/O Power Supply. This pin supplies power to the
digital logic and I/Os. It should be filtered and as quiet as possible.
37 TXPLVDD Power 1.8 V Power Supply.
38 TXGND Ground TXPVDD Ground.
39 TXPGND Ground TXPLVDD Ground.
40 EXT_SWING Analog input This pin sets the internal reference currents. Place an 887 Ω resistor (1% tolerance) between
this pin and ground.
41 HPD_ARC− Analog input Hot Plug Detect Signal and Audio Return Channel Inverted Input. This pin indicates to the
interface whether the receiver is connected.
42
ARC+
Analog input
Audio Return Channel (ARC) Input (5 V Tolerant).
43 TXDDC_SDA Digital I/O Serial Port Data I/O to Receiver. This pin serves as the master to the DDC bus. It supports a
5 V CMOS logic level.
44 TXDDC_SCL Digital output Serial Port Data Clock to Receiver. This pin serves as the master clock for the DDC bus.
It supports a 5 V CMOS logic level.
45 TXAVDD Power 1.8 V Power Supply for TMDS Outputs.
46
TXGND
Ground
TXAVDD Ground.
47 TXC− HDMI output Differential Clock Output. Differential clock output at the TMDS clock rate; supports
TMDS logic level.
48 TXC+ HDMI output Differential Clock Output. Differential clock output at the TMDS clock rate; supports
TMDS logic level.
49 TXGND Ground TXAVDD Ground.
50 TX0− HDMI output Differential Output Channel 0 Complement. Differential output of the red data at 10×
the pixel clock rate; supports TMDS logic level.
51 TX0+ HDMI output Differential Output Channel 0 True. Differential output of the red data at 10× the pixel clock
rate; supports TMDS logic level.
52 TXGND Ground TXAVDD Ground.
53
TX1−
HDMI output
Differential Output Channel 1 Complement. Differential output of the red data at 10×
the pixel clock rate; supports TMDS logic level.
54 TX1+ HDMI output Differential Output Channel 1 True. Differential output of the red data at 10× the pixel
clock rate; supports TMDS logic level.
55 TXAVDD Power 1.8 V Power Supply for TMDS Outputs.
Data Sheet ADV7623
Rev. D | Page 11 of 16
Pin No. Mnemonic Type Description
56 TX2− HDMI output Differential Output Channel 2 Complement. Differential output of the red data at 10×
the pixel clock rate; supports TMDS logic level.
57 TX2+ HDMI output Differential Output Channel 2 True. Differential output of the red data at 10× the pixel
clock rate; supports TMDS logic level.
58
TXGND
Ground
TXAVDD Ground.
59 CEC Digital I/O Consumer Electronics Control Channel (5 V Tolerant).
60 DGND Ground DVDD Ground.
61 DVDD Power Digital Supply Voltage (1.8 V).
62 ALSB Digital input This pin is used to set the I2C address of the Rx IO and the Tx main map.
63 CS Digital input Chip Select Pin. This pin must be set low or left floating for the chip to process I2C messages
that are destined for the ADV7623. The ADV7623 ignores I2C messages that it receives if
this pin is high.
64 EP_SCK Digital output SPI Clock Interface for the EDID/OSD.
65 EP_CS Digital output SPI Chip Selected Interface for the EDID/OSD.
66 EP_MOSI Digital output SPI Master Out/Slave In for the EDID/OSD.
67
EP_MISO
Digital input
SPI Master In/Slave Out for the EDID/OSD.
68 MCLK_IN Digital input Audio Reference Clock. 128 × N × fS with N = 1, 2, 3, or 4. Set to 128 × sampling frequency (fS),
256 × fS, 384 × fS, or 512 × fS. It supports CMOS logic levels from 1.8 V to 3.3 V.
69 SCLK_IN Digital input I2S Audio Clock. It supports CMOS logic levels from 1.8 V to 3.3 V.
70 AP5_IN Digital input Audio Input Port 5. It supports CMOS logic levels from 1.8 V to 3.3 V.
71 AP4_IN Digital input Audio Input Port 4. It supports CMOS logic levels from 1.8 V to 3.3 V.
72
DGNDIO
Ground
DVDDIO Ground.
73 DVDDIO Power Digital I/O Supply Voltage (3.3 V).
74 AP3_IN Digital input Audio Input Port 3. It supports CMOS logic levels from 1.8 V to 3.3 V.
75 AP2_IN Digital input Audio Input Port 2. It supports CMOS logic levels from 1.8 V to 3.3 V.
76 AP1_IN Digital input Audio Input Port 1. It supports CMOS logic levels from 1.8 V to 3.3 V.
77 AP0_IN Digital input Audio Input Port 0. It supports CMOS logic levels from 1.8 V to 3.3 V.
78 SDATA Digital I/O I2C Port Serial Data Input/Output Pin. SDATA is the data line for the control port.
79 SCL Digital input I2C Port Serial Clock Input. SCL is the clock line for the control port.
80 DGND Ground DVDD Ground.
81 DVDD Power Digital Supply Voltage (1.8 V).
82 INT1
(AMUTE1)
Digital output Interrupt Pin. This pin can be active low or active high. When status bits change, this pin is
triggered. The events that trigger an interrupt are under user control. This pin can also output
an audio mute signal.
83 INT2
(AMUTE2)
Digital output Interrupt Pin. This pin can be active low or active high. When status bits change, this pin is
triggered.
The events that trigger an interrupt are under user control. This pin can also output
an audio mute signal.
84 INT_TX Digital output Interrupt; Open Drain. A 2 kΩ pull-up resistor to the microcontroller I/O supply is recommended.
85 DGNDIO Ground DVDDIO Ground.
86 DVDDIO Power Digital I/O Supply Voltage (3.3 V).
87 AP0_OUT Digital output Audio Output Port 0.
88 AP1_OUT Digital output Audio Output Port 1.
89 AP2_OUT Digital output Audio Output Port 2.
90 AP3_OUT Digital output Audio Output Port 3.
91 AP4_OUT Digital output Audio Output Port 4.
92 DGND Ground DVDD Ground.
93 DVDD Power Digital Supply Voltage (1.8 V).
94 AP5_OUT Digital output Audio Output Port 5.
95 SCLK_OUT Digital output Audio Serial Clock Output.
96
MCLK_OUT
Digital output
Audio Master Clock Output.
97 RESET Digital input System Reset Input. Active low. A minimum low reset pulse width of 5 ms is required to reset
the ADV7623 circuitry.
98 PWRDN Digital input Active Low Power-Down Pin. If used, this pin should be pulled high to power up the
ADV7623. This pin can also be used as an in system power detect where internal EDID can
be powered from a 5 V signal of the HDMI port when it is connected to active equipment.
ADV7623 Data Sheet
Rev. D | Page 12 of 16
Pin No. Mnemonic Type Description
99 PGND Ground PVDD Ground.
100 PVDD Power PLL Supply Voltage (1.8 V).
101 XTAL Miscellaneous
analog
Input pin for 28.63636 MHz crystal or an external 1.8 V 28.63636 MHz clock oscillator source to
clock the ADV7623.
102 XTAL1 Miscellaneous
analog
Crystal Output Pin. This pin should be left floating if a clock oscillator is used.
103 PVDD Power PLL Supply Voltage (1.8 V).
104 PGND Ground PVDD Ground.
105 HP_CTRLA Digital output Hot Plug Detect for Port A.
106 5V_DETA Digital input 5 V Detect Pin for Port A in the HDMI Interface.
107 RTERM Miscellaneous
analog
This pin sets the internal termination resistance. A 500 Ω resistor between this pin and
ground should be used.
108 DDCA_SDA Digital I/O HDCP Slave Serial Data Port A. DDCA_SDA is a 3.3 V input/output that is 5 V tolerant.
109 DDCA_SCL Digital input HDCP Slave Serial Clock Port A. DDCA_SCL is a 3.3 V input that is 5 V tolerant.
110 CVDD Power Receiver Comparator Supply Voltage (1.8 V).
111 CGND Ground TVDD and CVDD Ground.
112 RXA_C− HDMI input Digital Input Clock Complement of Port A in the HDMI Interface.
113 RXA_C+ HDMI input Digital Input Clock True of Port A in the HDMI Interface.
114 TVDD Power Receiver Terminator Supply Voltage (3.3 V).
115 RXA_0− HDMI input Digital Input Channel 0 Complement of Port A in the HDMI Interface.
116
RXA_0+
HDMI input
Digital Input Channel 0 True of Port A in the HDMI Interface.
117
CGND
Ground
TVDD and CVDD Ground.
118 RXA_1− HDMI input Digital Input Channel 1 Complement of Port A in the HDMI Interface.
119 RXA_1+ HDMI input Digital Input Channel 1 True of Port A in the HDMI Interface.
120 TVDD Power Receiver Terminator Supply Voltage (3.3 V).
121 RXA_2− HDMI input Digital Input Channel 2 Complement of Port A in the HDMI Interface.
122 RXA_2+ HDMI input Digital Input Channel 2 True of Port A in the HDMI Interface.
123 HP_CTRLB Digital output Hot Plug Detect for Port B.
124 5V_DETB Digital input 5 V Detect Pin for Port B in the HDMI Interface.
125 DGND Ground DVDD Ground.
126 DVDD Power Digital Supply Voltage (1.8 V).
127 DDCB_SDA Digital I/O HDCP Slave Serial Data Port B. DDCB_SDA is a 3.3 V input/output that is 5 V tolerant.
128
DDCB_SCL
Digital input
HDCP Slave Serial Clock Port B. DDCB_SCL is a 3.3 V input that is 5 V tolerant.
129 CVDD Power Receiver Comparator Supply Voltage (1.8 V).
130 CGND Ground TVDD and CVDD Ground.
131 RXB_C− HDMI input Digital Input Clock Complement of Port B in the HDMI Interface.
132 RXB_C+ HDMI input Digital Input Clock True of Port B in the HDMI Interface.
133 TVDD Power Receiver Terminator Supply Voltage (3.3 V).
134 RXB_0− HDMI input Digital Input Channel 0 Complement of Port B in the HDMI Interface.
135 RXB_0+ HDMI input Digital Input Channel 0 True of Port B in the HDMI Interface.
136 CGND Ground TVDD and CVDD Ground.
137 RXB_1− HDMI input Digital Input Channel 1 Complement of Port B in the HDMI Interface.
138 RXB_1+ HDMI input Digital Input Channel 1 True of Port B in the HDMI Interface.
139 TVDD Power Receiver Terminator Supply Voltage (3.3 V).
140 RXB_2− HDMI input Digital Input Channel 2 Complement of Port B in the HDMI Interface.
141 RXB_2+ HDMI input Digital Input Channel 2 True of Port B in the HDMI Interface.
142 HP_CTRLC Digital output Hot Plug Detect for Port C.
143 5V_DETC Digital input 5 V Detect Pin for Port C in the HDMI Interface.
144 DDCC_SDA Digital I/O HDCP Slave Serial Data Port C. DDCC_SDA is a 3.3 V input/output that is 5 V tolerant.
Data Sheet ADV7623
Rev. D | Page 13 of 16
FUNCTIONAL OVERVIEW
HDMI RECEIVER
The ADV7623 front end incorporates a 4:1 multiplexed HDMI
receiver boasting Xpressview fast switching technology and
support for HDMI features including 3D TV, content type bits,
and advanced features, such as capability discovery and control.
Building on the feature set of existing Analog Devices HDMI
devices, the ADV7623 also offers support for all HDTV formats
up to 36-bit, 1080p Deep Color and all display resolutions up to
UXGA (1600 × 1200 at 60 Hz).
Xpressview fast switching technology, using Analog Devices
hardware-based HDCP engine that minimizes software overhead,
allows switching between any two input ports in less than 1 second.
A key feature of the ADV7623 is the on-chip character-based
OSD generator. The OSD generated can be converted to match
the input format 4:2:2 or 4:4:4 in RGB or YCrCb color space. The
OSD is overlaid at the output resolution for best performance. The
OSD portion of the image is optionally semitransparent using a
5-bit alpha blend between the input video and the OSD. The OSD
font characters are stored in either an external SPI flash or read
directly into the RAM when instructed or can be loaded in to
the on-chip RAM via the SPI or I2C.
With the inclusion of HDCP 1.4, displays can receive encrypted
video content. The HDMI interface of the ADV7623 allows for
authentication of a video receiver, decryption of encoded data
at the receiver, and renewability of that authentication during
transmission as specified by the HDCP 1.4 protocol. Repeater
support is also offered by the ADV7623.
The HDMI receiver offers advanced audio functionality. It supports
multichannel I2S audio for up to eight channels. It also supports
a 6-DSD channel interface with each channel carrying an over-
sampled 1-bit representation of the audio signal as delivered on
SACD. The ADV7623 can also receive HBR audio packet streams
and output them through the HBR interface in an S/PDIF format
conforming to the IEC 60958 standard. S/PDIF is supported via
the HPD back channel. The receiver also contains an audio mute
controller that can detect a variety of conditions that may result
in audible extraneous noise in the audio output. On detection of
these conditions, the audio data can be ramped to prevent audio
clicks or pops.
The ADV7623HDMI receiver incorporates active, programmable
equalization of the HDMI data signals that compensates for the
high frequency losses inherent in HDMI and DVI cabling, especially
at longer lengths and higher frequencies. The receiver also contains
a programmable data island packet interrupt generator.
HDMI TRANSMITTER
The ADV7623 features a single HDMI transmitter supporting
ARC, 3D TV formats as well as all HDTV formats up to 1080p,
36-bit Deep Color.
Supporting both single-ended and differential modes, the ARC
feature simplifies cabling by combining an upstream audio capability
in a conventional HDMI cable.
The transmitter features an on-chip MPU with an I2C master to
perform HDCP operations and EDID reading operations.
I2C INTERFACE
The ADV7623 supports a 2-wire serial (I2C-compatible) micro-
processor bus driving multiple peripherals. The ADV7623 is
controlled by an external I2C master device, such as a micro-
controller.
OTHER FEATURES
Other features include the following:
• Fully qualified software low level libraries, driver, and
application
• Complete input and output audio support
• Programmable interrupt request output pins: INT1, INT2,
and INT_TX
• Chip select
• Non-HDCP professional variant available
(ADV7623BSTZ-P). No evaluation board is available
for this variant.
• Low power consumption: 1.8 V digital core, 1.8 V analog,
and 3.3 V digital input/output, low power power-down
mode, and green PC mode
• Temperature range: 0°C to 70°C
• 20 mm × 20 mm, Pb-free, 144-lead LQFP
For more detailed product information about the ADV7623,
contact your local Analog Devices sales office.
ADV7623 Data Sheet
Rev. D | Page 14 of 16
OUTLINE DIMENSIONS
COM P LI ANT TO JE DEC STANDARDS M S-026-BFB
051706-A
0.27
0.22
0.17
1
36
37
73
72
108
144 109
TOP VIEW
(PINS DOWN)
0.50
BSC
LEAD PITCH
1.60
MAX
0.75
0.60
0.45
VIEW A
PIN 1
1.45
1.40
1.35
0.15
0.05
0.20
0.09
0.08
COPLANARITY
VIEW A
ROTATED 90° CCW
SEATING
PLANE
7°
3.5°
0°
22.20
22.00 SQ
21.80
20.20
20.00 SQ
19.80
Figure 6. 144-Lead Low Profile Quad Flat Package [LQFP]
(ST-144)
Dimensions shown in millimeters
ORDERING GUIDE
Model1 Model Description
Temperature
Range Package Description
Package
Option
ADV7623BSTZ HDCP Transceiver 0°C to 70°C 144-Lead Low Profile Quad Flat Package [LQFP] ST-144
ADV7623BSTZ-RL HDCP Transceiver (Reel) 0°C to 70°C 144-Lead Low Profile Quad Flat Package [LQFP] ST-144
ADV7623BSTZ-P Non-HDCP Transceiver 0°C to 70°C 144-Lead Low Profile Quad Flat Package [LQFP] ST-144
ADV7623BSTZ-P-RL Non-HDCP Transceiver (Reel) 0°C to 70°C 144-Lead Low Profile Quad Flat Package [LQFP] ST-144
EVAL-ADV7623EB1Z HDCP Transceiver Evaluation Board Evaluation Board
1 Z = RoHS Compliant Part.
Data Sheet ADV7623
Rev. D | Page 15 of 16
NOTES
ADV7623 Data Sheet
Rev. D | Page 16 of 16
NOTES
I2C refers to a communications protocol originally developed by Phillips Semiconductors (now NXP Semiconductors).
HDMI, the HDMI Logo, and High-Definition Multimedia Interface are trademarks or registered trademarks of HDMI Licensing LLC in the United States and other
countries.
©2013 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D08302-0-3/13(D)
