30008326
Vphase=10V
CH1 = CO, 5V/Div
CH2 = COMP, 5/Div
CH3 = Iout, 10A/Div
CH4 = SSPR Switch Signal, 4V/Div
Horizontal Resolution= 20 µs/Div
FIGURE 14. SSPR Short Circuit Transient (No-Load to
Short-Circuit)
Negative Current Limit
Under certain conditions synchronous buck regulators are
capable of sinking current from the output capacitors. This
energy is stored in the inductor and returned to the input
source. The LM25115A detects this current reversal by de-
tecting a negative voltage being developed across the current
sense resistor. The intent of this negative current comparator
is to protect the low-side MOSFET from excessive currents.
Excessive negative current can also lead to a large positive
voltage spike on the HS pin at the turn-off of the low-side
MOSFET. This voltage spike may damage the chip if its mag-
nitude exceeds the maximum voltage rating of the part. The
negative current comparator threshold is sufficiently negative
to allow inductor current to reverse at no load or light load
conditions. It is not intended to support discontinuous con-
duction mode with diode emulation by the low-side MOSFET.
The negative current comparator shown in Figure 11 monitors
the CV signal and compares this signal to a fixed 1V thresh-
old. This corresponds to a negative VCL voltage between CS
and VOUT of -17mV. The negative current limit comparator
turns off the low-side MOSFET for the remainder of the cycle
when the VCL input falls below this threshold.
Gate Driver Outputs (HO & LO)
The LM25115A provides two gate driver outputs, the floating
high-side gate driver HO and the synchronous rectifier low-
side driver LO. The low-side driver is powered directly by the
VCC regulator. The high-side gate driver is powered from a
bootstrap capacitor connected between HB and HS. An ex-
ternal diode connected between VCC and HB charges the
bootstrap capacitor when the HS is low. When the high-side
MOSFET is turned on, HB rises with HS to a peak voltage
equal to VCC + VHS - VD where VD is the forward drop of the
external bootstrap diode. Both output drivers have adaptive
dead-time control to avoid shoot through currents. The adap-
tive dead-time control circuit monitors the state of each driver
to ensure that one MOSFET is turned off before the other is
turned on. The HB and VCC capacitors should be placed
close to the pins of the LM25115A to minimize voltage tran-
sients due to parasitic inductances and the high peak output
currents of the drivers. The recommended range of the HB
capacitor is 0.047µF to 0.22µF.
Both drivers are controlled by the PWM logic signal from the
PWM latch. When the phase signal is low, the outputs are
held in the reset state with the low-side MOSFET on and the
high-side MOSFET off. When the phase signal switches to
the high state, the PWM latch reset signal is de-asserted. The
high-side MOSFET remains off until the PWM latch is set by
the PWM comparator (CRMIX > CV as shown in Figure 9).
When the PWM latch is set, the LO driver turns off the low-
side MOSFET and the HO driver turns on the high-side MOS-
FET. The high-side pulse is terminated when the phase signal
falls and SYNC input comparator resets the PWM latch.
Thermal Protection
Internal thermal shutdown circuitry is provided to protect the
integrated circuit in the event the maximum junction temper-
ature limit is exceeded. When activated, typically at 165 de-
grees Celsius, the controller is forced into a low power
standby state with the output drivers and the bias regulator
disabled. The device will restart when the junction tempera-
ture falls below the thermal shutdown hysteresis, which is
typically 25 degrees. The thermal protection feature is pro-
vided to prevent catastrophic failures from accidental device
overheating.
Standalone DC/DC Synchronous
Buck Mode
The LM25115A can be configured as a standalone DC/DC
synchronous buck controller. In this mode the LM25115A us-
es leading edge modulation in conjunction with valley current
mode control to control the synchronous buck power stage.
The internal oscillator within the LM25115A sets the clock
frequency for the high and low-side drivers of the external
synchronous buck power MOSFETs . The clock frequency in
the synchronous buck mode is programmed by the SYNC pin
resistor and RAMP pin capacitor. Connecting a resistor be-
tween a dc bias supply and the SYNC pin produces a current,
ISYNC, which sets the charging current of the RAMP pin ca-
pacitor. The RAMP capacitor is charged until its voltage
reaches the peak ramp threshold of 2.25V. The RAMP ca-
pacitor is then discharged for 300ns before beginning a new
PWM cycle. The 300ns reset time of the RAMP pin sets the
minimum off-time of the PWM controller in this mode. The in-
ternal clock frequency in the synchronous buck mode is set
by ISYNC, the ramp capacitor, the peak ramp threshold, and
the 300ns deadtime.
FCLK ≊ 1 / ((CRAMP x 2.25V) / (ISYNC x 3) + 300ns)
See the LM5115 dc evaluation board application note
(AN-1367) for more details on the synchronous buck mode.
Please note that LM25115A is similar to LM5115 except for
the tracking feature.
www.national.com 16
LM25115A