DATA SH EET
Product data sheet 2003 Apr 28
DISCRETE SEMICONDUCTORS
PESD5V2S18U
ESD protection array
M3D574
2003 Apr 28 2
NXP Semiconductors Product data sheet
ESD protection array PESD5V2S18U
FEATURES
Uni-directional ESD protection of
up to 18 lines
Maximum peak reverse po wer:
PPP = 100 W at tp = 8/20 µs
Low clamping voltage:
VCL = 12 V max. at IZSM = 10 A
Low leakage current:
IR = 100 nA typ. at VRWM = 5.2 V
IEC 61000-4-2, level 4 (ESD);
15 kV (air) and 8 kV (contact).
APPLICATIONS
Printer parallel ports
Computers and pe ripherals
Communication syste ms.
DESCRIPTION
Monolithic ESD prot ection device
designed to protect up to
18 transmission or data lines from the
damage caused by electrostatic
discharge (ESD) and surge puls es.
PINNING
PIN DESCRIPTION
1 to 5 cathode (k1 to k5)
6 and 16 common anode (a1; a2)
7 to 15 cathode (k6 to k14)
17 to 20 cathode (k 15 to k18)
handbook, 4 columns
MHC510
19
18
17
16
15
14
13
12
11
20
2
3
4
5
6
7
8
9
10
1
1
10
20
11
Fig.1 Simplified outline (SSOP20; SOT339-1) and symbol.
LIMITING VALUES
In accordance with the A bsolute Maxi m u m Rating System (IEC 60134).
ESD standards compliance
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
IPP non-repetitive peak reverse current tp = 8/20 µs10 A
PPP non-repetitive pea k reverse power
dissipation tp = 8/20 µs100 W
Tstg storage temperature 65 +150 °C
Tjjunction temperature 65 +150 °C
electrostatic dischar ge voltage IEC 61000-4-2 (c ontact discharge) 30 kV
HBM MIL-St d 883 10 kV
IEC 61000-4-2, level 4 (ESD) >15 kV (air); >8 kV (contact)
HBM MIL-Std 883, class 3 >4 kV
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ESD protection array PESD5V2S18U
THERMAL CHARACTE RISTICS
Note
1. Refer to SOT339-1 standard mounting conditions.
ELECTRICAL CHARACTERISTIC S
Tamb = 25 °C unless otherwise specified.
SYMBOL PARAMETER CONDITIONS VALUE UNIT
Rth j-a thermal resistance from junction to
ambient one or more diodes loaded 135 K/W
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
VRWM crest working reverse
voltage 5.2 V
IRreverse current VRWM = 5.2 V 0.1 1µA
VCL clamping voltage IZSM = 3 A; tp = 8/20 µs; see Fig.5 8 V
IZSM = 10 A; tp = 8/20 µs; see Fig.5 12 V
VBR breakdown voltage IZ = 5 mA 6.4 6.8 7.2 V
rdiff differential resistance IZ = 1 mA 40
IZ = 5 mA 8
Cddiode capacitan ce VR = 0; f = 1 MHz; see Fig.4 100 pF
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ESD protection array PESD5V2S18U
handbook, halfpage
103
102
10
MHC485
102101110
tp (ms)
PZSM
(W)
Fig.2 Maximum non-repetitive pea k re verse
power as a func tion of pulse duration.
handbook, halfpage
102
10
1
MHC486
102101110
tp (ms)
IZSM
(A)
Fig.3 Maximum non-repetitive pea k re verse
current as a func tion of pulse duration.
handbook, halfpage
40 01
Cd
(pF)
35
VR (V)
26
50
60
70
80
90
100
110
4
MHC487
Fig.4 Diode capacitance as a function of reverse
voltage; typical values.
f = 1 MHz; Tamb = 25 °C
handbook, halfpage
3 56789104
11
10
8
7
9
MHC488
VCL
(V)
IPP(A)
Fig.5 Clamping voltage as a functio n of pe ak
reverse pulse current; typical values.
tp = 8/20 µs
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ESD protection array PESD5V2S18U
MHC489
450
50
Note 1: attenuator is only used for open
socket high voltage measurements
IEC 1000-4-2 network
CZ = 150 pF; RZ = 330
1/18 PESD5V2S18U
RG 223/U
50 coax
RZ
CZ
ESD TESTER DIGITIZING
OSCILLOSCOPE
10×
ATTENUATOR
note 1
GND
unclamped +1 kV ESD voltage waveform
(IEC 100042 network) clamped +1 kV ESD voltage waveform
(IEC 100042 network)
unclamped 1 kV ESD voltage waveform
(IEC 100042 network) clamped 1 kV ESD voltage waveform
(IEC 100042 network)
GND
GND
GND
vertical scale = 200 V/Div
horizontal scale = 50 ns/Div vertical scale = 5 V/Div
horizontal scale = 50 ns/Div
vertical scale = 200 V/Div
horizontal scale = 50 ns/Div vertical scale = 5 V/Div
horizontal scale = 50 ns/Div
Fig.6 ESD clamping test set-up an d waveforms.
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ESD protection array PESD5V2S18U
PACKAGE OUTLINE
UNIT A1A2A3bpcD
(1) E(1) eH
ELL
pQ(1)
Zywv θ
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm 0.21
0.05 1.80
1.65 0.38
0.25 0.20
0.09 7.4
7.0 5.4
5.2 0.65 7.9
7.6 0.9
0.7 0.9
0.5 8
0
o
o
0.131.25 0.2 0.1
DIMENSIONS (mm are the original dimensions)
Note
1. Plastic or metal protrusions of 0.2 mm maximum per side are not included.
1.03
0.63
SOT339-1 MO-150 99-12-27
03-02-19
X
wM
θ
A
A1
A2
bp
D
HE
Lp
Q
detail X
E
Z
e
c
L
vMA
(A )
3
A
110
20 11
y
0.25
pin 1 index
0 2.5 5 mm
scale
S
SOP20: plastic shrink small outline package; 20 leads; body width 5.3 mm SOT339
-1
A
max.
2
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NXP Semiconductors Pr oduct data shee t
ESD protection array PESD5V2S18U
DATA SHEET STATUS
Notes
1. Please consult the most rec en tly issued document before initiating or co mpleting a design.
2. The product s tatus of device(s ) described in this document may have changed since this document was published
and may differ in case of multiple devices. The latest product status information is available on the Internet at
URL http://www.nxp.com.
DOCUMENT
STATUS(1) PRODUCT
STATUS(2) DEFINITION
Objective data sheet Development This document contains data from the objective specification for pro duct
development.
Preliminary data sheet Qualification This document contains data from the preliminary specification.
Product data sheet Production T his document contains the product specification.
DISCLAIMERS
General Information in this document is believed to be
accurate and reliable . H ow ev er, NXP Semiconductors
does not give any representations or warranties,
expressed or implied, as to the accuracy or completeness
of such information and shall have no liability for the
consequenc es of use of such information.
Right to make changes NXP Semiconductors
reserves the right to make changes to informa t ion
published in this doc ument, including without limitation
specifications and product descriptions, at any time and
without notice. This document supersedes and replaces all
information supplied prior to the publication hereof.
Suitability for use NXP Semiconductors products are
not designed, au thorized or warran ted to be suitable for
use in medical, military, aircraft, space or life support
equipment, nor in applications where failure or malfunction
of an NXP Semiconductors product can reason ably be
expected to result in pe rs onal injury, death or severe
property or environmental damage. NXP Semiconductors
accepts no liability for inclusion and/or use of NXP
Semiconductors products in such equipment or
applications and therefor e s uc h inclusion and/or use is at
the customer’s own risk .
Applications Applications that are described herein for
any of these products are for illustrative purposes only.
NXP Semiconductors makes no representation or
warranty that such applications will be suitable for the
specified use witho ut fu rth e r testing or modification .
Limiting values Stress above one or more limiting
values (as defined in the Absolute Maximum Ratings
System of IEC 60134) may cause permanent damage to
the device. Limiting values a re s t ress ratings only and
operation of the device at these or an y other conditions
above those given in the Characteristics sections of this
document is not implied. Exposure to limiting values for
extended periods may affect device reliability.
Terms and conditions of sale NXP Semiconductors
products are sold subject to the general terms and
conditions of commercial sale, as published at
http://www.nxp.com/profile/terms, including those
pertaining to warranty, intellectual property rights
infringement and limitation of liability, unless explicitly
otherwise agreed to in writing by NXP Semiconductors. In
case of any incons istency or conflict betwee n information
in this document an d such terms and conditio ns, the latter
will prevail.
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may be interpreted or construed as an offer to sell products
that is open for accept ance or the grant, conveyance or
implication of any license under any copyrights, patents or
other industr i al or inte llectual property righ ts.
Export control This document as well as the item(s)
described herein may be subject to export control
regulations. Export might require a prior authorization from
national author ities.
Quick refer ence data The Quick reference data is an
extract of th e product data given in the Limiting values an d
Characteristics sections of this document, and as such is
not complete, exhaus tive or legally binding.
NXP Semiconductors
Contact information
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© NXP B.V. 2009
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information pr e sent ed in this document d oes not form part of an y q uot ation or co ntract, is believed to be a ccur ate a nd re li a ble and may be chan ged
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Customer notification
This data sheet was changed to reflect the new company name NXP Semiconductors. No change s were
made to the content, except for the legal definitions and disclaimers.
Printed in The Netherlands 613514/01/pp8 Date of release: 2003 Apr 28 Document orde r number: 9397 750 10889