 
  
  
SCLS035E − MARCH 1984 − REVISED NOVEMBER 2004
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DWide Operating Voltage Range of 2 V to 6 V
DOperation From Very Slow Input
Transitions
DSame Pinouts as ’HC08
DOutputs Can Drive Up To 10 LSTTL Loads
DLow Power Consumption, 20-µA Max ICC
DTypical tpd = 14 ns
D±4-mA Output Drive at 5 V
DLow Input Current of 1 µA Max
DAllow Design of Either RC or Crystal
Oscillator Circuits
DTemperature-Compensated Threshold
Levels
DHigh Noise Immunity
description/ordering information
Each circuit functions as a quadruple AND gate.
They perform the Boolean function
Y+A•BorY+A)B in positive logic.
Because of the Schmitt action, the inputs have
different input threshold levels for positive- and
negative-going signals.
These circuits are temperature compensated and
can be triggered from the slowest of input ramps
and still give clean jitter-free output signals.
ORDERING INFORMATION
TAPACKAGE†ORDERABLE
PART NUMBER TOP-SIDE
MARKING
PDIP − N Tube of 25 SN74HC7001N SN74HC7001N
Tube of 50 SN74HC7001D
−40°C to 85°CSOIC − D Reel of 2500 SN74HC7001DR HC7001
−40 C to 85 C
SOIC − D
Reel of 250 SN74HC7001DT
HC7001
SOP − NS Reel of 2000 SN74HC7001NSR HC7001
CDIP − J Tube of 25 SNJ54HC7001J SNJ54HC7001J
−55°C to 125°CCFP − W Tube of 150 SNJ54HC7001W SNJ54HC7001W
−55 C to 125 C
LCCC − FK Tube of 55 SNJ54HC7001FK SNJ54HC7001FK
†Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.
Copyright 2004, Texas Instruments Incorporated
    !"#$%& "!&'& 
 &(!)$'!& "#))%& ' !( *#+,"'!& '%- )!#" "!&(!)$ !
*%"("'!& *%) % %)$ !( %.' &)#$%& '&') /'))'&0-
)!#"!& *)!"%&1 !% &! &%"%'),0 &",#% %&1 !( ',,
*')'$%%)-
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SN54HC7001 ...J OR W PACKAGE
SN74HC7001 . . . D, N, OR NS PACKAGE
(TOP VIEW)
SN54HC7001 . . . FK PACKAGE
(TOP VIEW)
NC − No internal connection
1
2
3
4
5
6
7
14
13
12
11
10
9
8
1A
1B
1Y
2A
2B
2Y
GND
VCC
4B
4A
4Y
3B
3A
3Y
3212019
910111213
4
5
6
7
8
18
17
16
15
14
4A
NC
4Y
NC
3B
1Y
NC
2A
NC
2B
1B
1A
NC
3Y
3A V
4B
2Y
GND
NC
CC
 
  
  
SCLS035E − MARCH 1984 − REVISED NOVEMBER 2004
2POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
FUNCTION TABLE
(each gate)
INPUTS
OUTPUT
A B
OUTPUT
Y
H H H
LXL
X L L
logic diagram, each gate (positive logic)
A
B
Y
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC −0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, IIK (VI < 0 or VI > VCC) (see Note 1) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, IOK (VO < 0 or VO > VCC) (see Note 1) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current, IO (VO = 0 to VCC) ±25 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through VCC or GND ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θJA (see Note 2): D package 86°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
N package 80°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NS package 76°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, Tstg −65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 3)
SN54HC7001 SN74HC7001
UNIT
MIN NOM MAX MIN NOM MAX
UNIT
VCC Supply voltage 2 5 6 2 5 6 V
VIInput voltage 0 VCC 0 VCC V
VOOutput voltage 0 VCC 0 VCC V
TAOperating free-air temperature −55 125 −40 85 °C
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
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%1& *'% !( %2%,!*$%&- ')'"%)" '' '& !%)
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"'&1% !) "!&&#% %% *)!#" /!# &!"%-
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  
  
SCLS035E − MARCH 1984 − REVISED NOVEMBER 2004
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
TA = 25°C SN54HC7001 SN74HC7001
UNIT
PARAMETER
TEST CONDITIONS
V
CC MIN TYP MAX MIN MAX MIN MAX
UNIT
2 V 0.7 1.2 1.5 0.7 1.5 0.7 1.5
V
T+
4.5 V 1.55 2.5 3.15 1.55 3.15 1.55 3.15 V
VT+
6 V 2.1 3.3 4.2 2.1 4.2 2.1 4.2
V
2 V 0.3 0.6 1 0.3 1 0.3 1
V
T−
4.5 V 0.9 1.6 2.45 0.9 2.45 0.9 2.45 V
VT−
6 V 1.2 2 3.2 1.2 3.2 1.2 3.2
V
2 V 0.2 0.6 1.2 0.2 1.2 0.2 1.2
V
V
T+
− V
T−
4.5 V 0.4 0.9 2.1 0.4 2.1 0.4 2.1 V
VT+ − VT−
6 V 0.5 1.3 2.5 0.5 2.5 0.5 2.5 V
2 V 1.9 1.998 1.9 1.9
I
OH
= −20 µA4.5 V 4.4 4.499 4.4 4.4
V
OH
V
= V
or V
IOH = −20 µA
6 V 5.9 5.999 5.9 5.9 V
VOH
IOH = −4 mA 4.5 V 3.98 4.3 3.7 3.84
V
IOH = −5.2 mA 6 V 5.48 5.8 5.2 5.34
2 V 0.002 0.1 0.1 0.1
I
OL
= 20 µA4.5 V 0.001 0.1 0.1 0.1
V
OL
V
= V
or V
IOL = 20 µA
6 V 0.001 0.1 0.1 0.1 V
VOL
IOL = 4 mA 4.5 V 0.17 0.26 0.4 0.33
V
IOL = 5.2 mA 6 V 0.15 0.26 0.4 0.33
IIVI = VCC or 0 6 V ±0.1 ±100 ±1000 ±1000 nA
ICC VI = VCC or 0, IO = 0 6 V 2 40 20 µA
Ci2 V to 6 V 3 10 10 10 pF
switching characteristics over recommended operating free-air temperature range, CL = 50 pF
(unless otherwise noted) (see Figure 1)
PARAMETER
FROM
TO
VCC
TA = 25°C SN54HC7001 SN74HC7001
UNIT
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
V
CC MIN TYP MAX MIN MAX MIN MAX
UNIT
2 V 60 130 195 163
t
pd
A or B Y4.5 V 18 26 39 33 ns
tpd
A or B
Y
6 V 14 22 33 28
ns
2 V 28 75 110 95
t
t
Any 4.5 V 8 15 22 19 ns
tt
Any
6 V 6 13 19 16
ns
operating characteristics, TA = 25°C
PARAMETER TEST CONDITIONS TYP UNIT
Cpd Power dissipation capacitance per gate No load 20 pF
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*%"("'!& ')% %1& 1!',- %.' &)#$%& )%%)2% % )1 !
"'&1% !) "!&&#% %% *)!#" /!# &!"%-
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  
  
SCLS035E − MARCH 1984 − REVISED NOVEMBER 2004
4POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
VOLTAGE WAVEFORM
INPUT RISE AND FALL TIMES
50%50% 10%10% 90% 90% VCC
0 V
trtf
Input
VOLTAGE WAVEFORMS
PROPAGATION DELAY AND OUTPUT TRANSITION TIMES
50%
50%50% 10%10% 90% 90%
V
CC
VOH
VOL
0 V
trtf
Input
In-Phase
Output
50%
tPLH tPHL
50% 50%
10% 10% 90%90% VOH
VOL
tr
tf
tPHL tPLH
Out-of-Phase
Output
Test
Point
From Output
Under Test
CL = 50 pF
(see Note A)
LOAD CIRCUIT
NOTES: A. CL includes probe and test-fixture capacitance.
B. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following
characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 6 ns, tf = 6 ns.
C. The outputs are measured one at a time, with one input transition per measurement.
D. t
PLH
and t
PHL
are the same as t
pd
.
Figure 1. Load Circuit and Voltage Waveforms
PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
SN74HC7001D ACTIVE SOIC D 14 50 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74HC7001DE4 ACTIVE SOIC D 14 50 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74HC7001DG4 ACTIVE SOIC D 14 50 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74HC7001DR ACTIVE SOIC D 14 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74HC7001DRE4 ACTIVE SOIC D 14 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74HC7001DRG4 ACTIVE SOIC D 14 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74HC7001DT ACTIVE SOIC D 14 250 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74HC7001DTE4 ACTIVE SOIC D 14 250 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74HC7001DTG4 ACTIVE SOIC D 14 250 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74HC7001N ACTIVE PDIP N 14 25 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type
SN74HC7001N3 OBSOLETE PDIP N 14 TBD Call TI Call TI
SN74HC7001NE4 ACTIVE PDIP N 14 25 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
PACKAGE OPTION ADDENDUM
www.ti.com 11-Nov-2009
Addendum-Page 1
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com 11-Nov-2009
Addendum-Page 2
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
SN74HC7001DR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
SN74HC7001DT SOIC D 14 250 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN74HC7001DR SOIC D 14 2500 367.0 367.0 38.0
SN74HC7001DT SOIC D 14 250 367.0 367.0 38.0
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
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