STM32F215xx STM32F217xx ARM-based 32-bit MCU, 150DMIPs, up to 1 MB Flash/128+4KB RAM, crypto, USB OTG HS/FS, Ethernet, 17 TIMs, 3 ADCs, 15 comm. interfaces & camera Features FBGA Core: ARM 32-bit CortexTM-M3 CPU with Adaptive real-time accelerator (ART AcceleratorTM) allowing 0-wait state execution performance from Flash memory, frequency up to 120 MHz, memory protection unit, 150 DMIPS/1.25 DMIPS/MHz (Dhrystone 2.1) Memories - Up to 1 Mbyte of Flash memory - 512 bytes of OTP memory - Up to 128 + 4 Kbytes of SRAM - Flexible static memory controller that supports Compact Flash, SRAM, PSRAM, NOR and NAND memories - LCD parallel interface, 8080/6800 modes Clock, reset and supply management - From 1.8 to 3.6 V application supply and I/Os - POR, PDR, PVD and BOR - 4 to 26 MHz crystal oscillator - Internal 16 MHz factory-trimmed RC (1% accuracy at 25 C) - 32 kHz oscillator for RTC with calibration - Internal 32 kHz RC with calibration Low power - Sleep, Stop and Standby modes - VBAT supply for RTC, 20 x 32 bit backup registers, and optional 4 KB backup SRAM 3 x 12-bit, 0.5 s A/D converters - up to 24 channels - up to 6 MSPS in triple interleaved mode 2 x 12-bit D/A converters General-purpose DMA - 16-stream DMA controller with centralized FIFOs and burst support Up to 17 timers - Up to twelve 16-bit and two 32-bit timers, up to 120 MHz, each with up to 4 IC/OC/PWM or pulse counter and quadrature (incremental) encoder input Debug mode - Serial wire debug (SWD) & JTAG interfaces - Cortex-M3 Embedded Trace MacrocellTM December 2011 LQFP64 (10 x 10 mm) LQFP100 (14 x 14 mm) LQFP144 (20 x 20 mm) LQFP176 (24 x 24 mm)(1) UFBGA176 (10 x 10 mm) Up to 140 I/O ports with interrupt capability: - Up to 136 fast I/Os up to 60 MHz - Up to 138 5 V-tolerant I/Os Up to 15 communication interfaces - Up to 3 x I2C interfaces (SMBus/PMBus) - Up to 4 USARTs and 2 UARTs (7.5 Mbit/s, ISO 7816 interface, LIN, IrDA, modem control) - Up to 3 SPIs (30 Mbit/s), 2 with muxed I2S to achieve audio class accuracy via audio PLL or external PLL - 2 x CAN interfaces (2.0B Active) - SDIO interface Advanced connectivity - USB 2.0 full-speed device/host/OTG controller with on-chip PHY - USB 2.0 high-speed/full-speed device/host/OTG controller with dedicated DMA, on-chip full-speed PHY and ULPI - 10/100 Ethernet MAC with dedicated DMA: supports IEEE 1588v2 hardware, MII/RMII 8- to 14-bit parallel camera interface: up to 48 Mbyte/s Cryptographic acceleration - Hardware acceleration for AES 128, 192, 256, Triple DES, HASH (MD5, SHA-1) - Analog true random number generator CRC calculation unit 96-bit unique ID Analog true random number generator Table 1. Reference Device summary Part number STM32F215xx STM32F215RG, STM32F215VG, STM32F215ZG, STM32F215RE, STM32F215VE, STM32F215ZE STM32F217xx STM32F217VG, STM32F217IG, STM32F217ZG, STM32F217VE, STM32F217IE, STM32F217ZE Doc ID 17050 Rev 6 1/168 www.st.com 1 Contents STM32F215xx, STM32F217xx Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2/168 2.1 Full compatibility throughout the family . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.2 Device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.2.1 ARM(R) CortexTM-M3 core with embedded Flash and SRAM . . . . . . . . . 17 2.2.2 Adaptive real-time memory accelerator (ART AcceleratorTM) . . . . . . . . 17 2.2.3 Memory protection unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.2.4 Embedded Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.2.5 CRC (cyclic redundancy check) calculation unit . . . . . . . . . . . . . . . . . . 18 2.2.6 Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.2.7 Multi-AHB bus matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.2.8 DMA controller (DMA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.2.9 Flexible static memory controller (FSMC) . . . . . . . . . . . . . . . . . . . . . . . 19 2.2.10 Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . 20 2.2.11 External interrupt/event controller (EXTI) . . . . . . . . . . . . . . . . . . . . . . . 20 2.2.12 Clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.2.13 Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.2.14 Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.2.15 Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.2.16 Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.2.17 Real-time clock (RTC), backup SRAM and backup registers . . . . . . . . 23 2.2.18 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 2.2.19 VBAT operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 2.2.20 Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 2.2.21 Inter-integrated circuit interface (IC) . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 2.2.22 Universal synchronous/asynchronous receiver transmitters (UARTs/USARTs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 2.2.23 Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 2.2.24 Inter-integrated sound (I2S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 2.2.25 SDIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 2.2.26 Ethernet MAC interface with dedicated DMA and IEEE 1588 support . 29 2.2.27 Controller area network (CAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 2.2.28 Universal serial bus on-the-go full-speed (OTG_FS) . . . . . . . . . . . . . . . 30 Doc ID 17050 Rev 6 STM32F215xx, STM32F217xx Contents 2.2.29 Universal serial bus on-the-go high-speed (OTG_HS) . . . . . . . . . . . . . 30 2.2.30 Audio PLL (PLLI2S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 2.2.31 Digital camera interface (DCMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 2.2.32 Cryptographic acceleration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 2.2.33 True random number generator (RNG) . . . . . . . . . . . . . . . . . . . . . . . . . 32 2.2.34 GPIOs (general-purpose inputs/outputs) . . . . . . . . . . . . . . . . . . . . . . . . 33 2.2.35 ADCs (analog-to-digital converters) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 2.2.36 DAC (digital-to-analog converter) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 2.2.37 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 2.2.38 Serial wire JTAG debug port (SWJ-DP) . . . . . . . . . . . . . . . . . . . . . . . . . 34 2.2.39 Embedded Trace MacrocellTM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 3 Pinouts and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 4 Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 5 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 5.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 5.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 5.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 5.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 5.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 5.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 5.1.6 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 5.1.7 Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 5.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 5.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 5.3.1 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 5.3.2 VCAP1/VCAP2 external capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 5.3.3 Operating conditions at power-up / power-down (regulator ON) . . . . . . 65 5.3.4 Operating conditions at power-up / power-down (regulator OFF) . . . . . 65 5.3.5 Embedded reset and power control block characteristics . . . . . . . . . . . 66 5.3.6 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 5.3.7 Wakeup time from low-power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 5.3.8 External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 5.3.9 Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 5.3.10 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Doc ID 17050 Rev 6 3/168 Contents 6 7 STM32F215xx, STM32F217xx 5.3.11 PLL spread spectrum clock generation (SSCG) characteristics . . . . . . 87 5.3.12 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 5.3.13 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 5.3.14 Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . . 92 5.3.15 I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 5.3.16 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 5.3.17 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 5.3.18 TIM timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 5.3.19 Communications interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 5.3.20 12-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 5.3.21 DAC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 5.3.22 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 5.3.23 VBAT monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 5.3.24 Embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 5.3.25 FSMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 5.3.26 Camera interface (DCMI) timing specifications . . . . . . . . . . . . . . . . . . 139 5.3.27 SD/SDIO MMC card host interface (SDIO) characteristics . . . . . . . . . 139 5.3.28 RTC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 6.1 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 6.2 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 Appendix A Application block diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 8 4/168 A.1 Main applications versus package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 A.2 Application example with regulator OFF . . . . . . . . . . . . . . . . . . . . . . . . . 152 A.3 USB OTG full speed (FS) interface solutions . . . . . . . . . . . . . . . . . . . . . 152 A.4 USB OTG high speed (HS) interface solutions . . . . . . . . . . . . . . . . . . . . 154 A.5 Complete audio player solutions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 A.6 Ethernet interface solutions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 Doc ID 17050 Rev 6 STM32F215xx, STM32F217xx List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. Table 39. Table 40. Table 41. Table 42. Table 43. Table 44. Table 45. Table 46. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 STM32F215xx and STM32F217xx: features and peripheral counts. . . . . . . . . . . . . . . . . . 12 Timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 USART feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 STM32F21x pin and ball definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Alternate function mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Limitations depending on the operating power supply range . . . . . . . . . . . . . . . . . . . . . . . 62 VCAP1/VCAP2 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Operating conditions at power-up / power-down (regulator ON) . . . . . . . . . . . . . . . . . . . . 65 Operating conditions at power-up / power-down (regulator OFF). . . . . . . . . . . . . . . . . . . . 65 Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 66 Typical and maximum current consumption in Run mode, code with data processing running from Flash memory (ART accelerator disabled) . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Typical and maximum current consumption in Run mode, code with data processing running from Flash memory (ART accelerator enabled) or RAM . . . . . . . . . . . . . . . . . . . 69 Typical and maximum current consumption in Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . 72 Typical and maximum current consumptions in Stop mode . . . . . . . . . . . . . . . . . . . . . . . . 74 Typical and maximum current consumptions in Standby mode . . . . . . . . . . . . . . . . . . . . . 75 Typical and maximum current consumptions in VBAT mode. . . . . . . . . . . . . . . . . . . . . . . . 75 Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 HSE 4-26 MHz oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 LSE oscillator characteristics (fLSE = 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 HSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Main PLL characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 PLLI2S (audio PLL) characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 SSCG parameters constraint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Flash memory programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Flash memory programming with VPP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 Flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 Characteristics of TIMx connected to the APB1 domain . . . . . . . . . . . . . . . . . . . . . . . . . . 99 Doc ID 17050 Rev 6 5/168 List of tables Table 47. Table 48. Table 49. Table 50. Table 51. Table 52. Table 53. Table 54. Table 55. Table 56. Table 57. Table 58. Table 59. Table 60. Table 61. Table 62. Table 63. Table 64. Table 65. Table 66. Table 67. Table 68. Table 69. Table 70. Table 71. Table 72. Table 73. Table 74. Table 75. Table 76. Table 77. Table 78. Table 79. Table 80. Table 81. Table 82. Table 83. Table 84. Table 85. Table 86. Table 87. Table 88. Table 89. Table 90. Table 91. 6/168 STM32F215xx, STM32F217xx Characteristics of TIMx connected to the APB2 domain . . . . . . . . . . . . . . . . . . . . . . . . . 100 I2C characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 SCL frequency (fPCLK1= 30 MHz.,VDD = 3.3 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 I2S characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 USB OTG FS startup time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 USB OTG FS DC electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 USB OTG FS electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 USB HS DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 Clock timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 ULPI timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 Ethernet DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 Dynamics characteristics: Ethernet MAC signals for SMI. . . . . . . . . . . . . . . . . . . . . . . . . 111 Dynamics characteristics: Ethernet MAC signals for RMII . . . . . . . . . . . . . . . . . . . . . . . . 111 Dynamics characteristics: Ethernet MAC signals for MII . . . . . . . . . . . . . . . . . . . . . . . . . 112 ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 ADC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 TS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 VBAT monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 Embedded internal reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings . . . . . . . . . . . . . . . . . 122 Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings . . . . . . . . . . . . . . . . . 123 Asynchronous multiplexed PSRAM/NOR read timings. . . . . . . . . . . . . . . . . . . . . . . . . . . 124 Asynchronous multiplexed PSRAM/NOR write timings . . . . . . . . . . . . . . . . . . . . . . . . . . 125 Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 Synchronous multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . 129 Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 Switching characteristics for PC Card/CF read and write cycles in attribute/common space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 Switching characteristics for PC Card/CF read and write cycles in I/O space . . . . . . . . . 136 Switching characteristics for NAND Flash read cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 Switching characteristics for NAND Flash write cycles. . . . . . . . . . . . . . . . . . . . . . . . . . . 139 DCMI characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 SD / MMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 RTC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 LQFP64 - 10 x 10 mm 64 pin low-profile quad flat package mechanical data . . . . . . . . . 142 LQPF100 - 14 x 14 mm 100-pin low-profile quad flat package mechanical data. . . . . . . 143 LQFP144 20 x 20 mm, 144-pin low-profile quad flat package mechanical data. . . . . . . . 144 LQFP176 - Low profile quad flat package 24 x 24 x 1.4 mm package mechanical data . 145 UFBGA176+25 - ultra thin fine pitch ball grid array 10 x 10 x 0.6 mm mechanical data . 147 Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 Main applications versus package for STM32F2xxx microcontrollers . . . . . . . . . . . . . . . 151 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 Doc ID 17050 Rev 6 STM32F215xx, STM32F217xx List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Figure 36. Compatible board design between STM32F10xx and STM32F2xx for LQFP64 package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Compatible board design between STM32F10xx and STM32F2xx for LQFP100 package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Compatible board design between STM32F10xx and STM32F2xx for LQFP144 package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Compatible board design between STM32F10xx and STM32F2xx for LQFP176 package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 STM32F21x block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Multi-AHB matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Startup in regulator OFF: slow VDD slope - power-down reset risen after VCAP_1/VCAP_2 stabilization . . . . . . . . . . . . . . . . . . . . . . . . 22 Startup in regulator OFF: fast VDD slope - power-down reset risen before VCAP_1/VCAP_2 stabilization . . . . . . . . . . . . . . . . . . . . . . 23 STM32F21x LQFP64 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 STM32F21x LQFP100 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 STM32F21x LQFP144 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 STM32F21x LQFP176 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 STM32F21x UFBGA176 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Number of wait states versus fCPU and VDD range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 External capacitor CEXT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Typical current consumption vs temperature, Run mode, code with data processing running from RAM, and peripherals ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Typical current consumption vs temperature, Run mode, code with data processing running from RAM, and peripherals OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Typical current consumption vs temperature, Run mode, code with data processing running from Flash, ART accelerator OFF, peripherals ON . . . . . . . . . . . . . . . 71 Typical current consumption vs temperature, Run mode, code with data processing running from Flash, ART accelerator OFF, peripherals OFF . . . . . . . . . . . . . . 71 Typical current consumption vs temperature in Sleep mode, peripherals ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Typical current consumption vs temperature in Sleep mode, peripherals OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Typical current consumption vs temperature in Stop mode . . . . . . . . . . . . . . . . . . . . . . . . 74 High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Low-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Typical application with an 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 ACCHSI versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 ACCLSI versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 PLL output clock waveforms in center spread mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 PLL output clock waveforms in down spread mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 I/O AC characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 Doc ID 17050 Rev 6 7/168 List of figures Figure 37. Figure 38. Figure 39. Figure 40. Figure 41. Figure 42. Figure 43. Figure 44. Figure 45. Figure 46. Figure 47. Figure 48. Figure 49. Figure 50. Figure 51. Figure 52. Figure 53. Figure 54. Figure 55. Figure 56. Figure 57. Figure 58. Figure 59. Figure 60. Figure 61. Figure 62. Figure 63. Figure 64. Figure 65. Figure 66. Figure 67. Figure 68. Figure 69. Figure 70. Figure 71. Figure 72. Figure 73. Figure 74. Figure 75. Figure 76. Figure 77. Figure 78. Figure 79. Figure 80. Figure 81. Figure 82. Figure 83. Figure 84. Figure 85. 8/168 STM32F215xx, STM32F217xx Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 I2C bus AC waveforms and measurement circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 SPI timing diagram - slave mode and CPHA = 1(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 SPI timing diagram - master mode(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 I2S slave timing diagram (Philips protocol)(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 I2S master timing diagram (Philips protocol)(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 USB OTG FS timings: definition of data signal rise and fall time . . . . . . . . . . . . . . . . . . . 109 ULPI timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 Ethernet SMI timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 Ethernet RMII timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 Ethernet MII timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 ADC accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 Power supply and reference decoupling (VREF+ not connected to VDDA). . . . . . . . . . . . . 117 Power supply and reference decoupling (VREF+ connected to VDDA). . . . . . . . . . . . . . . . 117 12-bit buffered /non-buffered DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms . . . . . . . . . . . . . . 122 Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms . . . . . . . . . . . . . . 123 Asynchronous multiplexed PSRAM/NOR read waveforms. . . . . . . . . . . . . . . . . . . . . . . . 124 Asynchronous multiplexed PSRAM/NOR write waveforms . . . . . . . . . . . . . . . . . . . . . . . 125 Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 Synchronous multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . 129 Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 PC Card/CompactFlash controller waveforms for common memory read access . . . . . . 131 PC Card/CompactFlash controller waveforms for common memory write access . . . . . . 132 PC Card/CompactFlash controller waveforms for attribute memory read access. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 PC Card/CompactFlash controller waveforms for attribute memory write access. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 PC Card/CompactFlash controller waveforms for I/O space read access . . . . . . . . . . . . 134 PC Card/CompactFlash controller waveforms for I/O space write access . . . . . . . . . . . . 135 NAND controller waveforms for read access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 NAND controller waveforms for write access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 NAND controller waveforms for common memory read access . . . . . . . . . . . . . . . . . . . . 138 NAND controller waveforms for common memory write access. . . . . . . . . . . . . . . . . . . . 138 SDIO high-speed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 SD default mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 LQFP64 - 10 x 10 mm 64 pin low-profile quad flat package outline . . . . . . . . . . . . . . . . 142 Recommended footprint(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 LQFP100, 14 x 14 mm 100-pin low-profile quad flat package outline . . . . . . . . . . . . . . . 143 Recommended footprint(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 LQFP144, 20 x 20 mm, 144-pin low-profile quad flat package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 Recommended footprint(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 LQFP176 - Low profile quad flat package 24 x 24 x 1.4 mm, package outline . . . . . . . . 145 UFBGA176+25 - ultra thin fine pitch ball grid array 10 x 10 x 0.6 mm, package outline . 147 Regulator OFF/internal reset ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 USB OTG FS (full speed) device-only connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 USB OTG FS (full speed) host-only connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 OTG FS (full speed) connection dual-role with internal PHY . . . . . . . . . . . . . . . . . . . . . . 153 Doc ID 17050 Rev 6 STM32F215xx, STM32F217xx Figure 86. Figure 87. Figure 88. Figure 89. Figure 90. Figure 91. Figure 92. Figure 93. Figure 94. Figure 95. List of figures OTG HS (high speed) device connection, host and dual-role in high-speed mode with external PHY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 Complete audio player solution 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 Complete audio player solution 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 Audio player solution using PLL, PLLI2S, USB and 1 crystal . . . . . . . . . . . . . . . . . . . . . . 156 Audio PLL (PLLI2S) providing accurate I2S clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 Master clock (MCK) used to drive the external audio DAC. . . . . . . . . . . . . . . . . . . . . . . . 157 Master clock (MCK) not used to drive the external audio DAC. . . . . . . . . . . . . . . . . . . . . 157 MII mode using a 25 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 RMII with a 50 MHz oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 RMII with a 25 MHz crystal and PHY with PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 Doc ID 17050 Rev 6 9/168 Introduction 1 STM32F215xx, STM32F217xx Introduction This datasheet provides the description of the STM32F215xx, and STM32F217xx lines of microcontrollers. For more details on the whole STMicroelectronics STM32TM family, please refer to Section 2.1: Full compatibility throughout the family. The STM32F215xx, and STM32F217xx datasheet should be read in conjunction with the STM32F20x/STM32F21x reference manual. They will be referred to as STM32F21x devices throughout the document. For information on programming, erasing and protection of the internal Flash memory, please refer to the STM32F20x/STM32F21x Flash programming manual (PM0059). The reference and Flash programming manuals are both available from the STMicroelectronics website www.st.com. For information on the CortexTM-M3 core please refer to the CortexTM-M3 Technical Reference Manual, available from the www.arm.com website at the following address: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0337e/. 10/168 Doc ID 17050 Rev 6 STM32F215xx, STM32F217xx 2 Description Description The STM32F21x family is based on the high-performance ARM(R) CortexTM-M3 32-bit RISC core operating at a frequency of up to 120 MHz. The family incorporates high-speed embedded memories (Flash memory up to 1 Mbyte, up to 128 Kbytes of system SRAM), up to 4 Kbytes of backup SRAM, and an extensive range of enhanced I/Os and peripherals connected to two APB buses, two AHB buses and a 32-bit multi-AHB bus matrix. The devices also feature an adaptive real-time memory accelerator (ART AcceleratorTM) which allows to achieve a performance equivalent to 0 wait state program execution from Flash memory at a CPU frequency up to 120 MHz. This performance has been validated using the CoreMark benchmark. All devices offer three 12-bit ADCs, two DACs, a low-power RTC, twelve general-purpose 16-bit timers including two PWM timers for motor control, two general-purpose 32-bit timers. a true number random generator (RNG). They also feature standard and advanced communication interfaces. New advanced peripherals include an SDIO, an enhanced flexible static memory control (FSMC) interface (for devices offered in packages of 100 pins and more), a cryptographic acceleration cell, and a camera interface for CMOS sensors. The devices also feature standard peripherals. Up to three I2Cs Three SPIs, two I2Ss. To achieve audio class accuracy, the I2S peripherals can be clocked via a dedicated internal audio PLL or via an external PLL to allow synchronization. 4 USARTs and 2 UARTs A USB OTG full-speed with high-speed capability (with the ULPI) Two CANs An SDIO interface Ethernet and camera interface available on STM32F217xx devices only. The STM32F215xx and STM32F217xx devices operate in the -40 to +105 C temperature range from a 1.8 V to 3.6 V power supply.A comprehensive set of power-saving modes allow the design of low-power applications. STM32F215xx and STM32F217xx devices are offered in four packages ranging from 64 pins to 176 pins. The set of included peripherals changes with the device chosen.These features make the STM32F215xx and STM32F217xx microcontroller family suitable for a wide range of applications: Motor drive and application control Medical equipment Industrial applications: PLC, inverters, circuit breakers Printers, and scanners Alarm systems, video intercom, and HVAC Home audio appliances Figure 5 shows the general block diagram of the device family. Doc ID 17050 Rev 6 11/168 STM32F215xx and STM32F217xx: features and peripheral counts Peripherals STM32F215Rx Flash memory in Kbytes 512 1024 STM32F215Vx 512 1024 STM32F215Zx 512 STM32F217Vx 1024 System 512 1024 STM32F217Zx 512 1024 STM32F217Ix 512 1024 128(112+16) SRAM in Kbytes Backup FSMC memory controller 4 4 4 Yes General-purpose 10 Advanced-control 2 Basic 2 Yes SPI / (I2S) 3 (2) Doc ID 17050 Rev 6 I2C 3 USART UART 4 2 USB OTG FS No 1 USB OTG HS 1 CAN 2 Camera interface No Yes Encryption GPIOs Yes 51 82 114 SDIO 12-bit ADC Number of channels 4 Yes No Random number generator Communication interfaces 4 No Ethernet Timers 4 STM32F215xx, STM32F217xx Table 2. 82 114 140 16 24 24 LQFP144 UFBGA176 LQFP176 Yes 3 16 16 24 12-bit DAC Number of channels Yes 2 Maximum CPU frequency 120 MHz Operating voltage 1.8 V to 3.6 V Ambient temperatures: -40 to +85 C /-40 to +105 C Operating temperatures Package LQFP64 LQFP100 LQFP144 LQFP100 12/168 Description Junction temperature: -40 to + 125 C STM32F215xx, STM32F217xx 2.1 Description Full compatibility throughout the family The STM32F215xx and STM32F217xx constitute the STM32F21x family whose members are fully pin-to-pin, software and feature compatible, allowing the user to try different memory densities and peripherals for a greater degree of freedom during the development cycle. The STM32F215xx and STM32F217xx devices maintain a close compatibility with the whole STM32F10xxx family. All functional pins are pin-to-pin compatible. The STM32F215xx and STM32F217xx, however, are not drop-in replacements for the STM32F10xxx devices: the two families do not have the same power scheme, and so their power pins are different. Nonetheless, transition from the STM32F10xxx to the STM32F21x family remains simple as only a few pins are impacted. Figure 3, Figure 4, and Figure 1 provide compatible board designs between the STM32F21x and the STM32F10xxx family. Figure 1. Compatible board design between STM32F10xx and STM32F2xx for LQFP64 package VSS VSS 48 33 32 47 49 31 VSS VSS 64 0 resistor or soldering bridge present for the STM32F10xx configuration, not present in the STM32F2xx configuration 17 1 16 ai15962b Doc ID 17050 Rev 6 13/168 Description STM32F215xx, STM32F217xx Figure 2. Compatible board design between STM32F10xx and STM32F2xx for LQFP100 package 633 633 633 2&5 RESISTOR OR SOLDERING BRIDGE PRESENT FOR THE 34-&XX CONFIGURATION NOT PRESENT IN THE 34-&XX CONFIGURATION 633 6$$ 6 33 4WO RESISTORS CONNECTED TO 6$$ 633 6 33 FOR THE 34-&XX 6 $$ 6 33 OR .# FOR THE 34-&XX 633 FOR 34-&XX 6$$ FOR 34-&XX AIC Figure 3. Compatible board design between STM32F10xx and STM32F2xx for LQFP144 package 633 633 633 RESISTOR OR SOLDERING BRIDGE PRESENT FOR THE 34-&XX CONFIGURATION NOT PRESENT IN THE 34-&XX CONFIGURATION 2&5 633 6$$ 6 33 4WO RESISTORS CONNECTED TO 6$$ 6 33 FOR THE 34-&XX 6 $$ 6 33 OR .# FOR THE 34-&XX 633 AIC 1. RFU = reserved for future use. 14/168 Doc ID 17050 Rev 6 STM32F215xx, STM32F217xx Figure 4. Description Compatible board design between STM32F10xx and STM32F2xx for LQFP176 package 2&5 6$$ 6 33 4WO RESISTORS CONNECTED TO 6 33 FOR THE 34-&XX 6 $$ 6 33 OR .# FOR THE 34-&XX -36 1. RFU = reserved for future use. Doc ID 17050 Rev 6 15/168 Description STM32F215xx, STM32F217xx 2.2 Device overview Figure 5. STM32F21x block diagram %XTERNAL MEMORY CONTROLLER &3-# $0 $5,0) #+ $ $)2 340 .84 3#,3$! ).4. )$ 6"53 3/& %THERNET -!# $-! &)&/ 0(9 -)) OR 2-)) AS !& -$)/ AS !& $-! &)&/ 53" /4' (3 3TREAMS $-! &)&/ &LASH -BYTE 32!- +" !(" -(Z 6$$ &)&/ 2# (3 '0)/ 0/24 ! 2# ,3 0";= '0)/ 0/24 " 0#;= '0)/ 0/24 # 0$;= '0)/ 0/24 $ 0%;= '0)/ 0/24 % #AMERA INTERFACE 53" /4' &3 0OWER MANAGMT 6OLTAGE REGULATOR 6 TO 6 /2 0 2ESET )NT 0,, 3UPPLY SUPERVISION 0/20$2 "/2 06$ '0)/ 0/24 & ,3 '0)/ 0/24 ( 84!, K(Z 24# '0)/ 0/24 ) !75 "ACKUP REGISTER $-! 4)- 07- 4)- CHANNELS %42 AS !& CHANNELS %42 AS !& CHANNELS AS !& 4)- B CHANNEL AS !& 4)- B CHANNEL AS !& 53!24 SMCARD IR$! 28 48 #+ #43 243 AS !& 53!24 SMCARD IR$! 28 48 #+ #43 243 AS !& 5!24 28 48 AS !& B 5!24 28 48 AS !& 4)- 28 48 #+ #43 243 AS !& SMCARD 53!24 IR$! 30) 4)- 4)- B B 53!24 -"PS 4EMPERATURE SENSOR 6$$! !$# !$# !$# $!# )& 30))3 -/3)$/54 -)3/$). 3#+#+ .3373 -#+ AS !& 30))3 -/3)$/54 -)3/$). 3#+#+ .3373 -#+ AS !& 3#, 3$! 3-"! AS !& )#3-"53 6$$! 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AS !& CHANNELS AS !& &)&/ $;= #-$ #+ AS !& /3#?). /3#?/54 B 4)- !("!0" !("!0" %84 )4 7+50 6$$! 633! .234 CHANNELS %42 AS !& B 4)- !& 6#!0 6#!0 +" "+302!- 4)- B $-! 633 6"!4 TO 6 6"!4 0#,+X '0)/ 0/24 ' 6$$ TO 6 )7$' 3TANDBY INTERFACE ,3 0);= 2ESET CLOCK -!.!'4 CONTROL &#,+ 0(;= 84!, /3# -(Z (#,+X 0';= $0 $3#, 3$! ).4. )$ 6"53 3/& 6$$ 6$$! 0&;= (39.# 639.# 0)8#,+ $;= 6$$ 6$$! 0!;= (!3( !(" -(Z 3TREAMS $-! 4$%3 !%3 #,+ .% ;= !;= $;= /%. 7%. .",;= ., .2%' .7!)4)/2$9 #$ .)/2$ )/72 ).4;= ).4. .))3 AS !& 2.' 32!- +" &)&/ 3 "53 &)&/ &)&/ 32!- 032!- ./2 &LASH 0# #ARD !4! .!.$ &LASH &)&/ %4- !2- #ORTEX - ) "53 -(Z !24 ACCELERATOR $ "53 0(9 -05 .6)# !##%, #!#(% 42!#%#,+ 42!#%$;= *4!' 37 !(" BUS MATRIX 3- .*4234 *4$) *4#+37#,+ *4$/37$ *4$/ 48 28 48 28 AIB 1. The timers connected to APB2 are clocked from TIMxCLK up to 120 MHz, while the timers connected to APB1 are clocked from TIMxCLK up to 60 MHz. 16/168 Doc ID 17050 Rev 6 STM32F215xx, STM32F217xx 2.2.1 Description ARM(R) CortexTM-M3 core with embedded Flash and SRAM The ARM Cortex-M3 processor is the latest generation of ARM processors for embedded systems. It was developed to provide a low-cost platform that meets the needs of MCU implementation, with a reduced pin count and low-power consumption, while delivering outstanding computational performance and an advanced response to interrupts. The ARM Cortex-M3 32-bit RISC processor features exceptional code-efficiency, delivering the high-performance expected from an ARM core in the memory size usually associated with 8- and 16-bit devices. With its embedded ARM core, the STM32F21x family is compatible with all ARM tools and software. Figure 5 shows the general block diagram of the STM32F21x family. 2.2.2 Adaptive real-time memory accelerator (ART AcceleratorTM) The ART AcceleratorTM is a memory accelerator which is optimized for STM32 industrystandard ARM(R) CortexTM-M3 processors. It balances the inherent performance advantage of the ARM Cortex-M3 over Flash memory technologies, which normally requires the processor to wait for the Flash memory at higher operating frequencies. To release the processor full 150 DMIPS performance at this frequency, the accelerator implements an instruction prefetch queue and branch cache which increases program execution speed from the 128-bit Flash memory. Based on CoreMark benchmark, the performance achieved thanks to the ART accelerator is equivalent to 0 wait state program execution from Flash memory at a CPU frequency up to 120 MHz. 2.2.3 Memory protection unit The memory protection unit (MPU) is used to manage the CPU accesses to memory to prevent one task to accidentally corrupt the memory or resources used by any other active task. This memory area is organized into up to 8 protected areas that can in turn be divided up into 8 subareas. The protection area sizes are between 32 bytes and the whole 4 gigabytes of addressable memory. The MPU is especially helpful for applications where some critical or certified code has to be protected against the misbehavior of other tasks. It is usually managed by an RTOS (realtime operating system). If a program accesses a memory location that is prohibited by the MPU, the RTOS can detect it and take action. In an RTOS environment, the kernel can dynamically update the MPU area setting, based on the process to be executed. The MPU is optional and can be bypassed for applications that do not need it. 2.2.4 Embedded Flash memory The STM32F21x devices embed a 128-bit wide Flash memory of 128 Kbytes, 256 Kbytes, 512 Kbytes, 768 Kbytes or 1 Mbytes available for storing programs and data. The devices also feature 512 bytes of OTP memory that can be used to store critical user data such as Ethernet MAC addresses or cryptographic keys. Doc ID 17050 Rev 6 17/168 Description 2.2.5 STM32F215xx, STM32F217xx CRC (cyclic redundancy check) calculation unit The CRC (cyclic redundancy check) calculation unit is used to get a CRC code from a 32-bit data word and a fixed generator polynomial. Among other applications, CRC-based techniques are used to verify data transmission or storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of verifying the Flash memory integrity. The CRC calculation unit helps compute a software signature during runtime, to be compared with a reference signature generated at link-time and stored at a given memory location. 2.2.6 Embedded SRAM All STM32F21x products embed: Up to 128 Kbytes of system SRAM accessed (read/write) at CPU clock speed with 0 wait states 4 Kbytes of backup SRAM. The content of this area is protected against possible unwanted write accesses, and is retained in Standby or VBAT mode. 2.2.7 Multi-AHB bus matrix The 32-bit multi-AHB bus matrix interconnects all the masters (CPU, DMAs, Ethernet, USB HS) and the slaves (Flash memory, RAM, FSMC, AHB and APB peripherals) and ensures a seamless and efficient operation even when several high-speed peripherals work simultaneously. Multi-AHB matrix 3 3 3 3 3 3 53"?(3?- -!# 53" /4' %THERNET (3 %4(%2.%4?- $-!?0 '0 $-! $-!?-%- $-!?0 3 BUS '0 $-! 3 - )#/$% - $#/$% !24 !##%, 3 $ BUS ) BUS !2#ORTEX - $-!?-%- Figure 6. &LASH MEMORY - 32! +BYTE - 32! +BYTE !(" PERIPH !(" PERIPH - - - !0" !0" &3-# 3TATIC -EM#TL "US MATRIX 3 AIB 18/168 Doc ID 17050 Rev 6 STM32F215xx, STM32F217xx 2.2.8 Description DMA controller (DMA) The devices feature two general-purpose dual-port DMAs (DMA1 and DMA2) with 8 streams each. They are able to manage memory-to-memory, peripheral-to-memory and memory-to-peripheral transfers. They share some centralized FIFOs for APB/AHB peripherals, support burst transfer and are designed to provide the maximum peripheral bandwidth (AHB/APB). The two DMA controllers support circular buffer management, so that no specific code is needed when the controller reaches the end of the buffer. The two DMA controllers also have a double buffering feature, which automates the use and switching of two memory buffers without requiring any special code. Each stream is connected to dedicated hardware DMA requests, with support for software trigger on each stream. Configuration is made by software and transfer sizes between source and destination are independent. The DMA can be used with the main peripherals: 2.2.9 SPI and I2S I2C USART and UART General-purpose, basic and advanced-control timers TIMx DAC SDIO Cryptographic acceleration Camera interface (DCMI) ADC. Flexible static memory controller (FSMC) The FSMC is embedded in all STM32F21x devices. It has four Chip Select outputs supporting the following modes: PC Card/Compact Flash, SRAM, PSRAM, NOR Flash and NAND Flash. Functionality overview: Write FIFO Code execution from external memory except for NAND Flash and PC Card Maximum frequency (fHCLK) for external access is 60 MHz LCD parallel interface The FSMC can be configured to interface seamlessly with most graphic LCD controllers. It supports the Intel 8080 and Motorola 6800 modes, and is flexible enough to adapt to specific LCD interfaces. This LCD parallel interface capability makes it easy to build costeffective graphic applications using LCD modules with embedded controllers or high performance solutions using external controllers with dedicated acceleration. Doc ID 17050 Rev 6 19/168 Description 2.2.10 STM32F215xx, STM32F217xx Nested vectored interrupt controller (NVIC) The STM32F215xx and STM32F217xx embed a nested vectored interrupt controller able to manage 16 priority levels, and handle up to 87 maskable interrupt channels plus the 16 interrupt lines of the CortexTM-M3. The NVIC main features are the following: Closely coupled NVIC gives low-latency interrupt processing Interrupt entry vector table address passed directly to the core Closely coupled NVIC core interface Allows early processing of interrupts Processing of late arriving, higher-priority interrupts Support tail chaining Processor state automatically saved Interrupt entry restored on interrupt exit with no instruction overhead This hardware block provides flexible interrupt management features with minimum interrupt latency. 2.2.11 External interrupt/event controller (EXTI) The external interrupt/event controller consists of 23 edge-detector lines used to generate interrupt/event requests. Each line can be independently configured to select the trigger event (rising edge, falling edge, both) and can be masked independently. A pending register maintains the status of the interrupt requests. The EXTI can detect an external line with a pulse width shorter than the Internal APB2 clock period. Up to 140 GPIOs can be connected to the 16 external interrupt lines. 2.2.12 Clocks and startup On reset the 16 MHz internal RC oscillator is selected as the default CPU clock. The 16 MHz internal RC oscillator is factory-trimmed to offer 1% accuracy. The application can then select as system clock either the RC oscillator or an external 4-26 MHz clock source. This clock is monitored for failure. If failure is detected, the system automatically switches back to the internal RC oscillator and a software interrupt is generated (if enabled). Similarly, full interrupt management of the PLL clock entry is available when necessary (for example if an indirectly used external oscillator fails). The advanced clock controller clocks the core and all peripherals using a single crystal or oscillator. In particular, the ethernet and USB OTG FS peripherals can be clocked by the system clock. Several prescalers and PLLs allow the configuration of the two AHB buses, the high-speed APB (APB2) and the low-speed APB (APB1) domains. The maximum frequency of the two AHB buses is 120 MHz and the maximum frequency the high-speed APB domains is 60 MHz. The maximum allowed frequency of the low-speed APB domain is 30 MHz. The devices embed a dedicate PLL (PLLI2S) which allow to achieve audio class performance. In this case, the I2S master clock can generate all standard sampling frequencies from 8 kHz to 192 kHz. 20/168 Doc ID 17050 Rev 6 STM32F215xx, STM32F217xx 2.2.13 Description Boot modes At startup, boot pins are used to select one out of three boot options: Boot from user Flash Boot from system memory Boot from embedded SRAM The boot loader is located in system memory. It is used to reprogram the Flash memory by using USART1 (PA9/PA10), USART3 (PC10/PC11 or PB10/PB11), CAN2 (PB5/PB13), USB OTG FS in Device mode (PA11/PA12) through DFU (device firmware upgrade). 2.2.14 Power supply schemes VDD = 1.8 to 3.6 V: external power supply for I/Os and the internal regulator (when enabled), provided externally through VDD pins. VSSA, VDDA = 1.8 to 3.6 V: external analog power supplies for ADC, DAC, Reset blocks, RCs and PLL. VDDA and VSSA must be connected to VDD and VSS, respectively. VBAT = 1.65 to 3.6 V: power supply for RTC, external clock, 32 kHz oscillator and backup registers (through power switch) when VDD is not present. Refer to Figure 17: Power supply scheme for more details. 2.2.15 Power supply supervisor The devices have an integrated power-on reset (POR) / power-down reset (PDR) circuitry coupled with a Brownout reset (BOR) circuitry. At power-on, BOR is always active, and ensures proper operation starting from 1.8 V. After the 1.8 V BOR threshold is reached, the option byte loading process starts, either to confirm or modify default thresholds, or to disable BOR permanently. Three BOR thresholds are available through option bytes. The device remains in reset mode when VDD is below a specified threshold, VPOR/PDR or VBOR, without the need for an external reset circuit. The devices also feature an embedded programmable voltage detector (PVD) that monitors the VDD/VDDA power supply and compares it to the VPVD threshold. An interrupt can be generated when VDD/VDDA drops below the VPVD threshold and/or when VDD/VDDA is higher than the VPVD threshold. The interrupt service routine can then generate a warning message and/or put the MCU into a safe state. The PVD is enabled by software. 2.2.16 Voltage regulator The regulator has four operating modes: Regulator ON - Main regulator mode (MR) - Low power regulator (LPR) - Power-down Regulator OFF - Regulator OFF/internal reset ON Doc ID 17050 Rev 6 21/168 Description STM32F215xx, STM32F217xx Regulator ON The regulator ON modes are activated by default on LQFP packages. On UFBGA176 package, they are activated by connecting REGOFF to VSS. VDD minimum value is 1.8 V. There are three regulator ON modes: MR is used in nominal regulation mode (Run) LPR is used in Stop mode Power-down is used in Standby mode: The regulator output is in high impedance: the kernel circuitry is powered down, inducing zero consumption (but the contents of the registers and SRAM are lost). Regulator OFF Regulator OFF/internal reset ON On UFBGA176 package, REGOFF must be connected to VDD. The regulator OFF/internal reset ON mode allows to supply externally a 1.2 V voltage source through VCAP_1 and VCAP_2 pins, in addition to VDD. The following conditions must be respected: - VDD should always be higher than VCAP_1 and VCAP_2 to avoid current injection between power domains. - If the time for VCAP_1 and VCAP_2 to reach 1.08 V is faster than the time for VDD to reach 1.8 V, then PA0 should be connected to the NRST pin (see Figure 7). Otherwise, PA0 should be asserted low externally during POR until VDD reaches 1.8 V (see Figure 8). In this mode, PA0 cannot be used as a GPIO pin since it allows to reset the part of the 1.2 V logic which is not reset by the NRST pin, when the internal voltage regulator in OFF. Figure 7. Startup in regulator OFF: slow VDD slope - power-down reset risen after VCAP_1/VCAP_2 stabilization 6$$ 0$2 6 6 6 6#!0? 6 #!0? TIME 0! TIED TO .234 .234 TIME 1. This figure is valid both whatever the internal reset mode (ON or OFF). 22/168 Doc ID 17050 Rev 6 STM32F215xx, STM32F217xx Figure 8. Description Startup in regulator OFF: fast VDD slope - power-down reset risen before VCAP_1/VCAP_2 stabilization 6$$ 0$2 6 6#!0? 6 #!0? 6 6 TIME 0! ASSERTED EXTERNALLY .234 TIME 2.2.17 Real-time clock (RTC), backup SRAM and backup registers The backup domain of the STM32F21x devices includes: The real-time clock (RTC) 4 Kbytes of backup SRAM 20 backup registers The real-time clock (RTC) is an independent BCD timer/counter. Dedicated registers contain the second, minute, hour (in 12/24 hour), week day, date, month, year, in BCD (binary-coded decimal) format. Correction for 28, 29 (leap year), 30, and 31 day of the month are performed automatically. The RTC provides a programmable alarm and programmable periodic interrupts with wakeup from Stop and Standby modes. It is clocked by a 32.768 kHz external crystal, resonator or oscillator, the internal low-power RC oscillator or the high-speed external clock divided by 128. The internal low-speed RC has a typical frequency of 32 kHz. The RTC can be calibrated using an external 512 Hz output to compensate for any natural quartz deviation. Two alarm registers are used to generate an alarm at a specific time and calendar fields can be independently masked for alarm comparison. To generate a periodic interrupt, a 16-bit programmable binary auto-reload downcounter with programmable resolution is available and allows automatic wakeup and periodic alarms from every 120 s to every 36 hours. A 20-bit prescaler is used for the time base clock. It is by default configured to generate a time base of 1 second from a clock at 32.768 kHz. The 4-Kbyte backup SRAM is an EEPROM-like area.It can be used to store data which need to be retained in VBAT and standby mode.This memory area is disabled to minimize power consumption (see Section 2.2.18: Low-power modes). It can be enabled by software. The backup registers are 32-bit registers used to store 80 bytes of user application data when VDD power is not present. Backup registers are not reset by a system, a power reset, or when the device wakes up from the Standby mode (see Section 2.2.18: Low-power modes). Like backup SRAM, the RTC and backup registers are supplied through a switch that is powered either from the VDD supply when present or the VBAT pin. Doc ID 17050 Rev 6 23/168 Description 2.2.18 STM32F215xx, STM32F217xx Low-power modes The STM32F21x family supports three low-power modes to achieve the best compromise between low power consumption, short startup time and available wakeup sources: Sleep mode In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can wake up the CPU when an interrupt/event occurs. Stop mode The Stop mode achieves the lowest power consumption while retaining the contents of SRAM and registers. All clocks in the 1.2 V domain are stopped, the PLL, the HSI RC and the HSE crystal oscillators are disabled. The voltage regulator can also be put either in normal or in low-power mode. The device can be woken up from the Stop mode by any of the EXTI line. The EXTI line source can be one of the 16 external lines, the PVD output, the RTC alarm / wakeup / tamper / time stamp events, the USB OTG FS/HS wakeup or the Ethernet wakeup. Standby mode The Standby mode is used to achieve the lowest power consumption. The internal voltage regulator is switched off so that the entire 1.2 V domain is powered off. The PLL, the HSI RC and the HSE crystal oscillators are also switched off. After entering Standby mode, the SRAM and register contents are lost except for registers in the backup domain and the backup SRAM when selected. The device exits the Standby mode when an external reset (NRST pin), an IWDG reset, a rising edge on the WKUP pin, or an RTC alarm / wakeup / tamper /time stamp event occurs. Note: The RTC, the IWDG, and the corresponding clock sources are not stopped when the device enters the Stop or Standby mode. 2.2.19 VBAT operation The VBAT pin allows to power the device VBAT domain from an external battery or an external supercapacitor. VBAT operation is activated when VDD is not present. The VBAT pin supplies the RTC, the backup registers and the backup SRAM. Note: 24/168 When the microcontroller is supplied from VBAT, external interrupts and RTC alarm/events do not exit it from VBAT operation. Doc ID 17050 Rev 6 STM32F215xx, STM32F217xx 2.2.20 Description Timers and watchdogs The STM32F215xx and STM32F217xx devices include two advanced-control timers, eight general-purpose timers, two basic timers and two watchdog timers. All timer counters can be frozen in debug mode. Table 3 compares the features of the advanced-control, general-purpose and basic timers. Table 3. Timer feature comparison Counter Counter Prescaler resolution type factor Timer type Timer DMA Capture/ Max Max Complementary request compare interface timer output generation channels clock clock Advanced- TIM1, control TIM8 16-bit Up, Any integer Down, between 1 Up/down and 65536 Yes 4 Yes 60 MHz 120 MHz TIM2, TIM5 32-bit Up, Any integer Down, between 1 Up/down and 65536 Yes 4 No 30 MHz 60 MHz TIM3, TIM4 16-bit Up, Any integer Down, between 1 Up/down and 65536 Yes 4 No 30 MHz 60 MHz TIM6, TIM7 16-bit Up Any integer between 1 and 65536 Yes 0 No 30 MHz 60 MHz TIM9 16-bit Up Any integer between 1 and 65536 No 2 No 60 MHz 120 MHz TIM10, TIM11 16-bit Up Any integer between 1 and 65536 No 1 No 60 MHz 120 MHz TIM12 16-bit Up Any integer between 1 and 65536 No 2 No 30 MHz 60 MHz TIM13, TIM14 16-bit Up Any integer between 1 and 65536 No 1 No 30 MHz 60 MHz General purpose Basic General purpose Advanced-control timers (TIM1, TIM8) The advanced-control timers (TIM1, TIM8) can be seen as three-phase PWM generators multiplexed on 6 channels. They have complementary PWM outputs with programmable inserted dead times. They can also be considered as complete general-purpose timers. Their 4 independent channels can be used for: Input capture Output compare PWM generation (edge- or center-aligned modes) One-pulse mode output Doc ID 17050 Rev 6 25/168 Description STM32F215xx, STM32F217xx If configured as standard 16-bit timers, they have the same features as the general-purpose TIMx timers. If configured as 16-bit PWM generators, they have full modulation capability (0100%). The TIM1 and TIM8 counters can be frozen in debug mode. Many of the advanced-control timer features are shared with those of the standard TIMx timers which have the same architecture. The advanced-control timer can therefore work together with the TIMx timers via the Timer Link feature for synchronization or event chaining. General-purpose timers (TIMx) There are ten synchronizable general-purpose timers embedded in the STM32F21x devices (see Table 3 for differences). TIM2, TIM3, TIM4, TIM5 The STM32F21x include 4 full-featured general-purpose timers. TIM2 and TIM5 are 32-bit timers, and TIM3 and TIM4 are 16-bit timers. The TIM2 and TIM5 timers are based on a 32-bit auto-reload up/downcounter and a 16-bit prescaler. The TIM3 and TIM4 timers are based on a 16-bit auto-reload up/downcounter and a 16-bit prescaler. They all feature 4 independent channels for input capture/output compare, PWM or one-pulse mode output. This gives up to 16 input capture/output compare/PWMs on the largest packages. The TIM2, TIM3, TIM4, TIM5 general-purpose timers can work together, or with the other general-purpose timers and the advanced-control timers TIM1 and TIM8 via the Timer Link feature for synchronization or event chaining. The counters of TIM2, TIM3, TIM4, TIM5 can be frozen in debug mode. Any of these general-purpose timers can be used to generate PWM outputs. TIM2, TIM3, TIM4, TIM5 all have independent DMA request generation. They are capable of handling quadrature (incremental) encoder signals and the digital outputs from 1 to 4 hall-effect sensors. TIM10, TIM11 and TIM9 These timers are based on a 16-bit auto-reload upcounter and a 16-bit prescaler. TIM10 and TIM11 feature one independent channel, whereas TIM9 has two independent channels for input capture/output compare, PWM or one-pulse mode output. They can be synchronized with the TIM2, TIM3, TIM4, TIM5 full-featured general-purpose timers. They can also be used as simple time bases. TIM12, TIM13 and TIM14 These timers are based on a 16-bit auto-reload upcounter and a 16-bit prescaler. TIM13 and TIM14 feature one independent channel, whereas TIM12 has two independent channels for input capture/output compare, PWM or one-pulse mode output. They can be synchronized with the TIM2, TIM3, TIM4, TIM5 full-featured general-purpose timers. They can also be used as simple time bases. Basic timers TIM6 and TIM7 These timers are mainly used for DAC trigger and waveform generation. They can also be used as a generic 16-bit time base. Independent watchdog The independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. It is clocked from an independent 32 kHz internal RC and as it operates independently from the 26/168 Doc ID 17050 Rev 6 STM32F215xx, STM32F217xx Description main clock, it can operate in Stop and Standby modes. It can be used either as a watchdog to reset the device when a problem occurs, or as a free-running timer for application timeout management. It is hardware- or software-configurable through the option bytes. The counter can be frozen in debug mode. Window watchdog The window watchdog is based on a 7-bit downcounter that can be set as free-running. It can be used as a watchdog to reset the device when a problem occurs. It is clocked from the main clock. It has an early warning interrupt capability and the counter can be frozen in debug mode. SysTick timer This timer is dedicated to real-time operating systems, but could also be used as a standard downcounter. It features: 2.2.21 A 24-bit downcounter Autoreload capability Maskable system interrupt generation when the counter reaches 0 Programmable clock source Inter-integrated circuit interface (IC) Up to three I2C bus interfaces can operate in multimaster and slave modes. They can support the Standard- and Fast-modes. They support the 7/10-bit addressing mode and the 7-bit dual addressing mode (as slave). A hardware CRC generation/verification is embedded. They can be served by DMA and they support SMBus 2.0/PMBus. 2.2.22 Universal synchronous/asynchronous receiver transmitters (UARTs/USARTs) The STM32F215xx and STM32F217xx embed four universal synchronous/asynchronous receiver transmitters (USART1, USART2, USART3 and USART6) and two universal asynchronous receiver transmitters (UART4 and UART5). These six interfaces provide asynchronous communication, IrDA SIR ENDEC support, multiprocessor communication mode, single-wire half-duplex communication mode and have LIN Master/Slave capability. The USART1 and USART6 interfaces are able to communicate at speeds of up to 7.5 Mbit/s. The other available interfaces communicate at up to 3.75 Mbit/s. USART1, USART2, USART3 and USART6 also provide hardware management of the CTS and RTS signals, Smart Card mode (ISO 7816 compliant) and SPI-like communication capability. All interfaces can be served by the DMA controller. Doc ID 17050 Rev 6 27/168 Description Table 4. STM32F215xx, STM32F217xx USART feature comparison USART Standard Modem SPI LIN irDA name features (RTS/CTS) master Smartcard (ISO 7816) Max. baud rate Max. baud rate in Mbit/s in Mbit/s (oversampling (oversampling by 16) by 8) APB mapping USART1 X X X X X X 1.87 7.5 APB2 (max. 60 MHz) USART2 X X X X X X 1.87 3.75 APB1 (max. 30 MHz) USART3 X X X X X X 1.87 3.75 APB1 (max. 30 MHz) UART4 X - X - X - 1.87 3.75 APB1 (max. 30 MHz) UART5 X - X - X - 3.75 3.75 APB1 (max. 30 MHz) USART6 X X X X X X 3.75 7.5 APB2 (max. 60 MHz) 2.2.23 Serial peripheral interface (SPI) The STM32F21x feature up to three SPIs in slave and master modes in full-duplex and simplex communication modes. SPI1 can communicate at up to 30 Mbits/s, while SPI2 and SPI3 can communicate at up to 15 Mbit/s. The 3-bit prescaler gives 8 master mode frequencies and the frame is configurable to 8 bits or 16 bits. The hardware CRC generation/verification supports basic SD Card/MMC modes. All SPIs can be served by the DMA controller. The SPI interface can be configured to operate in TI mode for communications in master mode and slave mode. 2.2.24 Inter-integrated sound (I2S) Two standard I2S interfaces (multiplexed with SPI2 and SPI3) are available. They can operate in master or slave mode, in simplex communication modes, and can be configured to operate with a 16-/32-bit resolution as input or output channels. Audio sampling frequencies from 8 kHz up to 192 kHz are supported. When either or both of the I2S interfaces is/are configured in master mode, the master clock can be output to the external DAC/CODEC at 256 times the sampling frequency. All I2Sx interfaces can be served by the DMA controller. 28/168 Doc ID 17050 Rev 6 STM32F215xx, STM32F217xx 2.2.25 Description SDIO An SD/SDIO/MMC host interface is available, that supports MultiMediaCard System Specification Version 4.2 in three different databus modes: 1-bit (default), 4-bit and 8-bit. The interface allows data transfer at up to 48 MHz in 8-bit mode, and is compliant with the SD Memory Card Specification Version 2.0. The SDIO Card Specification Version 2.0 is also supported with two different databus modes: 1-bit (default) and 4-bit. The current version supports only one SD/SDIO/MMC4.2 card at any one time and a stack of MMC4.1 or previous. In addition to SD/SDIO/MMC, this interface is fully compliant with the CE-ATA digital protocol Rev1.1. 2.2.26 Ethernet MAC interface with dedicated DMA and IEEE 1588 support Peripheral available only on the STM32F217xx devices. The STM32F217xx devices provide an IEEE-802.3-2002-compliant media access controller (MAC) for ethernet LAN communications through an industry-standard mediumindependent interface (MII) or a reduced medium-independent interface (RMII). The STM32F217xx requires an external physical interface device (PHY) to connect to the physical LAN bus (twisted-pair, fiber, etc.). the PHY is connected to the STM32F217xx MII port using 17 signals for MII or 9 signals for RMII, and can be clocked using the 25 MHz (MII) or 50 MHz (RMII) output from the STM32F217xx. The STM32F217xx includes the following features: Supports 10 and 100 Mbit/s rates Dedicated DMA controller allowing high-speed transfers between the dedicated SRAM and the descriptors (see the STM32F20x and STM32F21x reference manual for details) Tagged MAC frame support (VLAN support) Half-duplex (CSMA/CD) and full-duplex operation MAC control sublayer (control frames) support 32-bit CRC generation and removal Several address filtering modes for physical and multicast address (multicast and group addresses) 32-bit status code for each transmitted or received frame Internal FIFOs to buffer transmit and receive frames. The transmit FIFO and the receive FIFO are both 2 Kbytes, that is 4 Kbytes in total Supports hardware PTP (precision time protocol) in accordance with IEEE 1588 2008 (PTP V2) with the time stamp comparator connected to the TIM2 input Triggers interrupt when system time becomes greater than target time Doc ID 17050 Rev 6 29/168 Description 2.2.27 STM32F215xx, STM32F217xx Controller area network (CAN) The two CANs are compliant with the 2.0A and B (active) specifications with a bitrate up to 1 Mbit/s. They can receive and transmit standard frames with 11-bit identifiers as well as extended frames with 29-bit identifiers. Each CAN has three transmit mailboxes, two receive FIFOS with 3 stages and 28 shared scalable filter banks (all of them can be used even if one CAN is used). The 256 bytes of SRAM which are allocated for each CAN are not shared with any other peripheral. 2.2.28 Universal serial bus on-the-go full-speed (OTG_FS) The STM32F215xx and STM32F217xx embed an USB OTG full-speed device/host/OTG peripheral with integrated transceivers. The USB OTG FS peripheral is compliant with the USB 2.0 specification and with the OTG 1.0 specification. It has software-configurable endpoint setting and supports suspend/resume. The USB OTG full-speed controller requires a dedicated 48 MHz clock that is generated by a PLL connected to the HSE oscillator. The major features are: 2.2.29 Combined Rx and Tx FIFO size of 320 x 35 bits with dynamic FIFO sizing Supports the session request protocol (SRP) and host negotiation protocol (HNP) 4 bidirectional endpoints 8 host channels with periodic OUT support HNP/SNP/IP inside (no need for any external resistor) For OTG/Host modes, a power switch is needed in case bus-powered devices are connected Internal FS OTG PHY support Universal serial bus on-the-go high-speed (OTG_HS) The STM32F215xx and STM32F217xx devices embed a USB OTG high-speed (up to 480 Mb/s) device/host/OTG peripheral. The USB OTG HS supports both full-speed and high-speed operations. It integrates the transceivers for full-speed operation (12 MB/s) and features a UTMI low-pin interface (ULPI) for high-speed operation (480 MB/s). When using the USB OTG HS in HS mode, an external PHY device connected to the ULPI is required. The USB OTG HS peripheral is compliant with the USB 2.0 specification and with the OTG 1.0 specification. It has software-configurable endpoint setting and supports 30/168 Doc ID 17050 Rev 6 STM32F215xx, STM32F217xx Description suspend/resume. The USB OTG full-speed controller requires a dedicated 48 MHz clock that is generated by a PLL connected to the HSE oscillator. The major features are: 2.2.30 Combined Rx and Tx FIFO size of 1024x 35 bits with dynamic FIFO sizing Supports the session request protocol (SRP) and host negotiation protocol (HNP) 6 bidirectional endpoints 12 host channels with periodic OUT support Internal FS OTG PHY support External FS OTG PHY support through an I2C connection External HS or HS OTG operation supporting ULPI in SDR mode. The OTG PHY is connected to the microcontroller ULPI port through 12 signals. It can be clocked using the 60 MHz output. Internal USB DMA HNP/SNP/IP inside (no need for any external resistor) For OTG/Host modes, a power switch is needed in case bus-powered devices are connected Audio PLL (PLLI2S) The devices feature an additional dedicated PLL for audio I2S application. It allows to achieve error-free I2S sampling clock accuracy without compromising on the CPU performance, while using USB peripherals. The PLLI2S configuration can be modified to manage an I2S sample rate change without disabling the main PLL (PLL) used for CPU, USB and Ethernet interfaces. The audio PLL can be programmed with very low error to obtain sampling rates ranging from 8 kHz to 192 kHz. In addition to the audio PLL, a master clock input pin can be used to synchronize the I2S flow with an external PLL (or Codec output). 2.2.31 Digital camera interface (DCMI) The camera interface is not available in STM32F215xx devices. STM32F217xx products embed a camera interface that can connect with camera modules and CMOS sensors through an 8-bit to 14-bit parallel interface, to receive video data. The camera interface can sustain up to 27 Mbyte/s at 27 MHz or 48 Mbyte/s at 48 MHz. It features: Programmable polarity for the input pixel clock and synchronization signals Parallel data communication can be 8-, 10-, 12- or 14-bit Supports 8-bit progressive video monochrome or raw Bayer format, YCbCr 4:2:2 progressive video, RGB 565 progressive video or compressed data (like JPEG) Supports continuous mode or snapshot (a single frame) mode Capability to automatically crop the image Doc ID 17050 Rev 6 31/168 Description 2.2.32 STM32F215xx, STM32F217xx Cryptographic acceleration The STM32F215xx and STM32F217xx devices embed a cryptographic accelerator. This cryptographic accelerator provides a set of hardware acceleration for the advanced cryptographic algorithms usually needed to provide confidentiality, authentication, data integrity and non repudiation when exchanging messages with a peer. These algorithms consists of: Encryption/Decryption - DES/TDES (data encryption standard/triple data encryption standard): ECB (electronic codebook) and CBC (cipher block chaining) chaining algorithms, 64-, 128- or 192-bit key - AES (advanced encryption standard): ECB, CBC and CTR (counter mode) chaining algorithms, 128, 192 or 256-bit key Universal hash 2.2.33 - SHA-1 (secure hash algorithm) - MD5 It also provides a true random number generator that deliver 32-bit random numbers produced by an integrated analog circuit. True random number generator (RNG) All STM32F2xxx products embed a true RNG that delivers 32-bit random numbers produced by an integrated analog circuit. 32/168 Doc ID 17050 Rev 6 STM32F215xx, STM32F217xx 2.2.34 Description GPIOs (general-purpose inputs/outputs) Each of the GPIO pins can be configured by software as output (push-pull or open-drain, with or without pull-up or pull-down), as input (floating, with or without pull-up or pull-down) or as peripheral alternate function. Most of the GPIO pins are shared with digital or analog alternate functions. All GPIOs are high-current-capable and have speed selection to better manage internal noise, power consumption and electromagnetic emission. The I/O alternate function configuration can be locked if needed by following a specific sequence in order to avoid spurious writing to the I/Os registers. To provide fast I/O handling, the GPIOs are on the fast AHB1 bus with a clock up to 120 MHz that leads to a maximum I/O toggling speed of 60 MHz. 2.2.35 ADCs (analog-to-digital converters) Three 12-bit analog-to-digital converters are embedded and each ADC shares up to 16 external channels, performing conversions in the single-shot or scan mode. In scan mode, automatic conversion is performed on a selected group of analog inputs. Additional logic functions embedded in the ADC interface allow: Simultaneous sample and hold Interleaved sample and hold The ADC can be served by the DMA controller. An analog watchdog feature allows very precise monitoring of the converted voltage of one, some or all selected channels. An interrupt is generated when the converted voltage is outside the programmed thresholds. The events generated by the timers TIM1, TIM2, TIM3, TIM4, TIM5 and TIM8 can be internally connected to the ADC start trigger and injection trigger, respectively, to allow the application to synchronize A/D conversion and timers. 2.2.36 DAC (digital-to-analog converter) The two 12-bit buffered DAC channels can be used to convert two digital signals into two analog voltage signal outputs. The design structure is composed of integrated resistor strings and an amplifier in inverting configuration. This dual digital Interface supports the following features: two DAC converters: one for each output channel 8-bit or 12-bit monotonic output left or right data alignment in 12-bit mode synchronized update capability noise-wave generation triangular-wave generation dual DAC channel independent or simultaneous conversions DMA capability for each channel external triggers for conversion input voltage reference VREF+ Eight DAC trigger inputs are used in the device. The DAC channels are triggered through the timer update outputs that are also connected to different DMA streams. Doc ID 17050 Rev 6 33/168 Description 2.2.37 STM32F215xx, STM32F217xx Temperature sensor The temperature sensor has to generate a voltage that varies linearly with temperature. The conversion range is between 1.8 and 3.6 V. The temperature sensor is internally connected to the ADC1_IN16 input channel which is used to convert the sensor output voltage into a digital value. As the offset of the temperature sensor varies from chip to chip due to process variation, the internal temperature sensor is mainly suitable for applications that detect temperature changes instead of absolute temperatures. If an accurate temperature reading is needed, then an external temperature sensor part should be used. 2.2.38 Serial wire JTAG debug port (SWJ-DP) The ARM SWJ-DP interface is embedded, and is a combined JTAG and serial wire debug port that enables either a serial wire debug or a JTAG probe to be connected to the target. The JTAG TMS and TCK pins are shared with SWDIO and SWCLK, respectively, and a specific sequence on the TMS pin is used to switch between JTAG-DP and SW-DP. 2.2.39 Embedded Trace MacrocellTM The ARM Embedded Trace Macrocell provides a greater visibility of the instruction and data flow inside the CPU core by streaming compressed data at a very high rate from the STM32F21x through a small number of ETM pins to an external hardware trace port analyzer (TPA) device. The TPA is connected to a host computer using USB, Ethernet, or any other high-speed channel. Real-time instruction and data flow activity can be recorded and then formatted for display on the host computer that runs the debugger software. TPA hardware is commercially available from common development tool vendors. The Embedded Trace Macrocell operates with third party debugger software tools. 34/168 Doc ID 17050 Rev 6 STM32F215xx, STM32F217xx Pinouts and pin description STM32F21x LQFP64 pinout 6$$? 633? 0" 0" "//4 0" 0" 0" 0" 0" 0$ 0# 0# 0# 0! 0! Figure 9. 6"!4 0# 24#?!& 0# /3#?). 0# /3#?/54 0( /3#?). 0( /3#?/54 .234 0# 0# 0# 0# 633! 6$$! 0! 7+50 0! 0! 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 1 47 2 46 3 45 4 44 5 43 6 42 7 41 8 ,1&0 40 9 39 10 38 11 37 12 36 13 35 14 34 15 33 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 6$$? 6#!0? 0! 0! 0! 0! 0! 0! 0# 0# 0# 0# 0" 0" 0" 0" 0! 633? 6$$? 0! 0! 0! 0! 0# 0# 0" 0" 0" 0" 0" 6#!0? 6$$? 3 Pinouts and pin description AIB Doc ID 17050 Rev 6 35/168 Pinouts and pin description STM32F215xx, STM32F217xx 6$$? 2&5 0% 0% 0" 0" "//4 0" 0" 0" 0" 0" 0$ 0$ 0$ 0$ 0$ 0$ 0$ 0$ 0# 0# 0# 0! 0! Figure 10. STM32F21x LQFP100 pinout ,1&0 6$$? 633? 6#!0? 0! 0! 0! 0! 0! 0! 0# 0# 0# 0# 0$ 0$ 0$ 0$ 0$ 0$ 0$ 0$ 0" 0" 0" 0" 0! 633? 6$$? 0! 0! 0! 0! 0# 0# 0" 0" 0" 0% 0% 0% 0% 0% 0% 0% 0% 0% 0" 0" 6#!0? 6$$? 0% 0% 0% 0% 0% 6"!4 0# 24#?!& 0# /3#?). 0# /3#?/54 633? 6$$? 0( /3#?). 0( /3#?/54 .234 0# 0# 0# 0# 6$$? 633! 62%& 6$$! 0! 7+50 0! 0! AID 1. RFU means "reserved for future use". This pin can be tied to VDD,VSS or left unconnected. 36/168 Doc ID 17050 Rev 6 STM32F215xx, STM32F217xx Pinouts and pin description 2&5 0% 0% 0" 0" "//4 0" 0" 0" 0" 0" 0' 6$$? 633? 0' 0' 0' 0' 0' 0' 0$ 0$ 6$$? 633? 0$ 0$ 0$ 0$ 0$ 0$ 0# 0# 0# 0! 0! 6$$? Figure 11. STM32F21x LQFP144 pinout ,1&0 6$$? 633? 6#!0? 0! 0! 0! 0! 0! 0! 0# 0# 0# 0# 6$$? 633? 0' 0' 0' 0' 0' 0' 0' 0$ 0$ 6$$? 633? 0$ 0$ 0$ 0$ 0$ 0$ 0" 0" 0" 0" 633? 6$$? 0& 0& 0& 0' 0' 0% 0% 0% 633? 6$$? 0% 0% 0% 0% 0% 0% 0" 0" 6#!0? 6$$? 0! 633? 6$$? 0! 0! 0! 0! 0# 0# 0" 0" 0" 0& 0& 0% 0% 0% 0% 0% 6"!4 0# 24#?!& 0# /3#?). 0# /3#?/54 0& 0& 0& 0& 0& 0& 633? 6$$? 0& 0& 0& 0& 0& 0( /3#?). 0( /3#?/54 .234 0# 0# 0# 0# 6$$? 633! 62%& 6$$! 0! 7+50 0! 0! AID 1. RFU means "reserved for future use". This pin can be tied to VDD,VSS or left unconnected. Doc ID 17050 Rev 6 37/168 Pinouts and pin description STM32F215xx, STM32F217xx $$? 2&5 0% 0% 0" 0" "//4 0" 0" 0" 0" 0" 0' 6$$? 633? 0' 0' 0' 0' 0' 0' 0$ 0$ 6$$? 633? 0$ 0$ 0$ 0$ 0$ 0$ 0# 0# 0# 0! 0! 6$$? 633? 0) 0) 6 0) 0) 0) 0) Figure 12. STM32F21x LQFP176 pinout ,1&0 0) 0) 0( 0( 0( 6$$? 633? 6#!0? 0! 0! 0! 0! 0! 0! 0# 0# 0# 0# 6$$? 633? 0' 0' 0' 0' 0' 0' 0' 0$ 0$ 6$$? 633? 0$ 0$ 0$ 0$ 0$ 0$ 0" 0" 0" 0" 6$$? 633? 0( 633? 6$$? 0& 0& 0& 0' 0' 0% 0% 0% 633? 6$$? 0% 0% 0% 0% 0% 0% 0" 0" 6#!0? 6$$? 0( 0( 0( 0( 0( 0( 633? 6$$? 0! 0! 0! 0! 0# 0# 0" 0" 0" 0& 0& 0( 0( 0! 0% 0% 0% 0% 0% 6"!4 0) 24#?!& 0# 24#?!& 0# /3#?). 0# /3#?/54 0) 0) 0) 633? 6$$? 0& 0& 0& 0& 0& 0& 633? 6$$? 0& 0& 0& 0& 0& 0( /3#?). 0( /3#?/54 .234 0# 0# 0# 0# 6$$? 633! 62%& 6$$! 0! 7+50 0! 0! 0( 0( AID 1. RFU means "reserved for future use". This pin can be tied to VDD,VSS or left unconnected. 38/168 Doc ID 17050 Rev 6 STM32F215xx, STM32F217xx Pinouts and pin description Figure 13. STM32F21x UFBGA176 ballout 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 A PE3 PE2 PE1 PE0 PB8 PB5 PG14 PG13 PB4 PB3 PD7 PC12 PA15 PA14 PA13 B PE4 PE5 PE6 PB9 PB7 PB6 PG15 PG12 PG11 PG10 PD6 PD0 PC11 PC10 PA12 C VBAT PI7 PI6 PI5 VDD_3 RFU VDD_11 VDD_10 VDD_15 PG9 PD5 PD1 PI3 PI2 PA11 D PC13TAMP1 PI8TAMP2 PI9 PI4 VSS BOOT0 VSS_11 VSS_10 VSS_15 PD4 PD3 PD2 PH15 PI1 PA10 E PC14OSC32_IN PF0 PI10 PI11 PH13 PH14 PI0 PA9 VSS_13 VDD_13 PH2 VSS VSS VSS VSS VSS VSS_2 VCAP2 PC9 PA8 PC15- F OSC32_OUT G PH0OSC_IN VSS_5 VDD_5 PH3 VSS VSS VSS VSS VSS VSS_9 VDD_2 PC8 PC7 H PH1OSC_OUT PF2 PF1 PH4 VSS VSS VSS VSS VSS VSS_14 VDD_9 PG8 PC6 J NRST PF3 PF4 PH5 VSS VSS VSS VSS VSS VDD_14 VDD_8 PG7 PG6 K PF7 PF6 PF5 VDD_4 VSS VSS VSS VSS VSS PH12 PG5 PG4 PG3 L PF10 PF9 PF8 REGOFF PH11 PH10 PD15 PG2 M VSSA PC0 PC1 PC2 PC3 PB2 PG1 VSS_6 VSS_7 VCAP1 PH6 PH8 PH9 PD14 PD13 N VREF- PA1 PA0WKUP PA4 PC4 PF13 PG0 VDD_6 VDD_7 VDD_1 PE13 PH7 PD12 PD11 PD10 P VREF+ PA2 PA6 PA5 PC5 PF12 PF15 PE8 PE9 PE11 PE14 PB12 PB13 PD9 PD8 R VDDA PA3 PA7 PB1 PB0 PF11 PF14 PE7 PE10 PE12 PE15 PB10 PB11 PB14 PB15 AIB 1. RFU means "reserved for future use". This pin can be tied to VDD,VSS or left unconnected. 2. Top view. STM32F21x pin and ball definitions LQFP144 LQFP176 UFBGA176 Alternate functions LQFP100 Main function(3) (after reset) LQFP64 Type(1) Pins I / O Level(2) Table 5. - 1 1 1 A2 PE2 I/O FT PE2 TRACECLK/ FSMC_A23 / ETH_MII_TXD3 / EVENTOUT - 2 2 2 A1 PE3 I/O FT PE3 TRACED0/FSMC_A19/ EVENTOUT - 3 3 3 B1 PE4 I/O FT PE4 TRACED1/FSMC_A20 / DCMI_D4/ EVENTOUT - 4 4 4 B2 PE5 I/O FT PE5 TRACED2 / FSMC_A21 / TIM9_CH1 / DCMI_D6/ EVENTOUT - 5 5 5 B3 PE6 I/O FT PE6 TRACED3 / FSMC_A22 / TIM9_CH2 / DCMI_D7/ EVENTOUT 1 6 6 6 C1 VBAT Pin name S Other functions VBAT Doc ID 17050 Rev 6 39/168 Pinouts and pin description STM32F21x pin and ball definitions (continued) LQFP100 LQFP144 LQFP176 UFBGA176 - - - 7 D2 2 3 7 8 7 8 8 9 Pin name PI8(4) D1 PC13(4) E1 Type(1) LQFP64 Pins I / O Level(2) Table 5. STM32F215xx, STM32F217xx Other functions PI8(5) EVENTOUT RTC_AF2 PC13 EVENTOUT RTC_AF1 I/O FT PC14 (5) EVENTOUT OSC32_IN PC15 OSC32_OUT(6) I/O FT PC15(5) EVENTOUT OSC32_OUT I/O FT (6) -OSC32_IN (4) 4 9 9 10 - - - 11 D3 PI9 I/O FT PI9 CAN1_RX / EVENTOUT - - - 12 E3 PI10 I/O FT PI10 ETH_MII_RX_ER/ EVENTOUT - - - 13 E4 PI11 I/O FT PI11 OTG_HS_ULPI_DIR/ EVENTOUT - - - 14 F2 VSS_13 S VSS_13 - - - 15 F3 VDD_13 S VDD_13 - - 10 16 E2 PF0 I/O FT PF0 FSMC_A0 / I2C2_SDA/ EVENTOUT - - 11 17 H3 PF1 I/O FT PF1 FSMC_A1 / I2C2_SCL/ EVENTOUT - - 12 18 H2 PF2 I/O FT PF2 FSMC_A2 / I2C2_SMBA/ EVENTOUT - - 13 19 J2 PF3(6) I/O FT PF3 FSMC_A3/ EVENTOUT ADC3_IN9 J3 PF4(6) I/O FT PF4 FSMC_A4/ EVENTOUT ADC3_IN14 15 21 K3 PF5(6) I/O FT PF5 FSMC_A5/ EVENTOUT ADC3_IN15 - 10 16 22 G2 VSS_5 S VSS_5 - 11 17 23 G3 VDD_5 S VDD_5 - - 14 20 F1 Alternate functions (5) PC14(4) I/O FT Main function(3) (after reset) - - 18 24 K2 PF6(6) I/O FT PF6 TIM10_CH1 / FSMC_NIORD/ EVENTOUT ADC3_IN4 - - 19 25 K1 PF7(6) I/O FT PF7 TIM11_CH1/FSMC_NREG/ EVENTOUT ADC3_IN5 - - 20 26 L3 PF8(6) I/O FT PF8 TIM13_CH1 / FSMC_NIOWR/ EVENTOUT ADC3_IN6 - - 21 27 L2 PF9(6) I/O FT PF9 TIM14_CH1 / FSMC_CD/ EVENTOUT ADC3_IN7 - - 22 28 L1 PF10(6) I/O FT PF10 FSMC_INTR/ EVENTOUT ADC3_IN8 12 23 29 G1 PH0(6)-OSC_IN I/O FT PH0 EVENTOUT OSC_IN 6 13 24 30 H1 PH1(6)-OSC_OUT I/O FT PH1 EVENTOUT OSC_OUT 7 14 25 31 5 40/168 J1 NRST I/O NRST Doc ID 17050 Rev 6 STM32F215xx, STM32F217xx STM32F21x pin and ball definitions (continued) Type(1) UFBGA176 LQFP176 Alternate functions Other functions LQFP100 Main function(3) (after reset) LQFP64 LQFP144 Pins I / O Level(2) Table 5. Pinouts and pin description 8 15 26 32 M2 PC0(6) I/O FT PC0 OTG_HS_ULPI_STP/ EVENTOUT ADC123_ IN10 9 16 27 33 M3 PC1(6) I/O FT PC1 ETH_MDC/ EVENTOUT ADC123_ IN11 10 17 28 34 M4 PC2(6) PC2 SPI2_MISO / OTG_HS_ULPI_DIR / ETH_MII_TXD2/ EVENTOUT ADC123_ IN12 11 18 29 35 M5 (6) PC3 SPI2_MOSI / I2S2_SD / OTG_HS_ULPI_NXT / ETH_MII_TX_CLK/ EVENTOUT ADC123_ IN13 Pin name PC3 I/O FT I/O FT VDD_12 S VDD_12 VSSA S VSSA N1 VREF- S VREF- 21 32 38 P1 VREF+ S VREF+ 13 22 33 39 R1 VDDA S VDDA - 19 30 36 - 12 20 31 37 M1 - - - - 14 23 34 40 N3 PA0(7)-WKUP(6) I/O FT PA0-WKUP USART2_CTS/ UART4_TX/ ETH_MII_CRS / ADC123_IN0/ TIM2_CH1_ETR/ WKUP TIM5_CH1 / TIM8_ETR/ EVENTOUT USART2_RTS / UART4_RX/ ETH_RMII_REF_CLK / ETH_MII_RX_CLK / ADC123_IN1 TIM5_CH2 / TIM2_CH2/ EVENTOUT 15 24 35 41 N2 PA1(6) I/O FT PA1 16 25 36 42 P2 PA2(6) I/O FT PA2 USART2_TX/TIM5_CH3 / TIM9_CH1 / TIM2_CH3 / ETH_MDIO/ EVENTOUT - - - 43 F4 PH2 I/O FT PH2 ETH_MII_CRS/ EVENTOUT - - - 44 G4 PH3 I/O FT PH3 ETH_MII_COL/ EVENTOUT - - - 45 H4 PH4 I/O FT PH4 I2C2_SCL / OTG_HS_ULPI_NXT/ EVENTOUT - - - 46 PH5 I/O FT PH5 I2C2_SDA/ EVENTOUT J4 17 26 37 47 R2 (6) PA3 I/O FT PA3 Doc ID 17050 Rev 6 ADC123_IN2 USART2_RX/TIM5_CH4 / TIM9_CH2 / TIM2_CH4 / ADC123_IN3 OTG_HS_ULPI_D0 / ETH_MII_COL/ EVENTOUT 41/168 Pinouts and pin description STM32F21x pin and ball definitions (continued) Type(1) 18 27 38 48 Main function(3) (after reset) Pin name - VSS_4 S VSS_4 L4 REGOFF I/O REGOFF VDD_4 S VDD_4 UFBGA176 LQFP176 LQFP144 LQFP100 LQFP64 Pins I / O Level(2) Table 5. STM32F215xx, STM32F217xx 19 28 39 49 K4 20 29 40 50 N4 PA4(6) 21 30 41 51 P4 PA5(6) 22 31 42 52 P3 (6) PA6 I/O TT I/O TT I/O FT Alternate functions Other functions PA4 SPI1_NSS / SPI3_NSS / USART2_CK / DCMI_HSYNC / OTG_HS_SOF/ I2S3_WS/ EVENTOUT ADC12_IN4 /DAC1_OUT PA5 SPI1_SCK/ OTG_HS_ULPI_CK / TIM2_CH1_ETR/ TIM8_CHIN/ EVENTOUT ADC12_IN5 /DAC2_OUT PA6 SPI1_MISO / TIM8_BKIN/TIM13_CH1 / DCMI_PIXCLK / TIM3_CH1 / TIM1_BKIN/ EVENTOUT ADC12_IN6 ADC12_IN7 23 32 43 53 R3 PA7(6) I/O FT PA7 SPI1_MOSI/ TIM8_CH1N / TIM14_CH1 TIM3_CH2/ ETH_MII_RX_DV / TIM1_CH1N / RMII_CRS_DV/ EVENTOUT 24 33 44 54 N5 PC4(6) I/O FT PC4 ETH_RMII_RX_D0 / ETH_MII_RX_D0/ EVENTOUT ADC12_IN14 25 34 45 55 P5 PC5(6) I/O FT PC5 ETH_RMII_RX_D1 / ETH_MII_RX_D1 / EVENTOUT ADC12_IN15 26 35 46 56 R5 PB0(6) PB0 TIM3_CH3 / TIM8_CH2N/ OTG_HS_ULPI_D1/ ETH_MII_RXD2 / TIM1_CH2N/ EVENTOUT ADC12_IN8 PB1 TIM3_CH4 / TIM8_CH3N/ OTG_HS_ULPI_D2/ ETH_MII_RXD3 / OTG_HS_INTN / TIM1_CH3N/ EVENTOUT ADC12_IN9 I/O FT 27 36 47 57 R4 PB1(6) 28 37 48 58 M6 PB2 I/O FT PB2-BOOT1 I/O FT EVENTOUT - - 49 59 R6 PF11 I/O FT PF11 DCMI_12/ EVENTOUT - - 50 60 P6 PF12 I/O FT PF12 FSMC_A6/ EVENTOUT - - 51 61 M8 VSS_6 42/168 S VSS_6 Doc ID 17050 Rev 6 STM32F215xx, STM32F217xx STM32F21x pin and ball definitions (continued) Type(1) UFBGA176 LQFP176 S Main function(3) (after reset) LQFP100 Pin name LQFP64 LQFP144 Pins I / O Level(2) Table 5. Pinouts and pin description - - 52 62 N8 VDD_6 - - 53 63 N6 PF13 I/O FT PF13 FSMC_A7/ EVENTOUT - - 54 64 R7 PF14 I/O FT PF14 FSMC_A8/ EVENTOUT - - 55 65 P7 PF15 I/O FT PF15 FSMC_A9/ EVENTOUT - - 56 66 N7 PG0 I/O FT PG0 FSMC_A10/ EVENTOUT - - 57 67 M7 PG1 I/O FT PG1 FSMC_A11/ EVENTOUT - 38 58 68 R8 PE7 I/O FT PE7 FSMC_D4/TIM1_ETR/ EVENTOUT - 39 59 69 P8 PE8 I/O FT PE8 FSMC_D5/TIM1_CH1N/ EVENTOUT - 40 60 70 P9 PE9 I/O FT PE9 FSMC_D6/TIM1_CH1/ EVENTOUT Alternate functions VDD_6 - - 61 71 M9 VSS_7 S VSS_7 - - 62 72 N9 VDD_7 S VDD_7 - 41 63 73 R9 PE10 I/O FT PE10 FSMC_D7/TIM1_CH2N/ EVENTOUT - 42 64 74 P10 PE11 I/O FT PE11 FSMC_D8/TIM1_CH2/ EVENTOUT - 43 65 75 R10 PE12 I/O FT PE12 FSMC_D9/TIM1_CH3N/ EVENTOUT - 44 66 76 N11 PE13 I/O FT PE13 FSMC_D10/TIM1_CH3/ EVENTOUT - 45 67 77 P11 PE14 I/O FT PE14 FSMC_D11/TIM1_CH4/ EVENTOUT - 46 68 78 R11 PE15 I/O FT PE15 FSMC_D12/TIM1_BKIN/ EVENTOUT PB10 SPI2_SCK/ I2S2_SCK/ I2C2_SCL / USART3_TX / OTG_HS_ULPI_D3 / ETH_MII_RX_ER / OTG_HS_SCL / TIM2_CH3/ EVENTOUT PB11 I2C2_SDA/USART3_RX/ OTG_HS_ULPI_D4 / ETH_RMII_TX_EN/ ETH_MII_TX_EN / OTG_HS_SDA / TIM2_CH4/ EVENTOUT 29 47 69 79 R12 PB10 30 48 70 80 R13 PB11 31 49 71 81 M10 VCAP_1 I/O FT I/O FT S Other functions VCAP_1 Doc ID 17050 Rev 6 43/168 Pinouts and pin description STM32F21x pin and ball definitions (continued) 32 50 72 82 N10 Pin name Type(1) UFBGA176 LQFP176 LQFP144 LQFP100 LQFP64 Pins VDD_1 S I / O Level(2) Table 5. STM32F215xx, STM32F217xx Main function(3) (after reset) Alternate functions VDD_1 - - - 83 M11 PH6 I/O FT PH6 I2C2_SMBA / TIM12_CH1 / ETH_MII_RXD2/ EVENTOUT - - - 84 N12 PH7 I/O FT PH7 I2C3_SCL / ETH_MII_RXD3/ EVENTOUT - - - 85 M12 PH8 I/O FT PH8 I2C3_SDA / DCMI_HSYNC/ EVENTOUT - - - 86 M13 PH9 I/O FT PH9 I2C3_SMBA / TIM12_CH2/ DCMI_D0/ EVENTOUT - - - 87 L13 PH10 I/O FT PH10 TIM5_CH1_ETR / DCMI_D1/ EVENTOUT - - - 88 L12 PH11 I/O FT PH11 TIM5_CH2 / DCMI_D2/ EVENTOUT - - - 89 K12 PH12 I/O FT PH12 TIM5_CH3 / DCMI_D3/ EVENTOUT - - - 90 H12 VSS_14 S VSS_14 - - - 91 J12 VDD_14 S VDD_14 33 51 73 92 P12 34 52 74 93 P13 35 53 75 94 R14 36 54 76 95 R15 44/168 PB12 PB13 PB14 PB15 I/O FT I/O FT I/O FT I/O FT Other functions PB12 SPI2_NSS/I2S2_WS/ I2C2_SMBA/ USART3_CK/ TIM1_BKIN / CAN2_RX / OTG_HS_ULPI_D5/ ETH_RMII_TXD0 / ETH_MII_TXD0/ OTG_HS_ID/ EVENTOUT PB13 SPI2_SCK / I2S2_SCK / USART3_CTS/ TIM1_CH1N /CAN2_TX / OTG_HS_ULPI_D6 / ETH_RMII_TXD1 / ETH_MII_TXD1/ EVENTOUT PB14 SPI2_MISO/ TIM1_CH2N / TIM12_CH1 / OTG_HS_DM USART3_RTS/ TIM8_CH2N/ EVENTOUT PB15 SPI2_MOSI / I2S2_SD / TIM1_CH3N / TIM8_CH3N / TIM12_CH2 / OTG_HS_DP / RTC_50Hz/ EVENTOUT Doc ID 17050 Rev 6 OTG_HS_ VBUS STM32F215xx, STM32F217xx STM32F21x pin and ball definitions (continued) Type(1) UFBGA176 LQFP176 Alternate functions LQFP100 Main function(3) (after reset) LQFP64 LQFP144 Pins I / O Level(2) Table 5. Pinouts and pin description - 55 77 96 P15 PD8 I/O FT PD8 FSMC_D13 / USART3_TX/ EVENTOUT - 56 78 97 P14 PD9 I/O FT PD9 FSMC_D14 / USART3_RX/ EVENTOUT - 57 79 98 N15 PD10 I/O FT PD10 FSMC_D15 / USART3_CK/ EVENTOUT - 58 80 99 N14 PD11 I/O FT PD11 FSMC_A16/USART3_CTS/ EVENTOUT - 59 81 100 N13 PD12 I/O FT PD12 FSMC_A17/TIM4_CH1 / USART3_RTS/ EVENTOUT - 60 82 101 M15 PD13 I/O FT PD13 FSMC_A18/TIM4_CH2/ EVENTOUT - - 83 102 - - - Pin name VSS_8 S VSS_8 84 103 J13 VDD_8 S VDD_8 - 61 85 104 M14 PD14 I/O FT PD14 FSMC_D0/TIM4_CH3/ EVENTOUT - 62 86 105 L14 PD15 I/O FT PD15 FSMC_D1/TIM4_CH4/ EVENTOUT - - 87 106 L15 PG2 I/O FT PG2 FSMC_A12/ EVENTOUT - - 88 107 K15 PG3 I/O FT PG3 FSMC_A13/ EVENTOUT - - 89 108 K14 PG4 I/O FT PG4 FSMC_A14/ EVENTOUT - - 90 109 K13 PG5 I/O FT PG5 FSMC_A15/ EVENTOUT - - 91 110 J15 PG6 I/O FT PG6 FSMC_INT2/ EVENTOUT - - 92 111 J14 PG7 I/O FT PG7 FSMC_INT3 /USART6_CK/ EVENTOUT - - 93 112 H14 PG8 I/O FT PG8 USART6_RTS / ETH_PPS_OUT/ EVENTOUT - - 94 113 G12 VSS_9 S VSS_9 - - 95 114 H13 VDD_9 S VDD_9 37 63 96 115 H15 PC6 I/O FT PC6 Doc ID 17050 Rev 6 Other functions I2S2_MCK / TIM8_CH1/SDIO_D6 / USART6_TX / DCMI_D0/TIM3_CH1/ EVENTOUT 45/168 Pinouts and pin description STM32F21x pin and ball definitions (continued) Pin name Type(1) UFBGA176 LQFP176 LQFP144 LQFP100 LQFP64 Pins I / O Level(2) Table 5. STM32F215xx, STM32F217xx Main function(3) (after reset) Alternate functions 38 64 97 116 G15 PC7 I/O FT PC7 I2S3_MCK / TIM8_CH2/SDIO_D7 / USART6_RX / DCMI_D1/TIM3_CH2/ EVENTOUT 39 65 98 117 G14 PC8 I/O FT PC8 TIM8_CH3/SDIO_D0 /TIM3_CH3/ USART6_CK / DCMI_D2/ EVENTOUT 40 66 99 118 F14 PC9 I/O FT PC9 I2S2_CKIN/ I2S3_CKIN/ MCO2 / TIM8_CH4/SDIO_D1 / /I2C3_SDA / DCMI_D3 / TIM3_CH4/ EVENTOUT 41 67 100 119 F15 PA8 I/O FT PA8 MCO1 / USART1_CK/ TIM1_CH1/ I2C3_SCL/ OTG_FS_SOF/ EVENTOUT 42 68 101 120 E15 PA9 I/O FT PA9 USART1_TX/ TIM1_CH2 / I2C3_SMBA / DCMI_D0/ EVENTOUT 43 69 102 121 D15 PA10 I/O FT PA10 USART1_RX/ TIM1_CH3/ OTG_FS_ID/DCMI_D1/ EVENTOUT 44 70 103 122 C15 PA11 I/O FT PA11 USART1_CTS / CAN1_RX / TIM1_CH4 / OTG_FS_DM/ EVENTOUT 45 71 104 123 B15 PA12 I/O FT PA12 USART1_RTS / CAN1_TX/ TIM1_ETR/ OTG_FS_DP/ EVENTOUT 46 72 105 124 A15 PA13 I/O FT JTMS-SWDIO JTMS-SWDIO/ EVENTOUT 47 73 106 125 F13 VCAP_2 S VCAP_2 74 107 126 F12 VSS_2 S VSS_2 48 75 108 127 G13 VDD_2 S VDD_2 - - - - 128 E12 PH13 I/O FT PH13 TIM8_CH1N / CAN1_TX/ EVENTOUT - - - 129 E13 PH14 I/O FT PH14 TIM8_CH2N / DCMI_D4/ EVENTOUT - - - 130 D13 PH15 I/O FT PH15 TIM8_CH3N / DCMI_D11/ EVENTOUT - - - 131 E14 PI0 I/O FT PI0 TIM5_CH4 / SPI2_NSS / I2S2_WS / DCMI_D13/ EVENTOUT 46/168 Doc ID 17050 Rev 6 Other functions OTG_FS_ VBUS STM32F215xx, STM32F217xx STM32F21x pin and ball definitions (continued) Type(1) UFBGA176 LQFP144 Alternate functions LQFP100 Main function(3) (after reset) LQFP64 LQFP176 Pins I / O Level(2) Table 5. Pinouts and pin description - - - 132 D14 PI1 I/O FT PI1 SPI2_SCK / I2S2_SCK / DCMI_D8/ EVENTOUT - - - 133 C14 PI2 I/O FT PI2 TIM8_CH4 /SPI2_MISO / DCMI_D9/ EVENTOUT - - - 134 C13 PI3 I/O FT PI3 TIM8_ETR / SPI2_MOSI / I2S2_SD / DCMI_D10/ EVENTOUT - - - 135 D9 VSS_15 S VSS_15 - - - 136 C9 VDD_15 S VDD_15 Pin name 49 76 109 137 A14 PA14 I/O FT JTCK-SWCLK JTCK-SWCLK/ EVENTOUT 50 77 110 138 A13 PA15 I/O FT 51 78 111 139 B14 52 79 112 140 B13 53 80 113 141 A12 PC10 PC11 I/O FT I/O FT JTDI JTDI/ SPI3_NSS/ I2S3_WS/TIM2_CH1_ETR / SPI1_NSS/ EVENTOUT PC10 SPI3_SCK / I2S3_SCK / UART4_TX / SDIO_D2 / DCMI_D8 / USART3_TX/ EVENTOUT PC11 UART4_RX/ SPI3_MISO / SDIO_D3 / DCMI_D4/USART3_RX/ EVENTOUT PC12 I/O FT PC12 UART5_TX/SDIO_CK / DCMI_D9 / SPI3_MOSI / I2S3_SD / USART3_CK/ EVENTOUT - 81 114 142 B12 PD0 I/O FT PD0 FSMC_D2/CAN1_RX/ EVENTOUT - 82 115 143 C12 PD1 I/O FT PD1 FSMC_D3 / CAN1_TX/ EVENTOUT 54 83 116 144 D12 PD2 I/O FT PD2 TIM3_ETR/UART5_RX SDIO_CMD / DCMI_D11/ EVENTOUT - 84 117 145 D11 PD3 I/O FT PD3 FSMC_CLK/USART2_CTS/ EVENTOUT - 85 118 146 D10 PD4 I/O FT PD4 FSMC_NOE/USART2_RTS/ EVENTOUT - 86 119 147 C11 PD5 I/O FT PD5 FSMC_NWE/USART2_TX/ EVENTOUT - - 120 148 D8 VSS_10 S VSS_10 - - 121 149 C8 VDD_10 S VDD_10 Doc ID 17050 Rev 6 Other functions 47/168 Pinouts and pin description STM32F21x pin and ball definitions (continued) Type(1) UFBGA176 LQFP176 Alternate functions LQFP100 Main function(3) (after reset) LQFP64 LQFP144 Pins I / O Level(2) Table 5. STM32F215xx, STM32F217xx - 87 122 150 B11 PD6 I/O FT PD6 FSMC_NWAIT/USART2_RX / EVENTOUT - 88 123 151 A11 PD7 I/O FT PD7 USART2_CK/FSMC_NE1/F SMC_NCE2/ EVENTOUT - - 124 152 C10 PG9 I/O FT PG9 USART6_RX / FSMC_NE2/FSMC_NCE3/ EVENTOUT - - 125 153 B10 PG10 I/O FT PG10 FSMC_NCE4_1/ FSMC_NE3/ EVENTOUT Pin name - - 126 154 B9 PG11 I/O FT PG11 FSMC_NCE4_2 / ETH_MII_TX_EN / ETH _RMII_TX_EN/ EVENTOUT - - 127 155 B8 PG12 I/O FT PG12 FSMC_NE4 / USART6_RTS/ EVENTOUT PG13 FSMC_A24 / USART6_CTS /ETH_MII_TXD0/ ETH_RMII_TXD0/ EVENTOUT PG14 FSMC_A25 / USART6_TX /ETH_MII_TXD1/ ETH_RMII_TXD1/ EVENTOUT - - 128 156 A8 PG13 I/O FT - - 129 157 A7 PG14 I/O FT - - 130 158 D7 VSS_11 S VSS_11 - - 131 159 C7 VDD_11 S VDD_11 - - 132 160 B7 PG15 I/O FT PG15 JTDO/ TRACESWO/ SPI3_SCK / I2S3_SCK / TIM2_CH2 / SPI1_SCK/ EVENTOUT NJTRST NJTRST/ SPI3_MISO / TIM3_CH1 / SPI1_MISO/ EVENTOUT PB5 I2C1_SMBA/ CAN2_RX / OTG_HS_ULPI_D7 / ETH_PPS_OUT/TIM3_CH2 / SPI1_MOSI/ SPI3_MOSI / DCMI_D10 / I2S3_SD/ EVENTOUT 55 89 133 161 A10 PB3 JTDO/ I/O FT TRACESWO 56 90 134 162 A9 PB4 I/O FT 57 91 135 163 A6 48/168 PB5 I/O FT USART6_CTS / DCMI_D13/ EVENTOUT Doc ID 17050 Rev 6 Other functions STM32F215xx, STM32F217xx STM32F21x pin and ball definitions (continued) 58 92 136 164 B6 Pin name PB6 59 93 137 165 B5 PB7 60 94 138 166 D6 BOOT0 61 95 139 167 A5 62 96 140 168 B4 PB8 Type(1) UFBGA176 LQFP176 LQFP144 LQFP100 LQFP64 Pins I / O Level(2) Table 5. Pinouts and pin description I/O FT I/O FT I I/O FT Main function(3) (after reset) Alternate functions PB6 I2C1_SCL/ TIM4_CH1 / CAN2_TX / DCMI_D5/USART1_TX/ EVENTOUT PB7 I2C1_SDA / FSMC_NL(8) / DCMI_VSYNC / USART1_RX/ TIM4_CH2/ EVENTOUT BOOT0 VPP PB8 TIM4_CH3/SDIO_D4/ TIM10_CH1 / DCMI_D6 / ETH_MII_TXD3 / I2C1_SCL/ CAN1_RX/ EVENTOUT PB9 I/O FT PB9 SPI2_NSS/ I2S2_WS/ TIM4_CH4/ TIM11_CH1/ SDIO_D5 / DCMI_D7 / I2C1_SDA / CAN1_TX/ EVENTOUT - 97 141 169 A4 PE0 I/O FT PE0 TIM4_ETR / FSMC_NBL0 / DCMI_D2/ EVENTOUT - 98 142 170 A3 PE1 I/O FT PE1 FSMC_NBL1 / DCMI_D3/ EVENTOUT - - - - D5 VSS S VSS 63 - - - - VSS_3 S VSS_3 S VDD_3 99 143 171 C6 RFU(9) 64 100 144 172 C5 VDD_3 - Other functions - - - 173 D4 PI4 I/O FT PI4 TIM8_BKIN / DCMI_D5/ EVENTOUT - - - 174 C4 PI5 I/O FT PI5 TIM8_CH1 / DCMI_VSYNC/ EVENTOUT - - - 175 C3 PI6 I/O FT PI6 TIM8_CH2 / DCMI_D6/ EVENTOUT - - - 176 C2 PI7 I/O FT PI7 TIM8_CH3 / DCMI_D7/ EVENTOUT 1. I = input, O = output, S = supply, HiZ = high impedance. 2. FT = 5 V tolerant; TT = 3.6 V tolerant. 3. Function availability depends on the chosen device. 4. PC13, PC14, PC15 and PI8 are supplied through the power switch. Since the switch only sinks a limited amount of current (3 mA), the use of GPIOs PC13 to PC15 and PI8 in output mode is limited: the speed should not exceed 2 MHz with a maximum load of 30 pF and these I/Os must not be used as a current source (e.g. to drive an LED). Doc ID 17050 Rev 6 49/168 Pinouts and pin description STM32F215xx, STM32F217xx 5. Main function after the first backup domain power-up. Later on, it depends on the contents of the RTC registers even after reset (because these registers are not reset by the main reset). For details on how to manage these I/Os, refer to the RTC register description sections in the STM32F20x and STM32F21x reference manual, available from the STMicroelectronics website: www.st.com. 6. FT = 5 V tolerant except when in analog mode or oscillator mode (for PC14, PC15, PH0 and PH1). 7. If the device is delivered in an UFBGA176 package and if the REGOFF pin is set to VDD (Regulator OFF), then PA0 is used as an internal Reset (active low). 8. FSMC_NL pin is also named FSMC_NADV on memory devices. 9. RFU means "reserved for future use". This pin can be tied to VDD,VSS or left unconnected. 50/168 Doc ID 17050 Rev 6 Alternate function mapping AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 USART1/2/3 UART4/5/ USART6 USART2_CTS UART4_TX ETH_MII_CRS EVENTOUT UART4_RX ETH_MII _RX_CLK ETH_RMII _REF_CLK EVENTOUT Port SYS PA0-WKUP TIM1/2 TIM3/4/5 TIM2_CH1 TIM2_ETR TIM 5_CH1 TIM8/9/10/11 I2C1/I2C2/I2C3 SPI1/SPI2/I2S2 SPI3/I2S3 TIM8_ETR PA1 TIM2_CH2 TIM5_CH2 USART2_RTS PA2 TIM2_CH3 TIM5_CH3 TIM9_CH1 USART2_TX PA3 TIM2_CH4 TIM5_CH4 TIM9_CH2 USART2_RX PA4 SPI1_NSS PA5 TIM2_CH1 TIM2_ETR PA6 TIM1_BKIN PA7 TIM1_CH1N PA8 MCO1 SPI3_NSS I2S3_WS AF9 AF10 CAN1/CAN2/ OTG_FS/ OTG_HS TIM12/13/14 OTG_HS_ULPI_D0 AF11 AF12 AF13 ETH FSMC/SDIO/ OTG_HS DCMI ETH_MDIO EVENTOUT EVENTOUT OTG_HS_SOF SPI1_SCK TIM3_CH1 TIM8_BKIN SPI1_MISO TIM13_CH1 TIM3_CH2 TIM8_CH1N SPI1_MOSI TIM14_CH1 AF15 ETH _MII_COL USART2_CK TIM8_CH1N AF014 DCMI_HSYNC EVENTOUT DCMI_PIXCK EVENTOUT OTG_HS_ULPI_CK EVENTOUT ETH_MII _RX_DV ETH_RMII _CRS_DV EVENTOUT Doc ID 17050 Rev 6 TIM1_CH1 I2C3_SCL USART1_CK PA9 TIM1_CH2 I2C3_SMBA USART1_TX PA10 TIM1_CH3 USART1_RX PA11 TIM1_CH4 USART1_CTS CAN1_RX OTG_FS_DM EVENTOUT PA12 TIM1_ETR USART1_RTS CAN1_TX OTG_FS_DP EVENTOUT PA13 JTMS-SWDIO PA14 JTCK-SWCLK PA15 JTDI Pinouts and pin description 51/168 Table 6. OTG_FS_SOF EVENTOUT OTG_FS_ID DCMI_D0 EVENTOUT DCMI_D1 EVENTOUT EVENTOUT EVENTOUT TIM 2_CH1 TIM 2_ETR SPI1_NSS SPI3_NSS I2S3_WS EVENTOUT PB0 TIM1_CH2N TIM3_CH3 TIM8_CH2N OTG_HS_ULPI_D1 ETH _MII_RXD2 PB1 TIM1_CH3N TIM3_CH4 TIM8_CH3N OTG_HS_ULPI_D2 ETH _MII_RXD3 EVENTOUT OTG_HS_INTN EVENTOUT PB2 EVENTOUT JTDO/ TRACESWO PB4 JTRST TIM2_CH2 SPI1_SCK TIM3_CH1 SPI3_SCK I2S3_SCK SPI1_MISO SPI3_MISO SPI1_MOSI SPI3_MOSI I2S3_SD EVENTOUT EVENTOUT CAN2_RX PB5 TIM3_CH2 I2C1_SMBA PB6 TIM4_CH1 I2C1_SCL USART1_TX PB7 TIM4_CH2 I2C1_SDA USART1_RX PB8 TIM4_CH3 TIM10_CH1 I2C1_SCL PB9 TIM4_CH4 TIM11_CH1 I2C1_SDA PB10 TIM2_CH3 I2C2_SCL PB11 TIM2_CH4 I2C2_SDA PB12 TIM1_BKIN I2C2_SMBA PB13 TIM1_CH1N OTG_HS_ULPI_D7 FSMC_NL ETH _MII_TXD3 CAN1_TX USART3_TX OTG_HS_ULPI_D3 ETH_ MII_RX_ER USART3_RX SPI2_NSS I2S2_WS SPI2_SCK I2S2_SCK DCMI_D10 CAN2_TX CAN1_RX SPI2_NSS I2S2_WS SPI2_SCK I2S2_SCK ETH _PPS_OUT USART3_CK CAN2_RX USART3_CTS CAN2_TX EVENTOUT DCMI_VSYNC EVENTOUT SDIO_D4 DCMI_D6 EVENTOUT SDIO_D5 DCMI_D7 EVENTOUT OTG_HS_SCL ETH _MII_TX_EN OTG_HS_SDA ETH _RMII_TX_EN ETH _MII_TXD0 OTG_HS_ULPI_D5 OTG_HS_ID ETH _RMII_TXD0 ETH _MII_TXD1 OTG_HS_ULPI_D6 ETH _RMII_TXD1 OTG_HS_ULPI_D4 EVENTOUT DCMI_D5 EVENTOUT EVENTOUT EVENTOUT EVENTOUT STM32F215xx, STM32F217xx PB3 Alternate function mapping (continued) AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 USART1/2/3 UART4/5/ USART6 Port SYS PB14 PB15 TIM1/2 TIM3/4/5 TIM1_CH2N RTC_50Hz TIM1_CH3N TIM8/9/10/11 I2C1/I2C2/I2C3 SPI1/SPI2/I2S2 TIM8_CH2N SPI2_MISO TIM8_CH3N SPI2_MOSI I2S2_SD SPI3/I2S3 USART3_RTS AF9 AF10 CAN1/CAN2/ OTG_FS/ OTG_HS TIM12/13/14 AF11 AF12 AF13 ETH FSMC/SDIO/ OTG_HS DCMI TIM12_CH1 OTG_HS_DM TIM12_CH2 PC0 AF014 EVENTOUT OTG_HS_DP EVENTOUT OTG_HS_ULPI_STP PC1 AF15 EVENTOUT ETH_MDC EVENTOUT PC2 SPI2_MISO OTG_HS_ULPI_DIR ETH _MII_TXD2 EVENTOUT PC3 SPI2_MOSI OTG_HS_ULPI_NXT ETH _MII_TX_CLK EVENTOUT ETH_MII_RXD0 ETH_RMII_RXD0 ETH _MII_RXD1 ETH _RMII_RXD1 PC4 PC5 PC6 TIM3_CH1 TIM8_CH1 Doc ID 17050 Rev 6 PC7 TIM3_CH2 TIM8_CH2 PC8 TIM3_CH3 TIM8_CH3 TIM3_CH4 TIM8_CH4 PC9 MCO2 I2S2_MCK USART6_TX I2S3_MCK I2C3_SDA I2S2_CKIN EVENTOUT EVENTOUT SDIO_D6 DCMI_D0 EVENTOUT USART6_RX SDIO_D7 DCMI_D1 EVENTOUT USART6_CK SDIO_D0 DCMI_D2 EVENTOUT SDIO_D1 DCMI_D3 EVENTOUT SDIO_D2 DCMI_D8 EVENTOUT I2S3_CKIN STM32F215xx, STM32F217xx Table 6. PC10 SPI3_SCK I2S3_SCK USART3_TX UART4_TX PC11 SPI3_MISO USART3_RX UART4_RX SDIO_D3 DCMI_D4 EVENTOUT PC12 SPI3_MOSI I2S3_SD USART3_CK UART5_TX SDIO_CK DCMI_D9 EVENTOUT PC13 PC14-OSC32_IN PC15-OSC32_OUT PD0 CAN1_RX FSMC_D2 EVENTOUT PD1 CAN1_TX FSMC_D3 EVENTOUT PD2 TIM3_ETR UART5_RX PD3 USART2_CTS SDIO_CMD DCMI_D11 EVENTOUT FSMC_CLK EVENTOUT USART2_RTS FSMC_NOE EVENTOUT USART2_TX FSMC_NWE EVENTOUT PD6 USART2_RX FSMC_NWAIT EVENTOUT PD7 USART2_CK FSMC_NE1/ FSMC_NCE2 EVENTOUT PD8 USART3_TX FSMC_D13 EVENTOUT 52/168 PD9 USART3_RX FSMC_D14 EVENTOUT PD10 USART3_CK FSMC_D15 EVENTOUT PD11 USART3_CTS FSMC_A16 EVENTOUT USART3_RTS FSMC_A17 EVENTOUT FSMC_A18 EVENTOUT PD12 TIM4_CH1 PD13 TIM4_CH2 Pinouts and pin description PD4 PD5 Alternate function mapping (continued) AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 USART1/2/3 UART4/5/ USART6 Port SYS TIM1/2 TIM3/4/5 TIM8/9/10/11 I2C1/I2C2/I2C3 SPI1/SPI2/I2S2 SPI3/I2S3 AF9 AF10 CAN1/CAN2/ OTG_FS/ OTG_HS TIM12/13/14 AF11 AF12 AF13 ETH FSMC/SDIO/ OTG_HS DCMI AF014 PD14 TIM4_CH3 FSMC_D0 PD15 TIM4_CH4 FSMC_D1 PE0 TIM4_ETR FSMC_NBL0 DCMI_D2 FSMC_BLN1 DCMI_D3 PE1 ETH _MII_TXD3 AF15 EVENTOUT EVENTOUT EVENTOUT EVENTOUT PE2 TRACECLK FSMC_A23 EVENTOUT PE3 TRACED0 FSMC_A19 EVENTOUT PE4 TRACED1 FSMC_A20 DCMI_D4 EVENTOUT PE5 TRACED2 TIM9_CH1 FSMC_A21 DCMI_D6 EVENTOUT PE6 TRACED3 TIM9_CH2 FSMC_A22 DCMI_D7 EVENTOUT PE7 TIM1_ETR FSMC_D4 EVENTOUT PE8 TIM1_CH1N FSMC_D5 EVENTOUT Doc ID 17050 Rev 6 PE9 TIM1_CH1 FSMC_D6 EVENTOUT PE10 TIM1_CH2N FSMC_D7 EVENTOUT PE11 TIM1_CH2 FSMC_D8 EVENTOUT PE12 TIM1_CH3N FSMC_D9 EVENTOUT PE13 TIM1_CH3 FSMC_D10 EVENTOUT PE14 TIM1_CH4 FSMC_D11 EVENTOUT PE15 TIM1_BKIN EVENTOUT I2C2_SDA FSMC_A0 EVENTOUT PF1 I2C2_SCL FSMC_A1 EVENTOUT PF2 I2C2_SMBA FSMC_A2 EVENTOUT PF3 FSMC_A3 EVENTOUT PF4 FSMC_A4 EVENTOUT PF5 FSMC_A5 EVENTOUT PF6 TIM10_CH1 FSMC_NIORD EVENTOUT PF7 TIM11_CH1 FSMC_NREG EVENTOUT EVENTOUT PF8 TIM13_CH1 FSMC_NIOWR PF9 TIM14_CH1 FSMC_CD EVENTOUT FSMC_INTR EVENTOUT PF11 DCMI_D12 EVENTOUT PF12 FSMC_A6 EVENTOUT PF13 FSMC_A7 EVENTOUT PF14 FSMC_A8 EVENTOUT STM32F215xx, STM32F217xx FSMC_D12 PF0 PF10 Pinouts and pin description 53/168 Table 6. Alternate function mapping (continued) AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 USART1/2/3 UART4/5/ USART6 Port SYS TIM1/2 TIM3/4/5 TIM8/9/10/11 I2C1/I2C2/I2C3 SPI1/SPI2/I2S2 SPI3/I2S3 AF9 AF10 CAN1/CAN2/ OTG_FS/ OTG_HS TIM12/13/14 AF11 AF12 AF13 ETH FSMC/SDIO/ OTG_HS DCMI AF014 AF15 PF15 FSMC_A9 EVENTOUT PG0 FSMC_A10 EVENTOUT PG1 FSMC_A11 EVENTOUT PG2 FSMC_A12 EVENTOUT PG3 FSMC_A13 EVENTOUT PG4 FSMC_A14 EVENTOUT PG5 FSMC_A15 EVENTOUT FSMC_INT2 EVENTOUT PG6 PG7 USART6_CK PG8 USART6_RTS PG9 USART6_RX FSMC_INT3 EVENTOUT ETH _PPS_OUT EVENTOUT Doc ID 17050 Rev 6 FSMC_NE2/ FSMC_NCE3 FSMC_NCE4_1/ FSMC_NE3 PG10 EVENTOUT EVENTOUT ETH _MII_TX_EN FSMC_NCE4_2 ETH _RMII_TX_EN PG11 PG12 USART6_RTS PG13 UART6_CTS PG14 USART6_TX PG15 USART6_CTS ETH _MII_TXD0 ETH _RMII_TXD0 ETH _MII_TXD1 ETH _RMII_TXD1 STM32F215xx, STM32F217xx Table 6. EVENTOUT FSMC_NE4 EVENTOUT FSMC_A24 EVENTOUT FSMC_A25 EVENTOUT DCMI_D13 EVENTOUT PH0 - OSC_IN PH1 - OSC_OUT PH2 PH3 I2C2_SCL PH5 I2C2_SDA PH6 I2C2_SMBA PH7 I2C3_SCL PH8 I2C3_SDA PH9 ETH _MII_COL EVENTOUT OTG_HS_ULPI_NXT EVENTOUT EVENTOUT TIM12_CH1 ETH _MII_RXD2 EVENTOUT ETH _MII_RXD3 EVENTOUT DCMI_HSYNC DCMI_D0 EVENTOUT TIM5_CH1TIM5_ETR DCMI_D1 EVENTOUT PH11 TIM5_CH2 DCMI_D2 EVENTOUT PH12 TIM5_CH3 DCMI_D3 54/168 TIM8_CH1N TIM12_CH2 EVENTOUT PH10 PH13 I2C3_SMBA EVENTOUT CAN1_TX EVENTOUT EVENTOUT Pinouts and pin description PH4 ETH _MII_CRS Alternate function mapping (continued) AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 USART1/2/3 UART4/5/ USART6 Port SYS TIM1/2 TIM3/4/5 PH14 AF11 AF12 AF13 ETH FSMC/SDIO/ OTG_HS DCMI TIM8_CH3N SPI2_NSS I2S2_WS SPI2_SCK I2S2_SCK TIM5_CH4 PI1 PI2 SPI3/I2S3 AF10 TIM8_CH2N PH15 PI0 TIM8/9/10/11 I2C1/I2C2/I2C3 SPI1/SPI2/I2S2 AF9 CAN1/CAN2/ OTG_FS/ OTG_HS TIM12/13/14 AF014 AF15 DCMI_D4 EVENTOUT DCMI_D11 EVENTOUT DCMI_D13 EVENTOUT DCMI_D8 EVENTOUT EVENTOUT TIM8_CH4 SPI2_MISO DCMI_D9 PI3 TIM8_ETR SPI2_MOSI I2S2_SD DCMI_D10 EVENTOUT PI4 TIM8_BKIN DCMI_D5 EVENTOUT PI5 TIM8_CH1 DCMI_VSYNC EVENTOUT PI6 TIM8_CH2 DCMI_D6 EVENTOUT PI7 TIM8_CH3 DCMI_D7 EVENTOUT Pinouts and pin description 55/168 Table 6. PI8 Doc ID 17050 Rev 6 PI9 CAN1_RX EVENTOUT PI10 PI11 ETH _MII_RX_ER OTG_HS_ULPI_DIR EVENTOUT EVENTOUT STM32F215xx, STM32F217xx Memory mapping 4 STM32F215xx, STM32F217xx Memory mapping The memory map is shown in Figure 14. 56/168 Doc ID 17050 Rev 6 STM32F215xx, STM32F217xx Memory mapping Figure 14. Memory map 0xFFFF FFFF 0xE000 0000 0xDFFF FFFF 512-Mbyte block 7 Cortex-M3's internal peripherals 0xC000 0000 0xBFFF FFFF 512-Mbyte block 5 FSMC registers 512-Mbyte block 4 FSMC bank 3 & bank4 0x8000 0000 0x7FFF FFFF 0x6000 0000 0x5FFF FFFF 512-Mbyte block 3 FSMC bank1 & bank2 512-Mbyte block 2 Peripherals 0x4000 0000 0x3FFF FFFF 512-Mbyte block 1 SRAM 0x2000 0000 0x1FFF FFFF 512-Mbyte block 0 Code 0x0000 0000 0xA000 0000 - 0xA000 0FFF 0x9000 0000 - 0x9FFF FFFF Reserved SRAM (16 KB aliased by bit-banding) SRAM (112 KB aliased by bit-banding) Reserved Option Bytes Reserved System memory Reserved Flash Reserved Aliased to Flash, system memory or SRAM depending on the BOOT pins 0x2002 0000 - 0x3FFF FFFF 0x2001 C000 - 0x2001 FFFF 0x2000 0000 - 0x2001 BFFF 0x1FFF C008 - 0x1FFF FFFF 0x1FFF C000 - 0x1FFF C007 0x1FFF 7A10 - 0x1FFF 7FFF 0x1FFF 0000 - 0x1FFF 7A0F 0x0810 0000 - 0x0FFF FFFF 0x0800 0000 - 0x080F FFFF 0x0001 C000 - 0x07FF FFFF 0xA000 1000 - 0xBFFF FFFF FSMC bank3 NAND (NAND2) 0x8000 0000 - 0x8FFF FFFF FSMC bank2 NAND (NAND1) 0x7000 0000 - 0x7FFF FFFF FSMC bank1 NOR/PSRAM 4 0x6C00 0000 - 0x6FFF FFFF FSMC bank1 NOR/PSRAM 3 0x6800 0000 - 0x6BFF FFFF FSMC bank1 NOR/PSRAM 2 0x6400 0000 - 0x67FF FFFF FSMC bank1 NOR/PSRAM 1 0x6000 0000 - 0x63FF FFFF Reserved RNG HASH CRYP Reserved DCMI Reserved USB OTG FS Reserved USB OTG HS Reserved ETHERNET Reserved DMA2 DMA1 Reserved BKPSRAM Flash interface Reset clock controller (RCC) Reserved CRC Reserved Port I Port H Port G Port F Port E Port D Port C Port B Port A Reserved TIM11 TIM10 TIM9 EXTI SYSCFG Reserved SPI1 SDIO Reserved 512-Mbyte block 6 Not used 0xA000 0000 0x9FFF FFFF Reserved FSMC control register FSMC bank4 PC Card Reserved ADC1 - ADC2 - ADC3 Reserved USART6 USART1 Reserved TIM8 / PWM2 TIM1 / PWM1 Reserved DAC1/DAC2 PWR Reserved BxCAN2 BxCAN1 Reserved I2C3 I2C2 I2C1 UART5 UART4 USART3 USART2 Reserved SPI3/I2S3 SPI2/I2S2 Reserved IWDG WWDG RTC & BKP registers Reserved TIM14 TIM13 TIM12 TIM7 TIM6 TIM5 TIM4 TIM3 TIM2 0x5006 0C00 - 0x5FFF FFFF 0x5006 0800 - 0x5006 0FFF 0x5006 0400 - 0x5006 07FF 0x5006 0000 - 0x5006 03FF 0x5005 0400 - 0x5005 0FFF 0x5005 0000 - 0x5005 03FF 0x5004 0000 - 0x5004 0FFF 0x5000 0000 - 0x5003 FFFF 0x4002 9400 - 0x4FFF FFFF 0x4004 0000 - 0x4007 FFFF 0x4002 9400 - 0x4003 FFFF 0x4002 8000 - 0x4002 93FF 0x4002 6800 - 0x4002 7FFF 0x4002 6400 - 0x4002 67FF 0x4002 6000 - 0x4002 63FF 0x4002 5000 - 0x4002 5FFF 0x4002 4000 - 0x4002 4FFF 0x4002 3C00 - 0x4002 3FFF 0x4002 3800 - 0x4002 3BFF 0x4002 3400 - 0x4002 37FF 0x4002 3000 - 0x4002 33FF 0x4002 2400 - 0x4002 2FFF 0x4002 2000 - 0x4002 23FF 0x4002 1C00 - 0x4002 1FFF 0x4002 1800 - 0x4002 1BFF 0x4002 1400 - 0x4002 17FF 0x4002 1000 - 0x4002 13FF 0x4002 0C00 - 0x4002 0FFF 0x4002 0800 - 0x4002 0BFF 0x4002 0400 - 0x4002 07FF 0x4002 000 - 0x4002 03FF 0x4001 4C00 - 0x4001 FFFF 0x4001 4800 - 0x4001 4BFF 0x4001 4400 - 0x4001 47FF 0x4001 4000 - 0x4001 43FF 0x4001 3C00 - 0x4001 3FFF 0x4001 3800 - 0x4001 3BFF 0x4001 3400 - 0x4001 37FF 0x4001 3000 - 0x4001 33FF 0x4001 2C00 - 0x4001 2FFF 0x4001 2800 - 0x4001 2BFF 0x4001 2400 - 0x4001 27FF 0x4001 2000 - 0x4001 23FF 0x4001 1800 - 0x4001 1FFF 0x4001 1400 - 0x4001 17FF 0x4001 1000 - 0x4001 13FF 0x4001 0400 - 0x4001 07FF 0x4001 0000 - 0x4001 03FF 0x4000 7800 - 0x4000 FFFF 0x4000 7400 - 0x4000 77FF 0x4000 7000 - 0x4000 73FF 0x4000 6C00 - 0x4000 6FFF 0x4000 6800 - 0x4000 6BFF 0x4000 6400 - 0x4000 67FF 0x4000 6000 - 0x4000 63FF 0x4000 5C00 - 0x4000 5FFF 0x4000 5800 - 0x4000 5BFF 0x4000 5400 - 0x4000 57FF 0x4000 5000 - 0x4000 53FF 0x4000 4C00 - 0x4000 4FFF 0x4000 4800 - 0x4000 4BFF 0x4000 4400 - 0x4000 47FF 0x4000 4000 - 0x4000 43FF 0x4000 3C00 - 0x4000 3FFF 0x4000 3800 - 0x4000 3BFF 0x4000 3400 - 0x4000 37FF 0x4000 3000 - 0x4000 33FF 0x4000 2C00 - 0x4000 2FFF 0x4000 2800 - 0x4000 2BFF 0x4000 2400 - 0x4000 27FF 0x4000 2000 - 0x4000 23FF 0x4000 1C00 - 0x4000 1FFF 0x4000 1800 - 0x4000 1BFF 0x4000 1400 - 0x4000 17FF 0x4000 1000 - 0x4000 13FF 0x4000 0C00 - 0x4000 0FFF 0x4000 0800 - 0x4000 0BFF 0x4000 0400 - 0x4000 07FF 0x4000 0000 - 0x4000 03FF 0x0000 0000 - 0x000F FFFF Doc ID 17050 Rev 6 ai15989b 57/168 Electrical characteristics STM32F215xx, STM32F217xx 5 Electrical characteristics 5.1 Parameter conditions Unless otherwise specified, all voltages are referenced to VSS. 5.1.1 Minimum and maximum values Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at TA = 25 C and TA = TAmax (given by the selected temperature range). Data based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. Based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean3). 5.1.2 Typical values Unless otherwise specified, typical data are based on TA = 25 C, VDD = 3.3 V (for the 1.8 V VDD 3.6 V voltage range). They are given only as design guidelines and are not tested. Typical ADC accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range, where 95% of the devices have an error less than or equal to the value indicated (mean2). 5.1.3 Typical curves Unless otherwise specified, all typical curves are given only as design guidelines and are not tested. 5.1.4 Loading capacitor The loading conditions used for pin parameter measurement are shown in Figure 15. 5.1.5 Pin input voltage The input voltage measurement on a pin of the device is described in Figure 16. Figure 15. Pin loading conditions Figure 16. Pin input voltage 34-& PIN # P& 34-& PIN /3#?/54 (I : WHEN USING (3% OR ,3% -36 58/168 Doc ID 17050 Rev 6 6). /3#?/54 (I : WHEN USING (3% OR ,3% -36 STM32F215xx, STM32F217xx Power supply scheme Figure 17. Power supply scheme 6"!4 /54 '0 )/S ). & 6$$ )/ ,OGIC +ERNEL LOGIC #05 DIGITAL 2!- 6#!0? 6#!0? 6$$ N& & "ACKUP CIRCUITRY /3#+ 24# 7AKEUP LOGIC "ACKUP REGISTERS BACKUP 2!- 0O WER SWI TCH 6 ,EVEL SHIFTER 5.1.6 Electrical characteristics 6OLTAGE REGULATOR 633 &LASH MEMORY 2%'/&& 6$$ 6$$! 62%& N& & N& & 62%& 62%& !$# !NALOG 2#S 0,, 633! -36 1. Each power supply pair must be decoupled with filtering ceramic capacitors as shown above. These capacitors must be placed as close as possible to, or below, the appropriate pins on the underside of the PCB to ensure the good functionality of the device. 2. To connect REGOFF pin, refer to Section 2.2.16: Voltage regulator. 3. The two 2.2 F ceramic capacitors should not be connected when the voltage regulator is OFF. 4. The 4.7 F ceramic capacitor must be connected to one of the VDD pin. Doc ID 17050 Rev 6 59/168 Electrical characteristics 5.1.7 STM32F215xx, STM32F217xx Current consumption measurement Figure 18. Current consumption measurement scheme IDD_VBAT VBAT IDD VDD VDDA ai14126 5.2 Absolute maximum ratings Stresses above the absolute maximum ratings listed in Table 7: Voltage characteristics, Table 8: Current characteristics, and Table 9: Thermal characteristics may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Table 7. Voltage characteristics Symbol Ratings Min Max VDD-VSS External main supply voltage (including VDDA, VDD)(1) -0.3 4.0 VSS-0.3 VDD+4 VSS-0.3 4.0 Variations between different VDD power pins - 50 Variations between all the different ground pins - 50 Input voltage on five-volt tolerant VIN |VDDx| |VSSX - VSS| VESD(HBM) pin(2) Input voltage on any other pin Electrostatic discharge voltage (human body model) Unit V mV see Section 5.3.14: Absolute maximum ratings (electrical sensitivity) 1. All main power (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to the external power supply, in the permitted range. 2. VIN maximum value must always be respected. Refer to Table 8 for the values of the maximum allowed injected current. 60/168 Doc ID 17050 Rev 6 STM32F215xx, STM32F217xx Table 8. Electrical characteristics Current characteristics Symbol Ratings Max. IVDD Total current into VDD power lines (source)(1) 120 IVSS (1) 120 Total current out of VSS ground lines (sink) IIO Output current sunk by any I/O and control pin 25 Output current source by any I/Os and control pin 25 (3) Injected current on five-volt tolerant I/O IINJ(PIN) (2) IINJ(PIN) Injected current on any other pin (4) mA -5/+0 (4) Total injected current (sum of all I/O and control pins) Unit 5 (5) 25 1. All main power (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to the external power supply, in the permitted range. 2. Negative injection disturbs the analog performance of the device. See note in Section 5.3.20: 12-bit ADC characteristics. 3. Positive injection is not possible on these I/Os. A negative injection is induced by VIN<VSS. IINJ(PIN) must never be exceeded. Refer to Table 7 for the values of the maximum allowed input voltage. 4. A positive injection is induced by VIN>VDD while a negative injection is induced by VIN<VSS. IINJ(PIN) must never be exceeded. Refer to Table 7 for the values of the maximum allowed input voltage. 5. When several inputs are submitted to a current injection, the maximum IINJ(PIN) is the absolute sum of the positive and negative injected currents (instantaneous values). Table 9. Thermal characteristics Symbol TSTG TJ Ratings Storage temperature range Unit -65 to +150 C 125 C Maximum junction temperature 5.3 Operating conditions 5.3.1 General operating conditions Table 10. General operating conditions Symbol Value Parameter Conditions Min Max fHCLK Internal AHB clock frequency 0 120 fPCLK1 Internal APB1 clock frequency 0 30 fPCLK2 Internal APB2 clock frequency 0 60 1.8 3.6 1.8 3.6 2.4 3.6 1.65 3.6 VDD VDDA(1) VBAT Standard operating voltage Analog operating voltage (ADC limited to 1 M samples) Analog operating voltage (ADC limited to 2 M samples) Must be the same potential as VDD Backup operating voltage Doc ID 17050 Rev 6 (2) Unit MHz V V V 61/168 Electrical characteristics Table 10. General operating conditions (continued) Symbol VCAP1 VCAP2 PD STM32F215xx, STM32F217xx Parameter Conditions Min Max Unit 1.1 1.3 V LQFP64 - 444 LQFP100 - 434 LQFP144 - 500 LQFP176 - 526 UFBGA176 - 513 -40 85 -40 105 -40 105 -40 125 6 suffix version -40 105 7 suffix version -40 125 Internal core voltage to be supplied externally in REGOFF mode Power dissipation at TA = 85 C for suffix 6 or TA = 105 C for suffix 7(3) Ambient temperature for 6 suffix version Maximum power dissipation Ambient temperature for 7 suffix version Maximum power dissipation Low power dissipation (4) mW C TA TJ Low power dissipation (4) C Junction temperature range C 1. When the ADC is used, refer to Table 62: ADC characteristics. 2. It is recommended to power VDD and VDDA from the same source. A maximum difference of 300 mV between VDD and VDDA can be tolerated during power-up and power-down operation. 3. If TA is lower, higher PD values are allowed as long as TJ does not exceed TJmax. 4. In low power dissipation state, TA can be extended to this range as long as TJ does not exceed TJmax. Table 11. Limitations depending on the operating power supply range Operating power supply range ADC operation Maximum Flash memory access frequency (fFlashmax) VDD =1.8 to 2.1 V Conversion time up to 1 Msps 16 MHz with no Flash memory wait state VDD = 2.1 to 2.4 V Conversion time up to 1 Msps 18 MHz with no Flash memory wait state 62/168 Number of wait states at maximum CPU frequency (fCPUmax= 120 MHz)(1) FSMC controller operation Possible Flash memory operations (2) - Degraded speed performance up to 30 MHz - No I/O compensation 8-bit erase and program operations only 6(2) - Degraded speed performance up to 30 MHz - No I/O compensation 16-bit erase and program operations 7 I/O operation Doc ID 17050 Rev 6 STM32F215xx, STM32F217xx Table 11. Operating power supply range VDD = 2.4 to 2.7 V VDD = 2.7 to 3.6 V(3) Electrical characteristics Limitations depending on the operating power supply range ADC operation Maximum Flash memory access frequency (fFlashmax) Conversion time up to 2 Msps 24 MHz with no Flash memory wait state Conversion time up to 2 Msps 30 MHz with no Flash memory wait state Number of wait states at maximum CPU frequency (fCPUmax= 120 MHz)(1) FSMC controller operation Possible Flash memory operations 4(2) - Degraded speed performance up to 48 MHz - I/O compensation works 16-bit erase and program operations 3(2) - up to 60 MHz - Full-speed when VDD = operation 3.0 to 3.6 V - I/O - up to compensation 48 MHz works when VDD = 2.7 to 3.0 V 32-bit erase and program operations I/O operation 1. The number of wait states can be reduced by reducing the CPU frequency (see Figure 19). 2. Thanks to the ART accelerator and the 128-bit Flash memory, the number of wait states given here does not impact the execution speed from Flash memory since the ART accelerator allows to achieve a performance equivalent to 0 wait state program execution. 3. The voltage range for OTG USB FS can drop down to 2.7 V. However it is degraded between 2.7 and 3 V. Doc ID 17050 Rev 6 63/168 Electrical characteristics STM32F215xx, STM32F217xx Figure 19. Number of wait states versus fCPU and VDD range Wait states vs Fcpu and VDD range 8 7 Number of Wait states 6 5 1.8 to 2.1V 2.1 to 2.4V 4 2.4 to 2.7V 2.7 to 3.6V 3 2 1 0 4 8 12 16 20 24 28 32 36 40 44 48 52 56 60 64 68 72 76 80 84 88 92 96 100 104 108 112 116 120 0 Fcpu (MHz) AIB 5.3.2 VCAP1/VCAP2 external capacitor Stabilization for the main regulator is achieved by connecting an external capacitor to the VCAP1/VCAP2 pins. CEXT is specified in Table 12. Figure 20. External capacitor CEXT C ESR R Leak MS19044V1 1. Legend: ESR is the equivalent series resistance. Table 12. 64/168 VCAP1/VCAP2 operating conditions Symbol Parameter Conditions CEXT Capacitance of external capacitor 2.2 F ESR ESR of external capacitor <2 Doc ID 17050 Rev 6 STM32F215xx, STM32F217xx 5.3.3 Electrical characteristics Operating conditions at power-up / power-down (regulator ON) Subject to general operating conditions for TA. Table 13. Symbol tVDD 5.3.4 Operating conditions at power-up / power-down (regulator ON) Parameter Min Max VDD rise time rate 20 VDD fall time rate 20 Unit s/V Operating conditions at power-up / power-down (regulator OFF) Subject to general operating conditions for TA. Table 14. Symbol tVDD tVCAP Operating conditions at power-up / power-down (regulator OFF) Parameter Conditions Min Max VDD rise time rate Power-up 20 VDD fall time rate Power-down 20 VCAP_1 and VCAP_2 rise time rate Power-up 20 VCAP_1 and VCAP_2 fall time rate Power-down 20 Doc ID 17050 Rev 6 Unit s/V 65/168 Electrical characteristics 5.3.5 STM32F215xx, STM32F217xx Embedded reset and power control block characteristics The parameters given in Table 15 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 10. Table 15. Symbol VPVD 66/168 Embedded reset and power control block characteristics Parameter Programmable voltage detector level selection VPVDhyst(2) PVD hysteresis VPOR/PDR Power-on/power-down reset threshold VPDRhyst(2) PDR hysteresis Conditions Min Typ Max Unit PLS[2:0]=000 (rising edge) 2.09 2.14 2.19 V PLS[2:0]=000 (falling edge) 1.98 2.04 2.08 V PLS[2:0]=001 (rising edge) 2.23 2.30 2.37 V PLS[2:0]=001 (falling edge) 2.13 2.19 2.25 V PLS[2:0]=010 (rising edge) 2.39 2.45 2.51 V PLS[2:0]=010 (falling edge) 2.29 2.35 2.39 V PLS[2:0]=011 (rising edge) 2.54 2.60 2.65 V PLS[2:0]=011 (falling edge) 2.44 2.51 2.56 V PLS[2:0]=100 (rising edge) 2.70 2.76 2.82 V PLS[2:0]=100 (falling edge) 2.59 2.66 2.71 V PLS[2:0]=101 (rising edge) 2.86 2.93 2.99 V PLS[2:0]=101 (falling edge) 2.65 2.84 3.02 V PLS[2:0]=110 (rising edge) 2.96 3.03 3.10 V PLS[2:0]=110 (falling edge) 2.85 2.93 2.99 V PLS[2:0]=111 (rising edge) 3.07 3.14 3.21 V PLS[2:0]=111 (falling edge) 2.95 3.03 3.09 V - 100 - mV Falling edge TBD(1) 1.70 TBD V Rising edge TBD 1.74 TBD V - 40 - mV Doc ID 17050 Rev 6 STM32F215xx, STM32F217xx Table 15. Electrical characteristics Embedded reset and power control block characteristics (continued) Symbol Parameter Conditions Min Typ Max Unit Brownout level 1 threshold Falling edge 2.13 2.19 2.24 V VBOR1 Rising edge 2.23 2.29 2.33 V Brownout level 2 threshold Falling edge 2.44 2.50 2.56 V VBOR2 Rising edge 2.53 2.59 2.63 V Brownout level 3 threshold Falling edge 2.75 2.83 2.88 V VBOR3 Rising edge 2.85 2.92 2.97 - 100 - mV 0.5 1.5 3.0 ms - 160 200 mA - - 5.4 C VBORhyst(2) TRSTTEMPO (2)(3) BOR hysteresis Reset temporization IRUSH(2) InRush current on voltage regulator power-on (POR or wakeup from Standby) (2) InRush energy on voltage regulator power-on (POR or wakeup from Standby) ERUSH VDD = 1.8 V, TA = 105 C, IRUSH = 171 mA for 31 s 1. The product behavior is guaranteed by design down to the minimum VPOR/PDR value. 2. Guaranteed by design, not tested in production. 3. The reset temporization is measured from the power-on (POR reset or wakeup from VBAT) to the instant when first instruction is read by the user application code. 5.3.6 Supply current characteristics The current consumption is a function of several parameters and factors such as the operating voltage, ambient temperature, I/O pin loading, device software configuration, operating frequencies, I/O pin switching rate, program location in memory and executed binary code. The current consumption is measured as described in Figure 18: Current consumption measurement scheme. All Run mode current consumption measurements given in this section are performed using CoreMark code. Doc ID 17050 Rev 6 67/168 Electrical characteristics STM32F215xx, STM32F217xx Typical and maximum current consumption The MCU is placed under the following conditions: Table 16. At startup, all I/O pins are configured as analog inputs by firmware. All peripherals are disabled except if it is explicitly mentioned. The Flash memory access time is adjusted to fHCLK frequency (0 wait state from 0 to 30 MHz, 1 wait state from 30 to 60 MHz, 2 wait states from 60 to 90 MHz and 3 wait states from 90 to 120 MHz). When the peripherals are enabled HCLK is the system clock, fPCLK1 = fHCLK/4, and fPCLK2 = fHCLK/2, except is explicitly mentioned. The maximum values are obtained for VDD = 3.6 V and maximum ambient temperature (TA), and the typical values for TA= 25 C and VDD = 3.3 V unless otherwise specified. Typical and maximum current consumption in Run mode, code with data processing running from Flash memory (ART accelerator disabled) Max(1) Typ Symbol Parameter Conditions fHCLK 120 MHz 61 81 93 90 MHz 48 68 80 60 MHz 33 53 65 30 MHz 18 38 50 25 MHz 14 34 46 10 30 42 8 MHz 6 26 38 4 MHz 4 24 36 2 MHz 3 23 35 120 MHz 33 54 66 90 MHz 27 47 59 60 MHz 19 39 51 30 MHz 11 31 43 25 MHz 8 28 41 6 26 38 8 MHz 4 24 36 4 MHz 3 23 35 2 MHz 2 23 34 External clock(2), all peripherals enabled(3) 16 IDD Supply current in Run mode Unit TA = 25 C TA = 85 C TA = 105 C External clock(3), all peripherals disabled 16 MHz(4) MHz(4) mA 1. Based on characterization, tested in production at VDD max and fHCLK max with peripherals enabled. 2. External clock is 4 MHz and PLL is on when fHCLK > 25 MHz. 3. When the ADC is on (ADON bit set in the ADC_CR2 register), add an additional power consumption of 1.6 mA per ADC for the analog part. 4. In this case HCLK = system clock/2. 68/168 Doc ID 17050 Rev 6 STM32F215xx, STM32F217xx Table 17. Electrical characteristics Typical and maximum current consumption in Run mode, code with data processing running from Flash memory (ART accelerator enabled) or RAM (1) Max(2) Typ Symbol Parameter Conditions External clock(3), all peripherals enabled(4) fHCLK TA = 25 C TA = 85 C TA = 105 C 120 MHz 49 63 72 90 MHz 38 51 61 60 MHz 26 39 49 30 MHz 14 27 37 25 MHz 11 24 34 8 21 30 8 MHz 5 17 27 4 MHz 3 16 26 2 MHz 2 15 25 120 MHz 21 34 44 90 MHz 17 30 40 60 MHz 12 25 35 30 MHz 7 20 30 25 MHz 5 18 28 4.0 17.0 27.0 8 MHz 2.5 15.5 25.5 4 MHz 2.0 14.7 24.8 2 MHz 1.6 14.5 24.6 16 IDD Supply current in Run mode External clock(3), all peripherals disabled 16 MHz(5) MHz(5) Unit mA 1. Code and data processing running from SRAM1 using boot pins. 2. Based on characterization, tested in production at VDD max and fHCLK max with peripherals enabled. 3. External clock is 4 MHz and PLL is on when fHCLK > 25 MHz. 4. When the ADC is on (ADON bit set in the ADC_CR2 register), add an additional power consumption of 1.6 mA per ADC for the analog part. 5. In this case HCLK = system clock/2. Doc ID 17050 Rev 6 69/168 Electrical characteristics STM32F215xx, STM32F217xx Figure 21. Typical current consumption vs temperature, Run mode, code with data processing running from RAM, and peripherals ON # )$$25. M! # # # # # # #05 FREQUNECY -(Z -36 Figure 22. Typical current consumption vs temperature, Run mode, code with data processing running from RAM, and peripherals OFF # )$$25. M! # # # # # # #05 &REQUENCY -(Z -36 70/168 Doc ID 17050 Rev 6 STM32F215xx, STM32F217xx Electrical characteristics Figure 23. Typical current consumption vs temperature, Run mode, code with data processing running from Flash, ART accelerator OFF, peripherals ON )$$25. M! # # #05 FREQUNECY -(Z -36 Figure 24. Typical current consumption vs temperature, Run mode, code with data processing running from Flash, ART accelerator OFF, peripherals OFF ) $$25. M! # # #05 &REQUENCY -(Z -36 Doc ID 17050 Rev 6 71/168 Electrical characteristics Table 18. STM32F215xx, STM32F217xx Typical and maximum current consumption in Sleep mode Max(1) Typ Symbol Parameter Conditions External clock(2), all peripherals enabled(3) IDD Supply current in Sleep mode External clock(2), all peripherals disabled fHCLK TA = 25 C TA = 85 C TA = 105 C 120 MHz 38 51 61 90 MHz 30 43 53 60 MHz 20 33 43 30 MHz 11 25 35 25 MHz 8 21 31 16 MHz 6 19 29 8 MHz 3.6 17.0 27.0 4 MHz 2.4 15.4 25.3 2 MHz 1.9 14.9 24.7 120 MHz 8 21 31 90 MHz 7 20 30 60 MHz 5 18 28 30 MHz 3.5 16.0 26.0 25 MHz 2.5 16.0 25.0 16 MHz 2.1 15.1 25.0 8 MHz 1.7 15.0 25.0 4 MHz 1.5 14.6 24.6 2 MHz 1.4 14.2 24.3 Unit mA 1. Based on characterization, tested in production at VDD max and fHCLK max with peripherals enabled. 2. External clock is 4 MHz and PLL is on when fHCLK > 25 MHz. 3. Add an additional power consumption of 0.8 mA per ADC for the analog part. In applications, this consumption occurs only while the ADC is on (ADON bit is set in the ADC_CR2 register). 72/168 Doc ID 17050 Rev 6 STM32F215xx, STM32F217xx Electrical characteristics Figure 25. Typical current consumption vs temperature in Sleep mode, peripherals ON )$$3,%%0 M! # # # # # # # #05 &REQUENCY -(Z -36 Figure 26. Typical current consumption vs temperature in Sleep mode, peripherals OFF )$$3,%%0 M! # # # # # # # #05 &REQUENCY -(Z -36 Doc ID 17050 Rev 6 73/168 Electrical characteristics Table 19. STM32F215xx, STM32F217xx Typical and maximum current consumptions in Stop mode(1) Typ Symbol Parameter Conditions Supply current in Stop mode with main regulator in Run mode IDD_STOP Max TA = 25 C TA = 25 C TA = 85 C Unit TA = 105 C Flash in Stop mode, low-speed and high-speed internal RC oscillators and high-speed oscillator OFF (no independent watchdog) 0.55 1.2 11.00 20.00 Flash in Deep power down mode, low-speed and high-speed internal RC oscillators and high-speed oscillator OFF (no independent watchdog) 0.50 1.2 11.00 20.00 mA Flash in Stop mode, low-speed and high-speed Supply current internal RC oscillators and high-speed oscillator in Stop mode OFF (no independent watchdog) with main Flash in Deep power down mode, low-speed regulator in and high-speed internal RC oscillators and Low Power high-speed oscillator OFF (no independent mode watchdog) 0.35 1.1 8.00 15.00 0.30 1.1 8.00 15.00 1. All typical and maximum values will be further reduced by up to 50% as part of ST continuous improvement of test procedures. New versions of the datasheet will be released to reflect these changes. Figure 27. Typical current consumption vs temperature in Stop mode )DD?STOP?MR?FLHSTOP )DD?STOP?MR?FLHDEEP )DD?STOP?LP?FLHSTOP ) $$34/0 M! )DD?STOP?LP?FLHDEEP 4EMPERATURE # -36 1. All typical and maximum values from table 18 and figure 26 will be reduced over time by up to 50% as part of ST continuous improvement of test procedures. New versions of the datasheet will be released to reflect these changes 74/168 Doc ID 17050 Rev 6 STM32F215xx, STM32F217xx Table 20. Symbol Electrical characteristics Typical and maximum current consumptions in Standby mode Parameter Conditions Backup SRAM ON, RTC ON Supply current Backup SRAM OFF, RTC ON IDD_STBY in Standby Backup SRAM ON, RTC OFF mode Backup SRAM OFF, RTC OFF Typ Max TA = 25 C TA = 85 C TA = 105 C VDD = 1.8 V VDD= 2.4 V VDD = 3.3 V 4.8 5.2 5.8 15.1(1) 25.8(1) 4.2 4.5 5.1 12.4(1) 20.5(1) 2.3 2.5 3.2 12.5(1) 24.8(1) 1.6 1.8 2.5 9.8(1) 19.2(1) Unit VDD = 3.6 V A 1. Based on characterization, not tested in production. Table 21. Typical and maximum current consumptions in VBAT mode Typ Symbol Parameter Max TA = 25 C Conditions Backup SRAM ON, RTC ON Backup SRAM OFF, low-speed Backup IDD_VBAT domain supply oscillator and RTC ON current Backup SRAM ON, RTC OFF Backup SRAM OFF, RTC OFF TA = 85 C TA = 105 C VDD = 1.8 V VDD= 2.4 V VDD = 3.3 V 3.2 3.4 3.7 12(1) 19(1) 2.6 2.7 3.0 8(1) 10(1) 0.7 0.7 0.8 9(1) 16(1) 0.1 0.1 0.1 5(1) 7(1) Unit VDD = 3.6 V A 1. Based on characterization, not tested in production. On-chip peripheral current consumption The current consumption of the on-chip peripherals is given in Table 22. The MCU is placed under the following conditions: At startup, all I/O pins are configured as analog inputs by firmware. All peripherals are disabled unless otherwise mentioned The given value is calculated by measuring the current consumption - with all peripherals clocked off - with one peripheral clocked on (with only the clock applied) The code is running from Flash memory and the Flash memory access time is equal to 3 wait states at 120 MHz Prefetch and Cache ON When the peripherals are enabled, HCLK = 120MHz, fPCLK1 = fHCLK/4, and fPCLK2 = fHCLK/2 The typical values are obtained for VDD = 3.3 V and TA= 25 C, unless otherwise specified. Doc ID 17050 Rev 6 75/168 Electrical characteristics Table 22. STM32F215xx, STM32F217xx Peripheral current consumption Peripheral(1) AHB1 Typical consumption at 25 C GPIO A 0.45 GPIO B 0.43 GPIO C 0.46 GPIO D 0.44 GPIO E 0.44 GPIO F 0.42 GPIO G 0.44 GPIO H 0.42 GPIO I 0.43 OTG_HS + ULPI 3.64 CRC 1.17 BKPSRAM 0.21 DMA1 2.76 DMA2 2.85 ETH_MAC + ETH_MAC_TX ETH_MAC_RX ETH_MAC_PTP 2.99 OTG_FS 3.16 DCMI 0.60 FSMC 1.74 CRYPTO 0.39 HASH 0.50 RNG 0.43 Unit mA AHB2 AHB3 AHB2 76/168 Doc ID 17050 Rev 6 mA STM32F215xx, STM32F217xx Table 22. Electrical characteristics Peripheral current consumption (continued) Peripheral(1) Typical consumption at 25 C TIM2 0.61 TIM3 0.49 TIM4 0.54 TIM5 0.62 TIM6 0.20 TIM7 0.20 TIM12 0.36 TIM13 0.28 TIM14 0.25 USART2 0.25 USART3 0.25 UART4 0.25 UART5 0.26 I2C1 0.25 I2C2 0.25 I2C3 0.25 SPI2 0.20/0.10 SPI3 0.18/0.09 CAN1 0.31 APB1 Unit mA CAN2 0.30 (2) DAC channel 1 1.11 DAC channel 1(3) 1.11 PWR 0.15 WWDG 0.15 Doc ID 17050 Rev 6 77/168 Electrical characteristics Table 22. STM32F215xx, STM32F217xx Peripheral current consumption (continued) Peripheral(1) Typical consumption at 25 C SDIO 0.69 TIM1 1.06 TIM8 1.03 TIM9 0.58 TIM10 0.37 TIM11 0.39 APB2 mA (4) 2.13 ADC2(4) 2.04 (4) 2.12 ADC1 ADC3 Unit SPI1 1.20 USART1 0.38 USART6 0.37 1. External clock is 25 MHz (HSE oscillator with 25 MHz crystal) and PLL is on. 2. EN1 bit is set in DAC_CR register. 3. EN2 bit is set in DAC_CR register. 4. fADC = fPCLK2/2, ADON bit set in ADC_CR2 register. 5.3.7 Wakeup time from low-power mode The wakeup times given in Table 23 is measured on a wakeup phase with a 16 MHz HSI RC oscillator. The clock source used to wake up the device depends from the current operating mode: Stop or Standby mode: the clock source is the RC oscillator Sleep mode: the clock source is the clock that was set before entering Sleep mode. All timings are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 10. Table 23. Low-power mode wakeup timings Symbol tWUSLEEP(2) tWUSTOP(2) tWUSTDBY(2)(3) Min(1) Typ(1) Max(1) Unit Wakeup from Sleep mode - 1 - s Wakeup from Stop mode (regulator in Run mode) - 13 - Wakeup from Stop mode (regulator in low power mode) - 17 40 Wakeup from Stop mode (regulator in low power mode and Flash memory in Deep power down mode) - 110 - 260 375 480 Parameter Wakeup from Standby mode s s 1. Based on characterization, not tested in production. 2. The wakeup times are measured from the wakeup event to the point in which the application code reads the first instruction. 3. tWUSTDBY minimum and maximum values are given at 105 C and -45 C, respectively. 78/168 Doc ID 17050 Rev 6 STM32F215xx, STM32F217xx 5.3.8 Electrical characteristics External clock source characteristics High-speed external user clock generated from an external source The characteristics given in Table 24 result from tests performed using an high-speed external clock source, and under ambient temperature and supply voltage conditions summarized in Table 10. Table 24. High-speed external user clock characteristics Symbol Parameter Conditions Min Typ Max Unit 1 8 26 MHz fHSE_ext External user clock source frequency(1) VHSEH OSC_IN input pin high level voltage 0.7VDD - VDD VHSEL OSC_IN input pin low level voltage VSS - 0.3VDD tw(HSE) tw(HSE) OSC_IN high or low time(1) 5 - - tr(HSE) tf(HSE) OSC_IN rise or fall time(1) - - 20 OSC_IN input capacitance(1) - 5 - pF 45 - 55 % - - 1 A Cin(HSE) ns DuCy(HSE) Duty cycle IL V OSC_IN Input leakage current VSS VIN VDD 1. Guaranteed by design, not tested in production. Low-speed external user clock generated from an external source The characteristics given in Table 25 result from tests performed using an low-speed external clock source, and under ambient temperature and supply voltage conditions summarized in Table 10. Table 25. Low-speed external user clock characteristics Symbol Parameter Conditions Min Typ Max Unit - 32.768 1000 kHz 0.7VDD - VDD fLSE_ext User External clock source frequency(1) VLSEH OSC32_IN input pin high level voltage VLSEL OSC32_IN input pin low level voltage VSS - 0.3VDD tw(LSE) tf(LSE) OSC32_IN high or low time(1) 450 - - V tr(LSE) tf(LSE) Cin(LSE) ns OSC32_IN rise or fall time(1) OSC32_IN input capacitance(1) DuCy(LSE) Duty cycle IL OSC32_IN Input leakage current VSS VIN VDD - - 50 - 5 - pF 30 - 70 % - - 1 A 1. Guaranteed by design, not tested in production. Doc ID 17050 Rev 6 79/168 Electrical characteristics STM32F215xx, STM32F217xx Figure 28. High-speed external clock source AC timing diagram VHSEH 90% VHSEL 10% tr(HSE) tf(HSE) tW(HSE) tW(HSE) t THSE External clock source fHSE_ext OSC _IN IL STM32F ai17528 Figure 29. Low-speed external clock source AC timing diagram VLSEH 90% VLSEL 10% tr(LSE) tf(LSE) tW(LSE) OSC32_IN IL tW(LSE) t TLSE External clock source fLSE_ext STM32F ai17529 High-speed external clock generated from a crystal/ceramic resonator The high-speed external (HSE) clock can be supplied with a 4 to 26 MHz crystal/ceramic resonator oscillator. All the information given in this paragraph are based on characterization results obtained with typical external components specified in Table 26. In the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. Refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy). 80/168 Doc ID 17050 Rev 6 STM32F215xx, STM32F217xx Table 26. Symbol Electrical characteristics HSE 4-26 MHz oscillator characteristics(1) (2) Min Typ Max Unit Oscillator frequency 4 - 26 MHz RF Feedback resistor - 200 - k C Recommended load capacitance versus equivalent serial resistance of the crystal (RS)(3) RS = 30 - 15 - pF i2 HSE driving current VDD = 3.3 V, VIN = VSS with 30 pF load - - 1 mA gm Oscillator transconductance Startup 5 - - mA/V VDD is stabilized - 2 - ms fOSC_IN tSU(HSE(4) Parameter Conditions Startup time 1. Resonator characteristics given by the crystal/ceramic resonator manufacturer. 2. Based on characterization, not tested in production. 3. The relatively low value of the RF resistor offers a good protection against issues resulting from use in a humid environment, due to the induced leakage and the bias condition change. However, it is recommended to take this point into account if the MCU is used in tough humidity conditions. 4. tSU(HSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 8 MHz oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer For CL1 and CL2, it is recommended to use high-quality external ceramic capacitors in the 5 pF to 25 pF range (typ.), designed for high-frequency applications, and selected to match the requirements of the crystal or resonator (see Figure 30). CL1 and CL2 are usually the same size. The crystal manufacturer typically specifies a load capacitance which is the series combination of CL1 and CL2. PCB and MCU pin capacitance must be included (10 pF can be used as a rough estimate of the combined pin and board capacitance) when sizing CL1 and CL2. Refer to the application note AN2867 "Oscillator design guide for ST microcontrollers" available from the ST website www.st.com. Figure 30. Typical application with an 8 MHz crystal Resonator with integrated capacitors CL1 fHSE OSC_IN 8 MH z resonator CL2 REXT(1) RF OSC_OU T Bias controlled gain STM32F ai17530 1. REXT value depends on the crystal characteristics. Low-speed external clock generated from a crystal/ceramic resonator The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal/ceramic resonator oscillator. All the information given in this paragraph are based on characterization results obtained with typical external components specified in Table 27. In the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. Refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy). Doc ID 17050 Rev 6 81/168 Electrical characteristics Table 27. STM32F215xx, STM32F217xx LSE oscillator characteristics (fLSE = 32.768 kHz) (1) Symbol Parameter Conditions RF Feedback resistor C(2) Recommended load capacitance versus equivalent serial resistance of the crystal (RS)(3) I2 LSE driving current gm Oscillator Transconductance tSU(LSE)(4) Min Typ Max Unit - 18.4 - M RS = 30 k - - 15 pF VDD = 3.3 V, VIN = VSS - - 3.5 A 7 - - A/V - 2 - s startup time VDD is stabilized 1. Based on characterization, not tested in production. 2. Refer to the note and caution paragraphs below the table, and to the application note AN2867 "Oscillator design guide for ST microcontrollers". 3. The oscillator selection can be optimized in terms of supply current using an high quality resonator with small RS value for example MSIV-TIN32.768kHz. Refer to crystal manufacturer for more details 4. tSU(LSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 32.768 kHz oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer Note: For CL1 and CL2 it is recommended to use high-quality external ceramic capacitors in the 5 pF to 15 pF range selected to match the requirements of the crystal or resonator (see Figure 31). CL1 and CL2, are usually the same size. The crystal manufacturer typically specifies a load capacitance which is the series combination of CL1 and CL2. Load capacitance CL has the following formula: CL = CL1 x CL2 / (CL1 + CL2) + Cstray where Cstray is the pin capacitance and board or trace PCB-related capacitance. Typically, it is between 2 pF and 7 pF. Caution: To avoid exceeding the maximum value of CL1 and CL2 (15 pF) it is strongly recommended to use a resonator with a load capacitance CL 7 pF. Never use a resonator with a load capacitance of 12.5 pF. Example: if you choose a resonator with a load capacitance of CL = 6 pF, and Cstray = 2 pF, then CL1 = CL2 = 8 pF. Figure 31. Typical application with a 32.768 kHz crystal Resonator with integrated capacitors CL1 fLSE OSC32_IN 32.768 kH z resonator CL2 RF Bias controlled gain OSC32_OU T STM32F ai17531 82/168 Doc ID 17050 Rev 6 STM32F215xx, STM32F217xx Internal clock source characteristics The parameters given in Table 28 and Table 29 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 10. High-speed internal (HSI) RC oscillator Table 28. HSI oscillator characteristics (1) Symbol fHSI Parameter Min Typ Max Unit Conditions - 16 - MHz - - 1 % TA = -40 to 105 C -8 - 4.5 % TA = -10 to 85 C -4 - 4 % TA = 25 C -1 - 1 % HSI oscillator startup time - 2.2 4 s HSI oscillator power consumption - 60 80 A Frequency User-trimmed with the RCC_CR register(2) ACCHSI tsu(HSI)(3) IDD(HSI) Accuracy of the HSI oscillator Factorycalibrated 1. VDD = 3.3 V, TA = -40 to 105 C unless otherwise specified. 2. Refer to application note AN2868 "STM32F10xxx internal RC oscillator (HSI) calibration" available from the ST website www.st.com. 3. Guaranteed by design, not tested in production. Figure 32. ACCHSI versus temperature max avg 6 min 4 2 Normalized deviation (%) 5.3.9 Electrical characteristics 0 -2 -4 -6 -8 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 115 125 Temperature (C) -36 Doc ID 17050 Rev 6 83/168 Electrical characteristics STM32F215xx, STM32F217xx Low-speed internal (LSI) RC oscillator LSI oscillator characteristics (1) Table 29. Symbol Parameter fLSI(2) tsu(LSI) Min Typ Max Unit 17 32 47 kHz LSI oscillator startup time - 15 40 s LSI oscillator power consumption - 0.4 0.6 A Frequency (3) IDD(LSI)(3) 1. VDD = 3 V, TA = -40 to 105 C unless otherwise specified. 2. Based on characterization, not tested in production. 3. Guaranteed by design, not tested in production. Figure 33. ACCLSI versus temperature MAX AVG MIN .ORMALIZED DEVIATI ON 4EMPERAT URE # -36 5.3.10 PLL characteristics The parameters given in Table 30 and Table 31 are derived from tests performed under temperature and VDD supply voltage conditions summarized in Table 10. Table 30. Symbol Main PLL characteristics Parameter fPLL_IN PLL input clock(1) fPLL_OUT PLL multiplier output clock fPLL48_OUT 48 MHz PLL multiplier output clock fVCO_OUT PLL VCO output 84/168 Conditions Min Typ Max Unit (2) 1 2.10(2) MHz 24 - 120 MHz - - 48 MHz 192 - 432 MHz 0.95 Doc ID 17050 Rev 6 STM32F215xx, STM32F217xx Table 30. Symbol Electrical characteristics Main PLL characteristics (continued) Min Typ Max VCO freq = 192 MHz 75 - 200 VCO freq = 432 MHz 100 - 300 RMS - 25 - peak to peak - 150 - RMS - 15 - peak to peak - 200 - Main clock output (MCO) for RMII Ethernet Cycle to cycle at 50 MHz on 1000 samples - 32 - Main clock output (MCO) for MII Ethernet Cycle to cycle at 25 MHz on 1000 samples - 40 - Bit Time CAN jitter Cycle to cycle at 1 MHz on 1000 samples - 330 - IDD(PLL)(4) PLL power consumption on VDD VCO freq = 192 MHz VCO freq = 432 MHz 0.15 0.45 - 0.40 0.75 mA IDDA(PLL)(4) PLL power consumption on VDDA VCO freq = 192 MHz VCO freq = 432 MHz 0.30 0.55 - 0.40 0.85 mA tLOCK Parameter Conditions PLL lock time Unit s Cycle-to-cycle jitter System clock 120 MHz Period Jitter Jitter(3) ps 1. Take care of using the appropriate division factor M to obtain the specified PLL input clock values. The M factor is shared between PLL and PLLI2S. 2. Guaranteed by design, not tested in production. 3. The use of 2 PLLs in parallel could degraded the Jitter up to +30%. 4. Based on characterization, not tested in production. Table 31. Symbol PLLI2S (audio PLL) characteristics(1) Parameter fPLLI2S_IN PLLI2S input clock(2) fPLLI2S_OUT PLLI2S multiplier output clock fVCO_OUT PLLI2S VCO output tLOCK PLLI2S lock time Conditions Min Typ Max Unit 0.95(3) 1 2.10(3) MHz - - 216 MHz 192 - 432 MHz VCO freq = 192 MHz 75 - 200 VCO freq = 432 MHz 100 - 300 s Doc ID 17050 Rev 6 85/168 Electrical characteristics Table 31. STM32F215xx, STM32F217xx PLLI2S (audio PLL) characteristics(1) (continued) Symbol Parameter Conditions Cycle to cycle at 12,343 MHz on 48KHz period, N=432, P=4, R=5 Master I2S clock jitter Min Typ Max RMS - 90 - peak to peak - 280 - ps TBD - TBD ps - 400 - ps 0.15 0.45 - 0.40 0.75 mA - 0.40 0.85 mA Average frequency of 12,343 MHz N=432, P=4, R=5 on 256 samples (4) Jitter WS I2S clock jitter Cycle to cycle at 48 KHz on 1000 samples IDD(PLLI2S)(5) PLLI2S power consumption on VDD VCO freq = 192 MHz VCO freq = 432 MHz IDDA(PLLI2S)(5) PLLI2S power consumption on VDDA VCO freq = 192 MHz VCO freq = 432 MHz 0.30 0.55 1. TBD stands for "to be defined". 2. Take care of using the appropriate division factor M to have the specified PLL input clock values. 3. Guaranteed by design, not tested in production. 4. Value given with main PLL running. 5. Based on characterization, not tested in production. 86/168 Doc ID 17050 Rev 6 Unit STM32F215xx, STM32F217xx 5.3.11 Electrical characteristics PLL spread spectrum clock generation (SSCG) characteristics The spread spectrum clock generation (SSCG) feature allows to reduce electromagnetic interferences (see Table 38: EMI characteristics). It is available only on the main PLL. Table 32. SSCG parameters constraint Symbol Parameter Min Typ Max(1) Unit fMod Modulation frequency - - 10 KHz md Peak modulation depth 0.25 - 2 % - 215 - MODEPER * INCSTEP - -1 1. Guaranteed by design, not tested in production. Equation 1 The frequency modulation period (MODEPER) is given by the equation below: MODEPER = round [ f PLL_IN ( 4 x fMod ) ] fPLL_IN and fMod must be expressed in Hz. As an example: If fPLL_IN = 1 MHz and fMOD = 1 kHz, the modulation depth (MODEPER) is given by equation 1: 6 3 MODEPER = round [ 10 ( 4 x 10 ) ] = 25 Equation 2 Equation 2 allows to calculate the increment step (INCSTEP): INCSTEP = round [ ( ( 2 15 - 1 ) x md x f VCO_OUT ) ( 100 x 5 x MODEPER ) ] fVCO_OUT must be expressed in MHz. With a modulation depth (md) = 2 % (4 % peak to peak), and fVCO_OUT = 240 (in MHz): INCSTEP = round [ ( ( 2 15 - 1 ) x 2 x 240 ) ( 100 x 5 x 25 ) ] = 1258md(quantitazed)% An amplitude quantization error may be generated because the linear modulation profile is obtained by taking the quantized values (rounded to the nearest integer) of MODPER and INCSTEP. As a result, the achieved modulation depth is quantized. The percentage quantized modulation depth is given by the following formula: md quantized % = ( MODEPER x INCSTEP x 100 x 5 ) ( ( 2 15 - 1 ) x f VCO_OUT ) As a result: md quantized % = ( 25 x 1258 x 100 x 5 ) ( ( 2 15 - 1 ) x 240 ) = 1.99954%(peak) The error in modulation depth is consequently: 2.0 - 1.99954 = 0.00046%. Doc ID 17050 Rev 6 87/168 Electrical characteristics STM32F215xx, STM32F217xx Figure 34 and Figure 35 show the main PLL output clock waveforms in center spread and down spread modes, where: F0 is fPLL_OUT nominal. Tmode is the modulation period. md is the modulation depth. Figure 34. PLL output clock waveforms in center spread mode &REQUENCY 0,,?/54 MD & MD TMODE 4IME TMODE AI Figure 35. PLL output clock waveforms in down spread mode &REQUENCY 0,,?/54 & MD TMODE 4IME TMODE AI 5.3.12 Memory characteristics Flash memory The characteristics are given at TA = -40 to 105 C unless otherwise specified. Table 33. Symbol IDD Flash memory characteristics(1) Parameter Supply current Conditions Min Max Unit Read mode fHCLK = 120 MHz with 3 wait states, VDD = 3.3 V - 100 mA Write / Erase modes fHCLK = 120 MHz, VDD = 3.3 V - TBD mA 1. TBD stands for "to be defined". 88/168 Doc ID 17050 Rev 6 STM32F215xx, STM32F217xx Table 34. Symbol tprog Electrical characteristics Flash memory programming(1) Word programming time tERASE16KB Sector (16 KB) erase time tERASE64KB Sector (64 KB) erase time tERASE128KB Sector (128 KB) erase time tME Vprog Conditions Min(2) Typ Max(2) Unit Program/erase parallelism (PSIZE) = x 8/16/32 - 16 100(3) Program/erase parallelism (PSIZE) = x 8 - 400 800 Program/erase parallelism (PSIZE) = x 16 - 300 600 Program/erase parallelism (PSIZE) = x 32 - 250 500 Program/erase parallelism (PSIZE) = x 8 - 1200 2400 Program/erase parallelism (PSIZE) = x 16 - 700 1400 Program/erase parallelism (PSIZE) = x 32 - 550 1100 Program/erase parallelism (PSIZE) = x 8 - 2 4 Program/erase parallelism (PSIZE) = x 16 - 1.3 2.6 Program/erase parallelism (PSIZE) = x 32 - 1 2 Program/erase parallelism (PSIZE) = x 8 - 16 TBD Program/erase parallelism (PSIZE) = x 16 - 11 TBD Program/erase parallelism (PSIZE) = x 32 - 8 TBD 32-bit program operation 2.7 - 3.6 V 16-bit program operation 2.1 - 3.6 V 8-bit program operation 1.8 - 3.6 V Parameter Mass erase time Programming voltage s ms ms s s 1. TBD stands for "to be defined". 2. Based on characterization, not tested in production. 3. The maximum programming time is measured after 100K erase operations. Doc ID 17050 Rev 6 89/168 Electrical characteristics STM32F215xx, STM32F217xx Flash memory programming with VPP(1) Table 35. Min(2) Typ Max(2) Double word programming - 16 100(3) tERASE16KB Sector (16 KB) erase time - TBD - tERASE64KB Sector (64 KB) erase time - TBD - - TBD - - 6.8 - 2.7 - 3.6 V Symbol Parameter tprog Conditions tERASE128KB Sector (128 KB) erase time tME Mass erase time TA = 0 to +40 C Unit s Vprog Programming voltage VPP VPP voltage range 7 - 9 V IPP Minimum current sunk on the VPP pin 10 - - mA - - 1 hour tVPP(4) Cumulative time during which VPP is applied 1. TBD stands for "to be defined". 2. Guaranteed by design, not tested in production. 3. The maximum programming time is measured after 100K erase operations. 4. VPP should only be connected during programming/erasing. Table 36. Flash memory endurance and data retention Value Symbol NEND tRET Parameter Endurance Data retention Conditions Min(1) TA = -40 to +85 C (6 suffix versions) TA = -40 to +105 C (7 suffix versions) 10 1 kcycle(2) at TA = 85 C 30 1 kcycle(2) at TA = 105 C 10 10 kcycles (2) at TA = 55 C Unit kcycles Years 20 1. Based on characterization, not tested in production. 2. Cycling performed over the whole temperature range. 5.3.13 EMC characteristics Susceptibility tests are performed on a sample basis during device characterization. Functional EMS (electromagnetic susceptibility) While a simple application is executed on the device (toggling 2 LEDs through I/O ports). the device is stressed by two electromagnetic events until a failure occurs. The failure is indicated by the LEDs: 90/168 Electrostatic discharge (ESD) (positive and negative) is applied to all device pins until a functional disturbance occurs. This test is compliant with the IEC 61000-4-2 standard. FTB: A burst of fast transient voltage (positive and negative) is applied to VDD and VSS through a 100 pF capacitor, until a functional disturbance occurs. This test is compliant with the IEC 61000-4-4 standard. Doc ID 17050 Rev 6 STM32F215xx, STM32F217xx Electrical characteristics A device reset allows normal operations to be resumed. The test results are given in Table 37. They are based on the EMS levels and classes defined in application note AN1709. Table 37. EMS characteristics Symbol Parameter Conditions Level/ Class VFESD VDD = 3.3 V, LQFP100, TA = +25 C, Voltage limits to be applied on any I/O pin to fHCLK = 75 MHz, conforms to induce a functional disturbance IEC 61000-4-2 2B VEFTB Fast transient voltage burst limits to be applied through 100 pF on VDD and VSS pins to induce a functional disturbance VDD = 3.3 V, LQFP100, TA = +25 C, fHCLK = 75 MHz, conforms to IEC 61000-4-2 4A Designing hardened software to avoid noise problems EMC characterization and optimization are performed at component level with a typical application environment and simplified MCU software. It should be noted that good EMC performance is highly dependent on the user application and the software in particular. Therefore it is recommended that the user applies EMC software optimization and prequalification tests in relation with the EMC level requested for his application. Software recommendations The software flowchart must include the management of runaway conditions such as: Corrupted program counter Unexpected reset Critical Data corruption (control registers...) Prequalification trials Most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1 second. To complete these trials, ESD stress can be applied directly on the device, over the range of specification values. When unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note AN1015). Electromagnetic Interference (EMI) The electromagnetic field emitted by the device are monitored while a simple application, executing EEMBC(R) code, is running. This emission test is compliant with SAE IEC61967-2 standard which specifies the test board and the pin loading. Doc ID 17050 Rev 6 91/168 Electrical characteristics Table 38. Symbol STM32F215xx, STM32F217xx EMI characteristics Parameter Max vs. [fHSE/fCPU] Monitored frequency band Conditions Unit 8/120 MHz VDD = 3.3 V, TA = 25 C, LQFP176 package, conforming to SAE J1752/3 EEMBC, code running with ART enabled SEMI 5.3.14 0.1 to 30 MHz 21 30 to 130 MHz 28 130 MHz to 1GHz 31 SAE EMI Level 4 0.1 to 30 MHz 21 30 to 130 MHz 15 130 MHz to 1GHz 14 SAE EMI level 3.5 dBV - Peak level VDD = 3.3 V, TA = 25 C, LQFP176 package, conforming to SAE J1752/3 EEMBC, code running with ART enabled, PLL spread spectrum enabled dBV - Absolute maximum ratings (electrical sensitivity) Based on three different tests (ESD, LU) using specific measurement methods, the device is stressed in order to determine its performance in terms of electrical sensitivity. Electrostatic discharge (ESD) Electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combination. The sample size depends on the number of supply pins in the device (3 parts x (n+1) supply pins). This test conforms to the JESD22-A114/C101 standard. Table 39. ESD absolute maximum ratings Symbol Conditions Class Maximum value(1) TA = +25 C conforming to JESD22-A114 2 2000(2) Ratings VESD(HBM) Electrostatic discharge voltage (human body model) VESD(CDM) Electrostatic discharge voltage (charge device model) Unit V TA = +25 C conforming to JESD22-C101 II 500 1. Based on characterization results, not tested in production. 2. On VBAT pin, VESD(HBM) is limited to 1000 V. Static latch-up Two complementary static tests are required on six parts to assess the latch-up performance: A supply overvoltage is applied to each power supply pin A current injection is applied to each input, output and configurable I/O pin These tests are compliant with EIA/JESD 78A IC latch-up standard. 92/168 Doc ID 17050 Rev 6 STM32F215xx, STM32F217xx Table 40. Electrical sensitivities Symbol LU 5.3.15 Electrical characteristics Parameter Static latch-up class Conditions Class TA = +105 C conforming to JESD78A II level A I/O current injection characteristics As a general rule, current injection to the I/O pins, due to external voltage below VSS or above VDD (for standard, 3 V-capable I/O pins) should be avoided during normal product operation. However, in order to give an indication of the robustness of the microcontroller in cases when abnormal injection accidentally happens, susceptibility tests are performed on a sample basis during device characterization. Functional susceptibilty to I/O current injection While a simple application is executed on the device, the device is stressed by injecting current into the I/O pins programmed in floating input mode. While current is injected into the I/O pin, one at a time, the device is checked for functional failures. The failure is indicated by an out of range parameter: ADC error above a certain limit (>5 LSB TUE), out of spec current injection on adjacent pins or other functional failure (for example reset, oscillator frequency deviation). The test results are given in Table 41. Table 41. I/O current injection susceptibility Functional susceptibility Symbol IINJ Description Negative injection Positive injection Injected current on all FT pins -5 +0 Injected current on any other pin -5 +5 Unit mA Doc ID 17050 Rev 6 93/168 Electrical characteristics 5.3.16 STM32F215xx, STM32F217xx I/O port characteristics General input/output characteristics Unless otherwise specified, the parameters given in Table 42 are derived from tests performed under the conditions summarized in Table 10. All I/Os are CMOS and TTL compliant. Table 42. I/O static characteristics Symbol VIL VIH(1) VIL Parameter Conditions Typ Max VSS-0.3 - 0.8 2.0 - VDD+0.3 2.0 - 5.5 VSS-0.3 - 0.3VDD - 3.6(4) - 5.2(4) - 5.5(4) - 200 - 5% VDD(4) - - VSS VIN VDD - - 1 VIN = 5 V - - 3 30 40 50 8 11 15 Input low level voltage TTL ports 2.7 V VDD 3.6 V TT(2) I/O input high level voltage (3) FT I/O input high level voltage Input low level voltage CMOS ports 1.8 V VDD 3.6 V TT I/O input high level voltage VIH(1) Min 0.7VDD FT I/O input high level voltage CMOS ports 2.0 V VDD 3.6 V I/O Schmitt trigger voltage hysteresis(5) Vhys IO FT Schmitt trigger voltage hysteresis(5) I/O input leakage current (6) Ilkg RPU I/O FT input leakage current Weak pull-up equivalent resistor(7) (6) All pins except for PA10 and PB12 Unit V mV A VIN = VSS PA10 and PB12 k RPD Weak pull-down equivalent resistor All pins except for PA10 and PB12 PA10 and PB12 CIO(8) 30 40 50 8 11 15 VIN = VDD I/O pin capacitance 5 1. If VIH maximum value cannot be respected, the injection current must be limited externally to IINJ(PIN) maximum value. 2. TT = 3.6 V tolerant. 3. FT = 5 V tolerant. 4. With a minimum of 100 mV. 5. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization, not tested in production. 6. Leakage could be higher than the maximum value, if negative current is injected on adjacent pins. 7. Pull-up and pull-down resistors are designed with a true resistance in series with a switchable PMOS/NMOS. This MOS/NMOS contribution to the series resistance is minimum (~10% order). 8. Guaranteed by design, not tested in production. 94/168 Doc ID 17050 Rev 6 pF STM32F215xx, STM32F217xx Electrical characteristics All I/Os are CMOS and TTL compliant (no software configuration required). Their characteristics cover more than the strict CMOS-technology or TTL parameters. Output driving current The GPIOs (general purpose input/outputs) can sink or source up to 8 mA, and sink or source 20 mA (with a relaxed VOL/VOH). In the user application, the number of I/O pins which can drive current must be limited to respect the absolute maximum rating specified in Section 5.2: The sum of the currents sourced by all the I/Os on VDD, plus the maximum Run consumption of the MCU sourced on VDD, cannot exceed the absolute maximum rating IVDD (see Table 8). The sum of the currents sunk by all the I/Os on VSS plus the maximum Run consumption of the MCU sunk on VSS cannot exceed the absolute maximum rating IVSS (see Table 8). Output voltage levels Unless otherwise specified, the parameters given in Table 43 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 10. All I/Os are CMOS and TTL compliant. Table 43. Symbol VOL(2) VOH (3) VOL (2) VOH (3) Output voltage characteristics(1) Parameter Output low level voltage for an I/O pin when 8 pins are sunk at same time Output high level voltage for an I/O pin when 8 pins are sourced at same time Output low level voltage for an I/O pin when 8 pins are sunk at same time Output high level voltage for an I/O pin when 8 pins are sourced at same time VOL(2)(4) Output low level voltage for an I/O pin when 8 pins are sunk at same time VOH(3)(4) Output high level voltage for an I/O pin when 8 pins are sourced at same time VOL(2)(4) Output low level voltage for an I/O pin when 8 pins are sunk at same time VOH(3)(4) Output high level voltage for an I/O pin when 8 pins are sourced at same time Conditions Min Max TTL port IIO = +8 mA 2.7 V < VDD < 3.6 V - 0.4 CMOS port IIO =+ 8mA 2.7 V < VDD < 3.6 V IIO = +20 mA 2.7 V < VDD < 3.6 V IIO = +6 mA 2 V < VDD < 2.7 V Unit V VDD-0.4 - - 0.4 V 2.4 - - 1.3 V VDD-1.3 - - 0.4 V VDD-0.4 - 1. PC13, PC14, PC15 and PI8 are supplied through the power switch. Since the switch only sinks a limited amount of current (3 mA), the use of GPIOs PC13 to PC15 and PI8 in output mode is limited: the speed should not exceed 2 MHz with a maximum load of 30 pF and these I/Os must not be used as a current source (e.g. to drive an LED). 2. The IIO current sunk by the device must always respect the absolute maximum rating specified in Table 8 and the sum of IIO (I/O ports and control pins) must not exceed IVSS. 3. The IIO current sourced by the device must always respect the absolute maximum rating specified in Table 8 and the sum of IIO (I/O ports and control pins) must not exceed IVDD. 4. Based on characterization data, not tested in production. Doc ID 17050 Rev 6 95/168 Electrical characteristics STM32F215xx, STM32F217xx Input/output AC characteristics The definition and values of input/output AC characteristics are given in Figure 36 and Table 44, respectively. Unless otherwise specified, the parameters given in Table 44 are derived from tests performed under the ambient temperature and VDD supply voltage conditions summarized in Table 10. Table 44. OSPEEDRy [1:0] bit value(1) I/O AC characteristics(1)(2) Symbol Parameter Conditions fmax(IO)out Maximum frequency(3) 00 tf(IO)out Output high to low level fall time tr(IO)out Output low to high level rise time fmax(IO)out Maximum frequency(3) 01 Typ Max CL = 50 pF, VDD > 2.70 V - - 2 CL = 50 pF, VDD > 1.8 V - - 2 CL = 10 pF, VDD > 2.70 V - - TBD CL = 10 pF, VDD > 1.8 V - - TBD - - TBD CL = 50 pF, VDD = 1.8 V to 3.6 V ns - - TBD CL = 50 pF, VDD > 2.70 V - - 25 CL = 50 pF, VDD > 1.8 V - - 12.5(4) CL = 10 pF, VDD > 2.70 V - - 50(4) CL = 10 pF, VDD > 1.8 V - - TBD Output high to low level fall time CL = 50 pF, VDD < 2.7 V - - TBD CL = 10 pF, VDD > 2.7 V - - TBD CL = 50 pF, VDD < 2.7 V - - TBD tr(IO)out Output low to high level rise time CL = 10 pF, VDD > 2.7 V - - TBD CL = 40 pF, VDD > 2.70 V - - 50(4) CL = 40 pF, VDD > 1.8 V - - 25 CL = 10 pF, VDD > 2.70 V - - 100(4) CL = 10 pF, VDD > 1.8 V - - TBD CL = 50 pF, 2.4 < VDD < 2.7 V - - TBD CL = 10 pF, VDD > 2.7 V - - TBD CL = 50 pF, 2.4 < VDD < 2.7 V - - TBD CL = 10 pF, VDD > 2.7 V - - TBD 10 tf(IO)out Output high to low level fall time tr(IO)out Output low to high level rise time Doc ID 17050 Rev 6 Unit MHz tf(IO)out fmax(IO)out Maximum frequency(3) 96/168 Min MHz ns MHz ns STM32F215xx, STM32F217xx Table 44. OSPEEDRy [1:0] bit value(1) Electrical characteristics I/O AC characteristics(1)(2) (continued) Symbol Parameter Conditions Fmax(IO)out Maximum frequency(3) 11 - tf(IO)out Output high to low level fall time tr(IO)out Output low to high level rise time tEXTIpw Pulse width of external signals detected by the EXTI controller Min Typ Max CL = 30 pF, VDD > 2.70 V - - 100(4) CL = 30 pF, VDD > 1.8 V - - 50(4) CL = 10 pF, VDD > 2.70 V - - 200(4) CL = 10 pF, VDD > 1.8 V - - TBD CL = 20 pF, 2.4 < VDD < 2.7 V - - TBD CL = 10 pF, VDD > 2.7 V - - TBD CL = 20 pF, 2.4 < VDD < 2.7 V - - TBD CL = 10 pF, VDD > 2.7 V - - TBD 10 - - Unit MHz ns ns 1. The I/O speed is configured using the OSPEEDRy[1:0] bits. Refer to the STM32F20/21xxx reference manual for a description of the GPIOx_SPEEDR GPIO port output speed register. 2. TBD stands for "to be defined". 3. The maximum frequency is defined in Figure 36. 4. For maximum frequencies above 50 MHz, the compensation cell should be used. Figure 36. I/O AC characteristics definition 90% 10% 50% 50% 90% 10% EXT ERNAL OUTPUT ON 50pF tr(I O)out tr(I O)out T Maximum frequency is achieved if (tr + tf) 2/3)T and if the duty cycle is (45-55%) when loaded by 50pF ai14131 Doc ID 17050 Rev 6 97/168 Electrical characteristics 5.3.17 STM32F215xx, STM32F217xx NRST pin characteristics The NRST pin input driver uses CMOS technology. It is connected to a permanent pull-up resistor, RPU (see Table 42). Unless otherwise specified, the parameters given in Table 45 are derived from tests performed under the ambient temperature and VDD supply voltage conditions summarized in Table 10. Table 45. NRST pin characteristics Symbol Parameter Conditions Min Typ Max Unit VIL(NRST)(1) NRST Input low level voltage -0.5 - 0.8 VIH(NRST)(1) NRST Input high level voltage 2 - VDD+0.5 Vhys(NRST) NRST Schmitt trigger voltage hysteresis - 200 - mV 30 40 50 k - - 100 ns Weak pull-up equivalent resistor(2) RPU VF(NRST) V (1) VIN = VSS NRST Input filtered pulse VNF(NRST)(1) NRST Input not filtered pulse VDD > 2.7 V 300 - - ns TNRST_OUT Generated reset pulse duration Internal Reset source 20 - - s 1. Guaranteed by design, not tested in production. 2. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution to the series resistance must be minimum (~10% order). Figure 37. Recommended NRST pin protection 6$$ %XTERNAL RESET CIRCUIT .234 205 )NTERNAL 2ESET &ILTER & 34-&XXX AIC 2. The reset network protects the device against parasitic resets. 3. The user must ensure that the level on the NRST pin can go below the VIL(NRST) max level specified in Table 45. Otherwise the reset is not taken into account by the device. 98/168 Doc ID 17050 Rev 6 STM32F215xx, STM32F217xx 5.3.18 Electrical characteristics TIM timer characteristics The parameters given in Table 46 and Table 47 are guaranteed by design. Refer to Section 5.3.16: I/O port characteristics for details on the input/output alternate function characteristics (output compare, input capture, external clock, PWM output). Table 46. Symbol tres(TIM) Characteristics of TIMx connected to the APB1 domain(1) Parameter Timer resolution time Conditions AHB/APB1 prescaler distinct from 1, fTIMxCLK = 60 MHz AHB/APB1 prescaler = 1, fTIMxCLK = 30 MHz fEXT ResTIM tCOUNTER Min Max Unit 1 - tTIMxCLK 16.7 - ns 1 - tTIMxCLK 33.3 - ns Timer external clock frequency on CH1 to CH4 0 fTIMxCLK/2 MHz 0 30 MHz Timer resolution - 16/32 bit 65536 tTIMxCLK 1092 s - tTIMxCLK 71582788 s - 65536 x 65536 tTIMxCLK - 71.6 s 16-bit counter clock period 1 when internal clock is fTIMxCLK = 60 MHz 0.0167 selected APB1= 30 MHz 32-bit counter clock period 1 when internal clock is 0.0167 selected tMAX_COUNT Maximum possible count 1. TIMx is used as a general term to refer to the TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, and TIM12 timers. Doc ID 17050 Rev 6 99/168 Electrical characteristics Table 47. Symbol tres(TIM) STM32F215xx, STM32F217xx Characteristics of TIMx connected to the APB2 domain(1) Parameter Timer resolution time Conditions AHB/APB2 prescaler distinct from 1, fTIMxCLK = 120 MHz AHB/APB2 prescaler = 1, fTIMxCLK = 60 MHz fEXT ResTIM Timer external clock frequency on CH1 to CH4 Timer resolution fTIMxCLK = 120 MHz tCOUNTER 16-bit counter clock period APB2 = 60 MHz when internal clock is selected tMAX_COUNT Maximum possible count Min Max Unit 1 - tTIMxCLK 8.3 - ns 1 - tTIMxCLK 16.7 - ns 0 fTIMxCLK/2 MHz 0 60 MHz - 16 bit 1 65536 tTIMxCLK 0.0083 546 s - 65536 x 65536 tTIMxCLK - 35.79 s 1. TIMx is used as a general term to refer to the TIM1, TIM8, TIM9, TIM10, and TIM11 timers. 5.3.19 Communications interfaces I2C interface characteristics Unless otherwise specified, the parameters given in Table 48 are derived from tests performed under the ambient temperature, fPCLK1 frequency and VDD supply voltage conditions summarized in Table 10. STM32F215xx and STM32F217xx I2C interface meets the requirements of the standard I2C communication protocol with the following restrictions: the I/O pins SDA and SCL are mapped to are not "true" open-drain. When configured as open-drain, the PMOS connected between the I/O pin and VDD is disabled, but is still present. The I2C characteristics are described in Table 48. Refer also to Section 5.3.16: I/O port characteristics for more details on the input/output alternate function characteristics (SDA and SCL). 100/168 Doc ID 17050 Rev 6 STM32F215xx, STM32F217xx Table 48. Electrical characteristics I2C characteristics Standard mode I2C(1) Symbol Fast mode I2C(1)(2) Parameter Unit Min Max Min Max tw(SCLL) SCL clock low time 4.7 - 1.3 - tw(SCLH) SCL clock high time 4.0 - 0.6 - tsu(SDA) SDA setup time 250 - 100 - - (4) s (3) 900(3) th(SDA) SDA data hold time tr(SDA) tr(SCL) SDA and SCL rise time - 1000 20 + 0.1Cb 300 tf(SDA) tf(SCL) SDA and SCL fall time - 300 - 300 th(STA) Start condition hold time 4.0 - 0.6 - tsu(STA) Repeated Start condition setup time 4.7 - 0.6 - tsu(STO) Stop condition setup time 4.0 - 0.6 - s tw(STO:STA) Stop to Start condition time (bus free) 4.7 - 1.3 - s Cb Capacitive load for each bus line - 400 - 400 pF 0 0 ns s 1. Guaranteed by design, not tested in production. 2. fPCLK1 must be at least 2 MHz to achieve standard mode I2C frequencies. It must be at least 4 MHz to achieve fast mode I2C frequencies, and a multiple of 10 MHz to reach the 400 kHz maximum I2C fast mode clock. 3. The maximum hold time of the Start condition has only to be met if the interface does not stretch the low period of SCL signal. 4. The device must internally provide a hold time of at least 300ns for the SDA signal in order to bridge the undefined region of the falling edge of SCL. Doc ID 17050 Rev 6 101/168 Electrical characteristics STM32F215xx, STM32F217xx Figure 38. I2C bus AC waveforms and measurement circuit 6$$ 6$$ K K )# BUS 34-&XX 3$! 3#, 3 4!24 2%0%!4%$ 3 4!24 3 4!24 TSU34! 3$! TF3$! TR3$! TH34! 3#, TW3#,( TSU3$! TW3#,, TR3#, TW34/34! 3 4/0 TH3$! TSU34/ TF3#, AIB 1. Measurement points are done at CMOS levels: 0.3VDD and 0.7VDD. Table 49. SCL frequency (fPCLK1= 30 MHz.,VDD = 3.3 V)(1)(2) I2C_CCR value fSCL (kHz) RP = 4.7 k 400 0x8019 300 0x8021 200 0x8032 100 0x0096 50 0x012C 20 0x02EE 2 1. RP = External pull-up resistance, fSCL = I C speed, 2. For speeds around 200 kHz, the tolerance on the achieved speed is of 5%. For other speed ranges, the tolerance on the achieved speed 2%. These variations depend on the accuracy of the external components used to design the application. 102/168 Doc ID 17050 Rev 6 STM32F215xx, STM32F217xx Electrical characteristics I2S - SPI interface characteristics Unless otherwise specified, the parameters given in Table 50 for SPI or in Table 51 for I2S are derived from tests performed under the ambient temperature, fPCLKx frequency and VDD supply voltage conditions summarized in Table 10. Refer to Section 5.3.16: I/O port characteristics for more details on the input/output alternate function characteristics (NSS, SCK, MOSI, MISO for SPI and WS, CK, SD for I2S). Table 50. Symbol fSCK 1/tc(SCK) SPI characteristics(1) Parameter Conditions Min Max Master mode - 30 Slave mode - 30 - 8 ns % SPI clock frequency MHz tr(SCL) tf(SCL) SPI clock rise and fall time Capacitive load: C = 30 pF DuCy(SCK) SPI slave input clock duty cycle Slave mode 30 70 tsu(NSS)(2) NSS setup time Slave mode 4tPCLK - th(NSS)(2) NSS hold time Slave mode 2tPCLK - tw(SCLH) tw(SCLL)(2) SCK high and low time Master mode, fPCLK = 30 MHz, presc = 2 tPCLK-3 tPCLK+3 tsu(MI) (2) tsu(SI)(2) Data input setup time th(MI) (2) th(SI)(2) Data input hold time ta(SO)(2)(3) (2) Master mode 5 - Slave mode 5 - Master mode 5 - Slave mode 4 - Data output access time Slave mode, fPCLK = 20 MHz 0 3tPCLK tdis(SO)(2)(4) Data output disable time Slave mode 2 10 tv(SO) (2)(1) Data output valid time Slave mode (after enable edge) - 25 (2)(1) Data output valid time Master mode (after enable edge) - 5 Slave mode (after enable edge) 15 - Master mode (after enable edge) 2 - tv(MO) th(SO)(2) th(MO)(2) Unit ns Data output hold time 1. Remapped SPI1 characteristics to be determined. 2. Based on characterization, not tested in production. 3. Min time is for the minimum time to drive the output and the max time is for the maximum time to validate the data. 4. Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put the data in Hi-Z Doc ID 17050 Rev 6 103/168 Electrical characteristics STM32F215xx, STM32F217xx Figure 39. SPI timing diagram - slave mode and CPHA = 0 NSS input tc(SCK) th(NSS) SCK Input tSU(NSS) CPHA= 0 CPOL=0 tw(SCKH) tw(SCKL) CPHA= 0 CPOL=1 tv(SO) ta(SO) MISO OUT P UT tr(SCK) tf(SCK) th(SO) MS B O UT BI T6 OUT tdis(SO) LSB OUT tsu(SI) MOSI I NPUT B I T1 IN M SB IN LSB IN th(SI) ai14134c Figure 40. SPI timing diagram - slave mode and CPHA = 1(1) NSS input SCK Input tSU(NSS) CPHA=1 CPOL=0 CPHA=1 CPOL=1 tc(SCK) tw(SCKH) tw(SCKL) tv(SO) ta(SO) MISO OUT P UT MS B O UT tsu(SI) MOSI I NPUT th(NSS) th(SO) BI T6 OUT tr(SCK) tf(SCK) tdis(SO) LSB OUT th(SI) B I T1 IN M SB IN LSB IN ai14135 1. Measurement points are done at CMOS levels: 0.3VDD and 0.7VDD. 104/168 Doc ID 17050 Rev 6 STM32F215xx, STM32F217xx Electrical characteristics Figure 41. SPI timing diagram - master mode(1) High NSS input SCK Input SCK Input tc(SCK) CPHA= 0 CPOL=0 CPHA= 0 CPOL=1 CPHA=1 CPOL=0 CPHA=1 CPOL=1 tsu(MI) MISO INP UT tw(SCKH) tw(SCKL) tr(SCK) tf(SCK) MS BIN BI T6 IN LSB IN th(MI) MOSI OUTUT M SB OUT B I T1 OUT tv(MO) LSB OUT th(MO) ai14136 1. Measurement points are done at CMOS levels: 0.3VDD and 0.7VDD. Doc ID 17050 Rev 6 105/168 Electrical characteristics Table 51. STM32F215xx, STM32F217xx I2S characteristics(1) Symbol Parameter Conditions Min Max Master 1.23 1.24 Slave 0 TBD - TBD fCK 1/tc(CK) I2S clock frequency tr(CK) tf(CK) I2S clock rise and fall time capacitive load CL = 50 pF tv(WS) (2) WS valid time Master 0.3 - th(WS) (2) WS hold time Master 0 - WS setup time Slave 3 - WS hold time Slave 0 - tw(CKH) tw(CKL) (2) CK high and low time Master fPCLK= 120 MHz, presc = 7 396 - tsu(SD_MR) (2) tsu(SD_SR) (2) Data input setup time Master receiver Slave receiver 45 0 - th(SD_MR)(2)(3) th(SD_SR) (2)(3) Data input hold time Master receiver Slave receiver 13 0 - th(SD_MR) (2) th(SD_SR) (2) Data input hold time Master fPCLK = 120 MHz, Slave fPCLK=120 MHz 13 0 - tv(SD_ST) (2)(3) Slave transmitter (after enable edge) - 12 Data output valid time fPCLK = 120 MHz - 12 Slave transmitter (after enable edge) 10 - Master transmitter (after enable edge) - 4 fPCLK = 120 MHz 4 6 Master transmitter (after enable edge) 0 - tsu(WS) th(WS) (2) (2) (2) th(SD_ST) (2) tv(SD_MT) (2)(3) th(SD_MT) (2) Data output hold time Data output valid time Data output hold time MHz 1. TBD stands for "to be defined". 2. Based on design simulation and/or characterization results, not tested in production. 3. Depends on fPCLK. For example, if fPCLK=8 MHz, then TPCLK = 1/fPLCLK =125 ns. 106/168 Unit Doc ID 17050 Rev 6 ns STM32F215xx, STM32F217xx Electrical characteristics Figure 42. I2S slave timing diagram (Philips protocol)(1) CK Input tc(CK) CPOL = 0 CPOL = 1 tw(CKH) th(WS) tw(CKL) WS input tv(SD_ST) tsu(WS) SDtransmit LSB transmit(2) MSB transmit Bitn transmit tsu(SD_SR) LSB receive(2) SDreceive th(SD_ST) LSB transmit th(SD_SR) MSB receive Bitn receive LSB receive ai14881b 1. Measurement points are done at CMOS levels: 0.3 x VDD and 0.7 x VDD. 2. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first byte. Figure 43. I2S master timing diagram (Philips protocol)(1) tf(CK) tr(CK) CK output tc(CK) CPOL = 0 tw(CKH) CPOL = 1 tv(WS) th(WS) tw(CKL) WS output tv(SD_MT) SDtransmit LSB transmit(2) MSB transmit LSB receive(2) LSB transmit th(SD_MR) tsu(SD_MR) SDreceive Bitn transmit th(SD_MT) MSB receive Bitn receive LSB receive ai14884b 1. Based on characterization, not tested in production. 2. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first byte. Doc ID 17050 Rev 6 107/168 Electrical characteristics STM32F215xx, STM32F217xx USB OTG FS characteristics The USB OTG interface is USB-IF certified (Full-Speed). This interface is present in both the USB OTG HS and USB OTG FS controllers. Table 52. USB OTG FS startup time Symbol tSTARTUP(1) Parameter USB OTG FS transceiver startup time Max Unit 1 s 1. Guaranteed by design, not tested in production. Table 53. USB OTG FS DC electrical characteristics Symbol VDD Input levels Parameter Conditions USB OTG FS operating voltage Min.(1) Typ. Max.(1) Unit 3.0(2) - 3.6 VDI(3) Differential input sensitivity I(USB_FS_DP/DM, USB_HS_DP/DM) 0.2 - - VCM(3) Differential common mode range Includes VDI range 0.8 - 2.5 VSE(3) Single ended receiver threshold 1.3 - 2.0 VOL Static output level low - - 0.3 2.8 - 3.6 17 21 24 0.65 1.1 2.0 Output levels VOH Static output level high RL of 1.5 k to 3.6 V(4) RL of 15 k to VSS(4) PA11, PA12, PB14, PB15 (USB_FS_DP/DM, USB_HS_DP/DM) RPD RPU PA9, PB13 (OTG_FS_VBUS, OTG_HS_VBUS) V V V VIN = VDD k PA12, PB15 (USB_FS_DP, USB_HS_DP) VIN = VSS 1.5 1.8 2.1 PA9, PB13 (OTG_FS_VBUS, OTG_HS_VBUS) VIN = VSS 0.25 0.37 0.55 1. All the voltages are measured from the local ground potential. 2. The STM32F215xx and STM32F217xx USB OTG FS functionality is ensured down to 2.7 V but not the full USB OTG FS electrical characteristics which are degraded in the 2.7-to-3.0 V VDD voltage range. 3. Guaranteed by design, not tested in production. 4. RL is the load connected on the USB OTG FS drivers 108/168 Doc ID 17050 Rev 6 STM32F215xx, STM32F217xx Electrical characteristics Figure 44. USB OTG FS timings: definition of data signal rise and fall time Crossover points Differen tial data lines VCRS VS S Table 54. tr tf ai14137 USB OTG FS electrical characteristics(1) Driver characteristics Symbol Parameter Rise time(2) tr tf time(2) Fall trfm Conditions Min Max Unit CL = 50 pF 4 20 ns CL = 50 pF 4 20 ns tr/tf 90 110 % 1.3 2.0 V Rise/ fall time matching VCRS Output signal crossover voltage 1. Guaranteed by design, not tested in production. 2. Measured from 10% to 90% of the data signal. For more detailed informations, please refer to USB Specification - Chapter 7 (version 2.0). USB HS characteristics Table 55 shows the USB HS operating voltage. Table 55. USB HS DC electrical characteristics Symbol Input level Min.(1) Max.(1) Unit 2.7 3.6 V Min Nominal Max Unit 54 60 66 MHz 59.97 60 60.03 MHz 40 50 60 % 49.975 50 50.025 % - - 1.4 ms Parameter VDD Ethernet operating voltage 1. All the voltages are measured from the local ground potential. Table 56. Clock timing parameters Parameter(1) Frequency (first transition) Symbol 8-bit 10% FSTART_8BIT Frequency (steady state) 500 ppm FSTEADY Duty cycle (first transition) DSTART_8BIT 8-bit 10% Duty cycle (steady state) 500 ppm DSTEADY Time to reach the steady state frequency and TSTEADY duty cycle after the first transition Clock startup time after the de-assertion of SuspendM Peripheral TSTART_DEV - - 5.6 Host TSTART_HOST - - - - - - PHY preparation time after the first transition TPREP of the input clock ms s 1. Guaranteed by design, not tested in production. Doc ID 17050 Rev 6 109/168 Electrical characteristics STM32F215xx, STM32F217xx Figure 45. ULPI timing diagram #LOCK #ONTROL )N 5,0)?$)2 5,0)?.84 T3# T(# T3$ T($ DATA )N BIT T$# T$# #ONTROL OUT 5,0)?340 T$$ DATA OUT BIT AIC Table 57. ULPI timing Value(1) Parameter Symbol Control in (ULPI_DIR) setup time tSC Control in (ULPI_NXT) setup time Unit Min. Max. - 2.0 - 1.5 Control in (ULPI_DIR, ULPI_NXT) hold time tHC Data in setup time tSD - 2.0 Data in hold time tHD 0 - Control out (ULPI_STP) setup time and hold time tDC - 9.2 Data out available from clock rising edge tDD - 10.7 Min.(1) Max.(1) Unit 2.7 3.6 V ns 1. VDD = 2.7 V to 3.6 V and TA = -40 to 85 C. Ethernet characteristics Table 58 shows the Ethernet operating voltage. Table 58. Ethernet DC electrical characteristics Symbol Input level Parameter VDD Ethernet operating voltage 1. All the voltages are measured from the local ground potential. Table 59 gives the list of Ethernet MAC signals for the SMI (station management interface) and Figure 46 shows the corresponding timing diagram. 110/168 Doc ID 17050 Rev 6 STM32F215xx, STM32F217xx Electrical characteristics Figure 46. Ethernet SMI timing diagram tMDC ETH_MDC td(MDIO) ETH_MDIO(O) tsu(MDIO) th(MDIO) ETH_MDIO(I) ai15666c Dynamics characteristics: Ethernet MAC signals for SMI(1) Table 59. Symbol Rating Min Typ Max Unit tMDC MDC cycle time (2.38 MHz, AHB = 60 MHz) 411 420 425 ns td(MDIO) MDIO write data valid time 6 10 13 ns tsu(MDIO) Read data setup time TBD TBD TBD ns th(MDIO) TBD TBD TBD ns Read data hold time 1. TBD stands for "to be defined". Table 60 gives the list of Ethernet MAC signals for the RMII and Figure 47 shows the corresponding timing diagram. Figure 47. Ethernet RMII timing diagram RMII_REF_CLK td(TXEN) td(TXD) RMII_TX_EN RMII_TXD[1:0] tsu(RXD) tsu(CRS) tih(RXD) tih(CRS) RMII_RXD[1:0] RMII_CRS_DV ai15667 Table 60. Symbol Dynamics characteristics: Ethernet MAC signals for RMII Rating Min Typ Max Unit tsu(RXD) Receive data setup time 1 - 4 ns tih(RXD) Receive data hold time 1.5 - 2 ns tsu(CRS) Carrier sense set-up time 0 - 4 ns tih(CRS) Carrier sense hold time 2 - 2 ns td(TXEN) Transmit enable valid delay time 9 11 13 ns td(TXD) Transmit data valid delay time 9 11.5 14 ns Doc ID 17050 Rev 6 111/168 Electrical characteristics STM32F215xx, STM32F217xx Table 61 gives the list of Ethernet MAC signals for MII and Figure 47 shows the corresponding timing diagram. Figure 48. Ethernet MII timing diagram MII_RX_CLK MII_RXD[3:0] MII_RX_DV MII_RX_ER tsu(RXD) tsu(ER) tsu(DV) tih(RXD) tih(ER) tih(DV) MII_TX_CLK td(TXEN) td(TXD) MII_TX_EN MII_TXD[3:0] ai15668 Table 61. Dynamics characteristics: Ethernet MAC signals for MII(1) Symbol Rating Min Typ Max Unit tsu(RXD) Receive data setup time 7.5 - 10 ns tih(RXD) Receive data hold time 1 - 10 ns tsu(DV) Data valid setup time 4 - 10 ns tih(DV) Data valid hold time 0 - 10 ns tsu(ER) Error setup time 3.5 - 10 ns tih(ER) Error hold time 0 - 10 ns td(TXEN) Transmit enable valid delay time 7.5 11 14 ns td(TXD) Transmit data valid delay time 7.5 11 14 ns 1. TBD stands for "to be defined". CAN (controller area network) interface Refer to Section 5.3.16: I/O port characteristics for more details on the input/output alternate function characteristics (CANTX and CANRX). 112/168 Doc ID 17050 Rev 6 STM32F215xx, STM32F217xx 5.3.20 Electrical characteristics 12-bit ADC characteristics Unless otherwise specified, the parameters given in Table 62 are derived from tests performed under the ambient temperature, fPCLK2 frequency and VDDA supply voltage conditions summarized in Table 10. Table 62. Symbol ADC characteristics(1) Parameter VDDA Power supply VREF+ Positive reference voltage fADC fTRIG(3) VAIN RAIN(3) ADC clock frequency External trigger frequency Conditions Min Typ Max Unit 1.8 - 3.6 V 1.8(2) - VDDA V VDDA = 1.8 to 2.4 V 0.6 - 15 MHz VDDA = 2.4 to 3.6 V 0.6 - 30 MHz fADC = 30 MHz - - 823 kHz - - 17 1/fADC 0 (VSSA or VREFtied to ground) - VREF+ V - - 50 k 1.5 - 6 k 4 - TBD pF - - 0.100 s - - 3(6) 1/fADC - - 0.067 s - - 2(6) 1/fADC 0.100 - 16 s 3 - 480 1/fADC - 2 3 s fADC = 30 MHz 12-bit resolution 0.5 - 16.40 s fADC = 30 MHz 10-bit resolution 0.43 - 16.34 s fADC = 30 MHz 8-bit resolution 0.37 - 16.27 s fADC = 30 MHz 6-bit resolution 0.3 - 16.20 s Conversion voltage range(4) External input impedance See Equation 1 for details RADC(3)(5) Sampling switch resistance CADC(3) Internal sample and hold capacitor tlat(3) Injection trigger conversion latency tlatr(3) Regular trigger conversion latency tS(3) Sampling time tSTAB(3) Power-up time tCONV(3) Total conversion time (including sampling time) fADC = 30 MHz fADC = 30 MHz fADC = 30 MHz 9 to 492 (tS for sampling +n-bit resolution for successive approximation) Doc ID 17050 Rev 6 1/fADC 113/168 Electrical characteristics Table 62. Symbol fS(3) IVREF+(3) IDDA(3) STM32F215xx, STM32F217xx ADC characteristics(1) (continued) Parameter Sampling rate (fADC = 30 MHz) Conditions Min Typ Max Unit 12-bit resolution Single ADC - - 2 Msps 12-bit resolution Interleave Dual ADC mode - - 3.75 Msps 12-bit resolution Interleave Triple ADC mode - - 6 Msps fADC = 30 MHz 3 sampling time 12-bit resolution - 300 500 A fADC = 30 MHz 480 sampling time 12-bit resolution - - TBD A fADC = 30 MHz 3 sampling time 12-bit resolution - 1.6 1.8 fADC = 30 MHz 480 sampling time 12-bit resolution - ADC VREF DC current consumption in conversion mode ADC VDDA DC current consumption in conversion mode mA - TBD 1. TBD stands for "to be defined". 2. It is recommended to maintain the voltage difference between VREF+ and VDDA below 1.8 V. 3. Based on characterization, not tested in production. 4. VREF+ is internally connected to VDDA and VREF- is internally connected to VSSA. 5. RADC maximum value is given for VDD=1.8 V, and minimum value for VDD=3.3 V. 6. For external triggers, a delay of 1/fPCLK2 must be added to the latency specified in Table 62. Equation 1: RAIN max formula R AIN ( k - 0.5 ) - - R ADC = ------------------------------------------------------------N+2 f ADC x C ADC x ln ( 2 ) The formula above (Equation 1) is used to determine the maximum external impedance allowed for an error below 1/4 of LSB. N = 12 (from 12-bit resolution) and k is the number of sampling periods defined in the ADC_SMPR1 register. 114/168 Doc ID 17050 Rev 6 STM32F215xx, STM32F217xx a Table 63. Symbol Electrical characteristics ADC accuracy (1) Parameter Test conditions ET Total unadjusted error EO Offset error EG Gain error ED Differential linearity error EL Integral linearity error fPCLK2 = 60 MHz, fADC = 30 MHz, RAIN < 10 k, VDDA = 1.8 to 3.6 V Typ Max(2) 2 5 1.5 2.5 1.5 3 1 2 1.5 3 Unit LSB 1. Better performance could be achieved in restricted VDD, frequency and temperature ranges. 2. Based on characterization, not tested in production. Note: ADC accuracy vs. negative injection current: Injecting a negative current on any of the standard (non-robust) analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to add a Schottky diode (pin to ground) to standard analog pins which may potentially inject negative currents. Any positive injection current within the limits specified for IINJ(PIN) and IINJ(PIN) in Section 5.3.16 does not affect the ADC accuracy. Figure 49. ADC accuracy characteristics 6 6 ;,3")$%!, 2%& OR $$! DEPENDING ON PACKAGE = %' %4 %/ %, %$ , 3")$%!, 633! 6$$! AIC 1. Example of an actual transfer curve. 2. Ideal transfer curve. 3. End point correlation line. 4. ET = Total Unadjusted Error: maximum deviation between the actual and the ideal transfer curves. EO = Offset Error: deviation between the first actual transition and the first ideal one. EG = Gain Error: deviation between the last ideal transition and the last actual one. ED = Differential Linearity Error: maximum deviation between actual steps and the ideal one. EL = Integral Linearity Error: maximum deviation between any actual transition and the end point correlation line. Doc ID 17050 Rev 6 115/168 Electrical characteristics STM32F215xx, STM32F217xx Figure 50. Typical connection diagram using the ADC STM32F VDD RAIN(1) Sample and hold ADC converter VT 0.6 V RADC(1) AINx VAIN Cparasitic VT 0.6 V IL1 A 12-bit converter CADC(1) ai17534 1. Refer to Table 62 for the values of RAIN, RADC and CADC. 2. Cparasitic represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the pad capacitance (roughly 7 pF). A high Cparasitic value downgrades conversion accuracy. To remedy this, fADC should be reduced. 116/168 Doc ID 17050 Rev 6 STM32F215xx, STM32F217xx Electrical characteristics General PCB design guidelines Power supply decoupling should be performed as shown in Figure 51 or Figure 52, depending on whether VREF+ is connected to VDDA or not. The 10 nF capacitors should be ceramic (good quality). They should be placed them as close as possible to the chip. Figure 51. Power supply and reference decoupling (VREF+ not connected to VDDA) STM32F V REF+ (See note 1) 1 F // 10 nF V DDA 1 F // 10 nF V SSA/V REF(See note 1) ai17535 1. VREF+ and VREF- inputs are available only on 100-pin packages. Figure 52. Power supply and reference decoupling (VREF+ connected to VDDA) STM32F VREF+/VDDA (See note 1) 1 F // 10 nF VREF-/VSSA (See note 1) ai17536 1. VREF+ and VREF- inputs are available only on 100-pin packages. Doc ID 17050 Rev 6 117/168 Electrical characteristics STM32F215xx, STM32F217xx 5.3.21 DAC electrical characteristics Table 64. DAC characteristics Symbol Parameter Min Typ Max Unit Comments VDDA Analog supply voltage 1.8 - 3.6 V VREF+ Reference supply voltage 1.8 - 3.6 V VSSA Ground 0 - 0 V RLOAD(1) Resistive load with buffer ON 5 - - k RO(1) Impedance output with buffer OFF - - 15 k When the buffer is OFF, the Minimum resistive load between DAC_OUT and VSS to have a 1% accuracy is 1.5 M CLOAD(1) Capacitive load - - 50 pF Maximum capacitive load at DAC_OUT pin (when the buffer is ON). DAC_OUT Lower DAC_OUT voltage min(1) with buffer ON 0.2 - - V DAC_OUT Higher DAC_OUT voltage with buffer ON max(1) - - VDDA - 0.2 V DAC_OUT Lower DAC_OUT voltage min(1) with buffer OFF - 0.5 - mV DAC_OUT Higher DAC_OUT voltage with buffer OFF max(1) - - VREF+ - 1LSB - 170 240 IVREF+(2) IDDA(2) DNL(2) 118/168 Differential non linearity Difference between two consecutive code-1LSB) It gives the maximum output excursion of the DAC. It corresponds to 12-bit input code (0x0E0) to (0xF1C) at VREF+ = 3.6 V and (0x1C7) to (0xE38) at VREF+ = 1.8 V It gives the maximum output excursion of the DAC. DAC DC VREF current consumption in quiescent mode (Standby mode) DAC DC VDDA current consumption in quiescent mode (Standby mode) VREF+ VDDA V With no load, worst code (0x800) at VREF+ = 3.6 V in terms of DC consumption on the inputs A With no load, worst code (0xF1C) at VREF+ = 3.6 V in terms of DC consumption on the inputs - 50 75 - 280 380 A With no load, middle code (0x800) on the inputs - 475 625 A With no load, worst code (0xF1C) at VREF+ = 3.6 V in terms of DC consumption on the inputs - - 0.5 LSB Given for the DAC in 10-bit configuration. - - 2 LSB Given for the DAC in 12-bit configuration. Doc ID 17050 Rev 6 STM32F215xx, STM32F217xx Table 64. Symbol INL(2) Offset(2) Gain error(2) Electrical characteristics DAC characteristics (continued) Parameter Min Typ Max Unit - - 1 LSB Given for the DAC in 10-bit configuration. - - 4 LSB Given for the DAC in 12-bit configuration. - - 10 mV Given for the DAC in 12-bit configuration - - 3 LSB Given for the DAC in 10-bit at VREF+ = 3.6 V - - 12 LSB Given for the DAC in 12-bit at VREF+ = 3.6 V - - 0.5 % Given for the DAC in 12-bit configuration - 3 6 s CLOAD 50 pF, RLOAD 5 k Integral non linearity (difference between measured value at Code i and the value at Code i on a line drawn between Code 0 and last Code 1023) Offset error (difference between measured value at Code (0x800) and the ideal value = VREF+/2) Gain error Settling time (full scale: for a 10-bit input code transition (2) between the lowest and the tSETTLING highest input codes when DAC_OUT reaches final value 4LSB Comments THD(2) Total Harmonic Distortion Buffer ON - - - dB CLOAD 50 pF, RLOAD 5 k Update rate(1) Max frequency for a correct DAC_OUT change when small variation in the input code (from code i to i+1LSB) - - 1 MS/s CLOAD 50 pF, RLOAD 5 k - 6.5 10 s CLOAD 50 pF, RLOAD 5 k input code between lowest and highest possible ones. - -67 -40 dB No RLOAD, CLOAD = 50 pF Wakeup time from off state tWAKEUP(2) (Setting the ENx bit in the DAC Control register) PSRR+ (1) Power supply rejection ratio (to VDDA) (static DC measurement) 1. Guaranteed by design, not tested in production. 2. Guaranteed by characterization, not tested in production. Doc ID 17050 Rev 6 119/168 Electrical characteristics STM32F215xx, STM32F217xx Figure 53. 12-bit buffered /non-buffered DAC Buffered/Non-buffered DAC Buffer(1) R LOAD DACx_OUT 12-bit digital to analog converter C LOAD ai17157 1. The DAC integrates an output buffer that can be used to reduce the output impedance and to drive external loads directly without the use of an external operational amplifier. The buffer can be bypassed by configuring the BOFFx bit in the DAC_CR register. 5.3.22 Temperature sensor characteristics Table 65. TS characteristics Symbol Parameter TL(1) Avg_Slope(1) V25(1) tSTART(2) TS_temp(3)(2) Min Typ Max Unit VSENSE linearity with temperature - 1 2 C Average slope - 2.5 mV/C Voltage at 25 C - 0.76 V Startup time - 6 10 s 10 - - s Min Typ Max Unit K ADC sampling time when reading the temperature 1C accuracy 1. Based on characterization, not tested in production. 2. Guaranteed by design, not tested in production. 3. Shortest sampling time can be determined in the application by multiple iterations. 5.3.23 VBAT monitoring characteristics Table 66. VBAT monitoring characteristics Symbol Parameter R Resistor bridge for VBAT - 50 - Q Ratio on VBAT measurement - 2 - Error on Q -1 - +1 % ADC sampling time when reading the VBAT 1mV accuracy 5 - - s Er (1) TS_vbat(2)(2) 1. Guaranteed by design, not tested in production. 2. Shortest sampling time can be determined in the application by multiple iterations. 120/168 Doc ID 17050 Rev 6 STM32F215xx, STM32F217xx 5.3.24 Electrical characteristics Embedded reference voltage The parameters given in Table 67 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 10. Table 67. Symbol VREFINT Embedded internal reference voltage Parameter Conditions Min Typ Max Unit -40 C < TA < +105 C 1.18 1.21 1.24 V 10 - - s - 3 5 mV Temperature coefficient - 30 50 ppm/C Startup time - 6 10 s Internal reference voltage ADC sampling time when TS_vrefint(1) reading the internal reference voltage VRERINT_s (2) TCoeff(2) tSTART (2) Internal reference voltage spread over the temperature range VDD = 3 V 1. Shortest sampling time can be determined in the application by multiple iterations. 2. Guaranteed by design, not tested in production. 5.3.25 FSMC characteristics Asynchronous waveforms and timings Figure 54 through Figure 57 represent asynchronous waveforms and Table 68 through Table 71 provide the corresponding timings. The results shown in these tables are obtained with the following FSMC configuration: AddressSetupTime = 1 AddressHoldTime = 1 DataSetupTime = 1 BusTurnAroundDuration = 0x0 In all timing tables, the THCLK is the HCLK clock period. Doc ID 17050 Rev 6 121/168 Electrical characteristics STM32F215xx, STM32F217xx Figure 54. Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms TW.% &3-#?.% TV./%?.% T W./% T H.%?./% &3-#?./% &3-#?.7% TV!?.% &3-#?!;= T H!?./% !DDRESS TV",?.% T H",?./% &3-#?.",;= T H$ATA?.% T SU$ATA?./% TH$ATA?./% T SU$ATA?.% $ATA &3-#?$;= T V.!$6?.% TW.!$6 &3-#?.!$6 AIC 1. Mode 2/B, C and D only. In Mode 1, FSMC_NADV is not used. Table 68. Symbol Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings(1)(2) Min Max Unit 2THCLK- 0.5 2THCLK+0.5 ns 0.5 2.5 ns 2THCLK- 1 2THCLK+ 0.5 ns FSMC_NOE high to FSMC_NE high hold time 0 - ns FSMC_NEx low to FSMC_A valid - 4 ns th(A_NOE) Address hold time after FSMC_NOE high 0 - ns tv(BL_NE) FSMC_NEx low to FSMC_BL valid - 0.5 ns th(BL_NOE) FSMC_BL hold time after FSMC_NOE high 0 - ns tsu(Data_NE) Data to FSMC_NEx high setup time THCLK+ 0.5 - ns tsu(Data_NOE) Data to FSMC_NOEx high setup time THCLK+ 2.5 - ns th(Data_NOE) Data hold time after FSMC_NOE high 0 - ns Data hold time after FSMC_NEx high 0 - ns tv(NADV_NE) FSMC_NEx low to FSMC_NADV low - 2.5 ns - THCLK- 0.5 ns tw(NE) tv(NOE_NE) tw(NOE) th(NE_NOE) tv(A_NE) th(Data_NE) tw(NADV) Parameter FSMC_NE low time FSMC_NEx low to FSMC_NOE low FSMC_NOE low time FSMC_NADV low time 1. CL = 30 pF. 2. Based on characterization, not tested in production. 122/168 Doc ID 17050 Rev 6 STM32F215xx, STM32F217xx Electrical characteristics Figure 55. Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms tw(NE) FSMC_NEx FSMC_NOE tv(NWE_NE) tw(NWE) t h(NE_NWE) FSMC_NWE tv(A_NE) FSMC_A[25:0] th(A_NWE) Address tv(BL_NE) FSMC_NBL[1:0] th(BL_NWE) NBL tv(Data_NE) th(Data_NWE) Data FSMC_D[15:0] t v(NADV_NE) tw(NADV) FSMC_NADV(1) ai14990 1. Mode 2/B, C and D only. In Mode 1, FSMC_NADV is not used. Table 69. Symbol tw(NE) tv(NWE_NE) tw(NWE) th(NE_NWE) tv(A_NE) Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings(1)(2) Parameter Min Max Unit 3THCLK 3THCLK+ 4 ns FSMC_NEx low to FSMC_NWE low THCLK- 0.5 THCLK+ 0.5 ns FSMC_NWE low time THCLK- 0.5 THCLK+ 3 ns THCLK - ns - 0 ns THCLK- 3 - ns - 0.5 ns THCLK- 1 - ns FSMC_NE low time FSMC_NWE high to FSMC_NE high hold time FSMC_NEx low to FSMC_A valid th(A_NWE) Address hold time after FSMC_NWE high tv(BL_NE) FSMC_NEx low to FSMC_BL valid th(BL_NWE) FSMC_BL hold time after FSMC_NWE high tv(Data_NE) Data to FSMC_NEx low to Data valid - THCLK+ 5 ns th(Data_NWE) Data hold time after FSMC_NWE high THCLK+0.5 - ns tv(NADV_NE) FSMC_NEx low to FSMC_NADV low - 2 ns FSMC_NADV low time - THCLK+ 1.5 ns tw(NADV) 1. CL = 30 pF. 2. Based on characterization, not tested in production. Doc ID 17050 Rev 6 123/168 Electrical characteristics STM32F215xx, STM32F217xx Figure 56. Asynchronous multiplexed PSRAM/NOR read waveforms tw(NE) FSMC_NE tv(NOE_NE) t h(NE_NOE) FSMC_NOE t w(NOE) FSMC_NWE tv(A_NE) FSMC_A[25:16] t h(A_NOE) Address tv(BL_NE) th(BL_NOE) FSMC_NBL[1:0] NBL th(Data_NE) tsu(Data_NE) t v(A_NE) tsu(Data_NOE) Address FSMC_AD[15:0] t v(NADV_NE) th(Data_NOE) Data th(AD_NADV) tw(NADV) FSMC_NADV ai14892b Table 70. Symbol Asynchronous multiplexed PSRAM/NOR read timings(1)(2) Min Max Unit 3THCLK-1 3THCLK+1 ns FSMC_NEx low to FSMC_NOE low 2THCLK 2THCLK+0.5 ns FSMC_NOE low time THCLK-1 THCLK+1 ns FSMC_NOE high to FSMC_NE high hold time 0 - ns FSMC_NEx low to FSMC_A valid - 2 ns FSMC_NEx low to FSMC_NADV low 1 2.5 ns THCLK- 1.5 THCLK ns FSMC_AD(adress) valid hold time after FSMC_NADV high) THCLK - ns th(A_NOE) Address hold time after FSMC_NOE high THCLK - ns th(BL_NOE) FSMC_BL time after FSMC_NOE high 0 - ns tv(BL_NE) FSMC_NEx low to FSMC_BL valid - 1 ns tsu(Data_NE) Data to FSMC_NEx high setup time THCLK+ 2 - ns tsu(Data_NOE) Data to FSMC_NOE high setup time THCLK+ 3 - ns Data hold time after FSMC_NEx high 0 - ns th(Data_NOE) Data hold time after FSMC_NOE high 0 - ns tw(NE) tv(NOE_NE) tw(NOE) th(NE_NOE) tv(A_NE) tv(NADV_NE) tw(NADV) th(AD_NADV) th(Data_NE) Parameter FSMC_NE low time FSMC_NADV low time 1. CL = 30 pF. 2. Based on characterization, not tested in production. 124/168 Doc ID 17050 Rev 6 STM32F215xx, STM32F217xx Electrical characteristics Figure 57. Asynchronous multiplexed PSRAM/NOR write waveforms tw(NE) FSMC_NEx FSMC_NOE tv(NWE_NE) tw(NWE) t h(NE_NWE) FSMC_NWE tv(A_NE) FSMC_A[25:16] th(A_NWE) Address tv(BL_NE) th(BL_NWE) FSMC_NBL[1:0] NBL t v(A_NE) t v(Data_NADV) Address FSMC_AD[15:0] t v(NADV_NE) th(Data_NWE) Data th(AD_NADV) tw(NADV) FSMC_NADV ai14891B Table 71. Symbol Asynchronous multiplexed PSRAM/NOR write timings(1)(2) Parameter Min Max Unit tw(NE) FSMC_NE low time 4THCLK-1 4THCLK+1 ns tv(NWE_NE) FSMC_NEx low to FSMC_NWE low THCLK- 1 THCLK ns tw(NWE) FSMC_NWE low tim e 2THCLK 2THCLK+1 ns th(NE_NWE) FSMC_NWE high to FSMC_NE high hold time THCLK- 1 - ns tv(A_NE) FSMC_NEx low to FSMC_A valid - 0 ns tv(NADV_NE) FSMC_NEx low to FSMC_NADV low 1 2 ns tw(NADV) FSMC_NADV low time THCLK- 2 THCLK+ 2 ns th(AD_NADV) FSMC_AD(adress) valid hold time after FSMC_NADV high) THCLK - ns th(A_NWE) Address hold time after FSMC_NWE high THCLK- 0.5 - ns th(BL_NWE) FSMC_BL hold time after FSMC_NWE high THCLK- 1 - ns tv(BL_NE) FSMC_NEx low to FSMC_BL valid - 0.5 ns tv(Data_NADV) FSMC_NADV high to Data valid - THCLK+2 ns th(Data_NWE) Data hold time after FSMC_NWE high THCLK- 0.5 - ns 1. CL = 30 pF. 2. Based on characterization, not tested in production. Doc ID 17050 Rev 6 125/168 Electrical characteristics STM32F215xx, STM32F217xx Synchronous waveforms and timings Figure 58 through Figure 61 represent synchronous waveforms and Table 73 through Table 75 provide the corresponding timings. The results shown in these tables are obtained with the following FSMC configuration: BurstAccessMode = FSMC_BurstAccessMode_Enable; MemoryType = FSMC_MemoryType_CRAM; WriteBurst = FSMC_WriteBurst_Enable; CLKDivision = 1; (0 is not supported, see the STM32F20xxx/21xxx reference manual) DataLatency = 1 for NOR Flash; DataLatency = 0 for PSRAM In all timing tables, the THCLK is the HCLK clock period. Figure 58. Synchronous multiplexed NOR/PSRAM read timings "53452. TW#,+ TW#,+ &3-#?#,+ $ATA LATENCY TD#,+, .%X, T D#,+, .%X( &3-#?.%X TD#,+, .!$6, TD#,+, .!$6( &3-#?.!$6 TD#,+, !)6 TD#,+, !6 &3-#?!;= TD#,+, ./%( TD#,+, ./%, &3-#?./% TD#,+, !$)6 TSU!$6 #,+( TD#,+, !$6 &3-#?!$;= !$;= TH#,+( !$6 TSU!$6 #,+( $ TSU.7!)46 #,+( TH#,+( !$6 $ TH#,+( .7!)46 &3-#?.7!)4 7!)4#&' B 7!)40/, B TSU.7!)46 #,+( TH#,+( .7!)46 &3-#?.7!)4 7!)4#&' B 7!)40/, B TSU.7!)46 #,+( TH#,+( .7!)46 AIG 126/168 Doc ID 17050 Rev 6 STM32F215xx, STM32F217xx Table 72. Electrical characteristics Synchronous multiplexed NOR/PSRAM read timings(1)(2) Symbol tw(CLK) Parameter FSMC_CLK period Min Max Unit 2THCLK - ns td(CLKL-NExL) FSMC_CLK low to FSMC_NEx low (x=0..2) - 0 ns td(CLKL-NExH) FSMC_CLK low to FSMC_NEx high (x= 0...2) 1 - ns td(CLKL-NADVL) FSMC_CLK low to FSMC_NADV low - 1.5 ns td(CLKL-NADVH) FSMC_CLK low to FSMC_NADV high 2.5 - ns td(CLKL-AV) FSMC_CLK low to FSMC_Ax valid (x=16...25) - 0 ns td(CLKL-AIV) FSMC_CLK low to FSMC_Ax invalid (x=16...25) 0 - ns td(CLKL-NOEL) FSMC_CLK low to FSMC_NOE low - 1 ns td(CLKL-NOEH) FSMC_CLK low to FSMC_NOE high 1 - ns td(CLKL-ADV) FSMC_CLK low to FSMC_AD[15:0] valid - 3 ns td(CLKL-ADIV) FSMC_CLK low to FSMC_AD[15:0] invalid 0 - ns tsu(ADV-CLKH) FSMC_A/D[15:0] valid data before FSMC_CLK high 5 - ns th(CLKH-ADV) FSMC_A/D[15:0] valid data after FSMC_CLK high 0 - ns 1. CL = 30 pF. 2. Based on characterization, not tested in production. Doc ID 17050 Rev 6 127/168 Electrical characteristics STM32F215xx, STM32F217xx Figure 59. Synchronous multiplexed PSRAM write timings "53452. TW#,+ TW#,+ &3-#?#,+ $ATA LATENCY TD#,+, .%X, TD#,+, .%X( &3-#?.%X TD#,+, .!$6, TD#,+, .!$6( &3-#?.!$6 TD#,+, !6 TD#,+, !)6 &3-#?!;= TD#,+, .7%, TD#,+, .7%( &3-#?.7% TD#,+, !$)6 TD#,+, $ATA TD#,+, $ATA TD#,+, !$6 &3-#?!$;= !$;= $ $ &3-#?.7!)4 7!)4#&' B 7!)40/, B TSU.7!)46 #,+( TH#,+( .7!)46 TD#,+, .",( &3-#?.", AIG Table 73. Synchronous multiplexed PSRAM write timings(1)(2) Symbol tw(CLK) Parameter FSMC_CLK period Max Unit 2THCLK- 1 - ns td(CLKL-NExL) FSMC_CLK low to FSMC_NEx low (x=0..2) - 0 ns td(CLKL-NExH) FSMC_CLK low to FSMC_NEx high (x= 0...2) 2 - ns td(CLKL-NADVL) FSMC_CLK low to FSMC_NADV low - 2 ns td(CLKL-NADVH) FSMC_CLK low to FSMC_NADV high 3 - ns td(CLKL-AV) FSMC_CLK low to FSMC_Ax valid (x=16...25) - 0 ns td(CLKL-AIV) FSMC_CLK low to FSMC_Ax invalid (x=16...25) 7 - ns td(CLKL-NWEL) FSMC_CLK low to FSMC_NWE low - 1 ns td(CLKL-NWEH) FSMC_CLK low to FSMC_NWE high 0 - ns td(CLKL-ADIV) FSMC_CLK low to FSMC_AD[15:0] invalid 0 - ns td(CLKL-DATA) FSMC_A/D[15:0] valid data after FSMC_CLK low - 2 ns td(CLKL-NBLH) FSMC_CLK low to FSMC_NBL high 0.5 - ns 1. CL = 30 pF. 2. Based on characterization, not tested in production. 128/168 Min Doc ID 17050 Rev 6 STM32F215xx, STM32F217xx Electrical characteristics Figure 60. Synchronous non-multiplexed NOR/PSRAM read timings "53452. TW#,+ TW#,+ &3-#?#,+ TD#,+, .%X, TD#,+, .%X( $ATA LATENCY &3-#?.%X TD#,+, .!$6, TD#,+, .!$6( &3-#?.!$6 TD#,+, !)6 TD#,+, !6 &3-#?!;= TD#,+, ./%, TD#,+, ./%( &3-#?./% TSU$6 #,+( TH#,+( $6 TSU$6 #,+( $ &3-#?$;= TSU.7!)46 #,+( TH#,+( $6 $ TH#,+( .7!)46 &3-#?.7!)4 7!)4#&' B 7!)40/, B TSU.7!)46 #,+( T H#,+( .7!)46 &3-#?.7!)4 7!)4#&' B 7!)40/, B TSU.7!)46 #,+( TH#,+( .7!)46 AIF Table 74. Synchronous non-multiplexed NOR/PSRAM read timings Symbol Parameter (1)(2) Min Max Unit 2THCLK - ns tw(CLK) FSMC_CLK period td(CLKL-NExL) FSMC_CLK low to FSMC_NEx low (x=0..2) - 0 ns td(CLKL-NExH) FSMC_CLK low to FSMC_NEx high (x= 0...2) 1 - ns td(CLKL-NADVL) FSMC_CLK low to FSMC_NADV low - 2.5 ns td(CLKL-NADVH) FSMC_CLK low to FSMC_NADV high 4 - ns td(CLKL-AV) FSMC_CLK low to FSMC_Ax valid (x=16...25) - 0 ns td(CLKL-AIV) FSMC_CLK low to FSMC_Ax invalid (x=16...25) 3 - ns td(CLKL-NOEL) FSMC_CLK low to FSMC_NOE low - 1 ns td(CLKL-NOEH) FSMC_CLK low to FSMC_NOE high 1.5 - ns tsu(DV-CLKH) FSMC_D[15:0] valid data before FSMC_CLK high 8 - ns th(CLKH-DV) FSMC_D[15:0] valid data after FSMC_CLK high 3.5 - ns 1. CL = 30 pF. 2. Based on characterization, not tested in production. Doc ID 17050 Rev 6 129/168 Electrical characteristics STM32F215xx, STM32F217xx Figure 61. Synchronous non-multiplexed PSRAM write timings TW#,+ "53452. TW#,+ &3-#?#,+ TD#,+, .%X, TD#,+, .%X( $ATA LATENCY &3-#?.%X TD#,+, .!$6, TD#,+, .!$6( &3-#?.!$6 TD#,+, !6 TD#,+, !)6 &3-#?!;= TD#,+, .7%, TD#,+, .7%( &3-#?.7% TD#,+, $ATA &3-#?$;= TD#,+, $ATA $ $ &3-#?.7!)4 7!)4#&' B 7!)40/, B TSU.7!)46 #,+( TD#,+, .",( TH#,+( .7!)46 &3-#?.", AIG Table 75. Synchronous non-multiplexed PSRAM write timings(1)(2) Symbol Min Max Unit 2THCLK- 1 - ns - 1 ns td(CLKL-NExH) FSMC_CLK low to FSMC_NEx high (x= 0...2) 1 - ns td(CLKL-NADVL) FSMC_CLK low to FSMC_NADV low - 5 ns FSMC_CLK low to FSMC_NADV high 6 - ns td(CLKL-AV) FSMC_CLK low to FSMC_Ax valid (x=16...25) - 0 ns td(CLKL-AIV) FSMC_CLK low to FSMC_Ax invalid (x=16...25) 8 - ns td(CLKL-NWEL) FSMC_CLK low to FSMC_NWE low - 1 ns td(CLKL-NWEH) FSMC_CLK low to FSMC_NWE high 1 - ns - 2 ns 2 - ns tw(CLK) td(CLKL-NExL) td(CLKL- Parameter FSMC_CLK period FSMC_CLK low to FSMC_NEx low (x=0..2) NADVH) td(CLKL-Data) FSMC_D[15:0] valid data after FSMC_CLK low td(CLKL-NBLH) FSMC_CLK low to FSMC_NBL high 1. CL = 30 pF. 2. Based on characterization, not tested in production. 130/168 Doc ID 17050 Rev 6 STM32F215xx, STM32F217xx Electrical characteristics PC Card/CompactFlash controller waveforms and timings Figure 62 through Figure 67 represent synchronous waveforms together with Table 76 and Table 77 provides the corresponding timings. The results shown in this table are obtained with the following FSMC configuration: COM.FSMC_SetupTime = 0x04; COM.FSMC_WaitSetupTime = 0x07; COM.FSMC_HoldSetupTime = 0x04; COM.FSMC_HiZSetupTime = 0x00; ATT.FSMC_SetupTime = 0x04; ATT.FSMC_WaitSetupTime = 0x07; ATT.FSMC_HoldSetupTime = 0x04; ATT.FSMC_HiZSetupTime = 0x00; IO.FSMC_SetupTime = 0x04; IO.FSMC_WaitSetupTime = 0x07; IO.FSMC_HoldSetupTime = 0x04; IO.FSMC_HiZSetupTime = 0x00; TCLRSetupTime = 0; TARSetupTime = 0; In all timing tables, the THCLK is the HCLK clock period. Figure 62. PC Card/CompactFlash controller waveforms for common memory read access FSMC_NCE4_2(1) FSMC_NCE4_1 th(NCEx-AI) tv(NCEx-A) FSMC_A[10:0] th(NCEx-NREG) th(NCEx-NIORD) th(NCEx-NIOWR) td(NREG-NCEx) td(NIORD-NCEx) FSMC_NREG FSMC_NIOWR FSMC_NIORD FSMC_NWE td(NCE4_1-NOE) FSMC_NOE tw(NOE) tsu(D-NOE) th(NOE-D) FSMC_D[15:0] ai14895b 1. FSMC_NCE4_2 remains high (inactive during 8-bit access. Doc ID 17050 Rev 6 131/168 Electrical characteristics STM32F215xx, STM32F217xx Figure 63. PC Card/CompactFlash controller waveforms for common memory write access FSMC_NCE4_1 FSMC_NCE4_2 High tv(NCE4_1-A) th(NCE4_1-AI) FSMC_A[10:0] th(NCE4_1-NREG) th(NCE4_1-NIORD) th(NCE4_1-NIOWR) td(NREG-NCE4_1) td(NIORD-NCE4_1) FSMC_NREG FSMC_NIOWR FSMC_NIORD td(NCE4_1-NWE) tw(NWE) td(NWE-NCE4_1) FSMC_NWE FSMC_NOE MEMxHIZ =1 td(D-NWE) tv(NWE-D) th(NWE-D) FSMC_D[15:0] ai14896b 132/168 Doc ID 17050 Rev 6 STM32F215xx, STM32F217xx Electrical characteristics Figure 64. PC Card/CompactFlash controller waveforms for attribute memory read access FSMC_NCE4_1 tv(NCE4_1-A) FSMC_NCE4_2 th(NCE4_1-AI) High FSMC_A[10:0] FSMC_NIOWR FSMC_NIORD td(NREG-NCE4_1) th(NCE4_1-NREG) FSMC_NREG FSMC_NWE td(NCE4_1-NOE) tw(NOE) td(NOE-NCE4_1) FSMC_NOE tsu(D-NOE) th(NOE-D) FSMC_D[15:0](1) ai14897b 1. Only data bits 0...7 are read (bits 8...15 are disregarded). Doc ID 17050 Rev 6 133/168 Electrical characteristics STM32F215xx, STM32F217xx Figure 65. PC Card/CompactFlash controller waveforms for attribute memory write access FSMC_NCE4_1 FSMC_NCE4_2 High tv(NCE4_1-A) th(NCE4_1-AI) FSMC_A[10:0] FSMC_NIOWR FSMC_NIORD td(NREG-NCE4_1) th(NCE4_1-NREG) FSMC_NREG td(NCE4_1-NWE) tw(NWE) FSMC_NWE td(NWE-NCE4_1) FSMC_NOE tv(NWE-D) FSMC_D[7:0](1) ai14898b 1. Only data bits 0...7 are driven (bits 8...15 remains Hi-Z). Figure 66. PC Card/CompactFlash controller waveforms for I/O space read access FSMC_NCE4_1 FSMC_NCE4_2 th(NCE4_1-AI) tv(NCEx-A) FSMC_A[10:0] FSMC_NREG FSMC_NWE FSMC_NOE FSMC_NIOWR tw(NIORD) td(NIORD-NCE4_1) FSMC_NIORD tsu(D-NIORD) td(NIORD-D) FSMC_D[15:0] ai14899B 134/168 Doc ID 17050 Rev 6 STM32F215xx, STM32F217xx Electrical characteristics Figure 67. PC Card/CompactFlash controller waveforms for I/O space write access &3-#?.#%? &3-#?.#%? TV.#%X ! TH.#%? !) &3-#?!;= &3-#?.2%' &3-#?.7% &3-#?./% &3-#?.)/2$ TD.#%? .)/72 TW.)/72 &3-#?.)/72 !44X(): TV.)/72 $ TH.)/72 $ &3-#?$;= AIC Table 76. Switching characteristics for PC Card/CF read and write cycles in attribute/common space(1)(2) Symbol Parameter Min Max Unit tv(NCEx-A) FSMC_Ncex low to FSMC_Ay valid - 0 ns th(NCEx_AI) FSMC_NCEx high to FSMC_Ax invalid 4 - ns - 3.5 ns THCLK+ 4 - ns td(NREG-NCEx) FSMC_NCEx low to FSMC_NREG valid th(NCEx-NREG) FSMC_NCEx high to FSMC_NREG invalid td(NCEx-NWE) FSMC_NCEx low to FSMC_NWE low - 5THCLK+ 1 ns td(NCEx-NOE) FSMC_NCEx low to FSMC_NOE low - 5THCLK ns FSMC_NOE low width 8THCLK- 0.5 8THCLK+ 1 ns FSMC_NOE high to FSMC_NCEx high 5THCLK+ 2.5 - ns tw(NOE) td(NOE_NCEx) tsu (D-NOE) FSMC_D[15:0] valid data before FSMC_NOE high 4 - ns th (N0E-D) FSMC_N0E high to FSMC_D[15:0] invalid 2 - ns 8THCLK- 1 8THCLK+ 4 ns tw(NWE) FSMC_NWE low width td(NWE_NCEx) FSMC_NWE high to FSMC_NCEx high td(NCEx-NWE) FSMC_NCEx low to FSMC_NWE low - 5HCLK+ 1 ns FSMC_NWE low to FSMC_D[15:0] valid - 0 ns tv (NWE-D) 5THCLK+ 1.5 ns th (NWE-D) FSMC_NWE high to FSMC_D[15:0] invalid 8 THCLK - ns td (D-NWE) FSMC_D[15:0] valid before FSMC_NWE high 13THCLK - ns 1. CL = 30 pF. 2. Based on characterization, not tested in production. Doc ID 17050 Rev 6 135/168 Electrical characteristics Table 77. STM32F215xx, STM32F217xx Switching characteristics for PC Card/CF read and write cycles in I/O space(1)(2) Symbol Parameter tw(NIOWR) FSMC_NIOWR low width tv(NIOWR-D) FSMC_NIOWR low to FSMC_D[15:0] valid th(NIOWR-D) FSMC_NIOWR high to FSMC_D[15:0] invalid Min Max Unit 8THCLK - 0.5 - ns - 5THCLK- 1 ns 8THCLK- 3 - ns td(NCE4_1-NIOWR) FSMC_NCE4_1 low to FSMC_NIOWR valid - 5THCLK+ 1.5 ns th(NCEx-NIOWR) FSMC_NCEx high to FSMC_NIOWR invalid 5THCLK - ns td(NIORD-NCEx) FSMC_NCEx low to FSMC_NIORD valid - 5THCLK+ 1 ns th(NCEx-NIORD) FSMC_NCEx high to FSMC_NIORD) valid 5THCLK- 0.5 - ns 8THCLK+ 1 - ns FSMC_NIORD low width tw(NIORD) tsu(D-NIORD) FSMC_D[15:0] valid before FSMC_NIORD high td(NIORD-D) FSMC_D[15:0] valid after FSMC_NIORD high 9.5 ns 0 ns 1. CL = 30 pF. 2. Based on characterization, not tested in production. NAND controller waveforms and timings Figure 68 through Figure 71 represent synchronous waveforms, together with Table 78 and Table 79 provides the corresponding timings. The results shown in this table are obtained with the following FSMC configuration: COM.FSMC_SetupTime = 0x01; COM.FSMC_WaitSetupTime = 0x03; COM.FSMC_HoldSetupTime = 0x02; COM.FSMC_HiZSetupTime = 0x01; ATT.FSMC_SetupTime = 0x01; ATT.FSMC_WaitSetupTime = 0x03; ATT.FSMC_HoldSetupTime = 0x02; ATT.FSMC_HiZSetupTime = 0x01; Bank = FSMC_Bank_NAND; MemoryDataWidth = FSMC_MemoryDataWidth_16b; ECC = FSMC_ECC_Enable; ECCPageSize = FSMC_ECCPageSize_512Bytes; TCLRSetupTime = 0; TARSetupTime = 0; In all timing tables, the THCLK is the HCLK clock period. 136/168 Doc ID 17050 Rev 6 STM32F215xx, STM32F217xx Electrical characteristics Figure 68. NAND controller waveforms for read access &3-#?.#%X !,% &3-#?! #,% &3-#?! &3-#?.7% TD!,% ./% TH./% !,% &3-#?./% .2% TSU$ ./% TH./% $ &3-#?$;= AIC Figure 69. NAND controller waveforms for write access &3-#?.#%X !,% &3-#?! #,% &3-#?! TD!,% .7% TH.7% !,% &3-#?.7% &3-#?./% .2% TV.7% $ TH.7% $ &3-#?$;= AIC Doc ID 17050 Rev 6 137/168 Electrical characteristics STM32F215xx, STM32F217xx Figure 70. NAND controller waveforms for common memory read access &3-#?.#%X !,% &3-#?! #,% &3-#?! TD!,% ./% TH./% !,% &3-#?.7% TW./% &3-#?./% TSU$ ./% TH./% $ &3-#?$;= AIC Figure 71. NAND controller waveforms for common memory write access &3-#?.#%X !,% &3-#?! #,% &3-#?! TD!,% ./% TW.7% TH./% !,% &3-#?.7% &3-#?./% TD$ .7% TV.7% $ TH.7% $ &3-#?$;= AIC Table 78. Symbol tw(N0E) Switching characteristics for NAND Flash read cycles(1)(2) Parameter FSMC_NOE low width Max Unit 4THCLK- 1 4THCLK+ 2 ns tsu(D-NOE) FSMC_D[15-0] valid data before FSMC_NOE high 9 - ns th(NOE-D) FSMC_D[15-0] valid data after FSMC_NOE high 3 - ns td(ALE-NOE) FSMC_ALE valid before FSMC_NOE low - 3THCLK ns th(NOE-ALE) FSMC_NWE high to FSMC_ALE invalid 3THCLK+ 2 - ns 1. CL = 30 pF. 2. Based on characterization, not tested in production. 138/168 Min Doc ID 17050 Rev 6 STM32F215xx, STM32F217xx Table 79. Electrical characteristics Switching characteristics for NAND Flash write cycles(1)(2) Symbol tw(NWE) Parameter FSMC_NWE low width Min Max Unit 4THCLK- 1 4THCLK+ 3 ns - 0 ns tv(NWE-D) FSMC_NWE low to FSMC_D[15-0] valid th(NWE-D) FSMC_NWE high to FSMC_D[15-0] invalid 3THCLK - ns td(D-NWE) FSMC_D[15-0] valid before FSMC_NWE high 5THCLK - ns - 3THCLK+ 2 ns 3THCLK- 2 - ns td(ALE-NWE) FSMC_ALE valid before FSMC_NWE low th(NWE-ALE) FSMC_NWE high to FSMC_ALE invalid 1. CL = 30 pF. 2. Based on characterization, not tested in production. 5.3.26 Camera interface (DCMI) timing specifications Table 80. Symbol DCMI characteristics Parameter Frequency ratio DCMI_PIXCLK/fHCLK 5.3.27 Conditions Min DCMI_PIXCLK= 48 MHz Max Unit 0.4 SD/SDIO MMC card host interface (SDIO) characteristics Unless otherwise specified, the parameters given in Table 81 are derived from tests performed under ambient temperature, fPCLKx frequency and VDD supply voltage conditions summarized in Table 10. Refer to Section 5.3.16: I/O port characteristics for more details on the input/output alternate function characteristics (D[7:0], CMD, CK). Figure 72. SDIO high-speed mode tf tr tC tW(CKH) tW(CKL) CK tOV tOH D, CMD (output) tISU tIH D, CMD (input) ai14887 Doc ID 17050 Rev 6 139/168 Electrical characteristics STM32F215xx, STM32F217xx Figure 73. SD default mode CK tOVD tOHD D, CMD (output) ai14888 Table 81. Symbol SD / MMC characteristics Parameter Conditions Min Max Unit fPP Clock frequency in data transfer mode CL 30 pF 0 48 MHz - SDIO_CK/fPCLK2 frequency ratio - - 8/3 - tW(CKL) Clock low time, fPP = 16 MHz CL 30 pF 32 tW(CKH) Clock high time, fPP = 16 MHz CL 30 pF 31 tr Clock rise time CL 30 pF 3.5 tf Clock fall time CL 30 pF 5 ns CMD, D inputs (referenced to CK) tISU Input setup time CL 30 pF 2 tIH Input hold time CL 30 pF 0 ns CMD, D outputs (referenced to CK) in MMC and SD HS mode tOV Output valid time CL 30 pF tOH Output hold time CL 30 pF 6 ns 0.3 CMD, D outputs (referenced to CK) in SD default mode(1) tOVD Output valid default time CL 30 pF tOHD Output hold default time CL 30 pF 7 ns 0.5 1. Refer to SDIO_CLKCR, the SDI clock control register to control the CK output. 5.3.28 RTC characteristics Table 82. Symbol - 140/168 RTC characteristics Parameter fPCLK1/RTCCLK frequency ratio Conditions Any read/write operation from/to an RTC register Doc ID 17050 Rev 6 Min Max Unit 4 - - STM32F215xx, STM32F217xx Package characteristics 6 Package characteristics 6.1 Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK(R) packages, depending on their level of environmental compliance. ECOPACK(R) specifications, grade definitions and product status are available at: www.st.com. ECOPACK(R) is an ST trademark. Doc ID 17050 Rev 6 141/168 Package characteristics STM32F215xx, STM32F217xx Figure 75. Recommended footprint(1)(2) Figure 74. LQFP64 - 10 x 10 mm 64 pin low-profile quad flat package outline(1) A 48 33 A2 0.3 A1 E 49 b E1 12.7 32 0.5 10.3 e 10.3 64 17 1.2 1 D1 c 7.8 L1 D 16 12.7 L ai14398b ai14909 1. Drawing is not to scale. 2. Dimensions are in millimeters. Table 83. LQFP64 - 10 x 10 mm 64 pin low-profile quad flat package mechanical data inches(1) millimeters Symbol Min Typ A Max Min Typ 1.600 A1 0.050 A2 1.350 b 0.170 c 0.090 Max 0.0630 0.150 0.0020 0.0059 1.400 1.450 0.0531 0.0551 0.0571 0.220 0.270 0.0067 0.0087 0.0106 0.200 0.0035 0.0079 D 12.000 0.4724 D1 10.000 0.3937 E 12.000 0.4724 E1 10.000 0.3937 e 0.500 0.0197 0 3.5 7 0 3.5 7 L 0.450 0.600 0.750 0.0177 0.0236 0.0295 L1 1.000 0.0394 Number of pins N 64 1. Values in inches are converted from mm and rounded to 4 decimal digits. 142/168 Doc ID 17050 Rev 6 STM32F215xx, STM32F217xx Package characteristics Figure 76. LQFP100, 14 x 14 mm 100-pin low-profile quad flat package outline(1) Figure 77. Recommended footprint(1)(2) 0.25 mm 0.10 inch GAGE PLANE k D L D1 75 51 L1 D3 51 75 76 C 76 50 0.5 50 0.3 16.7 b 14.3 E3 E1 E 100 100 26 1.2 26 Pin 1 1 identification 25 1 C ccc 25 12.3 e A1 16.7 A2 ai14906 A SEATING PLANE C 1L_ME 1. Drawing is not to scale. 2. Dimensions are in millimeters. Table 84. LQPF100 - 14 x 14 mm 100-pin low-profile quad flat package mechanical data inches(1) millimeters Symbol Min Typ A Max Min Typ 1.600 A1 0.050 A2 1.350 b 0.170 c 0.090 D 15.800 D1 13.800 D3 Max 0.0630 0.150 0.0020 1.400 1.450 0.0531 0.0551 0.0571 0.220 0.270 0.0067 0.0087 0.0106 0.200 0.0035 16.000 16.200 0.6220 0.6299 0.6378 14.000 14.200 0.5433 0.5512 0.5591 12.000 0.0059 0.0079 0.4724 E 15.80v 16.000 16.200 0.6220 0.6299 0.6378 E1 13.800 14.000 14.200 0.5433 0.5512 0.5591 E3 12.000 e L 0.500 0.450 L1 k ccc 0.4724 0.600 0.0197 0.750 0.0177 1.000 0 3.5 0.0236 0.0295 0.0394 7 0.080 0 3.5 7 0.0031 1. Values in inches are converted from mm and rounded to 4 decimal digits. Doc ID 17050 Rev 6 143/168 Package characteristics STM32F215xx, STM32F217xx Figure 78. LQFP144, 20 x 20 mm, 144-pin low-profile quad flat package outline(1) Figure 79. Recommended footprint(1)(2) Seating plane C A A2 A1 c b ccc 0.25 mm gage plane C D k 108 109 73 1.35 72 0.35 D1 A1 D3 108 L 73 0.5 L1 72 109 17.85 19.9 E1 E 22.6 144 37 E3 1 36 19.9 22.6 a 144 Pin 1 identification 37 36 1 e ME_1A 1. Drawing is not to scale. 2. Dimensions are in millimeters. Table 85. LQFP144 20 x 20 mm, 144-pin low-profile quad flat package mechanical data inches(1) millimeters Symbol Min Typ A Max Min Typ 1.600 A1 0.050 A2 1.350 b 0.170 c 0.090 D 21.800 D1 Max 0.0630 0.150 0.0020 1.400 1.450 0.0531 0.0551 0.0571 0.220 0.270 0.0067 0.0087 0.0106 0.200 0.0035 22.000 22.200 0.8583 0.8661 0.874 19.800 20.000 20.200 0.7795 0.7874 0.7953 E 21.800 22.000 22.200 0.8583 0.8661 0.8740 E1 19.800 20.000 20.200 0.7795 0.7874 0.7953 D3 17.500 0.0059 0.0079 0.689 E3 17.500 0.6890 e 0.500 0.0197 L 0.450 L1 k ccc 0.600 0.750 1.000 0 3.5 0.0236 0.0295 0.0394 7 0.080 0 3.5 0.0031 1. Values in inches are converted from mm and rounded to 4 decimal digits. 144/168 0.0177 Doc ID 17050 Rev 6 7 STM32F215xx, STM32F217xx Package characteristics Figure 80. LQFP176 - Low profile quad flat package 24 x 24 x 1.4 mm, package outline C Seating plane 0.25 mm gauge plane A A2 k c A1 ccc C A1 HD L D L1 ZD ZE 89 132 88 133 b E 176 Pin 1 identification HE 45 44 1 e 1T_ME 1. Drawing is not to scale. Table 86. LQFP176 - Low profile quad flat package 24 x 24 x 1.4 mm package mechanical data inches(1) millimeters Symbol Min Typ A Max Min Typ 1.600 Max 0.0630 A1 0.050 0.150 0.0020 0.0059 A2 1.350 1.450 0.0531 0.0571 b 0.170 0.270 0.0067 0.0106 c 0.090 0.200 0.0035 0.0079 D 23.900 24.100 0.9409 0.9488 E 23.900 24.100 0.9409 0.9488 e 0.500 0.0197 HD 25.900 26.100 1.0197 1.0276 HE 25.900 26.100 1.0197 1.0276 0.450 0.750 0.0177 0.0295 (2) L L1 1.000 0.0394 ZD 1.250 0.0492 ZE 1.250 0.0492 Doc ID 17050 Rev 6 145/168 Package characteristics Table 86. k ccc STM32F215xx, STM32F217xx LQFP176 - Low profile quad flat package 24 x 24 x 1.4 mm package mechanical data 0 7 0.080 7 0.0031 1. Values in inches are converted from mm and rounded to 4 decimal digits. 2. L dimension is measured at gauge plane at 0.25 mm above the seating plane. 146/168 0 Doc ID 17050 Rev 6 STM32F215xx, STM32F217xx Package characteristics Figure 81. UFBGA176+25 - ultra thin fine pitch ball grid array 10 x 10 x 0.6 mm, package outline C Seating plane A2 ddd A4 C A A3 A1 A D B Ball A1 e F A F E e R 15 Ob 1 (176 balls) O eee M C A O fff M B A0E7_ME C 1. Drawing is not to scale. Table 87. UFBGA176+25 - ultra thin fine pitch ball grid array 10 x 10 x 0.6 mm mechanical data inches(1) millimeters Symbol Min Typ Max Min Typ Max A 0.460 0.530 0.600 0.0181 0.0209 0.0236 A1 0.050 0.080 0.110 0.002 0.0031 0.0043 A2 0.400 0.450 0.500 0.0157 0.0177 0.0197 A3 0.130 0.0051 A4 0.270 0.320 0.370 0.0106 0.0126 0.0146 b 0.230 0.280 0.330 0.0091 0.0110 0.0130 D 9.950 10.000 10.050 0.3740 0.3937 0.3957 E 9.950 10.000 10.050 0.3740 0.3937 0.3957 e 0.600 0.650 0.700 0.0236 0.0256 0.0276 F 0.400 0.450 0.500 0.0157 0.0177 0.0197 Doc ID 17050 Rev 6 147/168 Package characteristics Table 87. STM32F215xx, STM32F217xx UFBGA176+25 - ultra thin fine pitch ball grid array 10 x 10 x 0.6 mm mechanical data ddd 0.080 0.0031 eee 0.150 0.0059 fff 0.080 0.0031 1. Values in inches are converted from mm and rounded to 4 decimal digits. 148/168 Doc ID 17050 Rev 6 STM32F215xx, STM32F217xx 6.2 Package characteristics Thermal characteristics The maximum chip-junction temperature, TJ max, in degrees Celsius, may be calculated using the following equation: TJ max = TA max + (PD max x JA) Where: TA max is the maximum ambient temperature in C, JA is the package junction-to-ambient thermal resistance, in C/W, PD max is the sum of PINT max and PI/O max (PD max = PINT max + PI/Omax), PINT max is the product of IDD and VDD, expressed in Watts. This is the maximum chip internal power. PI/O max represents the maximum power dissipation on output pins where: PI/O max = (VOL x IOL) + ((VDD - VOH) x IOH), taking into account the actual VOL / IOL and VOH / IOH of the I/Os at low and high level in the application. Table 88. Package thermal characteristics Symbol JA Parameter Value Thermal resistance junction-ambient LQFP 64 - 10 x 10 mm / 0.5 mm pitch 45 Thermal resistance junction-ambient LQFP100 - 14 x 14 mm / 0.5 mm pitch 46 Thermal resistance junction-ambient LQFP144 - 20 x 20 mm / 0.5 mm pitch 40 Thermal resistance junction-ambient LQFP176 - 24 x 24 mm / 0.5 mm pitch 38 Thermal resistance junction-ambient UFBGA176 - 10x 10 mm / 0.5 mm pitch 39 Unit C/W Reference document JESD51-2 Integrated Circuits Thermal Test Method Environment Conditions - Natural Convection (Still Air). Available from www.jedec.org. Doc ID 17050 Rev 6 149/168 Part numbering 7 STM32F215xx, STM32F217xx Part numbering Table 89. Ordering information scheme Example: STM32 F 215 R E T 6 V xxx Device family STM32 = ARM-based 32-bit microcontroller Product type F = general-purpose Device subfamily 215 = STM32F21x, connectivity, USB OTG FS/HS, cryptographic acceleration 217= STM32F21x, connectivity, USB OTG FS/HS, camera interface, cryptographic acceleration, Ethernet Pin count R = 64 pins V = 100 pins Z = 144 pins I = 176 pins Flash memory size E = 512 Kbytes of Flash memory G = 1024 Kbytes of Flash memory Package T = LQFP H = UFBGA Temperature range 6 = Industrial temperature range, -40 to 85 C. 7 = Industrial temperature range, -40 to 105 C. Software option Internal code or Blank Options xxx = programmed parts TR = tape and reel For a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact your nearest ST sales office. 150/168 Doc ID 17050 Rev 6 STM32F215xx, STM32F217xx Appendix A A.1 Application block diagrams Application block diagrams Main applications versus package Table 90 gives examples of configurations for each package. Table 90. Main applications versus package for STM32F2xxx microcontrollers(1) 64 pins(2) 100 pins 144 pins 176 pins Config Config Config Config Config Config Config Config Config Config Config Config Config 1 2 3 1 2 3 4 1 2 3 4 1 2 OTG FS - - - X X X - X - X - X - FS - - - X X X X X X X X X - HS ULPI X - X X - - - X X - - X X USB OTG OTG HS FS X X X X - - - X X - - X X FS X X X X X X X X X X X X X Ethernet MII - - - - - X X - - X X X X - - - - X X X X X X X X X - X - - X X X X X X X X X SDIO X X - X X X 8-bit Data - - - X X X 10-bit Data - - - X X X 12-bit Data - - - X X X 14-bit Data - - - - - - - - X - X X X NOR/ RAM Muxed - - - X X X X X X X X X X NOR/ RAM - - - X X X X X X NAND - - - X X X*22 X*19 X X*19 X*22 X*19 X*22 X*22 CF - - - - - - - X X X X X X - X X - X X X - - X X - X USB OTG FS(3) (3) RMII SPI/I2S2 SPI/I2S3 SDIO DCMI(3) FSMC CAN X SDIO or DCMI SDIO or DCMI SDIO or DCMI X X X SDIO or DCMI X X X SDIO or DCMI X 1. X*y: FSMC address limited to "y". 2. Not available on STM32F2x7xx. 3. Not available on STM32F2x5xx. Doc ID 17050 Rev 6 151/168 Application block diagrams A.2 STM32F215xx, STM32F217xx Application example with regulator OFF Figure 82. Regulator OFF/internal reset ON 0OWER DOWN RESET RISEN AFTER 6#!0?6#!0? STABILIZATION 0OWER DOWN RESET RISEN BEFORE 6#!0?6#!0? STABILIZATION 6#!0? MONITORING %XT RESET CONTROLLER ACTIVE WHEN 6 #!0? 6 !PPLICATION RESET SIGNAL OPTIONAL 6$$ TO 6 0! 6$$ 6$$ TO 6 .234 !PPLICATION RESET SIGNAL OPTIONAL 0! 6$$ 2%'/&& .234 2%'/&& 6 6 6#!0? 6#!0? 6#!0? 6#!0? )22/&& AI 1. This mode is available only on UFBGA176. A.3 USB OTG full speed (FS) interface solutions Figure 83. USB OTG FS (full speed) device-only connection 6$$ 6 TO 6$$ 6OLATGE REGULATOR 6"53 0! /3#?). 0! 0! $$0 633 /3#?/54 53" 3TD " CONNECTOR 34-&XXX AI 1. The same application can be developed using the OTG HS in FS mode to achieve enhanced performance thanks to the large Rx/Tx FIFO and to a dedicated DMA controller. 152/168 Doc ID 17050 Rev 6 STM32F215xx, STM32F217xx Application block diagrams Figure 84. USB OTG FS (full speed) host-only connection 6$$ %. '0)/ '0)/ )21 /VERCURRENT #URRENT LIMITER POWER SWITCH 6 0WR 6"53 0! $- 0! /3#?). $0 0! 633 /3#?/54 53" 3TD ! CONNECTOR 34-&XX AIC 1. The current limiter is required only if the application has to support a VBUS powered device. A basic power switch can be used if 5 V are available on the application board. 2. The same application can be developed using the OTG HS in FS mode to achieve enhanced performance thanks to the large Rx/Tx FIFO and to a dedicated DMA controller. Figure 85. OTG FS (full speed) connection dual-role with internal PHY 6$$ 6 TO 6$$ VOLTAGE REGULATOR 6$$ '0)/ )21 %. /VERCURRENT #URRENT LIMITER POWER SWITCH 6 0WR 34-&XXX 0! 0! /3#?). 0! 6"53 $$0 /3#?/54 0! )$ 633 53"MICRO !" CONNECTOR '0)/ AIC 1. External voltage regulator only needed when building a VBUS powered device. 2. The current limiter is required only if the application has to support a VBUS powered device. A basic power switch can be used if 5 V are available on the application board. 3. The ID pin is required in dual role only. 4. The same application can be developed using the OTG HS in FS mode to achieve enhanced performance thanks to the large Rx/Tx FIFO and to a dedicated DMA controller. Doc ID 17050 Rev 6 153/168 Application block diagrams A.4 STM32F215xx, STM32F217xx USB OTG high speed (HS) interface solutions Figure 86. OTG HS (high speed) device connection, host and dual-role in high-speed mode with external PHY 34-&XXX &3 0(9 53" (3 /4' #TRL $0 $- NOT CONNECTED $0 5,0)?#,+ $- 5,0)?$;= 5,0) )$ 5,0)?$)2 6"53 5,0)?340 53" CONNECTOR 633 5,0)?.84 (IGH SPEED /4' 0(9 0,, 84 OR -(Z 84 -#/ OR -#/ 8) AIC 1. It is possible to use MCO1 or MCO2 to save a crystal. It is however not mandatory to clock the STM32F21x with a 24 or 26 MHz crystal when using USB HS. The above figure only shows an example of a possible connection. 2. The ID pin is required in dual role only. 154/168 Doc ID 17050 Rev 6 STM32F215xx, STM32F217xx A.5 Application block diagrams Complete audio player solutions Two solutions are offered, illustrated in Figure 87 and Figure 88. Figure 87 shows storage media to audio DAC/amplifier streaming using a software Codec. This solution implements an audio crystal to provide audio class I2S accuracy on the master clock (0.5% error maximum, see the Serial peripheral interface section in the reference manual for details). Figure 87. Complete audio player solution 1 XTAL 25 MHz or 14.7456 MHz Cortex-M3 core up to 120 MHz SPI LCD touch screen GPIO Control buttons Program memory OTG (host mode) + PHY USB Mass-storage device File System DAC + Audio ampli I2S Audio CODEC User application MMC/ SDCard SPI ai16039b Figure 88 shows storage media to audio Codec/amplifier streaming with SOF synchronization of input/output audio streaming using a hardware Codec. Figure 88. Complete audio player solution 2 XTAL 25 MHz or 14.7456 MHz Cortex-M3 core up to 120 MHz SPI/ FSMC LCD touch screen GPIO Control buttons Program memory USB Mass-storage device SOF OTG + PHY File System I2S User application MMC/ SDCard SPI Audio PLL +DAC Audio ampli SOF synchronization of input/output audio streaming ai16040b 1. SOF = start of frame. Doc ID 17050 Rev 6 155/168 Application block diagrams STM32F215xx, STM32F217xx Figure 89. Audio player solution using PLL, PLLI2S, USB and 1 crystal $IV BY - /3# 84!, -(Z OR -(Z UP TO $IV -(Z BY 0 0,, X . #ORTEX - CORE UP TO -(Z $IV BY 1 /4' -(Z 0,,)3 X . $IV BY 2 0(9 -#/02% -#/02% -#/ -#/ )3 ACCURACY -#,+ IN -#,+ OUT 3#,+ $!# !UDIO AMPLI AIB Figure 90. Audio PLL (PLLI2S) providing accurate I2S clock PLLI2S Phase lock detector CLKIN /M M=1,2,3,..,64 1 MHz PhaseC VCO 192 to 432 MHz I2S_MCK = 256 x FSAUDIO 11.2896 MHz for 44.1 kHz 12.2880 MHz for 48.0 kHz /N N=192,194,..,432 /R I2SCOM_CK I2S CTL I2S_MCK R=2,3,4,5,6,7 I2SD=2,3,4.. 129 ai16041b 156/168 Doc ID 17050 Rev 6 STM32F215xx, STM32F217xx Application block diagrams Figure 91. Master clock (MCK) used to drive the external audio DAC I2S controller I2S_CK I2S_MCK = 256 x FSAUDIO = 11.2896 MHz for FSAUDIO = 44.1 kHz = 12.2880 MHz for FSAUDIO = 48.0 kHz /I2SD 2,3,4,..,129 I2S_SCK(1) = I2S_MCK/8 for 16-bit stereo = I2S_MCK/4 for 32-bit stereo /8 /(2 x 16) FSAUDIO for 16-bit stereo /4 /(2 x 32) FSAUDIO for 32-bit stereo ai16042 1. I2S_SCK is the I2S serial clock to the external audio DAC (not to be confused with I2S_CK). Figure 92. Master clock (MCK) not used to drive the external audio DAC I2S controller I2S_SCK(1) I2SCOM_CK /I2SD /(2 x 16) FSAUDIO for 16-bit stereo /(2 x 32) FSAUDIO for 32-bit stereo ai16042 1. I2S_SCK is the I2S serial clock to the external audio DAC (not to be confused with I2S_CK). Doc ID 17050 Rev 6 157/168 Application block diagrams A.6 STM32F215xx, STM32F217xx Ethernet interface solutions Figure 93. MII mode using a 25 MHz crystal 34- -#5 -))?48?#,+ -))?48?%. -))?48$;= -))?#23 -))?#/, %THERNET -!# (#,+ %THERNET 0(9 -)) PINS -))?28?#,+ -))?28$;= -))?28?$6 -))?28?%2 )%%% 040 4IMER INPUT TRIGGER 4IMESTAMP 4)- COMPARATOR -)) -$# PINS -$)/ -$# 003?/54 84!, -(Z /3# 0,, (#,+ -#/-#/ 0(9?#,+ -(Z 84 -36 1. fHCLK must be greater than 25 MHz. 2. Pulse per second when using IEEE1588 PTP optional signal. Figure 94. RMII with a 50 MHz oscillator 34- -#5 %THERNET 0(9 2-))?48?%. %THERNET -!# 2-))?48$;= 2-))?28$;= (#,+ 2-))?#28?$6 2-))?2%&?#,+ )%%% 040 4IMER INPUT TRIGGER 4IMESTAMP 4)- COMPARATOR 2-)) PINS 2-)) -$# PINS -$)/ -$# OR OR -(Z SYNCHRONOUS -(Z 84!, /3# 0,, (#,+ /3# -(Z -(Z 84 -(Z -36 1. fHCLK must be greater than 25 MHz. 158/168 Doc ID 17050 Rev 6 STM32F215xx, STM32F217xx Application block diagrams Figure 95. RMII with a 25 MHz crystal and PHY with PLL 34-& -#5 %THERNET 0(9 2-))?48?%. %THERNET -!# 2-))?48$;= 2-))?28$;= (#,+ )%%% 040 2-))?#28?$6 2-))?2%&?#,+ 2-)) PINS 2%&?#,+ -$)/ 4IMER INPUT TRIGGER 4IMESTAMP 4)- COMPARATOR 2-)) -$# PINS -$# OR OR -(Z SYNCHRONOUS -(Z 84!, -(Z /3# 0,, (#,+ 0,, -#/-# 0(9?#,+ -(Z 84 -36 1. fHCLK must be greater than 25 MHz. 2. The 25 MHz (PHY_CLK) must be derived directly from the HSE oscillator, before the PLL block. Doc ID 17050 Rev 6 159/168 Revision history 8 STM32F215xx, STM32F217xx Revision history Table 91. Date Revision 02-Feb-2010 1 Initial release. 2 Updated datasheet status to PRELIMINARY DATA. Renamed high-speed SRAM, system SRAM. Added UFBGA176 package, and note 1 related to LQFP176 package in Table 2, Figure 12, and Table 89. Added information on ART accelerator and audio PLL (PLLI2S). Added Table 4: USART feature comparison. Several updates on Table 5: STM32F21x pin and ball definitions and Table 6: Alternate function mapping. ADC, DAC, oscillator, RTC_AF, WKUP and VBUS signals removed from alternate functions and moved to the "other functions" column in Table 5: STM32F21x pin and ball definitions. TRACESWO added in Figure 5: STM32F21x block diagram, Table 5: STM32F21x pin and ball definitions, and Table 6: Alternate function mapping. XTAL oscillator frequency updated on cover page, in Figure 5: STM32F21x block diagram and in Section 2.2.11: External interrupt/event controller (EXTI). Updated list of peripherals used for boot mode in Section 2.2.13: Boot modes. Added Regulator bypass mode in Section 2.2.16: Voltage regulator, and Section 5.3.4: Operating conditions at power-up / power-down (regulator OFF). Updated Section 2.2.17: Real-time clock (RTC), backup SRAM and backup registers. Added Note Note: in Section 2.2.18: Low-power modes. Added SPI TI protocol in Section 2.2.23: Serial peripheral interface (SPI). Updated Section 2.2.28: Universal serial bus on-the-go full-speed (OTG_FS), and Section 2.2.29: Universal serial bus on-the-go highspeed (OTG_HS). Added Section 5: Electrical characteristics, and Section 6.2: Thermal characteristics. Updated Table 86: LQFP176 - Low profile quad flat package 24 x 24 x 1.4 mm package mechanical data and Figure 80: LQFP176 - Low profile quad flat package 24 x 24 x 1.4 mm, package outline. Added Table 90: Main applications versus package for STM32F2xxx microcontrollers in A.1: Main applications versus package. Updated figures in Appendix A.3: USB OTG full speed (FS) interface solutions and A.4: USB OTG high speed (HS) interface solutions. Updated Figure 89: Audio player solution using PLL, PLLI2S, USB and 1 crystal and Figure 90: Audio PLL (PLLI2S) providing accurate I2S clock. Added random number generation feature. Added trademark for ART accelerator and updated Section 2.2.2: Adaptive real-time memory accelerator (ART AcceleratorTM). 13-Jul-2010 160/168 Document revision history Changes Doc ID 17050 Rev 6 STM32F215xx, STM32F217xx Table 91. Revision history Document revision history (continued) Date 25-Nov-2010 Revision Changes 3 Added WLCSP66 (64+2) package. Added note 1 related to LQFP176 on cover page. Update I/Os in Section : Features. Updated Table 6: Multi-AHB matrix. Added case of BOR inactivation using IRROFF on WLCSP devices in Section 2.2.15: Power supply supervisor. Reworked Section 2.2.16: Voltage regulator to clarify regulator off modes. Added Section 2.2.19: VBAT operation. Modified VDD_3 pin in Table 5: STM32F21x pin and ball definitions, and added note related to the FSMC_NL pin. Renamed BYPASS-REG REGOFF, and add IRROFF pin. Changed VSS_SA to VSS, and VDD_SA pin reserved for future use. Updated maximum HSE crystal frequency to 26 MHz. USART4/5 renamed UART4/5. USART4 pins renamed UART4 in Table 5: STM32F21x pin and ball definitions. Updated LIN and IrDA features for UART4/5 in Table 4: USART feature comparison. Section 5.2: Absolute maximum ratings: Updated VIN minimum and maximum values and note for non-five-volt tolerant pins in Table 7: Voltage characteristics. Updated IINJ(PIN) maximum values and related notes in Table 8: Current characteristics. Updated VDDA minimum value in Table 10: General operating conditions. Added Note 2 and updated Maximum CPU frequency in Table 11: Limitations depending on the operating power supply range; and added Figure 19: Number of wait states versus fCPU and VDD range. Renamed Brownout Low, medium and High reset thresholds, Renamed VBORL/VBORM/VBORH, VBOR1/VBOR2/VBOR3 in Table 15: Embedded reset and power control block characteristics. Changed fLSI typical value in Table 29: LSI oscillator characteristics. Added Figure 33: ACCLSI versus temperature. Changed fOSC_IN maximum value in Table 26: HSE 4-26 MHz oscillator characteristics. Changed fPLL_IN maximum value in Table 30: Main PLL characteristics, and updated jitter parameters in Table 31: PLLI2S (audio PLL) characteristics. Section 5.3.16: I/O port characteristics: updated VIH and VIL in Table 42: I/O static characteristics. Added Note 1 below Table 43: Output voltage characteristics. Updated RPD and RPU parameter description in Table 53: USB OTG FS DC electrical characteristics. Updated VREF+ minimum value in Table 62: ADC characteristics. Updated Table 67: Embedded internal reference voltage. Removed Ethernet and USB2 for 64-pin devices in Table 90: Main applications versus package for STM32F2xxx microcontrollers. Added A.2: Application example with regulator OFF, removed "OTG FS connection with external PHY" figure, updated Figure 84, Figure 85, and Figure 87 to add STULPI01B. Doc ID 17050 Rev 6 161/168 Revision history STM32F215xx, STM32F217xx Table 91. Document revision history (continued) Date 22-Apr-2011 162/168 Revision Changes 4 Changed datasheet status to "Full Datasheet". APB1 frequency changed form 36 MHz to 30 MHz. Introduced concept of SRAM1 and SRAM2. LQFP176 now in production. Removed WLCSP64+2 package. Updated Figure 3: Compatible board design between STM32F10xx and STM32F2xx for LQFP144 package and Figure 2: Compatible board design between STM32F10xx and STM32F2xx for LQFP100 package. Added camera interface for STM32F217Vx devices in Table 2: STM32F215xx and STM32F217xx: features and peripheral counts. Removed 16 MHz internal RC oscillator accuracy in Section 2.2.12: Clocks and startup. Updated Section 2.2.16: Voltage regulator. Modified I2S sampling frequency range in Section 2.2.12: Clocks and startup, Section 2.2.24: Inter-integrated sound (I2S), and Section 2.2.30: Audio PLL (PLLI2S). Updated Section 2.2.17: Real-time clock (RTC), backup SRAM and backup registers and description of TIM2 and TIM5 in Section : General-purpose timers (TIMx). Modified maximum baud rate (oversampling by 16) for USART1 in Table 4: USART feature comparison. Updated note related to RFU pin below Figure 10: STM32F21x LQFP100 pinout, Figure 11: STM32F21x LQFP144 pinout, Figure 12: STM32F21x LQFP176 pinout, Figure 13: STM32F21x UFBGA176 ballout, and Table 5: STM32F21x pin and ball definitions. Added RTC_50Hz as PB15 alternate function, and TT (3.6 V tolerant I/O) in Table 5: STM32F21x pin and ball definitions and Table 6: Alternate function mapping. PA15 added in Table 5: STM32F21x pin and ball definitions. In Table 5: STM32F21x pin and ball definitions, changed I2S2_CK and I2S3_CK to I2S2_SCK and I2S3_SCK, respectively. Removed ETH _RMII_TX_CLK for PC3/AF11 in Table 6: Alternate function mapping. Updated Table 7: Voltage characteristics and Table 8: Current characteristics. TSTG updated to -65 to +150 in Table 9: Thermal characteristics. Added CEXT and ESR in Table 10: General operating conditions as well as Section 5.3.2: VCAP1/VCAP2 external capacitor. Modified Note 3 in Table 11: Limitations depending on the operating power supply range. Updated Table 13: Operating conditions at power-up / power-down (regulator ON), and Table 14: Operating conditions at power-up / power-down (regulator OFF). Added OSC_OUT pin in Figure 15: Pin loading conditions. and Figure 16: Pin input voltage. Updated notes below Figure 15: Pin loading conditions. Updated VPVD, VBOR1, VBOR2, VBOR3, TRSTTEMPO typical value, and IRUSH, added ERUSH and Note 3 in Table 15: Embedded reset and power control block characteristics. Doc ID 17050 Rev 6 STM32F215xx, STM32F217xx Table 91. Revision history Document revision history (continued) Date 22-Apr-2011 Revision Changes Updated Typical and maximum current consumption conditions, as well as Table 16: Typical and maximum current consumption in Run mode, code with data processing running from Flash memory (ART accelerator disabled) and Table 17: Typical and maximum current consumption in Run mode, code with data processing running from Flash memory (ART accelerator enabled) or RAM. Added Figure 21, Figure 22, Figure 23, and Figure 24. Updated Table 18: Typical and maximum current consumption in Sleep mode, and added Figure 25 and Figure 26. Updated Table 20: Typical and maximum current consumptions in Standby mode and Table 21: Typical and maximum current consumptions in VBAT mode. Updated Table 19: Typical and maximum current consumptions in Stop mode. Added Figure 27: Typical current consumption vs temperature in Stop mode. Updated Table 20: Typical and maximum current consumptions in Standby mode and Table 21: Typical and maximum current consumptions in VBAT mode. Updated On-chip peripheral current consumption conditions and Table 22: Peripheral current consumption. Updated tWUSTDBY and tWUSTOP, and added Note 3 in Table 23: Lowpower mode wakeup timings. Maximum fHSE_ext and minimum tw(HSE) values updated in Table 24: High-speed external user clock characteristics. Updated C and gm in Table 26: HSE 4-26 MHz oscillator 4 characteristics. Updated RF, I2, gm, and tsu(LSE) in Table 27: LSE (continued) oscillator characteristics (fLSE = 32.768 kHz). Added Note 3 and updated ACCHSI, IDD(HSI) and tsu(HSI) in Table 28: HSI oscillator characteristics. Added Figure 32: ACCHSI versus temperature Updated fLSI, tsu(LSI) and IDD(LSI) in Table 29: LSI oscillator characteristics. Table 30: Main PLL characteristics: removed note 1, updated tLOCK, jitter, IDD(PLL) and IDDA(PLL), added Note 2 for fPLL_IN minimum and maximum values. Table 31: PLLI2S (audio PLL) characteristics: removed note 1, updated tLOCK, jitter, IDD(PLLI2S) and IDDA(PLLI2S), added Note 3 for fPLLI2S_IN minimum and maximum values. Added Note 1 in Table 32: SSCG parameters constraint. Updated Table 33: Flash memory characteristics. Modified Table 34: Flash memory programming and added Note 2 for tprog. Updated tprog and added Note 2 in Table 35: Flash memory programming with VPP. Modified Figure 37: Recommended NRST pin protection. Updated Table 38: EMI characteristics and EMI monitoring conditions in Section : Electromagnetic Interference (EMI). Added Note 2 related to VESD(HBM)in Table 39: ESD absolute maximum ratings. Added Section 5.3.15: I/O current injection characteristics. Updated Table 42: I/O static characteristics. Modified maximum frequency values and conditions in Table 44: I/O AC characteristics. Doc ID 17050 Rev 6 163/168 Revision history STM32F215xx, STM32F217xx Table 91. Document revision history (continued) Date 22-Apr-2011 164/168 Revision Changes Updated tres(TIM) in Table 46: Characteristics of TIMx connected to the APB1 domain. Modified tres(TIM) and fEXT Table 47: Characteristics of TIMx connected to the APB2 domain. Changed tw(SCKH) to tw(SCLH), tw(SCKL) to tw(SCLL), tr(SCK) to tr(SCL), and tf(SCK) to tf(SCL) in Table 48: I2C characteristics and Figure 38: I2C bus AC waveforms and measurement circuit. Added Table 53: USB OTG FS DC electrical characteristics and updated Table 54: USB OTG FS electrical characteristics. Updated VDD minimum value in Table 58: Ethernet DC electrical characteristics. Updated Table 62: ADC characteristics and RAIN equation. Updated RAIN equation. Updated Table 64: DAC characteristics. Updated tSTART in Table 65: TS characteristics. Updated Table 67: Embedded internal reference voltage. Modified FSMC_NOE waveform in Figure 54: Asynchronous nonmultiplexed SRAM/PSRAM/NOR read waveforms. Shifted end of FSMC_NEx/NADV/addresses/NWE/NOE/NWAIT of a half FSMC_CLK period, changed td(CLKH-NExH) to td(CLKL-NExH), td(CLKH-AIV) to td(CLKLAIV), td(CLKH-NOEH) to td(CLKL-NOEH), and td(CLKH-NWEH) to td(CLKL4 NWEH), and updated data latency from 1 to 0 in Figure 58: (continued) Synchronous multiplexed NOR/PSRAM read timings, Figure 59: Synchronous multiplexed PSRAM write timings, Figure 60: Synchronous non-multiplexed NOR/PSRAM read timings, and Figure 61: Synchronous non-multiplexed PSRAM write timings, Changed td(CLKH-NExH) to td(CLKL-NExH), td(CLKH-AIV) to td(CLKL-AIV), td(CLKH-NOEH) to td(CLKL-NOEH), td(CLKH-NWEH) to td(CLKL-NWEH), and modified tw(CLK) minimum value in Table 72, Table 73, Table 74, and Table 75. Updated R typical value in Table 66: VBAT monitoring characteristics.Updated note 2 in Table 68, Table 69, Table 70, Table 71, Table 72, Table 73, Table 74, and Table 75. Modified th(NIOWR-D) in Figure 67: PC Card/CompactFlash controller waveforms for I/O space write access. Modified FSMC_NCEx signal in Figure 68: NAND controller waveforms for read access, Figure 69: NAND controller waveforms for write access, Figure 70: NAND controller waveforms for common memory read access, and Figure 71: NAND controller waveforms for common memory write access. Specified Full speed (FS) mode for Figure 86: USB OTG HS peripheral-only connection in FS mode and Figure 87: USB OTG HS host-only connection in FS mode. Doc ID 17050 Rev 6 STM32F215xx, STM32F217xx Table 91. Revision history Document revision history (continued) Date 14-Jun-2011 Revision Changes 5 Added SDIO in Table 2: STM32F215xx and STM32F217xx: features and peripheral counts. Updated VIN for 5V tolerant pins in Table 7: Voltage characteristics. Updated jitter parameters description in Table 30: Main PLL characteristics. Remove jitter values for system clock in Table 31: PLLI2S (audio PLL) characteristics. Updated Table 38: EMI characteristics. Update Note 2 in Table 48: I2C characteristics. Updated Avg_Slope typical value and TS_temp minimum value in Table 65: TS characteristics. Updated TS_vbat minimum value in Table 66: VBAT monitoring characteristics. Updated TS_vrefint minimum value in Table 67: Embedded internal reference voltage. Added Software option in Section 7: Part numbering. In Table 90: Main applications versus package for STM32F2xxx microcontrollers, renamed USB1 and USB2, USB OTG FS and USB OTG HS, respectively; and removed USB OTG FS and camera interface for 64-pin package; added USB OTG HS on 64-pin package; and added Note 2 and Note 3. Updated disclaimer on cover page. Doc ID 17050 Rev 6 165/168 Revision history STM32F215xx, STM32F217xx Table 91. Document revision history (continued) Date 20-Dec-2011 166/168 Revision Changes 6 Updated SDIO register addresses in Figure 14: Memory map. Updated Figure 3: Compatible board design between STM32F10xx and STM32F2xx for LQFP144 package, Figure 2: Compatible board design between STM32F10xx and STM32F2xx for LQFP100 package, Figure 1: Compatible board design between STM32F10xx and STM32F2xx for LQFP64 package, and added Figure 4: Compatible board design between STM32F10xx and STM32F2xx for LQFP176 package. Updated Section 2.2.3: Memory protection unit. Updated Section 2.2.6: Embedded SRAM. Updated Section 2.2.28: Universal serial bus on-the-go full-speed (OTG_FS) to remove external FS OTG PHY support. In Table 5: STM32F21x pin and ball definitions: changed SPI2_MCK and SPI3_MCK to I2S2_MCK and I2S3_MCK, respectively. Added ETH _RMII_TX_EN alternate function to PG11. Added EVENTOUT in the list of alternate functions for I/O pin/balls. Removed OTG_FS_SDA, OTG_FS_SCL and OTG_FS_INTN alternate functions. In Table 6: Alternate function mapping: changed I2S3_SCK to I2S3_MCK for PC7/AF6, added FSMC_NCE3 for PG9, FSMC_NE3 for PG10, and FSMC_NCE2 for PD7. Removed OTG_FS_SDA, OTG_FS_SCL and OTG_FS_INTN alternate functions. Updated peripherals corresponding to AF12. Removed CEXT and ESR from Table 10: General operating conditions. Added maximum power consumption at TA=25 C in Table 19: Typical and maximum current consumptions in Stop mode. Added CRYPTO, RNG, and HASH consumption in Table 22: Peripheral current consumption. Updated md minimum value in Table 32: SSCG parameters constraint. Added examples in Section 5.3.11: PLL spread spectrum clock generation (SSCG) characteristics. Updated Table 50: SPI characteristics and Table 51: I2S characteristics. Updated Figure 45: ULPI timing diagram and Table 57: ULPI timing. Updated Table 59: Dynamics characteristics: Ethernet MAC signals for SMI, Table 60: Dynamics characteristics: Ethernet MAC signals for RMII, and Table 61: Dynamics characteristics: Ethernet MAC signals for MII. Updated maximum fS values in Table 62: ADC characteristics. Section 5.3.25: FSMC characteristics: updated Table 68 toTable 79, changed CL value to 30 pF, and modified FSMC configuration for asynchronous timings and waveforms. Updated Figure 59: Synchronous multiplexed PSRAM write timings. UpdatedTable 80: DCMI characteristics. Updated Table 87: UFBGA176+25 - ultra thin fine pitch ball grid array 10 x 10 x 0.6 mm mechanical data. Doc ID 17050 Rev 6 STM32F215xx, STM32F217xx Table 91. Revision history Document revision history (continued) Date 20-Dec-2011 Revision Changes Appendix A.3: USB OTG full speed (FS) interface solutions: updated Figure 84: USB OTG FS (full speed) host-only connection and added Note 2, updated Figure 85: OTG FS (full speed) connection dual-role with internal PHY and added Note 3 and Note 4, modified Figure 86: OTG HS (high speed) device connection, host and dual-role in highspeed mode with external PHY and added Note 2. 6 Appendix A.4: USB OTG high speed (HS) interface solutions: (continued) removed figures USB OTG HS device-only connection in FS mode and USB OTG HS host-only connection in FS mode, updated Figure 86: OTG HS (high speed) device connection, host and dual-role in highspeed mode with external PHY. Added Appendix A.6: Ethernet interface solutions. Updated disclaimer on last page. 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