© 2003 Fairchild Semiconductor Corporation DS500769 www.fairchildsemi.com
January 2003
Revised January 2003
100EL11 5V ECL 1:2 Differential Fanout Buffer
100EL11
5V ECL 1:2 Differential Fanout Buffer
General Description
The 100E L11 is a 5V 1: 2 different ial fan out buffer. One dif-
ferentia l input signal is fann ed ou t to tw o ide ntical di fferen-
tial outp uts . B y supp ly ing a con stan t r efe re nce level to o ne
input pin a single ended input condition is created.
With inputs open or both inputs at VEE the differential Q
outputs default LOW and Q outputs default HIGH.
The 100 series is temperature compensated.
Features
Typical propagation delay of 265 ps
Typical IEE of 26 mA
Typical Skew of 5 ps between outputs
Internal pull-down resistors on inputs
Fairchild MSOP-8 package is a drop-in replacement to
ON TSSOP-8
Meets or exceeds JEDEC specification EIA/JESD78 IC
latch-up test
Moisture Sensitivity Level 1
ESD Perform ance:
Human Body Mod el > 2000V
Machine Model > 200V
Ordering Code:
Devices also available in Tape and Reel. Spe ci fy by append ing suffix lette r “X” to the ord ering co de.
Connection Diagram
Top View
Pin Descriptions
Logic Diagram
Order Number Product Package DescriptionPackage Code
Number Top Mark
100EL11M M08A KEL11 8-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
100EL11M8
(Preliminary) MA08D KL11 8-Lead Molded Small Outline Package (MSOP), JEDEC MO-187, 3.0mm Wide
Pin Name Description
Q0, Q0, Q1, Q1ECL Data Outputs
D, D ECL Data Inputs
VCC Positive Supply
VEE Negative Supply
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100EL11
Absolute Maximum Ratings(Note 1) Recommended Operating
Conditions
Note 1: The Absolute Maximum Ratings are those v alues beyon d which
the saf ety of the device cannot be gu aranteed. Th e device shoul d not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the absolute maximum rating.
The R ecomm ended Oper ating Co ndition s table will def ine the condit ions
for actu al device operation.
100EL PECL DC Electrical Characteristics VCC = 5.0V; VEE = 0.0V (Note 2)
Note 2: Input and output parameters vary 1 to 1 with VCC. VEE can vary +0.8V/0.5V.
Note 3: Outputs ar e t erminat ed t hrough a 50 Re sistor to VCC 2.0V.
Note 4: VIHCMR minimum varies 1 to 1 with VEE. VIHCMR maximum varies 1 to 1 wi th V CC. The V IHCMR range is referenced to the most positive side of the dif-
ferential input signal. Normal operation is obtained if the HIGH level falls within the specified range and the peak-to-peak voltage li es betwe en VPPMIN and
1V.
Note 5: Absolute value of the input HIGH and LOW current should not exceed the absolute value of the stated MIn or Max specification.
Note: Devices are designed to meet the DC specifications after thermal equilibrium has been established. Circuit is tested with air flow greater than
500LFPM maintained.
PECL Supply Voltage (VCC) VEE = 0V 0.0V to +8.0V
NECL Supply Voltage (VEE) VCC = 0V 0.0V to 8.0V
PECL DC Input Voltage (VI) VEE = 0V 0.0V to +6.0V
NECL DC Input Voltage (VI) VCC = 0V 0.0V to 6.0V
DC Output Current (IOUT)
Continuous 50 mA
Surge 100 mA
Storage Temperature (TSTG)65°C to +150°C
PECL Power Supply
(VEE = 0V) VCC = 4.2V to 5.5V
NECL Power Supply
(VCC = 0V) VEE = 4.2V to 5.5V
Free Air Operating Temperature (TA)40°C to +85°C
Symbol Parameter 40°C 25°C 85°CUnits
Min Typ Max Min Typ Max Min Typ Max
IEE Power Supply Current 26 31 26 31 30 36 mA
VOH Output HIGH Voltage (Note 3) 3915 3995 4120 3975 4045 4120 3975 4050 4120 mV
VOL Output LOW Voltage (Note 3) 3170 3305 3445 3190 3295 3380 3190 3295 3380 mV
VIH Input HIGH Voltage (Single Ended) 3835 4120 3835 4120 3835 4120 mV
VIL Input LOW Voltage (Single Ended) 3190 3525 3190 3525 3190 3525 mV
VIHCMR Input HIGH Voltage Common Mode 2.5 4.6 2.5 4.6 2.5 4.6 V
Range (Differential) (Note 4)
IIH Input HIGH Current (Note 5) 150 150 150 µA
IIL Input LOW Current (Note 5) 0.5 0.5 0.5 µA
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100EL11
100EL NECL DC Electrical Characteristi cs VCC = 0.0V; VEE = 5.0V (Note 6)
Note 6: Input and output parameters vary 1 to 1 with VCC. VEE can vary +0.8V/0.5V.
Note 7: Outputs are terminated through a 50 Resistor to VCC 2.0V.
Note 8: VIHCMR minimum varies 1 to 1 with VEE. VIHCMR maximum varies 1 to 1 with VCC. The VIHCMR range is re fe ren ced to t he mo st po si ti ve sid e of the di f -
ferential in put sign al. Norm al operati on is obtaine d if the HIG H level fall s within th e specifi ed range and the peak -to-pea k voltage lies be twe en V PPMIN and
1V.
Note 9: Absolute va lue of the input HIGH and LOW c urrent should no t e xceed the absolu te va lue of the st at ed Min or Ma x specification.
Note: Devices are designed to meet the DC specifications after thermal equilibrium has been established. Circuit is tested with air flow greater than
500LFP M maintained.
AC Electrical Characteristics VCC = 5V; VEE = 0.0V or VCC = 0.0V; VEE = 5V (Note 10)(Note 11)
Note 10: VEE can vary +0.8V / 0.5V.
Note 11: Measured using a 750 mV input swing centered at VCC - 1.32V; 50% dut y cycl e cl ock source ; tr = tf = 250 ps (20% - 80%) at fIN = 1 MHz. All loading
with 50 to VCC 2.0V.
Note 12: Within-device skew defined as identical transitions on similar paths through a device.
Note 13: D ut y cycle sk ew is th e difference between a tPLH and tPHL propag at ion delay t hrough a de v ic e under ide nt ic al condit ions.
Switching Wa veforms
FIGURE 1. Differential to Differential Propagation Delay
FIGURE 2. Differential Output Edge Rates
Symbol Parameter 40°C25°C85°CUnits
Min Typ Max Min Typ Max Min Typ Max
IEE Power Supply Current 26 31 26 31 30 36 mA
VOH Output HIGH Voltage (Note 7) 1085 1005 880 1025 955 880 1025 955 880 mV
VOL Output LOW Voltage (Note 7) 1830 1695 1555 1810 1705 1620 1810 1705 1620 mV
VIH Input HIGH Voltage (Single Ended) 1165 880 1165 880 1165 880 mV
VIL Input LOW Voltage (Single Ended) 1810 1475 1810 1475 1810 -1475 mV
VIHCMR Input HIGH Voltage Common Mode 2.5 0.4 2.5 0.4 2.5 0.4 V
Range (Differential) (Note 8)
IIH Input HIGH Current (Note 9) 150 150 150 µA
IIL Input LOW Current (Note 9) 0.5 0.5 0.5 µA
Symbol Parameter 40°C25°C85°CUnits Figure
Min Typ Max Min Typ Max Min Typ Max Number
fMAX Maximum Toggle Frequency TBD TBD TBD GHz
tPLH, tPHL Propagation Delay to Output 135 260 385 190 265 340 215 290 365 ps Figure 1
tSKEW Within Device Skew (Note 12) 5 5 20 5 20 ps
Duty Cycle Skew (Note 13) 5 5 20 5 20
tJITTER Cycle-to-Cycle Jitter TBD TBD TBD ps
VPP Input Swing 150 1000 150 100 150 1000 mV Figure 1
tr, tfOutput Rise Times Q 100 225 350 100 225 350 100 225 350 ps Figure 2
(20% to 80%)
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100EL11
Physical Dimensions inches (millimeters) unless otherwise noted
8-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
Package Number M08A
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
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100EL11 5V ECL 1:2 Differential Fanout Buffer
Physical Dimensions in ches (millimeters) unless otherwise noted (Continued)
8-Lead Mold ed Small O u tline Package (MSOP), JEDEC MO-187, 3.0mm Wide
Package Number MA08D
Fairchild does not assume an y responsibility for u se of any circuitry descr ibed, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILDS PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life suppor t de vices o r syst ems are dev ic es or syste ms
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instruct ions fo r use pr ovi de d in the l abe ling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A crit ical componen t in any com ponen t of a life s uppor t
device or system whose failure to perform can be rea-
sonabl y e xpec ted to cause th e fa i lure of the l ife s upport
device or system, or to affect its safety or effectiveness.
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