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Usage of SKiiP Systems (SEMIKRON integrated intelligent Power)
1 Main Features of SKiiP Systems...........................................................................................................2
2 T ype Designation S ystem......................................................................................................................2
3 Which SKiiP System should I use? .......................................................................................................3
4 Technical Explanations..........................................................................................................................3
4.1 SKiiP technology ............................................................................................................................3
4.2 Family of Standard SKiiP Systems.................................................................................................4
4.3 Insulation........................................................................................................................................5
4.4 Properties of the GB and GD gate driver .......................................................................................5
4.4.1 User Interface - Digital Inputs..................................................................................................5
4.4.2 User interface - Analog Outputs..............................................................................................5
4.4.3 Requirements of the Auxiliary Power Supply..........................................................................7
4.4.4 Gate Driver Block Diagram .....................................................................................................8
4.4.5 Protection and super visory func tions......................................................................................8
4.4.5.1 OCP - (O)ver (C)urrent (P)rotection and Short Circuit Protection ...................................9
4.4.5.2 Over temperature protection............................................................................................9
4.4.5.3 Under Vo ltag e Pr otecti on o f the Suppl y Voltage .............................................................9
4.4.5.4 DC link over voltage protection........................................................................................9
4.4.5.5 Dead Time Generation (“TOP/BOTTOM interlock”).....................................................10
4.4.5.6 Shor t Pu ls e Sup pres sion ...............................................................................................11
4.4.5.7 Error Latch and Error Feedback....................................................................................11
4.4.5.8 Error Concept.................................................................................................................13
4.4.6 Integra ted Se nsor Funct ions.................................................................................................13
4.4.6.1 Integr a ted Curr ent Sens or .............................................................................................13
4.4.6.2 Integrated Temperature Sensor.....................................................................................15
4.4.6.3 Integr a ted DC link Voltage Mon itori ng...........................................................................16
4.5 Brake Chopper Driver used in SKiiP2 type „GDL“ .......................................................................17
4.6 Features of Standard Heat Sinks.................................................................................................18
4.6.1 Standard Heat Sink for forced Air Cooling............................................................................19
4.6.2 Standard Heat Sink for Liquid Cooling..................................................................................19
4.7 Options.........................................................................................................................................20
4.7.1 U-opti on: DC-li nk Volt age Sens e Mon itori ng ........................................................................20
4.7.2 F-Option: Connection to the SKiiP System using Fiber optic Interface ................................20
5 Accessories .........................................................................................................................................21
5.1 Snubber Capacitors......................................................................................................................21
5.2 AC Busbars ..................................................................................................................... .............21
5.3 DC-Link Capacitors and Bus Bars................................................................................................21
6 Application instructions........................................................................................................................24
6.1 ESD Protection.............................................................................................................................24
6.2 Connections to power terminals...................................................................................................24
6.3 Connection to the Signal Terminals of the Gate Driver................................................................24
6.4 Environmental Restrictions...........................................................................................................24
6.5 Parallel Operation of „GB“-type SKiiP Systems...........................................................................25
6.6 Electro-Magnetic Interference......................................................................................................26
6.7 Usage of Water Cooled Heat Sinks..............................................................................................26
6.8 Further Application Support..........................................................................................................26
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1 Main Features of SKiiP Systems
- SKiiP: SEMIKRON Intelligent Integrated Power is a power semiconductor subsystem
- SKiiP integrates power semiconductor switches, heat sink and gate driver unit with protection and
monitoring circuit
- SKiiP3 is the successor product for SKiiP2 with increased power density and is compatible to SKiiP2
- based on SKiiP pressure contact technology which allows a compact power module design with very
low thermal resistances, high thermal cycling capability and low parasitic stray inductances.
- equipped with closed loop current sensors, used for short circuit and over-current protection
- Normalized analog voltage signals of the actual AC-current value, the actual ceramic substrate
temperature value and the actual DC-link voltage value (optional, depends on type) are available at
the DIN41651 gate driver connector of the SKiiP for use in the control unit.
- Assembly of SKiiP is based on SKiiP technology, a pressure contact technology which allows a compact
power module design with very low thermal resistances and high thermal cycling capability.
2 Type Designation System
SKiiP n
G
o
G
p q
G
rr ss t
GGGG
uvv w
GG
SKiiP2 example *: SKiiP 3 4 2 G D 1 2 0 - 3 DU L
SKiiP3 example: SKiiP 5 1 3 G D 1 2 2 - 3 DU L
n nominal current IC (@ Theat sink=25°C) divided by 100 as e.g. 500A Æ 5, can contain 2 letters eg. 15,
o SKiiP2: chip specification / SKiiP3: insulation DCB (direct copper bonded) ceramic substrate type
0Æ standard aluminum nitride (AlN) DCB ceramic (SKiiP3 only)
1Æ standard aluminum oxide (Al2O3) DCB ceramic
p SKiiP generation , e.g. 3 for 3rd generation
q chip type as e.g. G = IGBT
r circuit
B Æ 2 pack (half bridge, dual)
H Æ 4 pack ( single phase bridge)
D Æ 6 pack ( 3 phase bridge)
DL Æ 6 pack + brake chopper
s voltage class
06 Æ VCES = 600 V
12 Æ VCES = 1200 V
17 Æ VCES = 1700 V
t chip generation
u number of used modular half bridges (2 packs)
v gate driver designator
DU Æ gate driver with DC-link voltage measurement and over voltage protection
D Æ gate driver witho ut DC-li nk voltage meas ur em ent
DUF Æ gate driver with DC-link voltage measurement, over voltage protection and F-Option
(optional for GB type only)
DF Æ gate driver without DC-link voltage measurement and F-Option (optional for GB type only)
w heat sink designator
L Æ standard profile for forced air cooling
W Æ standard profile for liquid cooling
* Please note: Information about the former SKiiP2 standard types before 01/04 (e.g .about type
designation) is available on request.
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3 Which SKiiP System should I use?
Generally speaking SKiiP3 is recommended for new designs when a suitable type is available, especially
in applications where a very high power density is required. The table gives a survey of the available
types (n.a. Ù not available; IC given at Tj = 150°C, Ts = 25°C).
6 pack (GD)
6 pack with brake-
chopper (GDL) 2 pack (GB)
SKiiP2 IC I
C I
C
600V 200A - 400A
contact
SEMIKRON 800A - 1600A
1200V 150A - 300A
150A - 300A 400A - 1200A
1700V 150A - 250A
contact
SEMIKRON 500A -1000A
SKiiP3 IC I
C I
C
600V 400A - 800A
n.a. n.a.
1200V 300A - 600A
n.a. 1000A - 2400A
1700V 500A n.a. 1000A - 2400A
Please note for SKiiP3 there do exist two types of ceramic substrate, Aluminum Nitrite and Aluminum
Oxide. The first one has a very good thermal conductivity which is suitable in water cooled applications,
whereas the later one is basically supposed for standard air cooled applications. For SKiiP2 only
Aluminum Oxide is used.
4 Technical Explanations
4.1 SKiiP technology
SKiiP technology is the patented technology on which SKiiP Systems are based. The main characteristic
features of SKiiP technology are
• the base plate free power section
• the spring pressure contact of all thermal and electrical contacts
• the internal low inductive paralleling of inverter legs
Fig. 1 SKiiP System power section assembly
The electrical main and auxiliary terminals are not soldered to the insulated ceramic substrate but
pressed. The insulated ceramic substrate is pressed to the heat sink. The pressure contacts are
responsible for superior thermal cycling capability of SKiiP Systems. In addition they provide simple
assembly.
Fig. 2 shows the paralleling of ceramic substrates to achieve high output current capability. This feature of
the SKiiP technology provides low stray inductance values in the commutation circuit and therefore allows
high utilization of the IGBT blocking voltage Vces.
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ceramic
s
ubstrate
Fig. 2 Paralleling of ceramic substrates
4.2 Family of Standard SKiiP Systems
Fig. 3 2-fold SKiiP System Fig. 4 3-fold SKiiP System
One SKiiP system contains 2, 3 or 4 single ceramic substrates as shown in the block diagrams.
Fig. 5 4-fold SKiiP System
Each ceramic substrate c ontains a full phas e leg with upper ( TO P) and lower ( BOT TOM) IG BT as well as
the corres ponding free wheeling dio des. The integrated gate dr iver defin es the ci rcuit. The follo wing table
gives a survey of the available circuits:
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2 substrates
( 2-fold) 3 substrates
( 3-fold) 4 substrates
( 4-fold)
circuit
GB SKiiP2/3 SKiiP2/3 SKiiP2/3
GD SKiiP2/3
GDL SKiiP2
Please note: To parallel 2, 3 or 4 power sections of the SKiiP System type the user must parallel the DC
and AC terminals to each other. SEMIKRON recommends dedicated bus bars for AC terminal paralleling
(please refer to chapter "Accessories").
4.3 Insulation
Magnetic transformers are used for insulation between gate driver primary and secondary side. The
circuit us ed f or the DC volt age meas urement is desig ned, manuf ac tured and test ed ac cor di ng to standar d
EN50178 (VDE 0160). The temperature sensor is insulated on the ceramic substrate.
Please note: the insulation of the temperature signal is a basic insulation only. Equipment which is
designed according to EN50178 must have further insulation for all parts which might be touched by a
person.
The SKiiP System insulation test voltage is depending on Vccmax. The individual insulation test voltage
level is given in the data sheets.
4.4 Properties of the GB and GD gate driver
4.4.1 User Interface - Digital Inputs
The figure below shows the schematic of the SKiiP 2 and SKiiP3 digital input lines. A 1nF capacitor is
connected to the input to obtain high noise immunity. This capacitor can cause for current limited line
drivers a little delay of few ns, which can be neglected. We recommend choosing the line drivers
according to the demanded length of the ribbon cable.
It is compulsory to use circuits which switch active to +15V and 0V. Pull up and open collector output
stages must not be used for TOP/BOT control signals.
1nF
6,81kOhm
3,32kOhm
ASIC
Input
BSS BSS
Fig. 6 User Interface - TOP/BOT input
4.4.2 User interface - Analog Outputs
The f igure bel o w sh ows the s c hematic of the SKi iP2 a nd SK ii P3 a nal og output l in es . T he 47 5 Ω resistor in
series with th e vo lta ge follower does avoid s hor t cir cui t damages . Please ens ur e t hat the maxim um dr iven
current by the output operational amplifier does not exceed 5mA.
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USignal U out
475Ohm
10kOhm
100pF
1nF
BSA BSA
-
+
Fig. 7 User Interface- Analog Signal Output
For a trou ble-free i nteract ion of SK iiP and user side co ntrol it is necess ary to ad apt the cus tomer input to
the SKiiP outputs. For that reason the auxiliary analog signal ground BSA shall be used when analog
signals are meas ured. T he ground BS A is on the SKi iP driver bo ard on the sam e poten tial as BS S, whic h
is the gr ound of the po wer suppl y. The d iffer ence is that th e BSA line is not use d for s upply cur rents and
for that reason no voltage drop due to supply current will be caused.
In the follo wing secti on a schem atic and a des cription is given f or an analog in put cir cuit on the contr oller
board of the user.
Fig. 8 Symmetric Wired Differential A mplifier
The circuit above is a symmetrical wired differential amplifier.
• At the input is a 10kΩ resistor (R1). The interference sensitivity of the over all circuit (user control,
driver) is reduced by a continuous current flow through this resistor.
• The capacitor C1 leak s differential and comm on mode high-frequenc y interf erence currents. T his
capacitor should not be larger than 100pF to ensure that there is no additional time delay in the
system.
• The symm etr ic al wirin g of the amplif ier is as f ollo ws. P leas e no te t hat no c ap ac ito r is i n p ar al le l t o
the feedback resistor and also to the resistor of the non-inverting input to ground (2R2). These
C3
+VCC
-VCC
-VCC
-VCC
+VCC
+VCC
user board
SKiiP
BSA
Analog
Output
AGND
AGND
R
2
R
2
R
2
R
2
2R
2
2R
2
R1
C1 R
3
C1
PE
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capacitors have often higher tolerances, so the common-mode rejection of the circuitry is reduced
by this effect.
• The input resistor should be split up and installed between the clamping-diodes. The current in
the diodes is limited by this resistor. A diode with a low reverse current should be selected e.g.
1N4148.
• If a low pass filtering shall be implemented in the input circuit, this should be done with a
capacitor between the input resistors (see dotted lines). In most cases this capacitor is not
necessar y and th e smoothi ng can b e realis ed by a s im ple R-C network (R3, C3) at the end of the
operational amplifier.
4.4.3 Requirements of the Aux iliary Power Supply
The table shows the required features of an appropriate power supply for a SKiiP System. In case that
the gate driver is supplied with 24V it is possible to use 15V provided at t he DIN 41651 connector of the
gate driver as an auxiliary power supply, e.g. for a level-shifter at the controller’s output signals.
SKiiP2 SKiiP3
unregulated 24V power supply 20V - 30V 13V - 30V
regulated power supply 15V ± 4%
15V please use input
of unregulated
24V power
supply
Iout15V
(can be used if 24 V supply is
active) < 50 mA < 50 mA
mimimum peak
current of auxiliary 15V
supply 1,5A -
imimum peak current of auxiliary 24V
supply 1,5A 1,5A
max. rise time of auxiliary 15V supply
the voltage slope has to be continuous
– no plateau in voltage slope)
50 ms -
max. rise time of auxiliary 24V supply
the voltage slope has to be continuous
– no plateau in voltage slope)
50 ms < 2 s
power on reset completed after 130 ms 150 ms
Please note: All values are related to one SKiiP. Do not apply switching signals during power on reset.
The current consumption of SKiiP Systems depends on the level of supply voltage used, the standby
current of the gate driver, the switching frequency, the capacitance of the IGBT gates in use and on the
actual main AC-current. In the data sheets for each gate driver an equation is given which describes the
current consumption depending on standby current, switching frequency and AC output current. Please
rate the power supply that way, that the continuous current is at least 20% higher that the calculated
consumption current from the SKiiP. The rated peak current of the supply must fulfill the specification in
the table.
Since SKiiP3 uses a switched amplifier for the compensated current sensor the current consumption of
SKiiP3 has been reduced towards SKiiP2.
In the datasheets the equation for the evaluation of the current consumption is given assuming supply
with 24V. Additionally the SKiiP2 datasheets provide an equation to calculate supply current for operation
with 15V.
Example for SKiiP2:
IS2 = supply current @ 24V supply voltage = 340mA + 490mA * fs/fsmax + 3,5mA*IAC/A
(stand by current) (current depending (current depending
on switching frequency.) on output current IAC)
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Example for SKiiP 3
IS2 = supply current @ 24V supply voltage = 280mA + 460mA * fs/kHz + 0,0003mA *(IAC/A )2
(stand by current) (current depending (current depending
on switching frequency.) on output current IAC)
Please note: The switch mode amplifier of SKiiP3 compensated current sensor causes a quadratic
relations h ip to AC current l eve l.
4.4.4 Gate Driver Block Diagram
unde r vo l t age
lockout, power
O
N reset
TOP
fast turn off
BOT
pulse
transformer
T
OP
pulse
transformer
B
OT
+15V stabilised
TOP
-8V
DC / DC
converter
prim ary si d e +15V stabilised
BOT
-8V
pulse shaper
+
interlock
with
deadtime
analogue
temperature
output
+
ϑDCB > ϑmax
error latch,
reset via
TOP=BOT=LOW
input
buffer
B
OT
input
buffer
T
OP
wide range
24 V supply input
(13V-30V)
X1
14
1
power
driver
T
OP
power
driver
B
OT
-UZK
load side
VGE
VGE
+UZK
U∼
∼∼
∼
I∼
∼∼
∼
ϑDCB
driver side
high side
flip flop
T
OP
high side
flip flop
B
OT
short pulse
suppression
T
OP
short pulse
suppression
B
OT
s
econdary sideprima r y sid e
∑ Iν > Imax
+
anal ogue current
sense output
normali se d : 10V =12 5% INENN
TOP
BOT
4 kVAC
option
analog DC link voltage monitoring
UDC_analog
option F:
fiber optic
link (TOP, ERR,
BOT)
Vcesat +
undervoltage
m
onitoring
Vcesat +
undervoltage
m
onitoring
spring contacts to power section
Fig. 9 Gate driver block diagram
Fig. 9 sho ws the func tiona lit y of the phase leg (Ù2- pack ) gate dr iver in a block diagr am . The 6 pack gate
driver incorporates the same functionality per phase. Additionally SKiiP2 features a ground fault
protection. T rip levels of the ground f ault protection are given in the corresponding data sheet. The table
below shows a list of functional differences between SKiiP2 and SKiiP3 gate driver:
Property SKiiP 2 SKiiP 3
power supply 20 V - 30 V +
15V regulated 13V - 30V
ground fault protection ( GD) Yes No
4.4.5 Protection and supervisory functions
SKiiP2/3 gate drivers feature the following protection and supervisory functions
• interlock and dead time generation for TOP and BOTTOM IGBT
• short pulse suppression
• input pulse shaping
• input signal clamping
• under voltage monitoring of the (internal) supply voltage on primary side
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• transient over voltage and inverted polarity protection by suppressor diode
• over temperature protection ( if forced air cooling is used)
• short circuit and over current protection
• Vcesat protection
• line to ground fault protection (only for type SKiiP2 GD)
• over voltage protection of the DC link voltage (optional; for SKiiP3 GD as standard)
The following chapter gives a description of the SKiiP System protection and supervisory functions as
illustrated in the block diagram. The datasheets include timing and trip level data.
4.4.5.1 OCP - (O)ver (C)urrent (P)rotection and Short Circuit Protection
As shown in the block diagram SKiiP Systems feature integrated current sensors per phase leg. These
current s ensors can be us ed f or AC cur rent con trol. In add ition they are use d to pr otect th e SKiiP S ystem
against over currents. If the AC output current is higher than the m aximum permissible level of 125 % IC
(exception: SKiiP3 with AlN ceramic substrate), the IGBTs are immediately switched off and switching
pulses f rom the controller a re ignored. T he error latch is s et. T he output ,,ERROR OUT “ is in HIGH state
Please note: the output ,,ERROR OUT“ is an open collector output, which needs an external pull up
resistor.
The over current protection reacts independently of the temperature level and provides a reliable
protection of the SKiiP System.
In addition a VCEsat monitoring circuit is implemented to protect the phase leg against internal short
circuit (“shoot through” protection).
4.4.5.2 Over temperature protection
The temperature of the ceramic substrate is monitored by an integrated temperature sensor. At a
maximum substrate temperature of T = 115 ± 5°C the IGBTs are switched off and switching pulses from
the controller are ignored. The error latch is set. The outputs ,,Overtemp. OUT“ and ,,ERROR OUT“ are in
HIGH state.
Please note: the output ,,ERROR OUT“ is an open collector output which needs an external pull up
resistor.
The over temperature trip threshold has been chosen at 115°C. For most air cooled applications this is
suffic ient to protec t the s ystem . But for water coole d system s or short tim e overlo ads the thr eshold m ight
be too high. In this case the user should evaluate the analog temperature output to protect the system.
4.4.5.3 Under Vo ltag e Pr otec ti on o f the Suppl y Voltage
The under voltage protection of the primary side monitors the internal 15V DC which is provided by the
internal DC-DC converter (converts the unregulated input voltage to 15V DC) or by controlled +15V DC
input (SKiiP2 only). If the under voltage trip level is reached, the IGBTs are switched off and switching
pulses f rom the contr oller ar e ignored . T he error latch is set. T he output ,,ERRO R O UT“ is in HIGH stat e.
The table below gives an overview of the trip levels.
under voltage trip level @ condition SKiiP 2 SKiiP 3
primary side, supply via 24 V pins 18,5V no trip level
primary side, supply via 15 V pins 13,5V -
internal regulated +15V 13,5V 13,5V
internal regulated -15V (for current sensor) -13,5V -13,5V
secondary side - 10V
4.4.5.4 DC link over voltage protection
This protection is implemented for the following types:
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Uzk monitoring SKiiP 2 SKiiP 3
GD types ( 6 - pack ) standard standard
GB types ( 2-pack) option -
GB types ( 3-pack) option option
GB types ( 4-pack) option option
If the operating DC link voltage is higher than VCCmax the IGBTs are turned off and switching pulses
from the controller are ignored. The error latch is set. The output ,,ERROR OUT“ is in HIGH state. The
trip level is given in the datasheet.
4.4.5.5 Dead Time Generation (“TOP/BOTTOM interlock”)
The interlock circuit prevents that the TOP and the BOT IGBT of one half bridge are switched on at the
same tim e (internal sh ort circuit). T he internal interlock tim e is adapted to the power sem iconductors , i.e.
it is chosen as small as possible to allow high duty cycle but guarantees a safety margin against shoot
through losses due to tail currents. The dead time does not add to a dead time given by the controller.
Thus the total dead tim e = m ax (built in dead time, c ontroller dead tim e) . It is possible to c ontrol the SKii P
System with one switching signal and its inverted signal. No error message will be generated when
overlap of switching signals occurs.
Please no te th at the pr opa gati on d elay of the dr iv er is the s um of interloc k dead ti me (tTD) and dr iv er Inp ut
output signal propagation delay of the driver (td(on/off)IO). The dead time is only active in case that the
opposite device is switching with an inverted pulse pattern.
Moreover the switching time of the IGBT chip has to be taken into account (not shown in the picture).
Fig. 10 Pulse Patter - dead time generation
TOPIN
BOTIN
VGETOP
VGEBOT
td(on/off)IO
tTD
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4.4.5.6 Short Pu ls e Sup pr es s ion
This circuit suppresses short turn-on and off-pulses. This way the IGBTs are protected against spurious
noise as they can occur due to bursts on the signal lines.
Pulses shorter than 625ns are for 100% probability suppressed and all pulses longer than 750ns get
through f or 100% pr ob ab il it y. Puls es with a len gth in- b et wee n 6 25ns and 750 ns can b e either su ppr ess ed
or get through.
Fig. 11 Pulse Pattern - Short Pulse Suppression
4.4.5.7 Error Latch and Error Feedback
Any error detected will s et the error latc h and for ce the output ,, ERROR OUT“ into HIGH state. S witching
pulses from the controller will be ignored. Reset of the error latch is only possible with no error present
and all input signals in LOW state for the time TpRESET =9µs.
All logical error outputs are open collector transistors with Vexternal = 3,3 - 30V / Imax=15mA. (Low signal =
"no error" - wire break monitoring). We recommend to set the external pull-up voltage as high as possible.
An external pull-up resistor Rpull-up to the controller logic high level is required. The resistor has to be in the
range: Vexternal/Imax < Rpull-up < 10kΩ)
Example:
for Vexternal = 15V the needed resistor should be in the range Rpull-up=(15V/15mA) - 10kΩ =1kΩ-10kOhm
The external filter capacitor Cext is not compulsory but for noise immunity reasons recommended. We
advice to choose a value of something in the range of a few nF, because the RC time constant must not
exceed the minimum error duration time of 9µs.
TOPIN
VGE_TOP
Short Pulses
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• For SKiiP2 the circuit can be seen in the following picture:
The c irc uit be lo w il luminate s the pr i nc ip le of the Error outp ut f or SK ii P2. The error trans is tor is an or d in ary
open col lector trans istor. T he resist or Rsens ac ts as se nsor for the short cir cuit protec tion. In cas e that t he
current exceeds the specified Imax=15mA the transistor will be turned off and the error signal can be
detected by the customer. This way the error transistor is short circuit proof.
Fig. 12 SKiiP2 - Open Collector Error Transistor
• For SKiiP3 this circuit is simpler as can be seen in the following picture.
Please note: The error output of SKiiP3 is not short circuit proof.
Fig. 13 SKiiP3 - Open Collector Error Transistor
ERROR
Detection C=1nF
Rpull_up
Vexternal
SKiiP int er nal part
C
ustomer
Cext
ERROR
Detection
+
-
Rsens=10Ω
C=1nF
Rpull_up
Vexternal
SKiiP int er nal part
C
ustomer
side
Short circuit
d
etection
Cext
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4.4.5.8 Error Concept
The error management of SKiiP can be described by the following table. Any error condition will cause
the error signals on the corresponding pins to go high on the open collector output (indicated by 9).
• Error Management of GD-Types
Pin 3
ERROR HB1 OUT Pin 6
ERROR HB2 OUT Pin 9
ERROR HB3 OUT Pin 11
Overte mp. OUT
Vce-protection HB1 9
Vce-protection HB2 9
Vce-protection HB3
9
OCP prote c tion HB 1 9 9 9
OCP prote c tion HB 2 9 9 9
OCP prote c tion HB 3 9 9 9
temperature protection 9 9 9 9
DC-link over voltage
protection 9 9 9
Ground Fault (SKiiP2 only) 9 9 9
Internal Supply Voltage Error 9 9 9
• Error Management of GB-Types
Pin 3
ERROR HB1 OUT Pin 11
Overte mp. OUT
Vce-protection HB1 9
OCP prote c tion HB 1 9
temperature protection 9 9
DC-link over voltage
protection 9
Internal Supply Voltage Error 9
4.4.6 Integrated Sensor Functions
The SKiiP System features the following integrated sensors
• compensated current sensor per phase leg
• temperature sensor on ceramic substrate
• sensing of DC link voltage (optional)
4.4.6.1 Integrated Current Sensor
The SKii P S ystem power sec tion inte grates on e c urr ent tr ansf o rm er per power s ect ion t o measur e the AC
output current. The measured current is normalized to a corresponding voltage at the DIN 41651
connector. The over current trip level is set to 10V .
In all SKiiP2 and SKiiP3 systems with aluminum oxide (Al2O3) ceramic substrate 100% of the rated DC
current IC corresponds to 8 V and the over current trip level ITRIPSC is set to 125% IC, equivalent to 10V.
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SKiiP3 S ystems with alum inum nitr ide (AlN) ceram ic substrate are f rom an electri cal point of view s imilar
to the sam e sized Al2O3 substrate based systems but have a bett er thermal conductivity and therefore a
higher rated DC-current. There is no difference of the driver board (as e.g. current normalization, over
current tr ip leve l etc.) . For that r eason b oth s ystem s have the sam e relati on between t he absol ute valu es
of current and corresponding voltage. Only the relation in percent to IC is different. Please refer to the
individual datasheets for the corresponding values.
The c urr ent trans f or mers are working ac c ordin g to the c om pens ati on princ i ple. The magnetic f ie ld caus ed
by the loa d current is detec ted by a m agnetic f ield sens or. This is not a Hall e lement b ut a sm all coil with
a high perm eable core. D ue to the properties of this sens ing elem ent there is no offset f ailure and alm ost
no temper atur e de pen dence. An elec tro nic c irc uit is evaluating th e va lu e of the field sens or and is feeding
a current into th e compensation coil thus k eeping the effective magnetic f ield to zero. The compensation
current gives an image of the load current and is evaluated across a burden resistor with an electronic
circuit.
The following figure illuminates the compensation principle with the SKiiP3 current sensor. The SKiiP3
current s ensor us es a switc h m ode contr oller f or the com pens ation curr ent ver sus a li near contr oller used
in the SKii P2 current s enso r. This leads to rem ark ably reduced cur rent cons um ption of the SKi iP3 cur rent
sensor.
S
First compensating coil
Second com pensating coil
Sens or coil
Primar y current
Output
Load resistor
I
S
I
PWM
A
A
Co ntrol param eter
Fig. 14 SKiiP3 compensated current sensor
The table below compares the data of SKiiP current sensors (one sensor per power section).
parameter SKiiP2 SKiiP3
continuos output current
per curent sensor 200Arms 400Arms
continuous outp ut curr en t, 2s
per current sensor 250Arms 500Arms
peak current, 10µs 3000 A 3000 A
bandwidth (-3dB) DC - 100 kHz DC - 50 kHz
response time < 1µs < 1µs
parasitic capacitance prim. - sec. 40pF 30pF
The accuracy of the current sensor depends on several points as there are:
• tolerance of current sensor electronic
• tolerance of burden resistor of current sensor
• tolerance of SKiiP internal amplification circuitry (e.g. by offset of operational amplifiers,
tolerances of external passive components etc.)
• tolerance due to temperature drift
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The maximum tolerance values can be calculated by the values given in the following equation:
∆I = IC * kIo + Iactual (kIerror - kIo + |∆T| * TCError)
Parameter SKiiP2 SKiiP3
Offset kIo 0,35% 0,13%
Gain Erro r kIerror 1,50% 1,50%
Temperature Coefficient TCError 0,001 % / K 0,002 % / K
IC is the Nominal current per DCB
∆I is the absolute deviation per DCB
Example:
The deviation at the current level Iactual =300A for a SKiiP3 (513GD172) at 85°C is (Ic = 500A):
Deviation = 500A * 0,13% + 300A * (1,5% - 0,13% + | 85°C-25°C | * 0,002% / K ) = 4, 76 A
Please note that the absolute deviation is given in relationship to the current per DCB. In case that a 2-
fold GB is used the deviation is the same compared to a GD type SKiiP for the same current per DCB.
A
bsolute Deviation of Current S ensor in A
for a SKiiP3 513GD172
0
1
2
3
4
5
6
7
8
9
0 100 200 300 400 500 600
Iactual / A
delta IC @+25°C
delta IC @+85°C
Fig. 15 Absolute Deviation of Current Sensor for a 513GD172
4.4.6.2 Integrated Temperature Sensor
The integrated temperature sensor is a semiconductor resistor with proportional characteristic (PTC
characteristic). The sensor is soldered onto the ceramic substrate close to the IGBT and freewheeling
diodes and indicates the actual substrate temperature. The sensor is insulated. An evaluation circuit
realized on the integrated driver provides a normalized, analog voltage signal of the actual ceramic
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substrate tem perature value (see next Fig.) The ceramic substrate tem perature is very close to the heat
sink temperature.
The accuracy of the temperature sensor is approximately ± 3°C (see also the following picture). Please
note that t he temperature sensor is desi gne d f or Tr > 30°C. T he tole ranc e ban d is very wide temperatur es
below 30°C.
0,0
1,0
2,0
3,0
4,0
5,0
6,0
7,0
8,0
9,0
10,0
11,0
12,0
020406080100120
Theatsink (°C)
Tanalog (V)
Min.Tana
Typ.Tana
Max.Tana
30
Fig. 16 Analog temperature signal Uanalog OUT vs. Tsensor : (at pin ,,Temp. analog OUT“)
4.4.6.3 Integrated DC link Volta ge Mon itori ng
With the option U ,,analog DC-link voltage-sense“, a normalized, analog voltage signal of the actual DC-
link v oltage level is availab le at the DI N 4 1651 co nnec tor of the g ate dr iver. The m easur ement is reali zed
by a high impedance dif ferential amplifier. The circuit is designed, m anufactured and tested according to
standard EN 501 78 (VDE 0 160) .
Normalization of the actual DC-link-voltage signal and input impedances of the measurement circuit is
shown in the table below.
SKiiP 2 and SKiiP 3
Vces VDC Ù VDCanalog Input Impedance Vccmax Ù VDCTripmin
600 V 400V Ù 9 V 5 MOhm 400V
1200 V 900V Ù 9 V 5 MOhm 900V
1700 V 1200V Ù 9 V 6,5 MOhm 1200V
The failure of the measured signal is ± 2% @ Ta = 25°C. The over voltage trip level is Vccmax. The analog
output signal VDCanalogOUT is filtered with a time constant of τ= 500 µs.
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4.5 Brake Chopper Driver used in SKiiP2 type „GDL“
X1
DC - INPUT
protection
+24V : polar ity
+15V : polar ity +
overvoltage
DC / DC
Converter
INHIBIT
ERROR
out
( no error = act. L OW )
(UCE < 0,6V;Isink,max = 2,5mA)
POR PWG
regulated +15V
power supply
+10V REF
ERROR
latch
UZ ≥ UMAX
VCE
monitoring
INHIBIT
ON
U1 ≤ UZ ≤ U2
TEMP. control
( ϑIGBT > 115°C )
+VCC
RLoad
VCE
RON
ROFF
option „E“ : UMAX = 730 V
U
ON = 681 V
U
OFF = 667 V
option „U“ : UMAX = 860 V
U
ON = 802 V
U
OFF = 786 V
all voltage levels ± 3%
-UZ
VGE
1 17
1 12 MODUL use
( Option „M“ )
X 11
SKiiP use
X 10
external
RESET
CHOPPER
ext.ON
load side
driver side
14
1
Fig. 17 Block diagram brake chopper driver
SKiiP2 G DL type incorporat es a 6- pac k (GD) and a br a k e c hopper . T he br ake chopper of the G DL S Ki i P2
is located at the right side assuming the DC terminals on the bottom.
The following paragraphs explain the functionality of the brake chopper driver according to the block
diagram Fig. 7:
Internal Control
The bang-ba ng contr oller generat es the ON and O FF signa ls f or the brak e chopper dependi ng on the DC
link voltage level. Once the hysteresis comparator is triggered, the minimum ON time for a discharging
pulse is t yp. 30 µs.
Two standard versions for 1200 V SKiiP2 are available.
Type Version E ( for Uline = 400 VAC) Version A ( for Uline = 460 VAC)
UZmax 730 V 860 V
UZon (Chopper On) 681 V 802 V
UZoff (Chopper Off) 667 V 786 V
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External Control
The input signal CHOPPER ext. ON (PIN 2) can be used for external switching (for example for
discharging the DC-link capacitor while having a service). External ON switching is only possible, if the
chopper ’s error latch is n ot s et and d oes n ot depe nd o n the ac tual value of th e DC l ink vol tage. T he m ax .
switching frequency should not exceed 5 kHz. As designed for open collector drive, this input is not
depending on a certain controller logic level. Active LOW from the controller means CHOPPER = ON
Protection
• The IGBT is protected against short circuit by VCE-monitoring.
• Heat sink temperature monitoring. The driver turns off at T = 115°C and the error memory is set.
• DC-voltage monitoring: If the DC voltage exceeds UZmax the driver turns off and the error memory is
set.
The chopper driver is protected against over voltage of the 15V supply by a suppressor diode. This
suppressor diode will be destroyed in case of reverse polarity of 15 V supply. The driver is protected
against reverse polarity of 24V power supply.
Error Memory
The error memory is set by various error signals. Switching ON the chopper IGBT is only possible if the
error memory is in NO ERROR state. Once the error latch is set, it will remain in ERROR condition until
no mor e er ror is pres ent and inp ut RESET (PIN 4) is active LOW for min. tpdRESET > 300 m s . Af ter star t up
of power supply a power on reset takes place.
Error conditions:
a) under voltage condition of the supply voltage
lim it valu e when us ing 15 V DC (± 4%): < 13,5 V
lim it valu e when us ing 24 V DC (20 ... 30 V): < 16 V
b) short circuit (VCE monitoring) of brake IGBT
c) DC-link over voltage: Uz > Uzmax
d) Over temperature: Tchip > 115 °C ± 5 °C
Error output
Setting of the error latc h will create an error signal at the ERROR OUT (PIN 3). T his output has an open
collect or transis tor which is optic ally contr olled. An external pull up r esistor (m ax. 30 V / 2,5 m A) mus t be
connected on the controller board to logic HIGH level. Active LOW at driver output means NO ERROR.
Power supply
The driver ma y be sup plied either with 24 VDC (20 .. .30 V) or with r egulated +15 VDC ± 4%. If 24 V supply
is used 15 V supply must not be used and vice versa.
DC / DC converter
The DC/DC c onverter provi des an iso lated po wer supp ly with lo w coupli ng cap acity for the gate dr ive and
its logic. An active LOW input at RESET (PIN 4) from the controller blocks the power supply for the
secondary side.
4.6 Features of Standard Heat Sinks
SKiiP S ystem s ar e equipped with h igh perf orm ance heat sink s. T he data sheets c ontain trans ient th erm al
data referenced to the built-in temperature sensor. This allows the calculation of junction temperature if
the generated losses are known. The given thermal resistances represent worst case values.
Evaluation of thermal impedance:
junction sensor ( subscript for sensor: "r"): Zth jr = Σ Rth jrn * [( 1 - e - t / tau n )] , n = 1,2,3..
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sensor ambient: Zthra = Σ Rth ran * [( 1 - e - t / tau n )] , n = 1,2,3..
To simplify the comparison with other power semiconductor modules SKiiP3 data sheets also contain the
thermal resistance between chip junction and heat sink (subscript for heat sink: "s"). These values are
given as typica l val ues .
Please note: The reference point for heat sink temperature (subscript "s") is directly below the hottest
chip => the temperature of the reference point is not available in the application environment.
All technical data of SKiiP Systems are incorporated into the SEMISEL simulation software which has
online access under http://www.semikron.com
For further explanations of the thermal modeling please read the SEMIKRON application hand book (also
available under http://www.semikron.com).
4.6.1 Standard Heat Sink for forced Air Cooling
The drawings are available in the datasheet section. The coefficients of the transient thermal impedance
are given in the data sheet (SKiiP3 only; SKiiP2 transient thermal impedances are available in a separate
docum ent) . The given air volumes are valid when the SE MIK RO N stan dar d fan S KF16 is used.
Please note: Strictly speaking the given transient thermal impedance (Zthjr) data are valid together with
the SEMIKRON standard heat sink only. They might be adapted for other forced air cooled heat sinks
which have a minimum root thickness of 14 mm.
4.6.2 Standard Heat Sink for Liquid Cooling
The drawings are available in the datasheet section. The coefficients of the transient thermal impedance
are given in the data sheet. (SKiiP3 only; SKiiP2 transient thermal impedances are available in a separate
document).
Please note: the given transient thermal impedance (Zthjr) data are vali d togeth er with the S EMI KRON
standard heat sink only and for 50%/50% water glycol cooling liquid. The usage of these value for other
liquid cooled heat sinks might cause severe deviations in calculation of thermal resistance.
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4.7 Options
4.7.1 U-option: DC-link Voltage Sense Monitoring
If a 2 pack SKiiP (,,GB“ t ype) is used with U-opt ion the analo g voltage signa l of the actual DC-l ink value
is present at Pin 12 of the driver interface instead of the signal for the actual heat sink temperature.
The 6 pack SKiiP (,,GD“ type) has DC bus bar voltage and temperature information in the standard
version available.
4.7.2 F-Option: Connection to the SKiiP System using Fiber optic Interface
W ith the ,,option - F“ switc hing and er ror signals are trans ferred via f iber optic c onnectors . The f iber optic
adapter is fixed at the cover of the SKiiP System, and connected to the integrated driver via a short flat
cable. Fiber optic connectors from Hewlett Packard’s HFBR - 0501 family are in use. The receiver type
HFBR 252 1 (bl ue) is used for the in put signals TOP IN ( U1) an d BOT IN (U3) . The transmitter t ype HFBR
1521 (grey) is used for the output ERROR OUT (U2). Please refer to the data sheet section for exact
position of the F-option.
Fig. 18 Picture showing F-Option
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5 Accessories
5.1 Snubber Capacitors
SEMIKRON provides film capacitors which can be adapted onto the DC-terminals of the SKiiP systems.
These capacitors reduce the over voltage peak during commutation and are recommended by
SEMIKRON. The table below lists the available types.
Capacitance/DC-voltage recommended for use with
ID number
470nF / 1000V 600V, 1200V Devices 41046230
220nF / 1250V 1700V Devices 41046220
5.2 AC Busbars
The AC outputs of SKiiP GB circuits must be paralleled externally
. SEMIKRON recommends dedicated bus bars for paralleling as shown below:
Item ID number
AC-bar for GB-Type 2-fold 41034390
AC-bar for GB-Type 3-fold 41034400
AC-bar for GB-Type 4-fold 41034410
5.3 DC-Link Capacitors and Bus Bars
SEMIKRON supplies tested capacitors banks with low stray inductance for direct mounting onto the
SKiiP. You can make a choice from the following most common references:
2-f old 2200 17,6 SKCB 2m 2- 45-2-12
3-f old 3300 26,4 SKCB 2m 2- 45-3-12
4-f old 4400 35,2 SKCB 2m 2- 45-4-12
2-fold 3300
2
3,6
S
KCB 3m3-45-2- 12
3-f old 5000 35,4 SKCB 3m 3- 45-3-12
4-f old 6600 47,2 SKCB 3m 3- 45-4-12
2-f old 4700 26,8 SKCB 4m 7- 40-2-12
3-f old 7000 40,2 SKCB 4m 7- 40-3-12
4-f old 9400 53,6 SKCB 4m 7- 40-4-12
2-f old 1500 17,6 SKCB 2m 2- 45-2-17
3-f old 2200 26,4 SKCB 2m 2- 45-3-17
4-f old 2900 35,2 SKCB 2m 2- 45-4-17
2-f old 2200 23,6 SKCB 3m 3- 45-2-17
3-f old 3300 35,4 SKCB 3m 3- 45-3-17
4-f old 4400 4,2 SKCB 3m 3- 45-4-17
2-f old 3100 26,8 SKCB 4m 7- 40-2-17
3-f old 4700 40,2 SKCB 4m 7- 40-3-17
4-f old 6300 53,6 SKCB 4m 7- 40-4-17
R
ated
voltage
(V)
S
urge
voltage
30s (V)
Rated capacitance
(µ
µµ
µF)
R
ipple current
(A)
(max, 100hz, Code Désignation
1050V 1200V
800 V
Skiip IGBT
1200V
Fig 19
Skiip IGBT
1700V
Fig 20
1250V
900V
1350V
720V 800V
SEMIKRON electrolytic capacitors have been specified for a drive application usage. Please check the
current in the capacitors for your own application before making a choice.
The following table gives the maximum ripple current per capacitor bank at 100Hz, 85°C, for 15 000 hours
life time.
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Voltage
R
ated
capacitance
(
µ
µµ
µ
F
)
Ripple current (A)
(max, 100hz, 85°c)
350 3300 10,9
400 2200 8,2
400 3300 10,1
400 4700 13,4
450 2200 8,8
450 3300 12,6
450 4700 14
The capacitor bank comes along with a reinforced support plate and the snubber capacitors. During
assembly, great care should be taken to avoid any damage onto the sharing resistors.
Fig. 19 DC Link Capacitor Bank for 1200V IGBTs
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Fig. 20 DC Link Capacitor Bank for 1700V IGBTs
For further details on capacitor banks see also the separate capacitor datasheets.
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6 Application instructions
6.1 ESD Protection
Every SKiiP System is equipped with an ESD protective cover. To avoid any electrostatic discharge do
not rem ove the pr otective cover bef or e the SK ii P System is com pletely instal le d. Us e conduc ti ve f loor and
grounded armbands during assembly.
6.2 Connections to power terminals
It is mandatory to use a laminated low-inductive bus bar structure to connect the DC link to the DC-
terminals of the SKiiP System. The DC link bank has to be designed this way that each DCB faces the
same im pedance to the voltage source respectively DC link bank. This way the current distribution is as
even distributed as possible. T he usage of high frequenc y film capacitors (see also section accessories)
on the DC link connections is necessary, to reduce the over voltages in case of a short circuit.
W hen a “G B” - type SKi i P S yst em is us ed t he AC terminals mus t be connect ed t o eac h o ther . S EMI KRO N
provides s uitable bus bars (see s ection acces sories”). And again the AC term inals have to be connec ted
as symmetric as possible to ensure the even current distribution.
Furthermore any control signals shall be kept as far away as possible from the DC link rail (because of
high dv/dt on the AC rails and high di/dt on the DC rails).
The torque level for DC and AC terminal screws as well as thread geometry is given in the datasheets.
The appli ed pullin g forces in any direction o n the term inals m ust be kept to a m inimum. F or that reason it
is com pulsory to take m easures to reduce th ese forces. W e recommend using fixing posts to relieve the
strain o n the AC term inals. T he posts shal l be m ounted direc tly onto the heat s ink . Forces c aused by th e
dc link capacitor bank have to be absorbed by the mechanical construction. Both measures have the
purpose to absorb any stresses from external parts to the terminals (e.g. the dc link capacitors or heavy
AC cables). Please keep the fixing posts as close as possible to the module.
The SKiiP System can be mounted in any position.
The rating and coolin g of the cab le must be c arried out i n that way that no therm al energy is fed i nto the
SKiiPPACK. For that reason the terminal temperature on the AC terminals shall not exceed 115°C at
400Arms and 70°C heat sink temperature. For the dc link terminals the temperature shall not exceed
115°C at 280Arms and 70°C heat sink temperature.
The AC outlet of SKiiP3 has a different position compared to SKiiP2; please refer to the data sheet for
exact position.
6.3 Connection to the Signal Terminals of the Gate Driver
The s tandard connect ion to a SKii P System is done via a DIN 416 51 connector . Because of volta ge drop
and for immunity against electromagnetic interference the maximum length of the flat cable should not
exceed 3 meters . T o avoi d inter f erenc es , t he f la t c ab le shou ld be placed as f ar as poss ible a way from the
power term inals, the po wer c ables, th e DC-link capac itor s and all ot her no ise sour ces . W e recomm end to
keep the ribbon cables as close to GND as possible (e.g. heat sink or the like).
Because of the EMC conc eptio n of the dr iver boar d the usage of expens ive sc reened flat ribb on cab les is
in ma ny applic ations not needed . Howev er in v er y noise int ensi ve ap plicati ons th e noise im m unity can be
improved by screened cable.
6.4 Environmental Restrictions
Humidity and climate class are shown in the data sheets. The documented classes specify the restrictions
for operation, storage and transport of SKiiP Systems.
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6.5 Parallel Operation of „GB“-type SKiiP Systems
In applications where paralleling of 2,3 or more GB type SKiiP systems is necessary, it has to be made
sure that no in-homogenous current distribution occurs. The reasons for this can be:
• different propagation time of driver boards (jitter of approx. 0...150ns)
• different switching times of devices (due to different Vge - thresholds)
• tolerance of forward voltage drop of diodes *
• tolerance of forward voltage drop of IGBTs
• no symmetric AC bus bar layout
• different cooling conditions of paralleled half bridges (e.g. in air cooled applications with thermal
stacking)
* For paralleling of „GB“-type SKi iP Systems, equal SKiiP System with equal Vf group must be used.
Please note: the on state voltage of the freewheeling diode of each „GB“-type SKiiP system is classified
in Vf-groups to avoid inhomogeneous current distribution within the paralleled dies. The Vf group of a
„GB“-type SKiiP System can be identified on the label.
The system designer has to make sure that there is sufficient inductance (a few µH should be in most
applications sufficient) between the AC output terminals of the 2 paralleled „GB“-type SKiiP Systems to
avoid inhomogeneous current distribution.
L might be realized by iron powder ferrites (e.g. COROVAC). The required inductance depends on DC
voltage, allowable “cross” current and the propagation time differences of the paralleled “GB”-type SKiiP
Systems.
For a maximum deviation of the maximum rated output current the inductance has to be rated with a
minimum value as shown in the picture below.
Fig. 21 Parall eled SKii Ps
Thus in an application with VCC= 900V, Ioutmax=2x600A=1200A, a perm issible current deviation of 10% of
the overall current the minimum value of the inductor is:
H
A
nsV
L
µ
1,1
1
200
*
%
1
0150*900
min ==
It has to be tak en into account that f or in-hom ogenous c urrent sharing the p ower m odules have to be de-
rated (e.g. in th e cas e abov e 1200A ou tput current are need ed, thus the m odules have to be r ated f or the
(600A each + 10%* 1200A) = 720A).
Iout Iout1
Iout2
VCC
VCE1
t
VCE2
t
t1 t2
dt
SKiiP1
SKiiP2
Iout
Iout1
Iout2
VCC
out
CC IdtV
L∆
⋅
=max
min
8VHU0DQXDOIRU6.LL36\VWHPV
3. Dezember 2003
Page: 26
von: 26
SB/KB/SP/SKD V031201 prelimi nary
SM/5/FO/000/006/Rev00/25.02.00
6.6 Electro-Magnetic Interference
The EMI relevant behavior is determined by the switching behavior on the one hand and on the coupling
characteristic to the surrounding environment on the other hand (see also application handbook).
With SKiiP3 a new generation of silicon is introduced, which reduces the total loss per ampere output
current compared to SKiiP2 and therefore shows different switching characteristics versus SKiiP2. This
must be taken into account when SKiiP2 is replaced by SKiiP3.
The ceramic substrate area of SKiiP3 is increased towards SKiiP2. Therefore the capacitive coupling
between heat sink and SKiiP3 is higher (please refer to data sheet parameter CCHC).
The coupling capacitance of SKiiP between the driver primary and secondary side is determined by the
signal and the DCDC transformers. The values can be seen in the following table.
GD GB
Cprim-sec 3x10pF 2x10pF
6.7 Usage of Water Cooled Heat Sinks
For the usage of water cooled heat sinks we recommend to take care of the following points:
• Always ensure to use the correct concentration of cooling liquid (for details see data sheet). In
case that the concentration of corrosion-inhibitors is too low, corrosion as consequential damage
may occur.
• Never leave cooling liquid in heat sinks which are temporarily not in use. This can lead to
corrosion as consequential damage on parts which become wet due to humidity.
• Please ensure that the cooling liquid is suitable for all metal parts in the cooling circuit (e.g. steel,
aluminum, other non-ferrous metals)
• Use only water which has been de-ionized (e.g. chlorine ions can accelerate the corrosion)
• The water hardness shall be kept to a minimum, to avoid scale. Please not that scale increase
the thermal resistance.
• The O2 content has to be kept to a minimum by a closed cooling circuit to avoid corrosion.
6.8 Further Application Support
For electrical and thermal design support please use SEMISEL. under SEMIKRON website
http://semisel.semikron.com or read the SEMIKRON application hand book (also available under
http://www.semikron.com).