SN54ABT16373A, SN74ABT16373A 16-BIT TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS SCBS160C - DECEMBER 1992 - REVISED MAY 1997 D D D D D D D D D SN54ABT16373A . . . WD PACKAGE SN74ABT16373A . . . DGG OR DL PACKAGE (TOP VIEW) Members of the Texas Instruments Widebus Family State-of-the-Art EPIC-B BiCMOS Design Significantly Reduces Power Dissipation 1OE 1Q1 1Q2 GND 1Q3 1Q4 VCC 1Q5 1Q6 GND 1Q7 1Q8 2Q1 2Q2 GND 2Q3 2Q4 VCC 2Q5 2Q6 GND 2Q7 2Q8 2OE Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17 Typical VOLP (Output Ground Bounce) < 0.8 V at VCC = 5 V, TA = 25C High-Impedance State During Power Up and Power Down Distributed VCC and GND Pin Configuration Minimizes High-Speed Switching Noise Flow-Through Architecture Optimizes PCB Layout High-Drive Outputs (-32-mA IOH, 64-mA IOL) Package Options Include Plastic 300-mil Shrink Small-Outline (DL) and Thin Shrink Small-Outline (DGG) Packages and 380-mil Fine-Pitch Ceramic Flat (WD) Package Using 25-mil Center-to-Center Spacings description The 'ABT16373A are 16-bit transparent D-type latches with 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. 1 48 2 47 3 46 4 45 5 44 6 43 7 42 8 41 9 40 10 39 11 38 12 37 13 36 14 35 15 34 16 33 17 32 18 31 19 30 20 29 21 28 22 27 23 26 24 25 1LE 1D1 1D2 GND 1D3 1D4 VCC 1D5 1D6 GND 1D7 1D8 2D1 2D2 GND 2D3 2D4 VCC 2D5 2D6 GND 2D7 2D8 2LE These devices can be used as two 8-bit latches or one 16-bit latch. When the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the levels set up at the D inputs. A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and the increased drive provide the capability to drive bus lines without need for interface or pullup components. OE does not affect internal operations of the latch. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. When VCC is between 0 and 2.1 V, the device is in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 2.1 V, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. The SN54ABT16373A is characterized for operation over the full military temperature range of -55C to 125C. The SN74ABT16373A is characterized for operation from -40C to 85C. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Widebus and EPIC-B are trademarks of Texas Instruments Incorporated. Copyright 1997, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 1 SN54ABT16373A, SN74ABT16373A 16-BIT TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS SCBS160C - DECEMBER 1992 - REVISED MAY 1997 FUNCTION TABLE (each 8-bit section) INPUTS OE LE D OUTPUT Q L H H H L H L L L L X Q0 H X X Z logic symbol 1OE 1LE 2OE 2LE 1D1 1D2 1D3 1D4 1D5 1D6 1D7 1D8 2D1 2D2 2D3 2D4 2D5 2D6 2D7 2D8 1 1EN 48 C3 24 2EN 25 C4 47 3D 2 1 46 3 44 5 43 6 41 8 40 9 38 11 37 12 36 13 4D 2 35 14 33 16 32 17 30 19 29 20 27 22 26 23 1Q1 1Q2 1Q3 1Q4 1Q5 1Q6 1Q7 1Q8 2Q1 2Q2 2Q3 2Q4 2Q5 2Q6 2Q7 2Q8 This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. logic diagram (positive logic) 1OE 1LE 1D1 1 2OE 48 47 2LE C1 2 1D 1Q1 24 25 C1 2D1 36 To Seven Other Channels To Seven Other Channels 2 POST OFFICE BOX 655303 1D * DALLAS, TEXAS 75265 13 2Q1 SN54ABT16373A, SN74ABT16373A 16-BIT TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS SCBS160C - DECEMBER 1992 - REVISED MAY 1997 absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 7 V Voltage range applied to any output in the high or power-off state, VO . . . . . . . . . . . . . . . . . . . -0.5 V to 5.5 V Current into any output in the low state, IO: SN54ABT16373A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 mA SN74ABT16373A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -18 mA Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -50 mA Package thermal impedance, JA (see Note 2): DGG package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89C/W DL package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65C to 150C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. The package thermal impedance is calculated in accordance with EIA/JEDEC Std JESD51. recommended operating conditions (see Note 3) SN54ABT16373A MAX MIN MAX 4.5 5.5 4.5 5.5 VCC VIH Supply voltage VIL VI Low-level input voltage IOH IOL High-level output current t/v Input transition rise or fall rate t/VCC TA Power-up ramp rate 200 Operating free-air temperature -55 High-level input voltage SN74ABT16373A MIN 2 2 0.8 Input voltage 0 Low-level output current Outputs enabled VCC -24 V V 0.8 0 UNIT VCC -32 V V mA 48 64 mA 10 10 ns/V s/V 200 125 -40 85 C NOTE 3: Unused inputs must be held high or low to prevent them from floating. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 3 SN54ABT16373A, SN74ABT16373A 16-BIT TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS SCBS160C - DECEMBER 1992 - REVISED MAY 1997 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VIK VOH TEST CONDITIONS VCC = 4.5 V, VCC = 4.5 V, II = -18 mA IOH = -3 mA VCC = 5 V, VCC = 4 4.5 5V VOL VCC = 4 4.5 5V MIN TA = 25C TYP MAX SN54ABT16373A MIN -1.2 MAX SN74ABT16373A MIN -1.2 -1.2 2.5 2.5 2.5 IOH = -3 mA IOH = -24 mA 3 3 3 2 2 IOH = -32 mA IOL = 48 mA 2* II IOZPU V V IOL = 64 mA 0.55 0.55* 0.55 100 VCC = 0 to 5.5 V, VI = VCC or GND UNIT 2 0.55 Vhys MAX V mV 1 1 1 A VCC = 0 to 2.1 V, VO = 0.5 V to 2.7 V, OE = X 50 50 50 A IOZPD VCC = 2.1 V to 0, VO = 0.5 V to 2.7 V, OE = X 50 50 50 A IOZH VCC = 2.1 V to 5.5 V, VO = 2.7 V, OE 2 V 10 10 10 A IOZL VCC = 2.1 V to 5.5 V, VO = 0.5 V, OE 2 V -10 -10 -10 A 100 A Ioff ICEX IO Outputs high VCC = 0, VI or VO 4.5 V VCC = 5.5 V, VO = 5.5 V VCC = 5.5 V, VO = 2.5 V 100 50 -50 -100 -180 Outputs high 50 -50 -180 -50 50 A -180 mA 2 2 2 5 5 V, V IO = 0, 0 VCC = 5.5 VI = VCC or GND 85 85 85 2 2 2 ICC VCC = 5.5 V, One input at 3.4 V, Other inputs at VCC or GND 1.5 1.5 1.5 Ci VI = 2.5 V or 0.5 V VO = 2.5 V or 0.5 V ICC Outputs low Outputs disabled Co mA mA 3.5 pF 9.5 pF * On products compliant to MIL-PRF-38535, this parameter does not apply. All typical values are at VCC = 5 V. This parameter is characterized, but not production tested. Not more than one output should be tested at a time, and the duration of the test should not exceed one second. This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND. timing requirements over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 1) VCC = 5 V, TA = 25C# MIN tw tsu MIN MAX SN74ABT16373A MIN UNIT MAX Pulse duration, LE high 3.3 3.3 3.3 ns Setup time, data before LE 1.5 2.4 1.5 ns 1 2.2 1 ns th Hold time, data after LE # These values apply only to the SN74ABT16373A. 4 MAX SN54ABT16373A POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 SN54ABT16373A, SN74ABT16373A 16-BIT TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS SCBS160C - DECEMBER 1992 - REVISED MAY 1997 switching characteristics over recommended ranges of supply voltage and operating free-air temperature, CL = 50 pF (unless otherwise noted) (see Figure 1) SN54ABT16373A PARAMETER FROM (INPUT) TO (OUTPUT) tPLH tPHL D Q tPLH tPHL LE Q tPZH tPZL OE Q tPHZ tPLZ OE Q VCC = 5 V, TA = 25C MIN MAX MIN TYP MAX 1.4 3.7 5.3 1.4 6.5 2 4 5.4 2 6.5 1.7 4.1 5.7 1.7 7 2.3 4.3 5.6 2.3 6.3 1.1 3.4 5 1.1 6.4 1.5 3.5 4.9 1.5 5.8 2.4 5.1 7.1 2.4 8.3 1.6 4.4 6.3 1.6 8 UNIT ns ns ns ns switching characteristics over recommended ranges of supply voltage and operating free-air temperature, CL = 50 pF (unless otherwise noted) (see Figure 1) SN74ABT16373A PARAMETER FROM (INPUT) TO (OUTPUT) tPLH tPHL D Q tPLH tPHL LE Q tPZH tPZL OE Q tPHZ tPLZ OE Q POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 VCC = 5 V, TA = 25C MIN MAX MIN TYP MAX 1.4 3.7 5.3 1.4 6.3 2 4 5.4 2 6.2 1.7 4.1 5.7 1.7 6.7 2.3 4.3 5.6 2.3 6.1 1.1 3.4 5 1.1 6.1 1.5 3.5 4.9 1.5 5.6 2.4 5.1 7.1 2.4 8.1 1.6 4.4 5.8 1.6 6.5 UNIT ns ns ns ns 5 SN54ABT16373A, SN74ABT16373A 16-BIT TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS SCBS160C - DECEMBER 1992 - REVISED MAY 1997 PARAMETER MEASUREMENT INFORMATION 500 From Output Under Test S1 7V Open GND CL = 50 pF (see Note A) 500 TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open 7V Open 3V LOAD CIRCUIT Timing Input 1.5 V 0V tw tsu 3V th 3V 1.5 V Input 1.5 V 0V Data Input 1.5 V 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VOLTAGE WAVEFORMS PULSE DURATION 3V 1.5 V Input 1.5 V 0V VOH 1.5 V Output 1.5 V VOL VOH 1.5 V 1.5 V VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS 1.5 V 1.5 V 0V tPZL tPLZ Output Waveform 1 S1 at 7 V (see Note B) tPLH tPHL Output 3V Output Control tPHL tPLH 1.5 V Output Waveform 2 S1 at Open (see Note B) 1.5 V 3.5 V VOL + 0.3 V VOL tPHZ tPZH 1.5 V VOH - 0.3 V VOH 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 , tr 2.5 ns, tf 2.5 ns. D. The outputs are measured one at a time with one transition per measurement. Figure 1. Load Circuit and Voltage Waveforms 6 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (C) Device Marking (3) (4/5) (6) 5962-9320001QXA ACTIVE CFP WD 48 1 Non-RoHS & Non-Green SNPB N / A for Pkg Type -55 to 125 5962-9320001QX A SNJ54ABT16373A WD 74ABT16373ADGGRE4 ACTIVE TSSOP DGG 48 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 ABT16373A 74ABT16373ADGGRG4 ACTIVE TSSOP DGG 48 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 ABT16373A SN74ABT16373ADGGR ACTIVE TSSOP DGG 48 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 ABT16373A SN74ABT16373ADL ACTIVE SSOP DL 48 25 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 ABT16373A SN74ABT16373ADLR ACTIVE SSOP DL 48 1000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 ABT16373A SN74ABT16373ADLRG4 ACTIVE SSOP DL 48 1000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 ABT16373A SNJ54ABT16373AWD ACTIVE CFP WD 48 1 Non-RoHS & Non-Green SNPB N / A for Pkg Type -55 to 125 5962-9320001QX A SNJ54ABT16373A WD (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com (4) 10-Dec-2020 There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF SN54ABT16373A, SN74ABT16373A : * Catalog: SN74ABT16373A * Enhanced Product: SN74ABT16373A-EP, SN74ABT16373A-EP * Military: SN54ABT16373A NOTE: Qualified Version Definitions: * Catalog - TI's standard catalog product * Enhanced Product - Supports Defense, Aerospace and Medical Applications * Military - QML certified for Military and Defense Applications Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 11-Mar-2017 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant SN74ABT16373ADGGR TSSOP DGG 48 2000 330.0 24.4 8.6 13.0 1.8 12.0 24.0 Q1 SN74ABT16373ADLR SSOP DL 48 1000 330.0 32.4 11.35 16.2 3.1 16.0 32.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 11-Mar-2017 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74ABT16373ADGGR TSSOP DGG 48 2000 367.0 367.0 45.0 SN74ABT16373ADLR SSOP DL 48 1000 367.0 367.0 55.0 Pack Materials-Page 2 MECHANICAL DATA MTSS003D - JANUARY 1995 - REVISED JANUARY 1998 DGG (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 48 PINS SHOWN 0,27 0,17 0,50 48 0,08 M 25 6,20 6,00 8,30 7,90 0,15 NOM Gage Plane 1 0,25 24 0- 8 A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 48 56 64 A MAX 12,60 14,10 17,10 A MIN 12,40 13,90 16,90 DIM 4040078 / F 12/97 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold protrusion not to exceed 0,15. Falls within JEDEC MO-153 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 MECHANICAL DATA MCFP010B - JANUARY 1995 - REVISED NOVEMBER 1997 WD (R-GDFP-F**) CERAMIC DUAL FLATPACK 48 LEADS SHOWN 0.120 (3,05) 0.075 (1,91) 0.009 (0,23) 0.004 (0,10) 1.130 (28,70) 0.870 (22,10) 0.370 (9,40) 0.250 (6,35) 0.390 (9,91) 0.370 (9,40) 0.370 (9,40) 0.250 (6,35) 48 1 0.025 (0,635) A 0.014 (0,36) 0.008 (0,20) 25 24 NO. OF LEADS** 48 56 A MAX 0.640 (16,26) 0.740 (18,80) A MIN 0.610 (15,49) 0.710 (18,03) 4040176 / D 10/97 NOTES: A. B. C. D. E. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. This package can be hermetically sealed with a ceramic lid using glass frit. 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