SN54ABT16373A, SN74ABT16373A
16-BIT TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCBS160C – DECEMBER 1992 – REVISED MAY 1997
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D
Members of the Texas Instruments
Widebus
Family
D
State-of-the-Art
EPIC-
ΙΙ
B
BiCMOS Design
Significantly Reduces Power Dissipation
D
Latch-Up Performance Exceeds 500 mA Per
JEDEC Standard JESD-17
D
Typical VOLP (Output Ground Bounce)
< 0.8 V at VCC = 5 V, TA = 25°C
D
High-Impedance State During Power Up
and Power Down
D
Distributed VCC and GND Pin Configuration
Minimizes High-Speed Switching Noise
D
Flow-Through Architecture Optimizes PCB
Layout
D
High-Drive Outputs (–32-mA IOH, 64-mA IOL)
D
Package Options Include Plastic 300-mil
Shrink Small-Outline (DL) and Thin Shrink
Small-Outline (DGG) Packages and 380-mil
Fine-Pitch Ceramic Flat (WD) Package
Using 25-mil Center-to-Center Spacings
description
The ’ABT16373A are 16-bit transparent D-type
latches with 3-state outputs designed specifically
for driving highly capacitive or relatively
low-impedance loads. They are particularly
suitable for implementing buffer registers, I/O
ports, bidirectional bus drivers, and working
registers.
These devices can be used as two 8-bit latches or one 16-bit latch. When the latch-enable (LE) input is high,
the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the levels set up
at the D inputs.
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high
or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive
the bus lines significantly . The high-impedance state and the increased drive provide the capability to drive bus
lines without need for interface or pullup components.
OE does not affect internal operations of the latch. Old data can be retained or new data can be entered while
the outputs are in the high-impedance state.
When VCC is between 0 and 2.1 V, the device is in the high-impedance state during power up or power down.
However , to ensure the high-impedance state above 2.1 V, OE should be tied to VCC through a pullup resistor;
the minimum value of the resistor is determined by the current-sinking capability of the driver.
The SN54ABT16373A is characterized for operation over the full military temperature range of –55°C to 125°C.
The SN74ABT16373A is characterized for operation from –40°C to 85°C.
Copyright 1997, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus and EPIC-ΙΙB are trademarks of Texas Instruments Incorporated.
SN54ABT16373A . . . WD PACKAGE
SN74ABT16373A . . . DGG OR DL PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
1OE
1Q1
1Q2
GND
1Q3
1Q4
VCC
1Q5
1Q6
GND
1Q7
1Q8
2Q1
2Q2
GND
2Q3
2Q4
VCC
2Q5
2Q6
GND
2Q7
2Q8
2OE
1LE
1D1
1D2
GND
1D3
1D4
VCC
1D5
1D6
GND
1D7
1D8
2D1
2D2
GND
2D3
2D4
VCC
2D5
2D6
GND
2D7
2D8
2LE
SN54ABT16373A, SN74ABT16373A
16-BIT TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCBS160C – DECEMBER 1992 – REVISED MAY 1997
2POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
FUNCTION TABLE
(each 8-bit section)
INPUTS OUTPUT
OE LE DQ
L H H H
LHL L
LLX Q
0
H X X Z
logic symbol†
†This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
1OE
2OE
1EN
1
C3
48
1LE
3D
47
1D1 46
1D2 44
1D3 43
1D4
1Q1
2
1Q2
3
1Q3
5
1Q4
6
41
1D5 40
1D6 38
1D7 37
1D8
1Q5
8
1Q6
9
1Q7
11
1Q8
12
4D
36
2D1 35
2D2 33
2D3 32
2D4
2Q1
13
2Q2
14
2Q3
16
2Q4
17
30
2D5 29
2D6 27
2D7 26
2D8
2Q5
19
2Q6
20
2Q7
22
2Q8
23
2EN
24
C4
25
2LE
1
2
logic diagram (positive logic)
1OE
1LE
1D1
To Seven Other Channels
1Q1
2OE
2LE
2D1 2Q1
To Seven Other Channels
1
48
47
24
25
36 C1
1D 132
C1
1D
SN54ABT16373A, SN74ABT16373A
16-BIT TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCBS160C – DECEMBER 1992 – REVISED MAY 1997
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, VI (see Note 1) –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage range applied to any output in the high or power-off state, VO –0.5 V to 5.5 V. . . . . . . . . . . . . . . . . . .
Current into any output in the low state, IO: SN54ABT16373A 96 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SN74ABT16373A 128 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, IIK (VI < 0) –18 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, IOK (VO < 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θJA (see Note 2): DGG package 89°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DL package 94°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, Tstg –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only , and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may af fect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The package thermal impedance is calculated in accordance with EIA/JEDEC Std JESD51.
recommended operating conditions (see Note 3)
SN54ABT16373A SN74ABT16373A
UNIT
MIN MAX MIN MAX
UNIT
VCC Supply voltage 4.5 5.5 4.5 5.5 V
VIH High-level input voltage 2 2 V
VIL Low-level input voltage 0.8 0.8 V
VIInput voltage 0 VCC 0 VCC V
IOH High-level output current –24 –32 mA
IOL Low-level output current 48 64 mA
∆t/∆vInput transition rise or fall rate Outputs enabled 10 10 ns/V
∆t/∆VCC Power-up ramp rate 200 200 µs/V
TAOperating free-air temperature –55 125 –40 85 °C
NOTE 3: Unused inputs must be held high or low to prevent them from floating.
SN54ABT16373A, SN74ABT16373A
16-BIT TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCBS160C – DECEMBER 1992 – REVISED MAY 1997
4POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
TA = 25°C SN54ABT16373A SN74ABT16373A
UNIT
PARAMETER
TEST
CONDITIONS
MIN TYP†MAX MIN MAX MIN MAX
UNIT
VIK VCC = 4.5 V, II = –18 mA –1.2 –1.2 –1.2 V
VCC = 4.5 V, IOH = –3 mA 2.5 2.5 2.5
VOH
VCC = 5 V, IOH = –3 mA 3 3 3
V
V
OH
VCC =45V
IOH = –24 mA 2 2
V
V
CC =
4
.
5
V
IOH = –32 mA 2* 2
VOL
VCC =45V
IOL = 48 mA 0.55 0.55
V
V
OL
V
CC =
4
.
5
V
IOL = 64 mA 0.55* 0.55
V
Vhys 100 mV
IIVCC = 0 to 5.5 V,
VI = VCC or GND ±1±1±1µA
IOZPU‡VCC = 0 to 2.1 V,
VO = 0.5 V to 2.7 V, OE = X ±50 ±50 ±50 µA
IOZPD‡VCC = 2.1 V to 0,
VO = 0.5 V to 2.7 V, OE = X ±50 ±50 ±50 µA
IOZH VCC = 2.1 V to 5.5 V,
VO = 2.7 V, OE ≥ 2 V 10 10 10 µA
IOZL VCC = 2.1 V to 5.5 V,
VO = 0.5 V, OE ≥ 2 V –10 –10 –10 µA
Ioff VCC = 0, VI or VO ≤ 4.5 V ±100 ±100 µA
ICEX Outputs high VCC = 5.5 V, VO = 5.5 V 50 50 50 µA
IO§VCC = 5.5 V, VO = 2.5 V –50 –100 –180 –50 –180 –50 –180 mA
Outputs high
V55VI0
2 2 2
ICC Outputs low VCC = 5.5 V, IO = 0,
VI=V
CC or GND
85 85 85 mA
Outputs disabled
VI
=
VCC
or
GND
2 2 2
∆ICC¶VCC = 5.5 V, One input at 3.4 V,
Other inputs at VCC or GND 1.5 1.5 1.5 mA
CiVI = 2.5 V or 0.5 V 3.5 pF
CoVO = 2.5 V or 0.5 V 9.5 pF
* On products compliant to MIL-PRF-38535, this parameter does not apply.
†All typical values are at VCC = 5 V.
‡This parameter is characterized, but not production tested.
§Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
¶This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND.
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (see Figure 1)
VCC = 5 V,
TA = 25°C#SN54ABT16373A SN74ABT16373A UNIT
MIN MAX MIN MAX MIN MAX
twPulse duration, LE high 3.3 3.3 3.3 ns
tsu Setup time, data before LE↓1.5 2.4 1.5 ns
thHold time, data after LE↓1 2.2 1 ns
#These values apply only to the SN74ABT16373A.
SN54ABT16373A, SN74ABT16373A
16-BIT TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCBS160C – DECEMBER 1992 – REVISED MAY 1997
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, CL = 50 pF (unless otherwise noted) (see Figure 1)
SN54ABT16373A
PARAMETER FROM
(INPUT) TO
(OUTPUT) VCC = 5 V,
TA = 25°CMIN MAX UNIT
MIN TYP MAX
tPLH
D
Q
1.4 3.7 5.3 1.4 6.5
ns
tPHL
D
Q
2 4 5.4 2 6.5
ns
tPLH
LE
Q
1.7 4.1 5.7 1.7 7
ns
tPHL
LE
Q
2.3 4.3 5.6 2.3 6.3
ns
tPZH
OE
Q
1.1 3.4 5 1.1 6.4
ns
tPZL
OE
Q
1.5 3.5 4.9 1.5 5.8
ns
tPHZ
OE
Q
2.4 5.1 7.1 2.4 8.3
ns
tPLZ
OE
Q
1.6 4.4 6.3 1.6 8
ns
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, CL = 50 pF (unless otherwise noted) (see Figure 1)
SN74ABT16373A
PARAMETER FROM
(INPUT) TO
(OUTPUT) VCC = 5 V,
TA = 25°CMIN MAX UNIT
MIN TYP MAX
tPLH
D
Q
1.4 3.7 5.3 1.4 6.3
ns
tPHL
D
Q
2 4 5.4 2 6.2
ns
tPLH
LE
Q
1.7 4.1 5.7 1.7 6.7
ns
tPHL
LE
Q
2.3 4.3 5.6 2.3 6.1
ns
tPZH
OE
Q
1.1 3.4 5 1.1 6.1
ns
tPZL
OE
Q
1.5 3.5 4.9 1.5 5.6
ns
tPHZ
OE
Q
2.4 5.1 7.1 2.4 8.1
ns
tPLZ
OE
Q
1.6 4.4 5.8 1.6 6.5
ns
SN54ABT16373A, SN74ABT16373A
16-BIT TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCBS160C – DECEMBER 1992 – REVISED MAY 1997
6POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
1.5 V
th
tsu
From Output
Under Test
CL = 50 pF
(see Note A)
LOAD CIRCUIT
S1
7 V
Open
GND
500 Ω
500 Ω
Data Input
Timing Input 1.5 V 3 V
0 V
1.5 V 1.5 V
3 V
0 V
3 V
0 V
1.5 V
tw
Input
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
PULSE DURATION
tPLH
tPHL
tPHL
tPLH
VOH
VOH
VOL
VOL
1.5 V 1.5 V 3 V
0 V
1.5 V1.5 V
Input
1.5 V
Output
Control
Output
W aveform 1
S1 at 7 V
(see Note B)
Output
W aveform 2
S1 at Open
(see Note B)
VOL
VOH
tPZL
tPZH
tPLZ
tPHZ
1.5 V1.5 V
3.5 V
0 V
1.5 V VOL + 0.3 V
1.5 V VOH – 0.3 V
≈ 0 V
3 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
Output
Output
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
7 V
Open
TEST S1
NOTES: A. CL includes probe and jig capacitance.
B. W aveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
W aveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2. 5 n s , tf≤ 2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.
1.5 V
Figure 1. Load Circuit and Voltage Waveforms
PACKAGE OPTION ADDENDUM
www.ti.com 10-Dec-2020
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead finish/
Ball material
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
5962-9320001QXA ACTIVE CFP WD 48 1 Non-RoHS &
Non-Green SNPB N / A for Pkg Type -55 to 125 5962-9320001QX
A
SNJ54ABT16373A
WD
74ABT16373ADGGRE4 ACTIVE TSSOP DGG 48 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 ABT16373A
74ABT16373ADGGRG4 ACTIVE TSSOP DGG 48 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 ABT16373A
SN74ABT16373ADGGR ACTIVE TSSOP DGG 48 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 ABT16373A
SN74ABT16373ADL ACTIVE SSOP DL 48 25 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 ABT16373A
SN74ABT16373ADLR ACTIVE SSOP DL 48 1000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 ABT16373A
SN74ABT16373ADLRG4 ACTIVE SSOP DL 48 1000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 ABT16373A
SNJ54ABT16373AWD ACTIVE CFP WD 48 1 Non-RoHS &
Non-Green SNPB N / A for Pkg Type -55 to 125 5962-9320001QX
A
SNJ54ABT16373A
WD
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
PACKAGE OPTION ADDENDUM
www.ti.com 10-Dec-2020
Addendum-Page 2
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN54ABT16373A, SN74ABT16373A :
•Catalog: SN74ABT16373A
•Enhanced Product: SN74ABT16373A-EP, SN74ABT16373A-EP
•Military: SN54ABT16373A
NOTE: Qualified Version Definitions:
•Catalog - TI's standard catalog product
•Enhanced Product - Supports Defense, Aerospace and Medical Applications
•Military - QML certified for Military and Defense Applications
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
SN74ABT16373ADGGR TSSOP DGG 48 2000 330.0 24.4 8.6 13.0 1.8 12.0 24.0 Q1
SN74ABT16373ADLR SSOP DL 48 1000 330.0 32.4 11.35 16.2 3.1 16.0 32.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 11-Mar-2017
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN74ABT16373ADGGR TSSOP DGG 48 2000 367.0 367.0 45.0
SN74ABT16373ADLR SSOP DL 48 1000 367.0 367.0 55.0
PACKAGE MATERIALS INFORMATION
www.ti.com 11-Mar-2017
Pack Materials-Page 2
MECHANICAL DATA
MTSS003D – JANUARY 1995 – REVISED JANUAR Y 1998
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DGG (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE
4040078/F 12/97
48 PINS SHOWN
0,25
0,15 NOM
Gage Plane
6,00
6,20 8,30
7,90
0,75
0,50
Seating Plane
25
0,27
0,17
24
A
48
1
1,20 MAX
M
0,08
0,10
0,50
0°–8°
56
14,10
13,90
48
DIM
A MAX
A MIN
PINS **
12,40
12,60
64
17,10
16,90
0,15
0,05
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
MECHANICAL DATA
MCFP010B – JANUARY 1995 – REVISED NOVEMBER 1997
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
WD (R-GDFP-F**) CERAMIC DUAL FLATPACK
4040176/D 10/97
48 LEADS SHOWN
48
48
25
56
0.610
(18,80)
0.710
(18,03)
0.7400.640
0.390 (9,91)
0.370 (9,40)
0.870 (22,10)
1.130 (28,70)
1
A
0.120 (3,05)
0.075 (1,91)
LEADS**
24
NO. OF
A MIN
A MAX (16,26)
(15,49)
0.025 (0,635)
0.009 (0,23)
0.004 (0,10)
0.370 (9,40)
0.250 (6,35)
0.370 (9,40)
0.250 (6,35)
0.014 (0,36)
0.008 (0,20)
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a ceramic lid using glass frit.
D. Index point is provided on cap for terminal identification only
E. Falls within MIL STD 1835: GDFP1-F48 and JEDEC MO-146AA
GDFP1-F56 and JEDEC MO-146AB
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