FLASH MEMORY
1
K9F1208D0A
K9F1208U0A
K9F1208Q0A K9F1216D0A
K9F1216U0A
K9F1216Q0A
Document Title
64M x 8 Bit , 32M x 16 Bit NAND Flash Memory
Revision History
The attached datasheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right
to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions about device. If you have
any questions, please contact the SAMSUNG branch office near you.
Revision No.
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
Remark
Preliminary
History
Initial issue.
TBGA(K9F12XXX0A-DCB0/DIB0) size information is changed.
(before) 9 x 11 /0.8mm pitch , Width 1.0 mm
(after ) To Be Decided.
TBGA(K9F12XXX0A-DCB0/DIB0) size information is changed.
(before) 9 x 11 /0.8mm pitch , Width 1.0 mm, to
(after) 8.5 x 15 /0.8mm pitch, Width 1.0mm
Pin numbering includes TBGA Dummy ball . (Page5)
Pin numbering excludes TBGA Dummy ball . (Page5)
Pin assignment of TBGA dummy ball is changed.
(before) DNU --> (after) N.C
1. Add the Rp vs tr ,tf & Rp vs ibusy graph for 1.8V device (Page 43)
2. Add the data protection Vcc guidence for 1.8V device - below about
1.1V. (Page 44)
The min. Vcc value 1.8V devices is changed.
K9F12XXQ0A : Vcc 1.65V~1.95V --> 1.70V~1.95V
Pb-free Package is added.
K9F1208U0A-FCB0,FIB0
K9F1208Q0A-HCB0,HIB0
K9F1216U0A-HCB0,HIB0
K9F1216U0A-PCB0,PIB0
K9F1216Q0A-HCB0,HIB0
K9F1208U0A-HCB0,HIB0
K9F1208U0A-PCB0,PIB0
Errata is added.(Front Page)-K9F12XXQ0A
tWC tWH tWP tRC tREH tRP tREA tCEA
Specification 45 15 25 50 15 25 30 45
Relaxed value 60 20 40 60 20 40 40 55
New definition of the number of invalid blocks is added.
(Minimum 1004 valid blocks are guaranteed for each contiguous 128Mb
memory space.)
1. 2.65V device is added.
2. Note is added.
(VIL can undershoot to -0.4V and VIH can overshoot to VCC +0.4V for
durations of 20 ns or less.)
Draft Date
Apr. 25th 2002
May. 9th 2002
July, 10th 2002
Aug, 10th 2002
Oct, 21th 2002
Nov, 21th 2002
Mar. 5th 2003
Mar. 13rd 2003
Mar. 17th 2003
Apr. 4th 2003
Jul. 4th 2003
Note : For more detailed features and specifications including FAQ, please refer to Samsung’s Flash web site.
http://www.samsung.com/Products/Semiconductor/Flash/TechnicalInfo/datasheets.htm
FLASH MEMORY
2
K9F1208D0A
K9F1208U0A
K9F1208Q0A K9F1216D0A
K9F1216U0A
K9F1216Q0A
Document Title
64M x 8 Bit , 32M x 16 Bit NAND Flash Memory
Revision History
The attached datasheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right
to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions about device. If you have
any questions, please contact the SAMSUNG branch office near you.
Revision No.
1.1
RemarkHistory
Errata is deleted.
AC parameters are changed.
tWC tWH tWP tRC tREH tRP tREA tCEA
Before 45 15 25 50 15 25 30 45
After 60 20 40 60 20 40 40 55
Draft Date
Aug. 1st 2003
Note : For more detailed features and specifications including FAQ, please refer to Samsung’s Flash web site.
http://www.samsung.com/Products/Semiconductor/Flash/TechnicalInfo/datasheets.htm
FLASH MEMORY
3
K9F1208D0A
K9F1208U0A
K9F1208Q0A K9F1216D0A
K9F1216U0A
K9F1216Q0A
GENERAL DESCRIPTION
FEATURES
• Voltage Supply
- 1.8V device(K9F12XXQ0A) : 1.70~1.95V
- 2.65V device(K9F12XXD0A) : 2.4~2.9V
- 3.3V device(K9F12XXU0A) : 2.7 ~ 3.6 V
• Organization
- Memory Cell Array
- X8 device(K9F1208X0A) : (64M + 2048K)bit x 8 bit
- X16 device(K9F1216X0A) : (32M + 1024K)bit x 16bit
- Data Register
- X8 device(K9F1208X0A) : (512 + 16)bit x 8bit
- X16 device(K9F1216X0A) : (256 + 8)bit x16bit
• Automatic Program and Erase
- Page Program
- X8 device(K9F1208X0A) : (512 + 16)Byte
- X16 device(K9F1216X0A) : (256 + 8)Word
- Block Erase :
- X8 device(K9F1208X0A) : (16K + 512)Byte
- X16 device(K9F1216X0A) : ( 8K + 256)Word
• Page Read Operation
- Page Size
- X8 device(K9F1208X0A) : (512 + 16)Byte
- X16 device(K9F1216X0A) : (256 + 8)Word
- Random Access : 12µs(Max.)
- Serial Page Access : 50ns(Min.)*
* K9F12XXQ0A : 60ns(Min.)
64M x 8 Bit / 32M x 16 Bit NAND Flash Memory
• Fast Write Cycle Time
- Program time : 200µs(Typ.)
- Block Erase Time : 2ms(Typ.)
• Command/Address/Data Multiplexed I/O Port
• Hardware Data Protection
- Program/Erase Lockout During Power Transitions
• Reliable CMOS Floating-Gate Technology
- Endurance : 100K Program/Erase Cycles
- Data Retention : 10 Years
• Command Register Operation
• Intelligent Copy-Back
• Unique ID for Copyright Protection
• Package
- K9F12XXX0A-YCB0/YIB0
48 - Pin TSOP I (12 x 20 / 0.5 mm pitch)
- K9F12XXX0A-DCB0/DIB0
63- Ball TBGA (8.5 x 15 , 1.0 mm width)
- K9F1208U0A-VCB0/VIB0
48 - Pin WSOP I (12X17X0.7mm)
- K9F12XXX0A-PCB0/PIB0
48 - Pin TSOP I (12 x 20 / 0.5 mm pitch)- Pb-free Package
- K9F12XXX0A-HCB0/HIB0-(8.5 x 15 , 1.0 mm width)
63- Ball TBGA - Pb-free Package
- K9F1208U0A-FCB0/FIB0
48 - Pin WSOP I (12X17X0.7mm)- Pb-free Package
* K9F1208U0A-V,F(WSOPI ) is the same device as
K9F1208U0A-Y,P(TSOP1) except package type.
Offered in 64Mx8bit or 32Mx16bit, the K9F12XXX0A is 512M bit with spare 16M bit capacity. The device is offered in 1.8V, 2.65V,
3.3V Vcc. Its NAND cell provides the most cost-effective solutIon for the solid state mass storage market. A program operation can
be performed in typical 200µs on the 528-byte(X8 device) or 264-word(X16 device) page and an erase operation can be performed in
typical 2ms on a 16K-byte(X8 device) or 8K-word(X16 device) block. Data in the page can be read out at 50ns(1.8V device : 60ns)
cycle time per byte(X8 device) or word(X16 device).. The I/O pins serve as the ports for address and data input/output as well as
command input. The on-chip write control automates all program and erase functions including pulse repetition, where required, and
internal verification and margining of data. Even the write-intensive systems can take advantage of the K9F12XXX0A′s extended reli-
ability of 100K program/erase cycles by providing ECC(Error Correcting Code) with real time mapping-out algorithm. The
K9F12XXX0A is an optimum solution for large nonvolatile storage applications such as solid state file storage and other portable
applications requiring non-volatility.
PRODUCT LIST
Part Number Vcc Range Organization PKG Type
K9F1208Q0A-D,H 1.70 ~ 1.95V X8 TBGA
K9F1216Q0A-D,H X16
K9F1208D0A-Y,P
2.4 ~ 2.9V
X8 TSOP1
K9F1208D0A-D,H TBGA
K9F1216D0A-Y,P X16 TSOP1
K9F1216D0A-D,H TBGA
K9F1208U0A-Y,P
2.7 ~ 3.6V
X8 TSOP1
K9F1208U0A-D,H TBGA
K9F1208U0A-V,F WSOP1
K9F1216U0A-Y,P X16 TSOP1
K9F1216U0A-D,P TBGA
FLASH MEMORY
4
K9F1208D0A
K9F1208U0A
K9F1208Q0A K9F1216D0A
K9F1216U0A
K9F1216Q0A
PIN CONFIGURATION (TSOP1)
K9F12XXU0A-YCB0,PCB0/YIB0,PIB0
N.C
N.C
N.C
N.C
N.C
N.C
R/B
RE
CE
N.C
N.C
Vcc
Vss
N.C
N.C
CLE
ALE
WE
WP
N.C
N.C
N.C
N.C
N.C
Vss
I/O15
I/O7
I/O14
I/O6
I/O13
I/O5
I/O12
I/O4
N.C
N.C
Vcc
N.C
N.C
N.C
I/O11
I/O3
I/O10
I/O2
I/O9
I/O1
I/O8
I/O0
Vss
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
N.C
N.C
N.C
N.C
N.C
N.C
R/B
RE
CE
N.C
N.C
Vcc
Vss
N.C
N.C
CLE
ALE
WE
WP
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
I/O7
I/O6
I/O5
I/O4
N.C
N.C
N.C
Vcc
Vss
N.C
N.C
N.C
I/O3
I/O2
I/O1
I/O0
N.C
N.C
N.C
N.C
X8X16 X16X8
PACKAGE DIMENSIONS
48-PIN LEAD/LEAD FREE PLASTIC THIN SMALL OUT-LINE PACKAGE TYPE(I)
48 - TSOP1 - 1220F Unit :mm/Inch
0.787±0.008
20.00±0.20
#1
#24
0.20+0.07
-0.03
0.008+0.003
-0.001
0.50
0.0197
#48
#25
0.488
12.40MAX
12.00
0.472
0.10
0.004 MAX
0.25
0.010
( )
0.039±0.002
1.00±0.05 0.002
0.05 MIN
0.047
1.20 MAX
0.45~0.75
0.018~0.030
0.724±0.004
18.40±0.10
0~8°
0.010
0.25 TYP
0.125+0.075
0.035
0.005+0.003
-0.001
0.50
0.020
( )
FLASH MEMORY
5
K9F1208D0A
K9F1208U0A
K9F1208Q0A K9F1216D0A
K9F1216U0A
K9F1216Q0A
K9F12XXX0A-DCB0,HCB0/DIB0,HIB0
R/B/WE/CEVssALE/WP
/RE CLE
NCNC
NC NC Vcc
NCNC I/O0
I/O1NC NC VccQ I/O5 I/O7
VssI/O6I/O4I/O3I/O2Vss
NC
NC
NC
NC NC
NC
NC NC
NC
NC
NC
NC
NC NC NC
NC
NC
NC
NC
NC
N.C
N.C N.C
N.C
N.C N.C
N.C
N.C
N.C N.C
N.CN.C
N.C N.C
N.C
N.C
N.C N.C
N.C
N.C N.C
N.C
N.C
N.C N.C
N.CN.C
N.C N.C
N.C
R/B/WE/CEVssALE/WP
/RE CLE
I/O7I/O5
I/O12 IO14 Vcc
I/O10I/O8 I/O1
I/O9I/O0 I/O3 VccQ I/O6 I/O15
VssI/O13I/O4I/O11I/O2Vss
NC
NC
NC
NC NC
NC
NC NC
NC
NC
NC
NC
NC NC NC
NC
NC
NC
NC
NC
X16
X8
PIN CONFIGURATION (TBGA)
3 4 5 6 1 2
A
B
C
D
G
E
F
H
3 4 5 6 1 2
A
B
C
D
G
E
F
H
Top View Top View
FLASH MEMORY
6
K9F1208D0A
K9F1208U0A
K9F1208Q0A K9F1216D0A
K9F1216U0A
K9F1216Q0A
8.50±0.10
#A1
Side View
Top View
63-Ball TBGA (measured in millimeters)
0.90±0.10
0.45±0.05
4 3 2 1
A
B
C
D
G
Bottom View
15.00±0.10
63-∅0.45±0.05
0.80 x 7= 5.60
15.00±0.10
0.80 x 5= 4.00
0.80
0.32±0.05
0.10MAX
B
A
2.80
2.00
8.50±0.10
(Datum B)
(Datum A)
0.20
M
A B
∅
0.80
0.80 x 11= 8.80
0.80 x 9= 7.20
6 5
15.00±0.10
E
F
H
#A1 INDEX MARK(OPTIONAL)
FLASH MEMORY
7
K9F1208D0A
K9F1208U0A
K9F1208Q0A K9F1216D0A
K9F1216U0A
K9F1216Q0A
PIN CONFIGURATION (WSOP1)
K9F1208U0A-VCB0,FCB0/VIB0,FIB0
PACKAGE DIMENSIONS
48-PIN LEAD/LEAD FREE PLASTIC VERY VERY THIN SMALL OUT-LINE PACKAGE TYPE (I)
48 - WSOP1 - 1217F Unit :mm
15.40±0.10
#1
#24
0.20 +0.07
-0.03 0.16 +0.07
-0.03
0.50TYP
(0.50±0.06)
#48
#25
12.00±0.10
0.10+0.075
-0.035
0.58±0.04
0.70 MAX
(0.1Max)
17.00±0.20
0°~8°
0.45~0.75
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
N.C
N.C
DNU
N.C
N.C
N.C
R/B
RE
CE
DNU
N.C
Vcc
Vss
N.C
DNU
CLE
ALE
WE
WP
N.C
N.C
DNU
N.C
N.C
N.C
N.C
DNU
N.C
I/O7
I/O6
I/O5
I/O4
N.C
DNU
N.C
Vcc
Vss
N.C
DNU
N.C
I/O3
I/O2
I/O1
I/O0
N.C
DNU
N.C
N.C
FLASH MEMORY
8
K9F1208D0A
K9F1208U0A
K9F1208Q0A K9F1216D0A
K9F1216U0A
K9F1216Q0A
PIN DESCRIPTION
NOTE : Connect all VCC and VSS pins of each device to common power supply outputs.
Do not leave VCC or VSS disconnected.
Pin Name Pin Function
I/O0 ~ I/O7
(K9F1208X0A)
I/O0 ~ I/O15
(K9F1216X0A)
DATA INPUTS/OUTPUTS
The I/O pins are used to input command, address and data, and to output data during read operations. The
I/O pins float to high-z when the chip is deselected or when the outputs are disabled.
I/O8 ~ I/O15 are used only in X16 organization device. Since command input and address input are x8 oper-
ation, I/O8 ~ I/O15 are not used to input command & address. I/O8 ~ I/O15 are used only for data input and
output.
CLE COMMAND LATCH ENABLE
The CLE input controls the activating path for commands sent to the command register. When active high,
commands are latched into the command register through the I/O ports on the rising edge of the WE signal.
ALE ADDRESS LATCH ENABLE
The ALE input controls the activating path for address to the internal address registers. Addresses are
latched on the rising edge of WE with ALE high.
CE
CHIP ENABLE
The CE input is the device selection control. When the device is in the Busy state, CE high is ignored, and
the device does not return to standby mode in program or erase operation. Regarding CE control during
read operation, refer to ’Page read’ section of Device operation .
RE READ ENABLE
The RE input is the serial data-out control, and when active drives the data onto the I/O bus. Data is valid
tREA after the falling edge of RE which also increments the internal column address counter by one.
WE WRITE ENABLE
The WE input controls writes to the I/O port. Commands, address and data are latched on the rising edge of
the WE pulse.
WP WRITE PROTECT
The WP pin provides inadvertent write/erase protection during power transitions. The internal high voltage
generator is reset when the WP pin is active low.
R/B
READY/BUSY OUTPUT
The R/B output indicates the status of the device operation. When low, it indicates that a program, erase or
random read operation is in process and returns to high state upon completion. It is an open drain output and
does not float to high-z condition when the chip is deselected or when outputs are disabled.
VccQOUTPUT BUFFER POWER
VccQ is the power supply for Output Buffer.
VccQ is internally connected to Vcc, thus should be biased to Vcc.
Vcc POWER
VCC is the power supply for device.
Vss GROUND
N.C NO CONNECTION
Lead is not internally connected.
DNU DO NOT USE
Leave it disconnected.
FLASH MEMORY
9
K9F1208D0A
K9F1208U0A
K9F1208Q0A K9F1216D0A
K9F1216U0A
K9F1216Q0A
512Byte 16 Byte
Figure 1-1. K9F1208X0A (X8) FUNCTIONAL BLOCK DIAGRAM
Figure 2-1. K9F1208X0A (X8) ARRAY ORGANIZATION
VCC
X-Buffers 512M + 16M Bit
Command
NAND Flash
ARRAY
(512 + 16)Byte x 131072
Y-Gating
Page Register & S/A
I/O Buffers & Latches
Latches
& Decoders
Y-Buffers
Latches
& Decoders
Register
Control Logic
& High Voltage
Generator Global Buffers Output
Driver
VSS
A9 - A25
A0 - A7
Command
CE
RE
WE
WP
I/0 0
I/0 7
VCC/VCCQ
VSS
A8
1st half Page Register
(=256 Bytes) 2nd half Page Register
(=256 Bytes)
128K Pages
(=4,096 Blocks)
512 Byte
8 bit
16 Byte
1 Block =32 Pages
= (16K + 512) Byte
I/O 0 ~ I/O 7
1 Page = 528 Byte
1 Block = 528 Byte x 32 Pages
= (16K + 512) Byte
1 Device = 528Bytes x 32Pages x 4096 Blocks
= 528 Mbits
Column Address
Row Address
(Page Address)
Page Register
CLE ALE
NOTE : Column Address : Starting Address of the Register.
00h Command(Read) : Defines the starting address of the 1st half of the register.
01h Command(Read) : Defines the starting address of the 2nd half of the register.
* A8 is set to "Low" or "High" by the 00h or 01h Command.
* L must be set to "Low".
* The device ignores any additional input of address cycles than reguired.
I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
1st Cycle A0A1A2A3A4A5A6A7
2nd Cycle A9A10 A11 A12 A13 A14 A15 A16
3rd Cycle A17 A18 A19 A20 A21 A22 A23 A24
4th Cycle A25 *L *L *L *L *L *L *L
FLASH MEMORY
10
K9F1208D0A
K9F1208U0A
K9F1208Q0A K9F1216D0A
K9F1216U0A
K9F1216Q0A
256Word 8 Word
Figure 2-2. K9F1216X0A (X16) ARRAY ORGANIZATION
NOTE : Column Address : Starting Address of the Register.
* L must be set to "Low".
* The device ignores any additional input of address cycles than reguired.
I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 I/O8 to 15
1st Cycle A0A1A2A3A4A5A6A7L*
2nd Cycle A9A10 A11 A12 A13 A14 A15 A16 L*
3rd Cycle A17 A18 A19 A20 A21 A22 A23 A24 L*
4th Cycle A25 L* L* L* L* L* L* L* L*
Page Register
(=256 Words)
128K Pages
(=4,096 Blocks)
256 Word
16 bit
8 Word
1 Block =32 Pages
= (8K + 256) Word
I/O 0 ~ I/O 15
1 Page = 264 Word
1 Block = 264 Word x 32 Pages
= (8K + 256) Word
1 Device = 264Words x 32Pages x 4096 Blocks
= 528 Mbits
Column Address
Row Address
(Page Address)
Page Register
Figure 1-2. K9F1216X0A (X16) FUNCTIONAL BLOCK DIAGRAM
VCC
X-Buffers 5126M + 16M Bit
Command
NAND Flash
ARRAY
(256 + 8)Word x 131072
Y-Gating
Page Register & S/A
I/O Buffers & Latches
Latches
& Decoders
Y-Buffers
Latches
& Decoders
Register
Control Logic
& High Voltage
Generator Global Buffers Output
Driver
VSS
A9 - A25
A0 - A7
Command
CE
RE
WE
WP
I/0 0
I/0 15
VCC/VCCQ
VSS
CLE ALE
FLASH MEMORY
11
K9F1208D0A
K9F1208U0A
K9F1208Q0A K9F1216D0A
K9F1216U0A
K9F1216Q0A
Product Introduction
The K9F1208X0A is a 528Mbit(553,648,218 bit) memory organized as 131,072 rows(pages) by 528 columns. Spare sixteen columns
are located from column address of 512 to 527. A 528-byte(x8 device), 264word(x16 device) data register is connected to memory
cell arrays accommodating data transfer between the I/O buffers and memory during page read and page program operations. The
memory array is made up of 16 cells that are serially connected to form a NAND structure. Each of the 16 cells resides in a different
page. A block consists of two NAND structured strings. A NAND structure consists of 16 cells. Total 135168 NAND cells reside in a
block. The array organization is shown in Figure 2. The program and read operations are executed on a page basis, while the erase
operation is executed on a block basis. The memory array consists of 4,096 separately erasable 16K-byte blocks. It indicates that the
bit by bit erase operation is prohibited on the K9F1208X0A.
The K9F1208X0A has addresses multiplexed into 8 I/O's. This scheme dramatically reduces pin counts and allows systems upgrades
to future densities by maintaining consistency in system board design. Command, address and data are all written through I/O's by
bringing WE to low while CE is low. Data is latched on the rising edge of WE. Command Latch Enable(CLE) and Address Latch
Enable(ALE) are used to multiplex command and address respectively, via the I/O pins. The 64M byte physical space requires 26
addresses(X8 device) or 25 addresses(X16 device), thereby requiring four cycles for byte-level addressing: column address, low row
address and high row address, in that order. Page Read and Page Program need the same four address cycles following the required
command input. In Block Erase operation, however, only the three row address cycles are used. Device operations are selected by
writing specific commands into the command register. Table 1 defines the specific commands of the K9F1208X0A.
The device provides simultaneous program/erase capability up to four pages/blocks. By dividing the memory array into four 128Mbit
separate planes, simultaneous multi-plane operation dramatically increases program/erase performance by 4X while still maintaining
the conventional 512 byte(X8 device) or 256 word(X16 device) structure.
The extended pass/fail status for multi-plane program/erase allows system software to quickly identify the failing page/block out of
selected multiple pages/blocks. Usage of multi-plane operations will be described further throughout this document.
In addition to the enhanced architecture and interface, the device incorporates copy-back program feature from one page to another
of the same plane without the need for transporting the data to and from the external buffer memory. Since the time-consuming burst-
reading and data-input cycles are removed, system performance for solid-state disk application is significantly increased.
The device includes one block sized OTP(One Time Programmable), which can be used to increase system security or to provide
identification capabilities. Detailed information can be obtained by contact with Samsung.
Table 1. Command Sets
NOTE : 1. The 00h command defines starting address of the 1st half of registers.
The 01h command defines starting address of the 2nd half of registers.
After data access on the 2nd half of register by the 01h command, the status pointer is
automatically moved to the 1st half register(00h) on the next cycle.
2. Page Program(True) and Copy-Back Program(True) are available on 1 plane operation.
Page Program(Dummy) and Copy-Back Program(Dummy) are available on the 2nd,3rd,4th plane of multi plane operation.
3. The 71h command should be used for read status of Multi Plane operation.
Caution : Any undefined command inputs are prohibited except for above command set of Table 1.
Function 1st. Cycle 2nd. Cycle 3rd. Cycle Acceptable Command
during Busy
Read 1 00h/01h(1) - -
Read 2 50h - -
Read ID 90h - -
Reset FFh - - O
Page Program (True)(2) 80h 10h -
Page Program (Dummy)(2) 80h 11h -
Copy-Back Program(True)(2) 00h 8Ah 10h
Copy-Back Program(Dummy)(2) 03h 8Ah 11h
Block Erase 60h D0h -
Multi-Plane Block Erase 60h----60h D0h -
Read Status 70h - - O
Read Multi-Plane Status 71h(3) - - O
FLASH MEMORY
12
K9F1208D0A
K9F1208U0A
K9F1208Q0A K9F1216D0A
K9F1216U0A
K9F1216Q0A
The device is arranged in four 128Mbit memory planes. Each plane contains 1,024 blocks and 528 byte(X8 device) or 264 word(X16
device) page registers. This allows it to perform simultaneous page program and block erase by selecting one page or block from
each plane. The block address map is configured so that multi-plane program/erase operations can be executed for every four
sequential blocks.
Plane 0 Plane 1 Plane 2 Plane 3
(1024 Block) (1024 Block) (1024 Block) (1024 Block)
Page 0
Page 1
Page 31
Page 30
Memory Map
Block 0
Page 0
Page 1
Page 31
Page 30
Block 1
Page 0
Page 1
Page 31
Page 30
Block 2
Page 0
Page 1
Page 31
Page 30
Block 3
Page 0
Page 1
Page 31
Page 30
Block 4
Page 0
Page 1
Page 31
Page 30
Block 5
Page 0
Page 1
Page 31
Page 30
Block 6
Page 0
Page 1
Page 31
Page 30
Block 7
Page 0
Page 1
Page 31
Page 30
Block 4088
Page 0
Page 1
Page 31
Page 30
Block 4089
Page 0
Page 1
Page 31
Page 30
Block 4090
Page 0
Page 1
Page 31
Page 30
Block 4091
Page 0
Page 1
Page 31
Page 30
Block 4092
Page 0
Page 1
Page 31
Page 30
Block 4093
Page 0
Page 1
Page 31
Page 30
Block 4094
Page 0
Page 1
Page 31
Page 30
Block 4095
528byte Page Registers
Figure 3. Memory Array Map
528byte Page Registers 528byte Page Registers 528byte Page Registers
FLASH MEMORY
13
K9F1208D0A
K9F1208U0A
K9F1208Q0A K9F1216D0A
K9F1216U0A
K9F1216Q0A
RECOMMENDED OPERATING CONDITIONS
(Voltage reference to GND, K9F12XXX0A-XCB0 :TA=0 to 70°C, K9F12XXX0A-XIB0:TA=-40 to 85°C)
Parameter Symbol K9F12XXQ0A(1.8V) K9F12XXD0A(2.65V) K9F12XXU0A(3.3V) Unit
Min Typ. Max Min Typ. Max Min Typ. Max
Supply Voltage VCC 1.70 1.8 1.95 2.4 2.65 2.9 2.7 3.3 3.6 V
Supply Voltage VCCQ 1.70 1.8 1.95 2.4 2.65 2.9 2.7 3.3 3.6 V
Supply Voltage VSS 0 0 0 0 0 0 0 0 0 V
ABSOLUTE MAXIMUM RATINGS
NOTE :
1. Minimum DC voltage is -0.6V on input/output pins. During transitions, this level may undershoot to -2.0V for periods <30ns.
Maximum DC voltage on input/output pins is VCC,+0.3V which, during transitions, may overshoot to VCC+2.0V for periods <20ns.
2. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to the conditions
as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Parameter Symbol Rating Unit
1.8V DEVICE 3.3V/2.65V DEVICE
Voltage on any pin relative to VSS
VIN/OUT -0.6 to + 2.45 -0.6 to + 4.6
V
VCC -0.2 to + 2.45 -0.6 to + 4.6
VCCQ -0.2 to + 2.45 -0.6 to + 4.6
Temperature Under Bias K9F12XXX0A-XCB0 TBIAS -10 to +125 °C
K9F12XXX0A-XIB0 -40 to +125
Storage Temperature K9F12XXX0A-XCB0 TSTG -65 to +150 °C
K9F12XXX0A-XIB0
Short Circuit Current Ios 5mA
FLASH MEMORY
14
K9F1208D0A
K9F1208U0A
K9F1208Q0A K9F1216D0A
K9F1216U0A
K9F1216Q0A
DC AND OPERATING CHARACTERISTICS(Recommended operating conditions otherwise noted.)
NOTE : VIL can undershoot to -0.4V and VIH can overshoot to VCC +0.4V for durations of 20 ns or less.
Parameter Symbol Test Conditions
K9F12XXX0A Unit
1.8V 2.65V 3.3V
Min Typ Max Min Typ Max Min Typ Max
Operating
Current
Sequential Read ICC1tRC=50ns, CE=VIL
IOUT=0mA -8 15 -10 20 -10 20
mA
Program ICC2- - 8 15 -10 20 -10 20
Erase ICC3- - 8 15 -10 20 -10 20
Stand-by Current(TTL) ISB1CE=VIH, WP=0V/VCC - - 1- - 1- - 1
Stand-by Current(CMOS) ISB2CE=VCC-0.2, WP=0V/VCC -10 50 -10 50 -10 50
µA
Input Leakage Current ILI VIN=0 to Vcc(max) - - ±10 - - ±10 - - ±10
Output Leakage Current ILO VOUT=0 to Vcc(max) - - ±10 - - ±10 - - ±10
Input High Voltage VIH*
I/O pins VCCQ
-0.4 -VCCQ
+0.3 VCCQ
-0.4 -VCCQ
+0.3 2.0 -VCCQ
+0.3
V
Except I/O pins VCC
-0.4 -VCC
+0.3 VCC
-0.4 -VCC
+0.3 2.0 -VCC
+0.3
Input Low Voltage, All
inputs VIL* --0.3 -0.4 -0.3 -0.5 -0.3 -0.8
Output High Voltage Level VOH
K9F12XXQ0A :IOH=-100µA
K9F12XXD0A :IOH=-100µA
K9F12XXU0A :IOH=-400µA
VCCQ
-0.1 - - VCCQ
-0.4 - - 2.4 - -
Output Low Voltage Level VOL
K9F12XXQ0A :IOL=100uA
K9F12XXD0A :IOL=100µA
K9F12XXU0A :IOL=2.1mA - - 0.1 - - 0.4 - - 0.4
Output Low Current(R/B)IOL(R/B)K9F12XXQ0A :VOL=0.1V
K9F12XXD0A :VOL=0.1V
K9F12XXU0A :VOL=0.4V 3 4 -3 4 -8 10 -mA
FLASH MEMORY
15
K9F1208D0A
K9F1208U0A
K9F1208Q0A K9F1216D0A
K9F1216U0A
K9F1216Q0A
CAPACITANCE(TA=25°C, VCC=1.8V/2.65V/3.3V, f=1.0MHz)
NOTE : Capacitance is periodically sampled and not 100% tested.
Item Symbol Test Condition Min Max Unit
Input/Output Capacitance CI/O VIL=0V -10 pF
Input Capacitance CIN VIN=0V -10 pF
VALID BLOCK
NOTE :
1. The device may include invalid blocks when first shipped. Additional invalid blocks may develop while being used. The number of valid blocks is pre-
sented with both cases of invalid blocks considered. Invalid blocks are defined as blocks that contain one or more bad bits. Do not erase or program
factory-marked bad blocks. Refer to the attached technical notes for a appropriate management of invalid blocks.
2. The 1st block, which is placed on 00h block address, is fully guaranteed to be a valid block, does not require Error Correction.
3. Minimum 1004 valid blocks are guaranteed for each contiguous 128Mb memory space.
Parameter Symbol Min Typ. Max Unit
Valid Block Number NVB 4,026 -4,096 Blocks
AC TEST CONDITION
(K9F12XXX0A-XCB0 :TA=0 to 70°C, K9F12XXX0A-XIB0:TA=-40 to 85°C
K9F12XXQ0A : Vcc=1.70V~1.95V , K9F12XXD0A : Vcc=2.4V~2.9V , K9F12XXU0A : Vcc=2.7V~3.6V unless otherwise noted)
Parameter K9F12XXQ0A K9F12XXD0A K9F12XXU0A
Input Pulse Levels 0V to VccQ0V to VccQ0.4V to 2.4V
Input Rise and Fall Times 5ns 5ns 5ns
Input and Output Timing Levels VccQ/2 VccQ/2 1.5V
K9F12XXQ0A:Output Load (VccQ:1.8V +/-10%)
K9F12XXD0A:Output Load (VccQ:2.65V +/-10%)
K9F12XXU0A:Output Load (VccQ:3.0V +/-10%) 1 TTL GATE and CL=30pF1 TTL GATE and CL=30pF1 TTL GATE and CL=50pF
K9F12XXU0A:Output Load (VccQ:3.3V +/-10%) - - 1 TTL GATE and CL=100pF
MODE SELECTION
NOTE : 1. X can be VIL or VIH.
2. WP should be biased to CMOS high or CMOS low for standby.
CLE ALE CE WE RE WP Mode
HL L HXRead Mode Command Input
LHLHX Address Input(4clock)
HL L H H Write Mode Command Input
LHLH H Address Input(4clock)
LLL H H Data Input
LLLHX Data Output
LLLH H XDuring Read(Busy) on K9F12XXX0A-Y,P or K9F1208U0A-V,F
X X X X HXDuring Read(Busy) on the devices except K9F12XXX0A-Y,P and
K9F1208U0A-V,F
X X X X X H During Program(Busy)
X X X X X H During Erase(Busy)
XX(1) XXXL Write Protect
X X HX X 0V/VCC(2) Stand-by
FLASH MEMORY
16
K9F1208D0A
K9F1208U0A
K9F1208Q0A K9F1216D0A
K9F1216U0A
K9F1216Q0A
AC TIMING CHARACTERISTICS FOR COMMAND / ADDRESS / DATA INPUT
NOTE: 1. If tCS is set less than 10ns, tWP must be minimum 35ns, otherwise, tWP may be minimum 25ns.
Parameter Symbol Min Max Unit
K9F12XXQ0A K9F12XXD0A K9F12XXU0A K9F12XXQ0A K9F12XXD0A K9F12XXU0A
CLE setup Time tCLS 0 0 0 - - - ns
CLE Hold Time tCLH 10 10 10 - - - ns
CE setup Time tCS 0 0 0 - - - ns
CE Hold Time tCH 10 10 10 - - - ns
WE Pulse Width tWP 40 25(1) 25(1) - - - ns
ALE setup Time tALS 0 0 0 - - - ns
ALE Hold Time tALH 10 10 10 - - - ns
Data setup Time tDS 20 20 20 - - - ns
Data Hold Time tDH 10 10 10 - - - ns
Write Cycle Time tWC 60 45 45 - - - ns
WE High Hold Time tWH 20 15 15 - - - ns
PROGRAM / ERASE CHARACTERISTICS
Parameter Symbol Min Typ Max Unit
Program Time tPROG -200 500 µs
Dummy Busy Time for Multi Plane Program tDBSY 1 10 µs
Number of Partial Program Cycles
in the Same Page Main Array Nop - - 1cycle
Spare Array - - 2cycles
Block Erase Time tBERS -2 3 ms
FLASH MEMORY
17
K9F1208D0A
K9F1208U0A
K9F1208Q0A K9F1216D0A
K9F1216U0A
K9F1216Q0A
AC CHARACTERISTICS FOR OPERATION
NOTE: 1. If reset command(FFh) is written at Ready state, the device goes into Busy for maximum 5us.
2. To break the sequential read cycle, CE must be held high for longer time than tCEH.
3. The time to Ready depends on the value of the pull-up resistor tied R/B pin.
Parameter Symbol Min Max Unit
K9F12XXQ0A K9F12XXD0A K9F12XXU0A K9F12XXQ0A K9F12XXD0A K9F12XXU0A
Data Transfer from Cell to Register tR---12 12 12 µs
ALE to RE Delay tAR 10 10 10 - - - ns
CLE to RE Delay tCLR 10 10 10 - - - ns
Ready to RE Low tRR 20 20 20 - - - ns
RE Pulse Width tRP 40 25 25 - - - ns
WE High to Busy tWB ---100 100 100 ns
Read Cycle Time tRC 60 50 50 - - - ns
RE Access Time tREA ---40 30 30 ns
CE Access Time tCEA ---55 45 45 ns
RE High to Output Hi-Z tRHZ ---30 30 30 ns
CE High to Output Hi-Z tCHZ ---20 20 20 ns
RE or CE High to Output hold tOH 15 15 15 - - - ns
RE High Hold Time tREH 20 15 15 - - - ns
Output Hi-Z to RE Low tIR 0 0 0 - - - ns
WE High to RE Low tWHR 60 60 60 - - - ns
Parameter Symbol Min Max Unit
K9F1208U0A-
Y,V,P,F only
Last RE High to Busy(at sequential read) tRB -100 ns
CE High to Ready(in case of interception by CE at read) tCRY -50 +tr(R/B)(3) ns
CE High Hold Time(at the last serial read)(2) tCEH 100 -ns
FLASH MEMORY
18
K9F1208D0A
K9F1208U0A
K9F1208Q0A K9F1216D0A
K9F1216U0A
K9F1216Q0A
NAND Flash Technical Notes
Identifying Invalid Block(s)
Invalid Block(s)
Invalid blocks are defined as blocks that contain one or more invalid bits whose reliability is not guaranteed by Samsung. The infor-
mation regarding the invalid block(s) is so called as the invalid block information. Devices with invalid block(s) have the same quality
level as devices with all valid blocks and have the same AC and DC characteristics. An invalid block(s) does not affect the perfor-
mance of valid block(s) because it is isolated from the bit line and the common source line by a select transistor. The system design
must be able to mask out the invalid block(s) via address mapping. The 1st block, which is placed on 00h block address, is fully guar-
anteed to be a valid block, does not require Error Correction.
All device locations are erased(FFh) except locations where the invalid block(s) information is written prior to shipping. The invalid
block(s) status is defined by the 6th byte(X8 device) or 1st word(X16 device) in the spare area. Samsung makes sure that either the
1st or 2nd page of every invalid block has non-FFh(X8 device) or non-FFFFh(X16 device) data at the column address of 517(X8
device) or 256 and 261(X16 device). Since the invalid block information is also erasable in most cases, it is impossible to recover the
information once it has been erased. Therefore, the system must be able to recognize the invalid block(s) based on the original
invalid block information and create the invalid block table via the following suggested flow chart(Figure 4). Any intentional erasure of
the original invalid block information is prohibited.
*Check "FFh" at the column address
Figure 4. Flow chart to create invalid block table.
Start
Set Block Address = 0
Check "FFh" ?
Increment Block Address
Last Block ?
End
No
Yes
Yes
Create (or update) No
Invalid Block(s) Table of the 1st and 2nd page in the block
517(X8 device) or 256 and 261(X16 device)
FLASH MEMORY
19
K9F1208D0A
K9F1208U0A
K9F1208Q0A K9F1216D0A
K9F1216U0A
K9F1216Q0A
NAND Flash Technical Notes (Continued)
Program Flow Chart
Start
I/O 6 = 1 ?
Write 00h
I/O 0 = 0 ?
No
*
If ECC is used, this verification
Write 80h
Write Address
Write Data
Write 10h
Read Status Register
Write Address
Wait for tR Time
Verify Data No
Program Completed
or R/B = 1 ?
Program Error
Yes
No
Yes
*
Program Error
Yes
: If program operation results in an error, map out
the block including the page in error and copy the
target data to another block.
*
operation is not needed.
Error in write or read operation
Within its life time, the additional invalid blocks may develop with NAND Flash memory. Refer to the qualification report for the actual
data.The following possible failure modes should be considered to implement a highly reliable system. In the case of status read fail-
ure after erase or program, block replacement should be done. Because program status fail during a page program does not affect
the data of the other pages in the same block, block replacement can be executed with a page-sized buffer by finding an erased
empty block and reprogramming the current target data and copying the rest of the replaced block. To improve the efficiency of mem-
ory space, it is recommended that the read or verification failure due to single bit error be reclaimed by ECC without any block
replacement. The said additional block failure rate does not include those reclaimed blocks.
Failure Mode Detection and Countermeasure sequence
Write
Erase Failure Status Read after Erase --> Block Replacement
Program Failure Status Read after Program --> Block Replacement
Read back ( Verify after Program) --> Block Replacement
or ECC Correction
Read Single Bit Failure Verify ECC -> ECC Correction
ECC : Error Correcting Code --> Hamming Code etc.
Example) 1bit correction & 2bit detection
FLASH MEMORY
20
K9F1208D0A
K9F1208U0A
K9F1208Q0A K9F1216D0A
K9F1216U0A
K9F1216Q0A
Erase Flow Chart
Start
I/O 6 = 1 ?
I/O 0 = 0 ?
No
*
Write 60h
Write Block Address
Write D0h
Read Status Register
or R/B = 1 ?
Erase Error
Yes
No
: If erase operation results in an error, map out
the failing block and replace it with another block.
*
Erase Completed
Yes
Read Flow Chart
Start
Verify ECC
No
Write 00h
Write Address
Read Data
ECC Generation
Reclaim the Error
Page Read Completed
Yes
NAND Flash Technical Notes (Continued)
Block Replacement
* Step1
When an error happens in the nth page of the Block ’A’ during erase or program operation.
* Step2
Copy the nth page data of the Block ’A’ in the buffer memory to the nth page of another free block. (Block ’B’)
* Step3
Then, copy the data in the 1st ~ (n-1)th page to the same location of the Block ’B’.
* Step4
Do not further erase Block ’A’ by creating an ’invalid Block’ table or other appropriate scheme.
Buffer memory of the controller.
1st Block A
Block B
(n-1)th
nth
(page)
1
2
{
∼
1st
(n-1)th
nth
(page)
{
∼
an error occurs.
FLASH MEMORY
21
K9F1208D0A
K9F1208U0A
K9F1208Q0A K9F1216D0A
K9F1216U0A
K9F1216Q0A
Samsung NAND Flash has three address pointer commands as a substitute for the two most significant column addresses. ’00h’
command sets the pointer to ’A’ area(0~255byte), ’01h’ command sets the pointer to ’B’ area(256~511byte), and ’50h’ command sets
the pointer to ’C’ area(512~527byte). With these commands, the starting column address can be set to any of a whole
page(0~527byte). ’00h’ or ’50h’ is sustained until another address pointer command is inputted. ’01h’ command, however, is effective
only for one operation. After any operation of Read, Program, Erase, Reset, Power_Up is executed once with ’01h’ command, the
address pointer returns to ’A’ area by itself. To program data starting from ’A’ or ’C’ area, ’00h’ or ’50h’ command must be inputted
before ’80h’ command is written. A complete read operation prior to ’80h’ command is not necessary. To program data starting from
’B’ area, ’01h’ command must be inputted right before ’80h’ command is written.
00h
(1) Command input sequence for programming ’A’ area
Address / Data input
80h 10h 00h 80h 10h
Address / Data input
The address pointer is set to ’A’ area(0~255), and sustained
01h
(2) Command input sequence for programming ’B’ area
Address / Data input
80h 10h 01h 80h 10h
Address / Data input
’B’, ’C’ area can be programmed.
It depends on how many data are inputted. ’01h’ command must be rewritten before
every program operation
The address pointer is set to ’B’ area(256~511), and will be reset to
’A’ area after every program operation is executed.
50h
(3) Command input sequence for programming ’C’ area
Address / Data input
80h 10h 50h 80h 10h
Address / Data input
Only ’C’ area can be programmed. ’50h’ command can be omitted.
The address pointer is set to ’C’ area(512~527), and sustained
’00h’ command can be omitted.
It depends on how many data are inputted.
’A’,’B’,’C’ area can be programmed.
Pointer Operation of K9F1208X0A(X8)
Table 2. Destination of the pointer
Command Pointer position Area
00h
01h
50h
0 ~ 255 byte
256 ~ 511 byte
512 ~ 527 byte
1st half array(A)
2nd half array(B)
spare array(C)
"A" area
256 Byte
(00h plane) "B" area
(01h plane) "C" area
(50h plane)
256 Byte 16 Byte
"A" "B" "C"
Internal
Page Register
Pointer select
commnad
(00h, 01h, 50h) Pointer
Figure 5. Block Diagram of Pointer Operation
FLASH MEMORY
22
K9F1208D0A
K9F1208U0A
K9F1208Q0A K9F1216D0A
K9F1216U0A
K9F1216Q0A
Samsung NAND Flash has two address pointer commands as a substitute for the most significant column address. ’00h’ command
sets the pointer to ’A’ area(0~255word), and ’50h’ command sets the pointer to ’B’ area(256~263word). With these commands, the
starting column address can be set to any of a whole page(0~263word). ’00h’ or ’50h’ is sustained until another address pointer com-
mand is inputted. To program data starting from ’A’ or ’B’ area, ’00h’ or ’50h’ command must be inputted before ’80h’ command is writ-
ten. A complete read operation prior to ’80h’ command is not necessary.
00h
(1) Command input sequence for programming ’A’ area
Address / Data input
80h 10h 00h 80h 10h
Address / Data input
The address pointer is set to ’A’ area(0~255), and sustained
50h
(2) Command input sequence for programming ’B’ area
Address / Data input
80h 10h 50h 80h 10h
Address / Data input
Only ’B’ area can be programmed. ’50h’ command can be omitted.
The address pointer is set to ’B’ area(256~263), and sustained
’00h’ command can be omitted.
It depends on how many data are inputted.
’A’,’B’ area can be programmed.
Pointer Operation of K9F1216X0A(X16)
Table 3. Destination of the pointer
Command Pointer position Area
00h
50h 0 ~ 255 word
256 ~ 263 word main array(A)
spare array(B)
"A" area
256 Word
(00h plane) "B" area
(50h plane)
8 Word
"A" "B"
Internal
Page Register
Pointer select
command
(00h, 50h) Pointer
Figure 6. Block Diagram of Pointer Operation
FLASH MEMORY
23
K9F1208D0A
K9F1208U0A
K9F1208Q0A K9F1216D0A
K9F1216U0A
K9F1216Q0A
System Interface Using CE don’t-care.
CE
WE tWP
tCH
tCS
Start Add.(4Cycle)80h Data Input
CE
CLE
ALE
WE
I/OXData Input
CE don’t-care
≈
≈
10h
For an easier system interface, CE may be inactive during the data-loading or sequential data-reading as shown below. The internal
528byte 1264word page registers are utilized as separate buffers for this operation and the system design gets more flexible. In addi-
tion, for voice or audio applications which use slow cycle time on the order of u-seconds, de-activating CE during the data-loading and
reading would provide significant savings in power consumption.
Start Add.(4Cycle)00h
CE
CLE
ALE
WE
I/OXData Output(sequential)
CE don’t-care
≈
R/BtR
RE
tCEA
out
tREA
CE
RE
I/OX
Figure 7. Program Operation with CE don’t-care.
Figure 8. Read Operation with CE don’t-care.
On K9F1208U0A-Y,P or K9F1208U0A-V,F
CE must be held
low during tR
FLASH MEMORY
24
K9F1208D0A
K9F1208U0A
K9F1208Q0A K9F1216D0A
K9F1216U0A
K9F1216Q0A
Command Latch Cycle
CE
WE
CLE
ALE
I/OXCommand
Address Latch Cycle
tCLS
tCS
tCLH
tCH
tWP
tALS tALH
tDS tDH
NOTE: 1. I/O8~15 must be set to "0" during command or address input.
I/O8~15 are used only for data bus.
Device I/O DATA
I/Ox Data In/Out
K9F1208X0A(X8 device) I/O 0 ~ I/O 7 ~528byte
K9F1216X0A(X16 device) I/O 0 ~ I/O 151) ~264word
CE
WE
CLE
ALE
I/OXA0~A7
tCLS
tCS tWC
tWP
tALS
tDS tDH
tALH tALS
tWH
tWC
tWP
tDS tDH
tALH tALS
tWH
tWC
tWP
tDS tDH
tALH tALS
tWH tALH
tDS tDH
tWP
A9~A16 A17~A24 A25
FLASH MEMORY
25
K9F1208D0A
K9F1208U0A
K9F1208Q0A K9F1216D0A
K9F1216U0A
K9F1216Q0A
Input Data Latch Cycle
CE
CLE
WE
DIN 0 DIN 1 DIN n
ALE tALS
tCLH
tWC
tCH
tDS tDH tDS tDH tDS tDH
tWP
tWH
tWP tWP
Serial access Cycle after Read(CLE=L, WE=H, ALE=L)
RE
CE
R/B
Dout Dout Dout
tRC
tREA
tRR
tOH
tREA
tREH tREA tOH
tRHZ*
≈
≈
≈
≈≈≈≈
NOTES : Transition is measured ±200mV from steady state voltage with load.
This parameter is sampled and not 100% tested.
I/Ox
I/Ox
tCHZ*
tRHZ*
FLASH MEMORY
26
K9F1208D0A
K9F1208U0A
K9F1208Q0A K9F1216D0A
K9F1216U0A
K9F1216Q0A
tCHZ
tOH
Status Read Cycle
CE
WE
CLE
RE
I/OX70h Status Output
tCLR
tCLH
tCS
tWP tCH
tDS tDH tREA
tIR tOH
tOH
tWHR
tCEA
tCLS
READ1 OPERATION (READ ONE PAGE)
X8 device : m = 528 , Read CMD = 00h or 01h
X16 device : m = 264 , Read CMD = 00h
1)
NOTES : 1) is only valid on K9F1208U0A-Y,P or K9F1208U0A-V,F
On K9F1208U0A-Y,P or K9F1208U0A-V,F
CE must be held
low during tR
1)
CE
CLE
R/B
I/OX
WE
ALE
RE
Busy
00h or 01h A0 ~ A7A9 ~ A16 A17 ~ A24 Dout N Dout N+1 Dout N+2
Column
Address Page(Row)
Address
tWB tAR
tRtRC tRHZ
tRR
Dout m
tRB
tCRY
tWC
≈≈ ≈
A25
tCEH
1)
N Address
tCHZ
tRHZ
tOH
≈ ≈ ≈ ≈ ≈ ≈ ≈ ≈
FLASH MEMORY
27
K9F1208D0A
K9F1208U0A
K9F1208Q0A K9F1216D0A
K9F1216U0A
K9F1216Q0A
On K9F1208U0A-Y,P or K9F1208U0A-V,F
CE must be held
low during tR
On K9F1208U0A-Y,P or K9F1208U0A-V,F
CE must be held
low during tR
Read1 Operation (Intercepted by CE)
CE
CLE
R/B
I/OX
WE
ALE
RE
Busy
00h or 01h A0 ~ A7A9 ~ A16 A17 ~ A24 Dout N Dout N+1 Dout N+2
Page(Row)
Address
Address
Column
tWB tAR tCHZ
tR
tRR
tRC
Read2 Operation (Read One Page)
CE
CLE
R/B
I/OX
WE
ALE
RE
50h A0 ~ A7A9 ~ A16 A17 ~ A24 Dout n+m
M Address
n+M
tAR
tR
tWB
tRR
A0~A3 : Valid Address
A4~A7 : Don′t care
≈
≈
A25
A25
Selected
Row
Start
address M
512 16
tOH
≈≈≈≈≈≈≈≈
FLASH MEMORY
28
K9F1208D0A
K9F1208U0A
K9F1208Q0A K9F1216D0A
K9F1216U0A
K9F1216Q0A
Page Program Operation
CE
CLE
R/B
I/OX
WE
ALE
RE
80h 70h I/O0
Din
NDin 10h
527
A0 ~ A7A17 ~ A24A9 ~ A16
Sequential Data
Input Command Column
Address Page(Row)
Address 1 up to 528 Byte Data
Serial Input Program
Command Read Status
Command
I/O0=0 Successful Program
I/O0=1 Error in Program
tPROG
tWB
tWC tWC tWC
Sequential Row Read Operation (Within a Block)
CE
CLE
R/B
I/OX
WE
ALE
RE
00h A0 ~ A7
Busy
M
Output
A9 ~ A16 A17 ~ A24 Dout
NDout
N+1 Dout
527 Dout
0Dout
1Dout
527
Busy
M+1
Output
N
Ready
≈≈
≈
≈
≈
≈
A25
≈
≈
≈
A25
≈
≈ ≈ ≈ ≈ ≈ ≈ ≈
≈ ≈ ≈
FLASH MEMORY
29
K9F1208D0A
K9F1208U0A
K9F1208Q0A K9F1216D0A
K9F1216U0A
K9F1216Q0A
BLOCK ERASE OPERATION (ERASE ONE BLOCK)
CE
CLE
R/B
I/OX
WE
ALE
RE
60h A17 ~ A24A9 ~ A16
Auto Block Erase Setup Command Erase Command Read Status
Command I/O0=1 Error in Erase
DOh 70h I/O 0
Busy
tWB tBERS
I/O0=0 Successful Erase
Page(Row)
Address
tWC
A25
FLASH MEMORY
30
K9F1208D0A
K9F1208U0A
K9F1208Q0A K9F1216D0A
K9F1216U0A
K9F1216Q0A
Multi-Plane Page Program Operation
CE
CLE
R/B
I/OX
WE
ALE
RE
80h Din
NDin11h
m
A
0
~ A
7
A
17
~ A
24
A
9
~ A
16
Sequential Data
Input Command Column
Address Page(Row)
Address 1 up to 528 Byte Data
Serial Input
Program
Max. three times repeatable
tDBSY
tWB
tWC
≈
≈
≈
A
25
≈
Command
Last Plane Input & Program
t
DBSY :
typ. 1us
max. 10us
(Dummy)
Din
NDin10h
527
A
0
~ A
7
A
17
~ A
24
A
9
~ A
16
tPROG
tWB
≈≈
≈
A
25
≈
I/O
80h
A0 ~ A7 & A9 ~ A25
I/O0~7
R/B
528 Byte Data
Address &
Data Input11h 80h Address &
Data Input11h 80h Address &
Data Input11h 80h Address &
Data Input10h
Ex.) Four-Plane Page Program
tDBSY tDBSY tDBSY tPROG
Program Confirm
Command
(True)
80h 71h
71h
Read Multi-Plane
Status Command
A0 ~ A7 & A9 ~ A25
528 Byte DataA0 ~ A7 & A9 ~ A25
528 Byte DataA0 ~ A7 & A9 ~ A25
528 Byte Data
≈≈ ≈ ≈ ≈ ≈ ≈
≈ ≈ ≈ ≈ ≈≈≈
FLASH MEMORY
31
K9F1208D0A
K9F1208U0A
K9F1208Q0A K9F1216D0A
K9F1216U0A
K9F1216Q0A
Multi-Plane Block Erase Operation
Block Erase Setup Command Erase Confirm Command
Read Multi-Plane
StatusCommand
Max. 4 times repeatable
60h
A9 ~ A25
I/O0~7
R/B
Address
60h A9 ~ A25
60h A9 ~ A25
60h A9 ~ A25
D0h 71h
tBERS
* For Multi-Plane Erase operation, Block address to be erased should be repeated before "D0H" command.
Ex.) Four-Plane Block Erase Operation
CE
CLE
R/B
I/OX
WE
ALE
RE
60h A17 ~ A24A9 ~ A16 DOh 71h I/O 0
Busy
tWB tBERS
Page(Row)
Address
tWC
A25
FLASH MEMORY
32
K9F1208D0A
K9F1208U0A
K9F1208Q0A K9F1216D0A
K9F1216U0A
K9F1216Q0A
Read ID Operation
CE
CLE
I/OX
WE
ALE
RE
90h
Read ID Command Maker Code
00h ECh Device
tREA
Address. 1cycle
A5h C0h
Multi Plane Code
ID Defintition Table
90 ID : Access command = 90H
Description
1st Byte
2nd Byte
3rd Byte
4th Byte
Maker Code
Device Code
Must be don’t -cared
Supports Multi Plane Operation
Device Device Code
K9F1208Q0A 36h
K9F1208D0A 76h
K9F1208U0A 76h
K9F1216Q0A XX46h
K9F1216D0A XX56h
K9F1216U0A XX56h
Code
FLASH MEMORY
33
K9F1208D0A
K9F1208U0A
K9F1208Q0A K9F1216D0A
K9F1216U0A
K9F1216Q0A
Copy-Back Program Operation
CE
CLE
R/B
I/OX
WE
ALE
RE
00h 70h I/O0
8Ah
A0~A7A17~A24A9~A16
Column
Address Page(Row)
Address Read Status
Command
I/O0=0 Successful Program
I/O0=1 Error in Program
tPROG
tWB
tWC
A0~A7A17~A24A9~A16
Column
Address Page(Row)
Address
Busy
tWB
tR
≈
A25 A25 10h
Copy-Back Data
Input Command
On K9F1208U0A-Y,P or K9F1208U0A-V,F
CE must be held low during tR
Busy
≈
≈ ≈ ≈ ≈ ≈ ≈
≈ ≈ ≈ ≈ ≈ ≈ ≈ ≈ ≈ ≈
≈
FLASH MEMORY
34
K9F1208D0A
K9F1208U0A
K9F1208Q0A K9F1216D0A
K9F1216U0A
K9F1216Q0A
Device Operation
PAGE READ
Upon initial device power up, the device defaults to Read1 mode. This operation is also initiated by writing 00h to the command regis-
ter along with four address cycles. Once the command is latched, it does not need to be written for the following page read operation.
Three types of operations are available : random read, serial page read and sequential row read.
The random read mode is enabled when the page address is changed. The 528 bytes(x8 device) or 264words(x16 device)of data
within the selected page are transferred to the data registers in less than 12µs(tR). The system controller can detect the completion of
this data transfer(tR) by analyzing the output of R/B pin. CE must be held low while in busy for K9F12XXU0A-YXB0 or K9F1208U0A-
VXB0, while CE is don’t-care with K9F12XXX0A-DXB0. If CE goes high before the device returns to Ready, the random read opera-
tion is interrupted and Busy returns to Ready as the defined by tCRY. Since the operation was aborted, the serial page read does not
output valid data. Once the data in a page is loaded into the registers, they may be read out in 50ns(1.8V device : 60ns) cycle time by
sequentially pulsing RE. High to low transitions of the RE clock output the data stating from the selected column address up to the last
column address.
The way the Read1 and Read2 commands work is like a pointer set to either the main area or the spare area. The spare area of 512
to 527 bytes (x8 device) or 256 to 263 words(x16 device)may be selectively accessed by writing the Read2 command. Addresses A0
to A3 set the starting address of the spare area while addresses A4 to A7 are ignored. The Read1 command(00h/01h) is needed to
move the pointer back to the main area. Figures 7 to 10 show typical sequence and timings for each read operation.
Sequential Row Read is available only on K9F12XXX0A-Y,P or K9F1208U0A-V,F :
After the data of last column address is clocked out, the next page is automatically selected for sequential row read. Waiting 10µs
again allows reading the selected page. The sequential row read operation is terminated by bringing CE high. Unless the operation
is aborted, the page address is automatically incremented for sequential row read as in Read1 operation and spare sixteen bytes of
each page may be sequentially read. The Sequential Read 1 and 2 operation is allowed only within a block and after the last page of
a block is readout, the sequential read operation must be terminated by bringing CE high. When the page address moves onto the
next block, read command and address must be given. Figures 9, 10 show typical sequence and timings for sequential row read
operation.
FLASH MEMORY
35
K9F1208D0A
K9F1208U0A
K9F1208Q0A K9F1216D0A
K9F1216U0A
K9F1216Q0A
Figure 7. Read1 Operation
Start Add.(4Cycle)00h Data Output(Sequential)
CE
CLE
ALE
R/B
WE
I/O0~7
RE
tR
On K9F1208U0A-Y,P or K9F1208U0A-V,F
CE must be held low during tR
X8 device : A0 ~ A7 & A9 ~ A25 (00h Command)
Data Field Spare Field
Main array
(01h Command)
Data Field Spare Field
1st half array 2st half array
NOTE: 1) After data access on 2nd half array by 01h command, the start pointer is automatically moved to 1st half
array (00h) at next cycle. 01h command is only available on X8 device(K9F1208X0A).
X16 device : A0 ~ A7 & A9 ~ A25 1)
FLASH MEMORY
36
K9F1208D0A
K9F1208U0A
K9F1208Q0A K9F1216D0A
K9F1216U0A
K9F1216Q0A
Figure 8. Read2 Operation
50h Data Output(Sequential)
Spare Field
CE
CLE
ALE
R/B
WE
Start Add.(4Cycle)
I/OX
RE
Figure 9. Sequential Row Read1 Operation (only for K9F1208U0A-Y,P and K9F1208U0A-V,F valid within a block)
00h
01h A0 ~ A7 & A9 ~ A25
I/OX
R/B
Start Add.(4Cycle) Data Output Data Output Data Output
1st 2nd Nth
(528 Byte) (528 Byte)
tRtRtR
tR
The Sequential Read 1 and 2 operation is allowed only within a block and after the last page of a block is read-
out, the sequential read operation must be terminated by bringing CE high. When the page address moves onto
the next block, read command and address must be given.
≈
( 00h Command)
Data Field Spare Field
( 01h Command)
Data Field Spare Field
1st half array 2nd half array
1st
2nd
Nth
1st half array 2nd half array
1st
2nd
Nth
Block
On K9F1208U0A-Y,P or K9F1208U0A-V,F
CE must be held low during tR
X8 device : A0 ~ A3 & A9 ~ A25
Main array
Data Field Spare Field
X16 device : A0 ~ A2 & A9 ~ A25
X8 device : A4 ~ A7 Don’t care
X16 device : A3 ~ A7 are "L"
FLASH MEMORY
37
K9F1208D0A
K9F1208U0A
K9F1208Q0A K9F1216D0A
K9F1216U0A
K9F1216Q0A
Figure 10. Sequential Row Read2 Operation (only for K9F1208U0A-Y,P and K9F1208U0A-V,F valid within a block)
PAGE PROGRAM
The device is programmed basically on a page basis, but it does allow multiple partial page programing of a byte or consecutive bytes
up to 528 bytes(x8 device) or 264words(x16 device), in a single page program cycle. The number of consecutive partial page pro-
gramming operation within the same page without an intervening erase operation must not exceed 1 for main array and 2 for spare
array. The addressing may be done in any random order in a block. A page program cycle consists of a serial data loading period in
which up to 528 bytes(x8 device) or 264words(x16 device) of data may be loaded into the page register, followed by a non-volatile
programming period where the loaded data is programmed into the appropriate cell. Serial data loading can be started from 2nd half
array by moving pointer. About the pointer operation, please refer to the attached technical notes.
The serial data loading period begins by inputting the Serial Data Input command(80h), followed by the four cycle address input and
then serial data loading. The bytes other than those to be programmed do not need to be loaded.The Page Program confirm com-
mand(10h) initiates the programming process. Writing 10h alone without previously entering the serial data will not initiate the pro-
gramming process. The internal write state control automatically executes the algorithms and timings necessary for program and
verify, thereby freeing the system controller for other tasks. Once the program process starts, the Read Status Register command
may be entered, with RE and CE low, to read the status register. The system controller can detect the completion of a program cycle
by monitoring the R/B output, or the Status bit(I/O 6) of the Status Register. Only the Read Status command and Reset command are
valid while programming is in progress. When the Page Program is complete, the Write Status Bit(I/O 0) may be checked(Figure 11).
The internal write verify detects only errors for "1"s that are not successfully programmed to "0"s. The command register remains in
Read Status command mode until another valid command is written to the command register.
50h
A0 ~ A3 & A9 ~ A25
I/OX
R/B
Start Add.(4Cycle) Data Output Data Output Data Output
2nd Nth
(16Byte) (16Byte)
1st
Figure 11. Program & Read Status Operation
80h
A0 ~ A7 & A9 ~ A25
I/O0~7
R/B
Address & Data Input I/O0Pass
528 Byte Data
10h 70h
Fail
tRtRtR
tPROG
≈
Data Field Spare Field
1st
Block
(A4 ~ A7 :
Don’t Care)
Nth
FLASH MEMORY
38
K9F1208D0A
K9F1208U0A
K9F1208Q0A K9F1216D0A
K9F1216U0A
K9F1216Q0A
Figure 12. Block Erase Operation
BLOCK ERASE
The Erase operation is done on a block(16K Byte) basis. Block address loading is accomplished in three cycles initiated by an Erase
Setup command(60h). Only address A14 to A25 is valid while A9 to A13 is ignored. The Erase Confirm command(D0h) following the
block address loading initiates the internal erasing process. This two-step sequence of setup followed by execution command
ensures that memory contents are not accidentally erased due to external noise conditions.
At the rising edge of WE after the erase confirm command input, the internal write controller handles erase and erase-verify. When
the erase operation is completed, the Write Status Bit(I/O 0) may be checked. Figure 12 details the sequence.
60h
Block Add. : A14 ~ A25
I/OX
R/B
Address Input(3Cycle) I/O0Pass
D0h 70h
Fail
tBERS
Multi-Plane Page Program
Multi-Plane Page Program is an extension of Page Program, which is executed for a single plane with 528 byte page registers. Since
the device is equipped with four memory planes, activating the four sets of 528 byte page registers enables a simultaneous program-
ming of four pages. Partial activation of four planes is also permitted.
After writing the first set of data up to 528 byte into the selected page register, Dummy Page Program command (11h) instead of
actual Page Program (10h) is inputted to finish data-loading of the current plane and move to the next plane. Since no programming
process is involved, R/B remains in Busy state for a short period of time(tDBSY). Read Status command (standard 70h or alternate
71h) may be issued to find out when the device returns to Ready state by polling the Ready/Busy status bit(I/O 6). Then the next set
of data for one of the other planes is inputted with the same command and address sequences. After inputting data for the last plane,
actual True Page Program (10h) instead of dummy Page Program command (11h) must be followed to start the programming pro-
cess. The operation of R/B and Read Status is the same as that of Page Program. Since maximum four pages are programmed
simultaneously, pass/fail status is available for each page when the program operation completes. The extended status bits (I/O1
through I/O 4) are checked by inputting the Read Multi-Plane Status Register. Status bit of I/O 0 is set to "1" when any of the pages
fails. Multi-Plane page Program with "01h" pointer is not supported, thus prohibited.
Figure 13. Four-Plane Page Program
80h 11h 80h 11h 80h 11h 80h 10h
Data
Input
Plane 0 Plane 1 Plane 2 Plane 3
(1024 Block) (1024 Block) (1024 Block) (1024 Block)
Block 0
Block 4
Block 4092
Block 4088
Block 1
Block 5
Block 4093
Block 4089
Block 2
Block 6
Block 4094
Block 4090
Block 3
Block 7
Block 4095
Block 4091
80h
A0 ~ A7 & A9 ~ A25
I/OX
R/B
528 bytes(x8 device)
Address &
Data Input 11h 80h Address &
Data Input 11h 80h Address &
Data Input 11h 80h Address &
Data Input 10h
tDBSY tDBSY tDBSY tPROG
71h
or 264words(x16 device)
FLASH MEMORY
39
K9F1208D0A
K9F1208U0A
K9F1208Q0A K9F1216D0A
K9F1216U0A
K9F1216Q0A
Restriction in addressing with Multi Plane Page Program
While any block in each plane may be addressable for Multi-Plane Page Program, the five least significant addresses(A9-A13) for the
selected pages at one operation must be the same. Figure 14 shows an example where 2nd page of each addressed block is
selected for four planes. However, any arbitrary sequence is allowed in addressing multiple planes as shown in Figure15.
80h Plane 2 11h 80h 11h 80h 11h 80h 10h
Plane 0 Plane3 Plane 1
Plane 0 Plane 1 Plane 2 Plane 3
(1024 Block) (1024 Block) (1024 Block) (1024 Block)
Page 0
Page 1
Page 31
Page 30
Block 0
Page 0
Page 1
Page 31
Page 30
Block 1
Page 0
Page 1
Page 31
Page 30
Block 2
Page 0
Page 1
Page 31
Page 30
Block 3
Figure 16. Multi-Plane Page Program & Read Status Operation
80h
A0 ~ A7 & A9 ~ A25
I/O0~7
R/B
Address & Data Input I/O Pass
10h 71h
Fail
tPROG
Last Plane input
Multi-Plane Block Erase
Basic concept of Multi-Plane Block Erase operation is identical to that of Multi-Plane Page Program. Up to four blocks, one from each
plane can be simultaneously erased. Standard Block Erase command sequences (Block Erase Setup command followed by three
address cycles) may be repeated up to four times for erasing up to four blocks. Only one block should be selected from each plane.
The Erase Confirm command initiates the actual erasing process. The completion is detected by analyzing R/B pin or Ready/Busy
status (I/O 6). Upon the erase completion, pass/fail status of each block is examined by reading extended pass/fail status(I/O 1
through I/O 4).
Figure 17. Four Block Erase Operation
60h
A0 ~ A7 & A9 ~ A25
I/OX
R/B
Address
60h 60h 60h D0h 71h I/O Pass
Fail
tBERS
(3 Cycle) Address
(3 Cycle) Address
(3 Cycle) Address
(3 Cycle)
Figure 14. Multi-Plane Program & Read Status Operation
Figure 15. Addressing Multiple Planes
528 bytes(x8 device)
or 264words(x16 device)
FLASH MEMORY
40
K9F1208D0A
K9F1208U0A
K9F1208Q0A K9F1216D0A
K9F1216U0A
K9F1216Q0A
Copy-Back Program
Figure 18. One Page Copy-Back program Operation
00h
A0 ~ A7 & A9 ~ A25
I/OX
R/B
Add.(4Cycles) I/O0Pass
8Ah 70h
Fail
tPROG
A0 ~ A7 & A9 ~ A25
Add.(4Cycles)
tR
Source Address Destination Address
The copy-back program is configured to quickly and efficiently rewrite data stored in one page within the plane to another page within
the same plane without utilizing an external memory. Since the time-consuming sequently-reading and its re-loading cycles are
removed, the system performance is improved. The benefit is especially obvious when a portion of a block is updated and the rest of
the block also need to be copied to the newly assigned free block. The operation for performing a copy-back program is a sequential
execution of page-read without burst-reading cycle and copying-program with the address of destination page. A normal read opera-
tion with "00h" command and the address of the source page moves the whole 528byte data into the internal page registers. As soon
as the device returns to Ready state, Page-Copy Data-input command (8Ah) with the address cycles of destination page followed
may be written. The Program Confirm command (10h) is required to actually begin the programming operation. Copy-Back Program
operation is allowed only within the same memory plane. Once the Copy-Back Program is finished, any additional partial page pro-
gramming into the copied pages is prohibited before erase. A14 and A15 must be the same between source and target page.
Figure18 shows the command sequence for single plane operation. "When there is a program-failure at Copy-Back operation,
error is reported by pass/fail status. But, if Copy-Back operations are accumulated over time, bit error due to charge loss is
not checked by external error detection/correction scheme. For this reason, two bit error correction is recommended for the
use of Copy-Back operation."
10h
FLASH MEMORY
41
K9F1208D0A
K9F1208U0A
K9F1208Q0A K9F1216D0A
K9F1216U0A
K9F1216Q0A
Multi-Plane Copy-Back Program
Multi-Plane Copy-Back Program is an extension of one page Copy-Back Program into four plane operation. Since the device is
equipped with four memory planes, activating the four sets of 528 bytes(x8 device) or 264words(x16 device)page registers enables a
simultaneous Multi-Plane Copy-Back programming of four pages. Partial activation of four planes is also permitted.
First, normal read operation with the "00h"command and address of the source page moves the whole 528 byte data into internal
page buffers. Any further read operation for transferring the addressed pages to the corresponding page register must be executed
with "03h" command instead of "00h" command. Any plane may be selected without regard to "00h" or "03h". Up to four planes may
be addressed. Data moved into the internal page registers are loaded into the destination plane addresses. After the input of com-
mand sequences for reading the source pages, the same procedure as Multi-Plane Page programming except for a replacement
address command with "8Ah" is executed. Since no programming process is involved during data loading at the destination plane
address , R/B remains in Busy state for a short period of time(tDBSY). Read Status command (standard 70h or alternate 71h) may be
issued to find out when the device returns to Ready state by polling the Ready/Busy status bit(I/O 6). After inputting data for the last
plane, actual True Page Program (10h) instead of dummy Page Program command (11h) must be followed to start the programming
process. The operation of R/B and Read Status is the same as that of Page Program. Since maximum four pages are programmed
simultaneously, pass/fail status is available for each page when the program operation completes. No pointer operation is supported
with Multi-Plane Copy-Back Program. Once the Multi-Plane Copy-Back Program is finished, any additional partial page pro-
gramming into the copied pages is prohibited before erase once the Multi-Plane Copy-Back Program is finished.
Figure 19. Four-Plane Copy-Back Program
8Ah 11h 8Ah 11h 8Ah 11h 8Ah 10h
Destination
Plane 0 Plane 1 Plane 2 Plane 3
(1024 Block) (1024 Block) (1024 Block) (1024 Block)
Block 0
Block 4
Block 4092
Block 4088
Block 1
Block 5
Block 4093
Block 4089
Block 2
Block 6
Block 4094
Block 4090
Block 3
Block 7
Block 4095
Block 4091
00h 03h 03h 03h
Source
Plane 0 Plane 1 Plane 2 Plane 3
(1024 Block) (1024 Block) (1024 Block) (1024 Block)
Block 4
Block 4092
Block 4088
Block 5
Block 4093
Block 2
Block 6
Block 4094
Block 4090
Block 3
Block 7
Block 4095
Block 4091
Address
Address
Input
Input
Block 0 Block 1
Block 4089
Block 4089
Max Three Times Repeatable
Max Three Times Repeatable
FLASH MEMORY
42
K9F1208D0A
K9F1208U0A
K9F1208Q0A K9F1216D0A
K9F1216U0A
K9F1216Q0A
00h
A0 ~ A7 & A9 ~ A25
I/OX
R/B
Source Address
Add.(4Cyc.)03h
Figure 20. Four-Plane Copy-Back Page Program (Continued)
tRtDBSY
A0 ~ A7 & A9 ~ A25
Destination Address
Add.(4Cyc.)11h 71h
A0 ~ A7 & A9 ~ A25
Source Address
Add.( 4Cyc.)
8Ah
03h
A0 ~ A7 & A9 ~ A25
Source Address
Add.( 4Cyc.)
≈
≈
A0 ~ A7 & A9 ~ A25
Destination Address
Add.(4Cyc.)11h
8Ah
A0 ~ A7 & A9 ~ A25
Destination Address
Add.(4Cyc.)10h
8Ah
tRtPROG
tDBSY
Max. 4 times ( 4 Cycle Source Address Input) repeatableMax. 4 times (4 Cycle Destination Address Input) repeatable
tR : Normal Read Busy tDBSY : Typical 1us, Max 10us
≈
≈≈
≈
tR
FLASH MEMORY
43
K9F1208D0A
K9F1208U0A
K9F1208Q0A K9F1216D0A
K9F1216U0A
K9F1216Q0A
READ STATUS
The device contains a Status Register which may be read to find out whether program or erase operation is completed, and whether
the program or erase operation is completed successfully. After writing 70h command to the command register, a read cycle outputs
the content of the Status Register to the I/O pins on the falling edge of CE or RE, whichever occurs last. This two line control allows
the system to poll the progress of each device in multiple memory connections even when R/B pins are common-wired. RE or CE
does not need to be toggled for updated status. Refer to table 4 for specific Status Register definitions. The command register
remains in Status Read mode until further commands are issued to it. Therefore, if the status register is read during a random read
cycle, a read command(00h or 50h) should be given before sequential page read cycle.
For Read Status of Multi Plane Program/Erase, the Read Multi-Plane Status command(71h) should be used to find out whether
multi-plane program or erase operation is completed, and whether the program or erase operation is completed successfully. The
pass/fail status data must be checked only in the Ready condition after the completion of Multi-Plane program or erase operation.
Table4. Read Staus Register Definition
NOTE : 1. I/O 0 describes combined Pass/Fail condition for all planes. If any of the selected multiple pages/blocks fails in Program/
Erase operation, it sets "Fail" flag.
2. The pass/fail status applies only to the corresponding plane.
I/O No. Status Definition by 70h Command Definition by 71h Command
I/O 0 Total Pass/Fail Pass : "0" Fail : "1" Pass : "0"(1) Fail : "1"
I/O 1 Plane 0 Pass/Fail Must be don’t -cared Pass : "0"(2) Fail : "1"
I/O 2 Plane 1 Pass/Fail Must be don’t -cared Pass : "0"(2) Fail : "1"
I/O 3 Plane 2 Pass/Fail Must be don’t -cared Pass : "0"(2) Fail : "1"
I/O 4 Plane 3 Pass/Fail Must be don’t -cared Pass : "0"(2) Fail : "1"
I/O 5 Reserved Must be don’t -cared Must be don’t-cared
I/O 6 Device Operation Busy : "0" Ready : "1" Busy : "0" Ready : "1"
I/O 7 Write Protect Protected : "0" Not Protected : "1" Protected : "0" Not Protected : "1"
FLASH MEMORY
44
K9F1208D0A
K9F1208U0A
K9F1208Q0A K9F1216D0A
K9F1216U0A
K9F1216Q0A
Read ID
The device contains a product identification mode, initiated by writing 90h to the command register, followed by an address input of
00h. Four read cycles sequentially output the manufacture code(ECh), and the device code, Reserved(A5h), Multi plane operation
code(C0h) respectively. A5h must be don’t-cared. C0h means that device supports Multi Plane operation. The command register
remains in Read ID mode until further commands are issued to it. Figure 21 shows the operation sequence.
Figure 21. Read ID Operation 1
CE
CLE
I/O0~7
ALE
RE
WE
90h 00h ECh
Address. 1cycle Maker code Device code
tCEA
tAR
tREA Device A5h C0h
Multi-Plane code
tWHR
Code
Device Device Code
K9F1208Q0A 36h
K9F1208D0A 76h
K9F1208U0A 76h
K9F1216Q0A XX46h
K9F1216D0A XX56h
K9F1216U0A XX56h
FLASH MEMORY
45
K9F1208D0A
K9F1208U0A
K9F1208Q0A K9F1216D0A
K9F1216U0A
K9F1216Q0A
Figure 22. RESET Operation
RESET
The device offers a reset feature, executed by writing FFh to the command register. When the device is in Busy state during random
read, program or erase mode, the reset operation will abort these operations. The contents of memory cells being altered are no
longer valid, as the data will be partially programmed or erased. The command register is cleared to wait for the next command, and
the Status Register is cleared to value C0h when WP is high. Refer to table 5 for device status after reset operation. If the device is
already in reset state a new reset command will not be accepted by the command register. The R/B pin transitions to low for tRST
after the Reset command is written. Refer to Figure 22 below.
Table5. Device Status
After Power-up After Reset
Operation Mode Read 1 Waiting for next command
FFh
I/O0~7
R/BtRST
FLASH MEMORY
46
K9F1208D0A
K9F1208U0A
K9F1208Q0A K9F1216D0A
K9F1216U0A
K9F1216Q0A
READY/BUSY
The device has a R/B output that provides a hardware method of indicating the completion of a page program, erase and random
read completion. The R/B pin is normally high but transitions to low after program or erase command is written to the command regis-
ter or random read is started after address loading. It returns to high when the internal controller has finished the operation. The pin is
an open-drain driver thereby allowing two or more R/B outputs to be Or-tied. Because pull-up resistor value is related to tr(R/B) and
current drain during busy(ibusy) , an appropriate value can be obtained with the following reference chart(Fig 23). Its value can be
determined by the following guidance.
VCC
R/B
open drain output
Device
GND
Rp
Figure 23. Rp vs tr ,tf & Rp vs ibusy
ibusy
Busy
Ready Vcc
VOH
tf tr
VOL
1.8V device - VOL : 0.1V, VOH : VccQ-0.1V
3.3V device - VOL : 0.4V, VOH : 2.4V
C
L
2.65V device - VOL : 0.4V, VOH : VccQ-0.4V
FLASH MEMORY
47
K9F1208D0A
K9F1208U0A
K9F1208Q0A K9F1216D0A
K9F1216U0A
K9F1216Q0A
tr,tf [s]
Ibusy [A]
Rp(ohm)
Ibusy
tr
@ Vcc = 3.3V, Ta = 25°C , CL = 100pF
1K 2K 3K 4K
100n
200n
300n 3m
2m
1m
100
tf
200
300
400
3.6 3.6 3.6 3.6
2.4
1.2
0.8
0.6
Rp(min, 1.8V part) = VCC(Max.) - VOL(Max.)
IOL + ΣIL = 1.85V
3mA + ΣIL
where IL is the sum of the input currents of all devices tied to the R/B pin.
Rp value guidance
Rp(max) is determined by maximum permissible limit of tr
Rp(min, 3.3V part) = VCC(Max.) - VOL(Max.)
IOL + ΣIL = 3.2V
8mA + ΣIL
tr,tf [s]
Ibusy [A]
Rp(ohm)
Ibusy
tr
@ Vcc = 1.8V, Ta = 25°C , CL = 30pF
1K 2K 3K 4K
100n
200n
300n 3m
2m
1m
30
tf
60 90 120
1.7 1.7 1.7 1.7
1.7
0.85
0.57 0.43
Rp(min, 2.65V part) = VCC(Max.) - VOL(Max.)
IOL + ΣIL = 2.5V
3mA + ΣIL
tr,tf [s]
Ibusy [A]
Rp(ohm)
Ibusy
tr
@ Vcc = 2.65V, Ta = 25°C , CL = 30pF
1K 2K 3K 4K
100n
200n
300n 3m
2m
1m
30
tf
60 90 120
2.3 2.3 2.3 2.3
2.3
1.1
0.75 0.55
FLASH MEMORY
48
K9F1208D0A
K9F1208U0A
K9F1208Q0A K9F1216D0A
K9F1216U0A
K9F1216Q0A
The device is designed to offer protection from any involuntary program/erase during power-transitions. An internal voltage detector
disables all functions whenever Vcc is below about 1.1V(1.8V device), 1.8V(2.65V device), 2V(3.3V device). WP pin provides hard-
ware protection and is recommended to be kept at VIL during power-up and power-down. A recovery time of minimum 10µs is
required before internal circuit gets ready for any command sequences as shown in Figure 24. The two step command sequence for
program/erase provides additional software protection.
Figure 24. AC Waveforms for Power Transition
VCC
WP
High
≈
≈
WE
Data Protection & Power-up sequence
1.8V device : ~ 1.5V
3.3V device : ~ 2.5V
1.8V device : ~ 1.5V
3.3V device : ~ 2.5V
10µs
≈≈
2.65V device : ~ 2.0V 2.65V device : ~ 2.0V
