PRELIMINARY TECHNICAL DATA CDMA Power Management System Preliminary Technical Data ADP3500 FEATURES Handles all CDMA Baseband and RF/IF Power Management Functions LDOs Optimized for Specific CDMA Subsystems Four Backup LDOs for Stand-By mode operation Four Li-Ion Battery Charge Modes 5mA Pre Charge Low Current Charge Full Current Charge Regulator mode (no current limit) Ambient Temperature: -30 C to +85 C 64pin 7x7 LQFP package LOGIC BLOCK DELAY 10mS BATTERY CHARGER KEYPAD I/F INTERRUPT CONTROL REFERENCE TE POWER ON GPIO LDO CONTROL LDO1 to 11 SERIAL I/F RESET VOLTAGE DETECTOR 32KHz OUTPUT CONTROL RTC COUNTER LE APPLICATIONS CDMA/CDMA2000/PCS Handsets GENERAL DESCRIPTION RESET OUTPUT ADP3500 STAY-ALIVE TIMER Figure 1. Functional Block Diagram O B SO The ADP3500 is a multifunction power system chip optimized for CDMA cell phone power management. It contains 15 LDOs. Sophisticated controls are available for power up during battery charging, keypad interface, GPIO/INT function and RTC function. The battery charger has four modes as Pre-charge, Low Current Charge, Full Current Charge, and Regulator modes, and is designed for Li-Ion/Li-Polymer batteries. ANALOG BLOCK REV. PrP 2/6/02 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or apatent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-873 ANALOG DEVICES, INC., 2002 PRELIMINARY TECHNICAL DATA ADP3500 - SPECIFICATIONS MAIN FUNCTIONS TA =-30 to +85C, CVBAT=1F MLCC, VBAT=3.6V unless otherwise noted. See Table 2 for COUT. Symbol IGND OPERATING GND CURRENT Stand-by mode operation (light load) IGND Conditions Typ Max LDO3b : ON, connect to RTCV through Schottky diode. RTC/32K OSC : Active All other LDOs: OFF All logic inputs : VBAT or GND MVBAT: OFF 25 40 A LDO1b, 2b, 3b, 6b: ON Io=1mA for LDO1b & 3b Io=300A for LDO2b & 6b All other LDOs: OFF RTC/32K OSC: Active MVBAT: OFF All logic output: no load 60 125 A LDO1, 2, 3, 6, all Sub-LDO: ON, Io=70% load All other LDOs: OFF RTC/32K OSC: Active MVBAT: ON All logic outputs: no load 275 A LDO5: OFF All other LDOs: ON, 70% load RTC/32K OSC: Active All logic outputs: no load MVBAT: ON 650 A 160 35 +85 12 5.5 C C C V V Max 2.99 Units V B SO LE Stand-by mode operation (Mid-load) Active operation Min TE Parameter SHUTDOWN GND CURRENT Power OFF Thermal Shutdown Threshold Thermal Shutdown Hysteresis Operational Temperature range Adapter Voltage range (recommendation) VBAT Voltage range Tope VADP VBAT -30 5.5 3.3 Units LDO SPECIFICATIONS TA =25C, CVBAT=1F MLCC, VBAT = Vout+1V, NRCAP=0.1F. See Table 2 for COUT. Baseband VDD Main-LDO (LDO #1a) Symbol VLDO#1 OUTPUT CAPACITOR REQUIRED FOR STABILITY DROPOUT VOLTAGE Start-up time from shutdown GND Current C LDO#1 O Parameter OUTPUT VOLTAGE Conditions Io = 1 to 150 mA Ta= -30 to +85C Min 2.81 Typ 2.90 F 2.2 VDO Io = 150 mA ILDO#1 Io = 150 mA Parameter OUTPUT VOLTAGE Symbol VLDO#1b Conditions Io = 1mA Ta= -30 to +85C GND Current ILDO#1b 200 250 50 mV S A Baseband VDD Sub-LDO (LDO #1b) REV.PrP 2/6/02 Min 2.8 Typ 2.87 10 -2- Max 3.0 Units V A PRELIMINARY TECHNICAL DATA ADP3500 Baseband AVDD Main-LDO (LDO #2a) Parameter OUTPUT Voltage OUTPUT default voltage OUTPUT Voltage VLDO#2 VLDO#2 Conditions 16 steps, 20mV/step, Ta= 25C, Io=50mA Code : 1000 Code : 0111 Io = 50 mA, Ta= 25C 16 steps, 20mV/step, Io=50mA, Ta= -30 to +85C Code : 1000 Code : 0111 VLDO#2 C LDO#2 Io = 50 mA, Ta= -30 to +85C VDO VNOISE Io = 50 mA f = 1KHz f = 100 Hz to 100 kHz ILDO#2 Io = 50 mA Parameter OUTPUT Voltage Symbol VLDO#2b Conditions Io = 300 A, VLDO#2a=2.6V Ta= -30 to +85C GND Current ILDO#2b LE Baseband AVDD Sub-LDO (LDO #2b) REFO switch Symbol RON ILEAK Conditions Ta= -30~+85C, Io=500A LDO2: ON, Switch: OFF B SO Parameter On resistance Off leak Min Typ Max Units 2.30 2.60 2.46 2.36 2.66 2.52 2.43 2.74 2.6 V V V 2.29 2.57 2.36 2.66 2.47 2.81 V V 2.42 1 2.52 2.66 V F 210 50 120 250 50 TE OUTPUT default voltage OUTPUT CAPACITOR REQUIRED FOR STABILITY DROPOUT VOLTAGE RIPPLE REJECTION OUTPUT NOISE VOLTAGE Start-up time from shutdown GND Current Symbol VLDO#2 Min 2.50 Typ Max 2.70 mV dB VRMS S A Units V A 5 Min Typ 50 0.01 Max 130 1 Units A Min 2.85 Typ 3.0 Max 3.09 Units V Coin Cell Main-LDO (LDO #3a) Parameter OUTPUT VOLTAGE Symbol VLDO#3 Dropout Voltage OUTPUT CAPACITOR REQUIRED FOR STABILITY Start-up time from shutdown GND Current VDO C LDO#3 Conditions Io = 1 to 50 mA Ta= -30 to +85C Io= 50 mA ILDO#3 Io = 50 mA Parameter OUTPUT VOLTAGE Symbol VLDO#3b Conditions Io=1mA Ta= -30 to +85C GND Current ILDO#3b 140 mV F 250 50 S A 1 O Coin Cell Sub-LDO (LDO #3b) Min 2.85 Typ 2.97 Max 3.15 Units V A 10 Audio LDO (LDO #4) Parameter OUTPUT VOLTAGE Symbol VLDO#4 OUTPUT CAPACITOR REQUIRED FOR STABILITY Dropout Voltage RIPPLE REJECTION OUTPUT NOISE VOLTAGE Start-up time from shutdown GND Current C LDO#4 REV.PrP 2/6/02 VDO Conditions Io = 1 to 180 mA Ta = -30 to +85C Min 2.81 Typ 2.90 VNOISE ILDO#4 Io = 180 mA -3- Units V F 2.2 Io = 180 mA f = 1KHz f = 100 Hz to 10 kHz Max 2.99 200 50 50 250 50 mV dB VRMS S A PRELIMINARY TECHNICAL DATA ADP3500 Vibrator LDO (LDO #5) Parameter Output Voltage Symbol VLDO#5 Dropout Voltage Output capacitor required for stability GND Current VDO C LDO#5 ILDO#5 Conditions Io = 1 to 150 mA Ta= -30 to +85C Io = 150mA Min 2.75 Typ 2.9 Max 3.05 200 mV F A 2.2 Io = 150 mA Units V 50 Baseband Core Main-LDO (LDO #6a) Parameter Output Voltage Symbol VLDO#6 Conditions Io = 1 to 50 mA Ta= -30 to +85C Output capacitor required for stability Dropout Voltage Start-up time from shutdown GND Current C LDO#6 VDO Io = 50 mA ILDO#6 Io = 50 mA Parameter OUTPUT VOLTAGE Symbol VLDO#6b Conditions Io = 300 A Ta= -30 to +85C GND Current ILDO#6b Symbol VLDO#7 Output capacitor required for stability Dropout voltage Ripple rejection Output noise voltage Start-up time from shutdown GND Current C LDO#7 VDO Max 2.68 TE 160 250 50 Min 2.5 Typ 2.57 Max 2.7 5 LE Parameter Output voltage Typ 2.60 1 Baseband Core Sub-LDO (LDO #6b) RF Rx1 LDO (LDO #7) Min 2.52 Conditions Io = 1 to 100 mA Ta= -30 to +85C ILDO#7 Io=100mA Symbol VLDO#8 Conditions Io = 1 to 150 mA Ta= -30 to +85C B SO VNOISE Io = 100 mA f = 1KHz f = 100 Hz to 100KHz Min 2.81 Typ 2.9 Max 2.99 Units V F mV S A Units V A Units V F mV dB VRMS S A 1.5 200 50 40 250 50 RF Tx LDO (LDO #8) Parameter Output voltage Output capacitor required for stability Dropout voltage Ripple Rejection Output noise voltage Start-up time from shutdown GND Current C LDO#8 VDO ILDO#8 Io=150mA Parameter Output voltage Symbol VLDO#9 Conditions Io = 1 to 50 mA Ta= -30 to +85C Output capacitor required for stability Dropout voltage Ripple Rejection Output noise voltage Start-up time from shutdown GND Current C LDO#9 VDO O VNOISE Io = 150mA f = 1KHz f = 100 Hz to 100KHz Min 2.81 Typ 2.9 Max 2.99 Units V F mV dB VRMS S A 2.2 200 50 40 250 50 RF Rx 2 LDO (LDO #9) Min 2.81 Typ 2.9 Max 2.99 F mV dB VRMS S A 1 VNOISE Io = 50mA f = 1KHz f = 100 Hz to 100KHz ILDO#9 Io=50mA Symbol VLDO#10 Conditions Io= 1 to 50 mA Ta= -30 to +85C Units V 150 50 40 250 50 RF Optional LDO (LDO #10) Parameter Output voltage REV.PrP 2/6/02 -4- Min 2.81 Typ 2.9 Max 2.99 Units V PRELIMINARY TECHNICAL DATA Output capacitor required for stability Dropout voltage Ripple rejection Output noise voltage Start-up Time from Shutdown GND Current C LDO#10 VDO ADP3500 F mV dB VRMS S A 1 VNOISE Io = 50mA f = 1KHz f = 100 Hz to 100KHz ILDO#10 Io=50mA Parameter Output voltage Symbol VLDO#11 Conditions Io = 1 to 100 mA Ta= -30 to +85C Output capacitor required for stability Ripple rejection Output noise voltage Start-up Time from Shutdown GND Current C LDO#11 150 50 40 250 50 Optional LDO (LDO #11) Min 1.42 Typ 1.5 Max 1.58 Units V F dB VRMS S A 2.2 50 50 250 50 ILDO#11 Io=150mA Parameter LDO1 detect voltage LDO1 release voltage Symbol VDET1 VDET1 Conditions Ta= -30 to +85C Ta= -30 to +85C Min 2.7 LDO1 Hysteresis LDO6 detect voltage LDO6 release voltage VHYS1 VDET6 VDET6 Ta= -30 to +85C Ta= -30 to +85C Ta= -30 to +85C 35 2.3 LDO6 Hysteresis VHYS6 Ta= -30 to +85C 40 60 100 mV Min Typ Max Units 2.484 2.673 2.508 2.697 6 2 3 6 65 2.533 2.727 V/V V/V mV/lsb mA mV mV A A Min Typ Max Units 3.926 4.150 4.170 4.190 3.980 4.190 4.210 4.230 4.034 4.230 4.250 4.270 V V V V 3.905 4.130 4.146 4.166 3.980 4.190 4.210 4.230 4.065 4.250 4.278 4.300 V V V V TE VNOISE f = 1KHz f = 100 Hz to 100KHz Voltage Detector for LDO1 and LDO6 Typ 2.72 2.77 Max VLDO1 Units V V BATTERY VOLTAGE DIVIDER: MVBAT LE -NOM 52 2.33 2.40 85 VLDO6 mV V V -NOM B SO TA =-30 to 85C, CVBAT=10F MLCC, CAdapter=1F MLCC unless otherwise noted Parameter MVBAT Output voltage 5 - bit programmable O MVBAT Output voltage step Output drive current capability MVBAT Load Regulation MVBAT Output Voltage Step Operating Battery Current Shutdown Current Symbol VMVBAT Vstep Iout VBAT Conditions VBAT=4.35V, MVEN = 1 code 10000 code 01111 VBAT=4.35V, MVEN = 1 1 0 < Iout < 100 A VBAT = 4.35 V, MVEN = 1 VBAT = 4.35 V, MVEN = 1 VBAT = 4.35 V, MVEN = 0 5 85 1 BATTERY CHARGER TA =-30 to 85C, CVBAT =10F MLCC, CAdapter =1F MLCC, 4.0V ADAPTER 12V unless otherwise noted Parameter Charger Control Voltage Range 2 - bit programmable Charger Control Voltage Range 2 - bit programmable REV.PrP 2/6/02 Symbol VBAT SENSE VBAT SENSE Conditions Ta= 25 C, VR_SENSE = 6mV & 115mV, 5.5V ADAPTER 12V (note 1) code 00 (default) code 01 code 10 code 11 Ta= -20 to 55C, VR_SENSE = 6mV & 115mV, 5.5V ADAPTER 12V (note 1) code 00 (default) code 01 code 10 code 11 -5- PRELIMINARY TECHNICAL DATA Charger Detect Off Threshold Charger Supply Current Current Limit Threshold High Current Limit (Full charge current enabled) Low Current Limit (Full charge current disabled) Pre-Charge Current Source Base Pin Drive Current Deep Discharge Lock-Out (Releasing voltage) Deep Discharge Lock-Out Hysteresis ISENSE Bias Current BATID pull-up resistor to ADAPTER Minimum Load for Stability ADAPT ERVBAT ADAPT ERVBAT IADAPTER ADAPT ER-VISNS DDLO ADP3500 110 165 225 mV 5 23 50 mV 2 mA ADAPTER=5V, VBAT=4.3V ADAPTER=5V VBAT=3.6V 135 160 185 mV VBAT=3.0 V 40 55 70 mV VBAT DDLO Note 2. VBAT<DDLO, Ta=25C, 5mA Precharge, VBAT ramping up 3 15 5 28 2.675 7 2.78 mA mA V 1 130 10 mV A K mA 200 IISNS RBATID IL VISNS=5V TE Charger Detect On Threshold 70 BATID=H. Note 3. 100 O B SO LE Note 1: Overhead includes external components, including sense resistor, PNP and isolation diode. 2: DDLO hysteresis is dependent upon DDLO threshold value. If DDLO threshold is at maximum, DDLO hysteresis is at maximum at the same time. 3: Guaranteed but not tested. REV.PrP 2/6/02 -6- PRELIMINARY TECHNICAL DATA ADP3500 LOGICS DC Specifications TA =25C, CVBAT=1F MLCC, VBAT = 3.6 V Symbol Conditions Min VIH VIL O Supply Current of RTCV Typ Max 0.28 0.28 V V 0.4 V 0.15 V 0.5 470 VIH VIL 2.25 0.5 470 VOH VOL IOH=400A IOL=-1.8mA VOL IOL=-100mA VOL IOL=-1.8mA 2.69 TE IOH=400A IOL=-1.8mA 2.69 LE VOH VOL VIH VIL Vhys 0.8xVBAT VIH VIL Vhys VOL 0.8xVBAT VIH VIL Vhys VOH VOL IOH=400A IOL=-1.8mA VOL OFFLEAK IOL=-1.8mA VOL IOL=-1.8mA VIH VIL VADP=5 to 12V IOSC 0.2xVBAT 950 0.2xVBAT 950 IOL=-1.8mA 0.1xVBAT 0.7xVBAT 0.2xVBAT 300 0.9xRTCV 0.005 V V mV V V mV V V V mV 0.1xRTCV V V 0.1xRTCV 1 V A 0.1xRTCV V 0.2xVADP V V V 0.8xVADP 0.16 x VADP 1 RTCV=3V, VBAT=0V All logic: No load. Units V V mV V V V mV V V 2.25 B SO Parameter CS, CLKIN, RESETIN-, TCXO_ON, SLEEP-, KEYPADROW (Internal 10K pull-up) Input High Voltage Input Low Voltage Hysteresis GPIO, DATA Input High Voltage Input Low Voltage Hysteresis Output High Voltage Output Low Voltage INTOutput High Voltage Output Low Voltage BLIGHT (Open Drain Output) Output Low Voltage KEYPADCOL (Open Drain Output) Output Low Voltage PWRONKEY-, OPT1 (Internal 140K Pull-up) Input High Voltage Input Low Voltage Hysteresis OPT2- (Input/Open Drain Output) Input High Voltage Input Low Voltage Hysteresis Output Low Voltage OPT3 Input High Voltage Input Low Voltage Hysteresis 32KOUT Output High Voltage Output Low Voltage RESET+ (Open Drain Output) Output Low Voltage OFF Leak RSTDELAY-, RESETOUT- (Open Drain Output) Output Low Voltage BATID (Internal 100K pull-up) Input High Voltage Input Low Voltage Hysteresis A VADP: Adapter voltage AC Specifications All specs include temperature unless otherwise noted Parameter Operational Supply Range Oscillator Frequency Start-up Time (note) Frequency deviation REV.PrP 2/6/02 Symbol RTCV FCLK tSTART fDEV Conditions RTCV=0V to 3V RTCV=2 to 3V -7- Min 2 Typ 32.768 100 TBD Max 3.1* 200 Units V KHz mS PRELIMINARY TECHNICAL DATA fJITTER/S EC Frequency Jitter Cycle to Cycle >100cycles Long term Drift RTCV=3V, 3 minutes 40* 50* 10* SERIAL INTERFACE Min. 50 50 100 100 100 62 50 40 Typ. Max 50 50 50 Units nS nS nS nS nS S nS nS nS nS nS Test Condition/Comments CLK set-up time CS set-up time CLK "High" Duration CLK "Low" Duration CS hold time CS recovery time Input data set-up time Input data hold time Data output delay time Data output floating time Data output floating time after CS goes low. TE Parameter tCKS tCSS tCKH tCKL tCSH tCSR tDS tDH tRD tRZ tCSZ Note: These parameters are not tested. ABSOLUTE MAXIMUM RATINGS B SO LE Voltage on ADAPTER pin to GND ...................................... -0.3, 15Vmax Voltage on VBAT pin to GND .......................................... -0.3, 7Vmax Voltage on Pin 6-13, 21-28 to GND .................................... -0.3, VLDO1+0.3Vmax Voltage on Pin 1, 62-64 .................................................. - 0.3, VBAT+0.3V max Voltage on Pin 20, 32 ..................................................... - 0.3, VRTCV+0.3V max Voltage on Pin 60, 61 ...................................................... - 0.3, VADAPTER+0.3V max Voltage on Pin 2-5, 14, 30, 31, 33 ........................................ - 0.3, 7V max Storage Temperature Range .............................................. - 65 to +150 C Operating Temperature Range ........................................... - 30 to +85C Maximum Junction Temperature ........................................ 125C JA Thermal Impedance (LQFP-64) ..................................... 2 layer board 76C/W JA Thermal Impedance (LQFP-64) ..................................... 4 layer board 54C/W Lead Temperature Range (Soldering, 60sec) ........................... 300C ORDERING GUIDE Temperature Range -30 C to 85 C Package LQFP 64 pins O Model ADP3500AST REV.PrP 2/6/02 ADP3500 RTCV=3V, TA=25C -8- nS nS ppm PRELIMINARY TECHNICAL DATA ADP3500 LDO8 (RF Tx) AGND VBAT LDO9 (RF Rx2) LDO10 (RF Option) BVS AGND MVBAT NRCAP ADAPTER BASE ISENSE BATID OPT2- PW PIN CONFIGURATION 64 49 1 48 VBAT OPT3 KEYPADCOL0 LDO7 (RF Rx1) KEYPADCOL1 LDO6 (Baseband Core) KEYPADCOL2 VBAT KEYPADCOL3 LDO5 (Vibrator) KEYPADROW0 LDO4 (Audio) KEYPADROW1 VBAT KEYPADROW2 LDO2 (Baseband AVDD) KEYPADROW3 REFO KEYPADROW4 AGND KEYPADROW5 LDO3 (RTC/Coin-cell) TCXO_ON VBAT SLEEP- LDO1 (Baseband VDD) BLIGHT LDO11 (Option) VBAT DGND INT- RSTDELAY- 33 17 TE 16 TEST RESET+ RESETOUT- RESETIN- CLKIN CS DATA GPIO3 GPIO2 GPIO1 GPIO0 OSC RTCV AGND 32 Figure 2. Pin Configuration PIN DESCRIPTION I/O I O O O O I I I I I I I Supply VBAT LDO1 LDO1 LDO1 LDO1 LDO1 LDO1 LDO1 LDO1 LDO1 LDO1 LDO1 I LDO1 O O - VBAT LDO1 - I/O RTCV RTCV LDO1 22 GPIO1 I/O LDO1 23 GPIO2 I/O LDO1 24 GPIO3 I/O LDO1 25 26 27 28 29 I/O I I I O LDO1 LDO1 LDO1 LDO1 RTCV 13 SLEEP- BLIGHT DGND INTRTCV 18 19 20 21 OSCOUT AGND OSCIN GPIO0 O 14 15 16 17 DATA CS CLKIN RESETIN32KOUT REV.PrP 2/6/02 Function Optional Power ON input. ADP3500 will keep "power ON" during this pin goes "High". Keypad Column Strobe 0 (Open Drain, pull low) Keypad Column Strobe 1 (Open Drain, pull low) Keypad Column Strobe 2 (Open Drain, pull low) Keypad Column Strobe 3 (Open Drain, pull low) Keypad Row Input 0. Pulled up internally, 10K Keypad Row Input 1. Pulled up internally, 10K Keypad Row Input 2. Pulled up internally, 10K Keypad Row Input 3. Pulled up internally, 10K Keypad Row Input 4. Pulled up internally, 10K Keypad Row Input 5. Pulled up internally, 10K Logic input pin for Main LDOs (LDO1, LDO2, LDO3, LDO6) turning on control. L: OFF, H: ON Logic input pin for RF Rx LDOs (LDO7 and LDO9). Gating register data with this input for these LDOs. LDO7 and LDO9 are turned OFF when SLEEP- goes Low even if the registers set to ON. LED drive. Open drain output. Digital Ground Interrupt signal output Supply input for RTC, 32KHz OSC, and some other logics. Connects to Coin cell battery in typical operation. Connect to 32.768KHz crystal. Analog Ground Connect to 32.768KHz crystal. General Purpose Input and Output port. Integrated Interrupt function. Interrupt occurs both falling and raising edge. General Purpose Input and Output port. Integrated Interrupt function. Interrupt occurs both falling and raising edge. General Purpose Input and Output port. Integrated Interrupt function. Interrupt occurs both falling and raising edge. General Purpose Input and Output port. Integrated Interrupt function. Interrupt occurs both falling and raising edge. Serial Interface data input and output. Serial Interface Chip Select input. Active High input. Serial Interface Clock input. Reset input signal for internal reset signal and starts Stay-Alive timer. 32.768KHz output. Output after 30mS when Reset is released. LE Mnemonic OPT3 KEYPADCOL0 KEYPADCOL1 KEYPADCOL2 KEYPADCOL3 KEYPADROW0 KEYPADROW1 KEYPADROW2 KEYPADROW3 KEYPADROW4 KEYPADROW5 TCXO_ON B SO Pin 1 2 3 4 5 6 7 8 9 10 11 12 -9- PRELIMINARY TECHNICAL DATA 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 VBAT LDO11 LDO1 VBAT LDO3 AGND REFO LDO2 VBAT LDO4 LDO5 VBAT LDO6 LDO7 VBAT LDO8 AGND LDO9 VBAT LDO10 BVS NRCAP AGND MVBAT BASE ADAPTER BATID O O O O O O O O O O O O O O O I 61 62 63 64 ISENSE PWRONKEYOPT1OPT2- Reset output. Invert signal of RESETOUT-. Open drain and low OFF leak. Reset output. Follows Voltage Detector operation. Open drain output. Test pin. If the pin tied to RTCV, test mode runs. Connect to GND for normal operation. Reset output. 50mS delayed. Connect to baseband' reset input as typical application. Open drain output. Supply input. Connect to Battery. VBAT Regulator #11 output. Use for Optional circuit. VBAT Regulator #1 output. Use for Baseband I/O supply. Supply input. Connect to Battery. VBAT Regulator #3 output. If VBAT>2.7V, the output is always active. Use for Coin cell supply. Analog Ground VBAT Output of LDO2 through FET switch. VBAT Regulator #2 output. Use for Baseband analog supply. Supply input. Connect to Battery. VBAT Regulator #4 output. Use for General analog supplies. Ex. Speaker Amp. VBAT Regulator #5 output. Use for Vibrator. Supply input. Connect to Battery. VBAT Regulator #6 output. Use for Baseband core supply. VBAT Regulator #7 output. Use for RF Rx IC supply. Gated with SLEEP- signal input. Supply input. Connect to Battery. VBAT Regulator #8 output. Use for RF Tx IC supply. Analog Ground VBAT Regulator #9 output. Use for RF Rx IC supply. Gated with SLEEP- input signal. Supply input. Connect to Battery. VBAT Regulator #10 output. Use for Optional circuit. Battery Voltage Sense input for Charger. Connect to Battery. VBAT Noise reduction capacitor. 0.1F MLCC. Analog Ground VBAT Battery voltage divider output. Buffered internally. Connect to Baseband ADC. ADAPTER Base drive output for PNP pass transistor AC adapter input. Use to charger supply. ADAPTER Battery identification. 100K pulled up internally. "L": Battery exist, "H": No battery. If BATID="H", Charger operates with "No current Limit". ADAPTER Charge current sense input VBAT Power ON/OFF key input. Pulled up internally (140K). VBAT Optional Power ON input. ADP3500 will keep "power ON" during this pin goes "Low". VBAT Optional Power ON input. ADP3500 will keep "power ON" during this pin goes "Low". While the part is powered up, the input is pulled to Low (GND) internally. Don't connect to any supply or signal source. O I I I I/O REV.PrP 2/6/02 ADP3500 RTCV RTCV RTCV RTCV TE O O I O LE RESET+ RESETOUTTEST RSTDELAY- B SO 30 31 32 33 - 10 - PRELIMINARY TECHNICAL DATA ADP3500 BLOCK DIAGRAM VBAT AGND ADAPTER ISENSE BASE 56 50 39 19 52 48 45 42 37 34 59 61 BVS 58 54 60 BATID 57 MVBAT (VBAT Measure) 40 REFO 55 NRCAP 36 LDO1 (Baseband VDD) LDO2 41 LDO2 (Baseband AVDD) LDO3 38 LDO3 (RTC/Coin-cell) 100K VBAT Charger_Detect Battery Charger 140K PWRONKEYOPT1OPT2OPT3 62 63 64 1 Charger Control POWERON_N OPT1_N DDLO REF power_on OPT2_N OPT3 RTC Alarm LDO_EN LDO1 sync PWROFF Main ON/OFF LOGIC CLK 5 KEYPADCOL0 KEYPADCOL1 KEYPADCOL2 KEYPADCOL3 KEYPADROW0 KEYPADROW1 KEYPADROW2 KEYPADROW3 KEYPADROW4 KEYPADROW5 BLIGHT DGND 2 4 LDO1 Level trans LDO7 Level trans LDO8 KEY PAD I/F 7 9 LDO5 4 6 8 5 INT 5 LDO9 6 10 11 LDO10 LDO1 GPIO_INT / gpi_intrst 14 LDO11 15 26 27 25 21 22 23 24 LDO6 Sub LDO4 Level trans Serial I/F DATA GPIO + INT DATA 46 LDO6 (Baseband Core) 43 LDO4 (Audio) 44 LDO5 (Vibrator) 47 LDO7 (RF Rx1) 49 LDO8 (RF Tx) 51 LDO9 (RF Rx2) 53 LDO10 (RF Option) 35 LDO11 (Option) 13 28 SLEEPTCXO_ON RESETIN- 17 RTCV 32 TEST 33 RSTDELAY- 31 RESETOUTRESET+ Voltage Detector B SO CS CLKIN DATA GPIO0 GPIO1 GPIO2 GPIO3 3 ON/OFF LOGIC LE INT- Main INT_N Level trans Sub Main ON/OFF LOGIC Data In 16 LDO1 Sub TE Delay 10mS Main ON/OFF LOGIC voltage_detect CLK LPF REF BATID Level trans CLKs DGND Level Translator VBAT & RTCV LDO1 12 LDO1 Level Translator OSC IN 20 OSC OUT 18 32K OUT 29 DGND 32KHz Delay 30mS RTC /clock CLKs Data Open Drain Delay 50mS Data RESETIN_N O Stay/Alive Timer 0.25-8sec REV.PrP 2/6/02 RTCV Figure 3. Overall Block Diagram - 11 - RTCV 30 PRELIMINARY TECHNICAL DATA ADP3500 Theory of Operations As illustrated in Figure 1 at the beginning, ADP3500 can be divided into two high level blocks - Analog and Logic. The Analog block mainly consists of LDO regulators, battery charger, reference voltage, and voltage detector sub-blocks, all of which are powered by the main power source(VBAT), namely the main battery or the charging adapter. On the other hand, the Logic block is more complicated. All the Logic sub-blocks are also powered by VBAT except the RTC counter, 32MHz Output control, RESET Output, and Stay-Alive Timer. These sub-blocks are powered from RTCV pin, as indicated in Figure 4 in shaded area. [VBAT] POWER ON 4 KEYPAD I/F 3 GPIO 2 SERIAL I/F 7 INTERRUPT CONTROL 8 LDO CONTROL RESET [RTCV]- RTC BLOCK 10 DELAY 10mS ANALOG BLOCK LE 1 6 TE 5 32K OUTPUT CONTROL RTC COUNTER 11 STAY-ALIVE TIMER B SO RESET OUTPUT 9 Figure 4. Power partitioning of sub-blocks 1. ANALOG BLOCKS 1.1 LOW DROP-OUT(LDO) REGULATORS There are total four Sub-LDOs for each LDO1, 2, 3, and 6, in order to meet lower power consumption at light load (stand-by operation). They are used at low load condition, but they are continuously ON even if the each Main-LDOs are ON. The LDO3 and 3b are used for Coin cell and LDO3b is always ON until Main battery (VBAT) is downed to 2.5V due to DDLO function. LDO7 and 9 are controlled with SLEEP- signal. For detail of LDO ON/OFF control, please refer to Section "2.8 LDO Control". O Table 1. Ground currents of LDOs with each handset operations. Baseband Baseband LDO names Coin Cell Audio Vibrator VDD Core Baseband AVDD RF Rx1 RF Tx RF Rx2 RF Option Option Main Total LDO REF IGND LDO # Power OFF 1 OFF 6 OFF 3 10A 4 OFF 5 OFF 2 OFF 7 OFF 8 OFF 9 OFF 10 OFF 11 OFF 20A 30A Light load Standby Mid-load mode Active load 10A 5A 10A OFF OFF 5A OFF OFF OFF OFF OFF 20A 50A 60A 55A 60A OFF OFF 55A OFF OFF OFF 50A OFF 20A 300A 60A 55A 60A OFF OFF 55A 50A 50A 50A 50A OFF 20A 450A Talk Ring 60A 60A 55A 55A 60A 60A 50A 50A OFF 50A 55A 55A 50A 50A 50A 50A 50A 50A 50A 50A 50A 50A 20A 20A 550A 600A REV.PrP 2/6/02 - 12 - PRELIMINARY TECHNICAL DATA ADP3500 Table 2. LDO operation overview LDO1a LDO1b LDO2a LDO2b LDO3a LDO3b LDO4 LDO5 LDO6a LDO6b LDO7 LDO8 LDO9 LDO10 LDO11 Current Rating (mA) Baseband VDD 150 Baseband VDD sub 1 Baseband AVDD 50 Baseband AVDD sub 0.3 RTC/Coin Cell 50 RTC/Coin Cell sub 1 Audio 180 Vibrator 150 Baseband Core 50 Baseband Core sub 0.3 RF Rx1 100 RF Tx 150 RF Rx2 50 RF Option 50 Option 100 Voltage (Typ) Or Range 2.90V 2.87V 2.36V~2.66V 2.33V~2.63V 3.0V 2.97V 2.9V 2.9V 2.6V 2.57V 2.9V 2.9V 2.9V 2.9V 1.5V Names Program steps N/A N/A 16 16 N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A Step size (mV) N/A N/A 20 20 N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A Default Cout 2.52V 2.49V - 2.2F 2.2F 1F 1F 1F 1F 2.2F 2.2F 1F 1F 2.2F 2.2F 1F 1F 2.2F TE Regulator 1.2 BATTERY CHARGER LE 1.2.1. Block Diagram Cvbat RSENSE AC Adapter CADAPTER ISENSE BASE B SO ADAPTER + V(ISENSE) - VBAT BVS Battery Pre-charge 5m A gm EN gm EN DDLO MVBAT MVBAT EN EN REF 100K BVS O BATID BATID REV.PrP 2/6/02 CHI LDO_ CHEN EN LOGIC Block Charger_ Detect Figure 5. Battery charger block diagram - 13 - CHV MVEN 0/1 MV4:0 PRELIMINARY TECHNICAL DATA 1.2.2. Flow Chart Battery charger start VADAPTER>VBAT ? N Y Set Charger Detect flag DDLO comparator will operate if VBAT>2V. Even if VBAT<2V, precharge is continuously applying 5mA. RESETIN- should be asserted until baseband chip active. Then, CHEN=1 as default. VBAT>DDLO ? LDO3b: ON Set Low Current Charge IADAPTER=250mA (50mV on Rsense) Pre-charge: OFF B SO Determined by external sense resistor BATID=0 ? LE BATID=0: Battery connected BATID=1: Battery disconnected TE Pre-charge 5mA O LDO1, 1b, 2, 2b, 3, 6, 6b Voltage Detector all enabled Voltage Detector VLDO6>2.5V AND VLDO1>2.7V ? Figure 6. Charger flow chart A REV.PrP 2/6/02 - 14 - Current Loop Disabled Voltage Loop Regulates VBAT to 4.0V Pre-charge: OFF ADP3500 PRELIMINARY TECHNICAL DATA ADP3500 A Reset sequence runs Baseband sets Charge Voltage Baseband sets MVBAT gain Baseband Enables Full charge current? (CHI=1?) N TE CHI=0: Full current charge OFF CHI=1: Full current charge ON Y LE Low Current Charge: OFF Set Full current charge IADAPTER=750mA (150mV on Rsense) B SO N Baseband CHEN=0? Y Charging Terminated Figure 7. Charger flow chart B O 1.2.3. Charger Detect function The ADP3500 will detect that a charging adapter has been applied when the voltage at the ADAPTER pin exceeds the voltage at BATSNS. The ADAPTER pin voltage must exceed the BVS voltage by a small positive offset. This offset has hysteresis to prevent jitter at the detection threshold. The charger detection comparator will set the Charger_Detect flag in the 20h register and generate an interrupt to the system. If the ADAPTER input voltage drops below the detection threshold, charging will stop automatically and the Charger_Detect flag will be cleared and generate an interrupt also. 1.2.4. DDLO function and operation The ADP3500 contains a comparator that will lock out system operation if the battery voltage drops to the point of deep discharge. When the battery voltage exceeds 2.675 V, the reference will start as will the sub-LDO 3b. If the battery voltage drops below the hysteresis level, the reference and LDO's will be shut down, if for some reason they are still active. Since LDO1 will be in deep dropout and well below the voltage detector threshold at this point, the reset generator will have already shut down the rest of the system via RESET+, RESETOUT-, and RSTDELAY-. If a charging adapter has been applied to the system, the DDLO comparator will force the charging current to trickle charge if the battery is below the DDLO threshold. During this time, the charging current is limited to 5 mA. When the battery voltage exceeds the upper threshold, the low current charging is enabled, which allows 55 mV (typical) across the external charge current sense resistor. See also Figure 6, the Battery Charger Flowchart. 1.3 MVBAT The ADP3500 provides a scaled buffered output voltage for use in reading the battery voltage with an A/D converter. The battery voltage is divided down to be nominally 2.600 V at full scale battery of 4.35 V. To assist with calibrating out system errors in the REV.PrP 2/6/02 - 15 - PRELIMINARY TECHNICAL DATA ADP3500 ADP3500 and the external A/D converter, this full scale voltage may be trimmed digitally with 5 bits stored in register 12h. At full scale input voltage, the output voltage of MVBAT can be scaled in 6 mV steps, allowing a very fine calibration of the battery voltage measurement. The MVBAT buffer is enabled by the MVEN bit of register 11h, and will consume less than 1 uA of leakage current when disabled. 1.4 REFERENCE The ADP3500 has an internal, temperature compensated and trimmed band-gap reference. The battery charger and LDO's all use this system reference. This reference is not available for use externally. However, to reduce thermal noise in the LDOs, the reference voltage is brought out to the NRCAP pin through a 50kohm internal resistor. A cap on the NRCAP pin will complete a low pass filter that will reduce the noise on the reference voltage. All the LDO's, with the exception of LDO3, use the filtered reference. 2. LOGIC BLOCKS * * * * * * GPIO and INT ports control Key-pad interface LED light control LDO functions Clock and Reset output control Stay-Alive timer LE ADP3500 has following logic functions. * Three wire Serial Interface (CS, CLK, DATA) * RTC counter section has Year, Month, Day, Week, Hour, Minute, and Second, and controls Leap year, and days in month automatically. * Detect Alarms based on RTC counter. * Periodically constant interrupt feature. (2Hz, 1Hz, 1/60Hz, 1/3600Hz, Once a months) TE Since the reference voltage appears at NRCAP through a 50kohm series internal impedance, it is very important to never place any load current on this pin. Even a volt meter with 10 megohm input impedance will affect the resulting reference voltage by about 6 or 7 mV, affecting the accuracy of the LDO's and charger. If for some reason the reference must be measured, be certain to use a high impedance range on the volt meter or a discrete high impedance buffer prior to the measurement system. O B SO Following is a block diagram based on Logic circuit. REV.PrP 2/6/02 - 16 - PRELIMINARY TECHNICAL DATA ADP3500 [VBAT] voltage detect_delay voltage_detect DELAY 10mS chager_detect SYNC. power_on PWRONKEY_N OPT1_N Interrupt register block OPT2_N OPT3 POWER OFF pwronkey_n_sync, opt1_n_sync, opt3_sync SYNC. SYNC. batid DATA IN Analog block BLIGHT LED control BL KEY PAD I/F control DGND KEYPADROW GPIO[3:0] 4 KEY PAD I/F 6 4 INT control register (reset & mask) keypad_int GPIO control GPIO TE KEYPADCOL INT_N TCXO_ON SLEEP_N LDO control register write_enable write_data[7:0] CS CLKIN DATA Serial I/F Analog control registers sp_addr[4:0] 32K OSC rtc_clk32k clk32k rt OSCIN 32K CLK output control Output data select clk512 Address decode B SO RTC t 32K OUT ct alarm_int analog block LDO Control RTC_CS resetin_n (reset for registers) rtc_resetin_n OSCOUT LE Data select RESETIN_N Analog Blocks Test mode cont Test mode register block clk1k Stay-Alive Timer test_ldoenable RTC register block rtc_test TEST rtc_voltage_detect RESETOUT_N RSTDELAY_N test_mode rtc_voltage_detect reset output control RESET [RTCV] Figure 8. LOGIC block diagram O 2.1 RESET 2.1.1 RESETIN- signal The internal reset function is activated by external reset input, RESETIN-, and this is an asynchronous signal. The internal reset signal is used in the following blocks. * Serial I/F * Interrupt control * Stay-Alive timer * Registers (refer to the Register section for detail). LDOs, controlled by Serial I/F, are applied "RESET" by RESETIN-. LDO4, LDO5, LDO7, LDO8, LDO9, LDO10, LDO11 and REF0 are set to "0". In case RESETIN- has noise, the internal circuit may be in reset and cause the system unexpected result. Please take enough treatment. RESETIN- is level translated from LDO1 to both VBAT and RTCV supplies. REV.PrP 2/6/02 - 17 - PRELIMINARY TECHNICAL DATA ADP3500 2.1.2 RESET output control and 32KHz output control Using Voltage Detect signal, device generates 32K OUT, RSTDELAY-, RESETOUT-, and RESET signals. About 32mS after rtc_voltage_detect (Voltage Detect signal in RTCV supply) signal goes from "0" to "1", 32K OUT signal is generated from internal RTC_CLK32K signal. RSTDELAY_N (RSTDELAY-) goes to "0" when rtc_voltage_detect is "0", and it goes to "1" at 50mS after the "0" to "1" transition of rtc_voltage_detect. RESETOUT_N (RESETOUT-) and RESET toggle their states. Signal clk512 is a 512Hz, which generated in USEC counter block. 2.2 SERIAL INTERFACE tCSR CS tCKS tCSS tCSH tCKH tCKL Serial DATA ADDR5 TE CLKIN ADDR4 0 CTRL1 (W) CTRL2 (W) DATA7 1 DATA0 LE Serial I/F WRITE Timing CS tCKS tCSS tCKH tCKL B SO CLKIN Serial DATA ADDR5 ADDR4 0 CTRL1 (R) CTRL2 (R) DATA7 1 tCSR DATA0 tRD tCSZ Serial I/F READ Timing Single Mode CS O tCKS tCSS tCKH tCKL CLKIN Serial DATA ADDR5 ADDR4 0 CTRL1 (R) CTRL2 (R) DATA7 1 DATA0 tRD Serial I/F READ Timing Continuous Mode Figure 9. Serial Interface signal Table 3. Set up and Hold Specifications Parameter Min. REV.PrP 2/6/02 Typ. Max Units Test Condition/Comments - 18 - ADDR5 tRZ ADDR4 PRELIMINARY TECHNICAL DATA ADP3500 tCKS tCSS tCKH tCKL tCSH tCSR tDS tDH tRD tRZ tCSZ 200 400 400 400 500 62 200 200 nS nS nS nS nS S nS nS nS nS nS 300 300 300 CLK set-up time CS set-up time CLK "High" Duration CLK "Low" Duration CS hold time CS recovery time Input data set-up time Input data hold time Data output delay time Data output floating time Data output floating time after CS goes low. 2.2.1. Function block resetin_n CS CLKIN DATAIN Serial To Parallel Conversion sp_addr [5:0] write_enable Creation of write Data sp_data [7:0] LE RW_SEL TE ADP3500 integrates the serial bus interface for easy communication with the system. The data bus consists of three wires, CLK, CS, and DATA, and is capable of Serial to Parallel / Parallel to Serial conversion of data, as well as clock transfer. Parallel to Serial Conversion DATA Synchlonization and Data Selection ps_data [7:0] B SO Figure 10. Serial Interface block diagram Serial interface block works during the time period at CS signal enable. After the falling edge of CLKIN signal right after the rising edge of CS signal, Address, transfer control signal and write data are held in sequentially. In case DATA READ, each of data will be prepared by rising edge of CLKIN and baseband chip may want to read or latch the data at falling edge of CLKIN. While CS is not asserted, CLKIN is ignored. If CS goes "L" while CLKIN is continuously applied or input DATA, all data is canceled and DATA line would be High impedance. In this case, user needs to input the data again. Please note that CLKIN should be stayed "L" when CS goes H. RTC counter registers should be accessed at a certain time (>62S) later after CS assertion. Asserting RESETIN_N (RESETIN-) signal resets the block.. O Notes: * CLKIN=10KHz to 1MHz, 20/80% duty cycle. * CLKIN should be "L" when CS goes "H". * In case of RTC counter access, the access should be approximately 62S, (2 clock cycles of CLK32K) after the CS signal is asserted, to hold the RTC value. * The CS should not be asserted for 62S, (2 clock cycles of CLK32K) after the CS is released. * CS signal should never be asserted for 1 sec or longer, otherwise RTC counter makes error. 2.2.2 Data input/output timing 5 4 3 2 Address(6bit) REV.PrP 2/6/02 1 0 1 0 R/W(2bit) - 19 - 7 6 5 4 3 Read DATA(8bit) 2 1 0 PRELIMINARY TECHNICAL DATA ADP3500 Figure 11. Serial I/F Data read/write timing SP_ADDR[5:0] : 6bit address SP_CTRL[1:0] : 2bit Read/Write control (01: Write, 10: Read) SP_DATA[7:0] : 8bit Input/Output Data * All transfer will be done MSB first. 2.3 GPIO+INT GPIO block has 4 channel I/O function and interrupt. With GPIO CONTROL register (1Ah), it is possible to control Input or Output setting of each channel individually. The output data is set in GPIO register (1Ch). When the port is set as input mode, the input signal transition from "1" to "0" and from "0" to "1", then generate interrupt signal with Edge detection. The held interrupt signals are reset by GPIO INT RESET register (1Dh). Setting GPIO MASK register (1Bh) to "1" enables the interrupt of GPIO. (Not MASKED, "1" at default in reset.) TE 2.4 INT REGISTER LE In case the interrupt event has occurred, "1", the signal is held in this register. INT detect and Reset are synchronized at the rising edge of CLK32K. In case the interrupt event and reset signal are occurred at same time, interrupt event has priority. RESETIN_N signal resets INT register (1Eh) to "0" (No INT detected), except alarm_int and ctfg_int. INT MASK register (1Fh) to "1" (not masked). This block masks alarm_int and ctfg_int, which generated in RTCV block, but these signals are reset with ALARM CONTROL register (0Dh) and CTFG CONTROL register (0Eh). The interrupt signal, INT_N, is an "inverted OR" signal of value in INT register and GPIO register. DATA-IN register is a port to read an interrupt status. The input data are through SYNC block except Alarm signal. Since this is for just read back purpose, user cannot write any data. SYNC block B SO BATID Register RTC Alarm Charger_Detect DATA_IN registor (Addr: 20h) OPT3 O OPT1- PWRONKEY- Figure 12. DATA-IN block 2.5 KEYPAD CONTROL & LED DRIVE KEYPADCOL[3:0] are Open Drain output. The KEYPADROW[5:0] are Falling edge trigger input (input state transition from "1" to "0") and generate Interrupt signal, and are pulled up to LDO1. By providing 4 keypad-column outputs and 6 keypadrow inputs the ADP3500 can monitor up to 24 keys with baseband chip. Writing Column outputs and Reading Row inputs are controlled through serial interface. The address of the KEYPADROW is 19h, and KEYPADCOL is 18h. Initial register value is "0" that means an output of KEYPADCOL is "High Impedance". Back-light drive is an open drain output. Maximum current of internal FET is 100mA. Initial register value is "0" that means the output of BLIGHT is "High impedance". REV.PrP 2/6/02 - 20 - PRELIMINARY TECHNICAL DATA ADP3500 2.6 POWER ON INPUT PWRONKEY and OPT1 have pull-up resistors, and others are not. In addition to these inputs, other internal input signals such as charger_detect and Alarm signal (alarm_int) from RTC enable Main and Sub LDOs of LDO1, 2, 3 and LDO6. Power ON status is hold by a latch data in Delay circuit, called voltage_detect_delay (please see 4.8 for more detail). OPT3 has a lower voltage threshold. OPT2 is different structure to the other inputs, and is pulled down to zero by internal signal when phone is Power ON status, in order to make sure to have Power ON status even if short-term disconnection is happened. Following is a block diagram and Power on sequence. VBAT 140K 140K TE voltage_detect_delay charger_detect alarm_int PWRONKEYOPT1- power_on LE OPT2OPT3 B SO INT Block Figure 13. Power ON input block diagram Voltage_detect_delay charger_detect alarm_int PWRONKEYOPT1OPT2OPT3 : Voltage Detect Signal (10mS delay) : Charger Detect Signal : Alarm Detect Signal (Alarm 1 or 2) : Power On key input : Power On signal : Power On signal : Power On signal O * * * * * * * REV.PrP 2/6/02 - 21 - (1: Assert) (1: Assert) (1: Assert) (0: Assert) (0: Assert) (0: Assert) (1: Assert) PRELIMINARY TECHNICAL DATA ADP3500 POWER OFF POWER ON PowerOnKey POWERON LDO1, 2, 3, 6 LDO1b, 2b, 6b Voltage Detector 10mS voltage_detect_delay 50mS RSTDELAY- OPT2 TE INT- Clear INT- Serial I/F Clear INT- and set PWROFF(21h)=1 Figure 14. Power ON sequence 2.7 10 MILISECOND DELAY LE This block generates a 10mS delayed signal after the reset of the voltage_detect signal is released. After 10mS (11 clocks of 1024Hz) since the voltage_detect signal is asserted, the voltage_detect_delay signal is asserted. If the duration of the voltage_detect signal is less than 10mS, voltage_detect_delay signal will not be asserted. When the voltage_detect signal is released, the voltage_detect_delay signal is also released simultaneously. The voltage_detect_delay signal can be reset with writing "1" in POWER OFF register (21h). B SO * User just need to write "1" in the POWER OFF register to reset voltage_detect _delay, and not need to over-write it with "0". 2.8 LDO CONTROL The LDO control block controls Power ON/OFF of LDO block. The function in this block has: * Hardware control using external signals * Software control using serial interface * Mixture of hardware and software above O LDO1, LDO2, LDO3, and LDO6 are structured with Main and Sub LDOs. LDO4, LDO5, LDO7, LDO8, LDO9, LDO10, and LDO11 are set through serial interface but LDO7 and LDO9 are gated (AND gate) with SLEEP- signal, in order to get into Sleep mode. If the SLEEP- signal is enabled (goes "Low"), the outputs of LDO7 and LDO9 are turned OFF. Remainder of LDOs as LDO1, LDO2, and LDO6 is controlled by "Power On Logic". A Sub LDO called "LDO3b" is independent control and this LDO control block doesn't control LDO3b. And Main LDO3 called "LDO3a" is turned on by power_on signal, but Sub LDO3 called "LDO3b" is always ON while Battery supplies and LDO3b is only controlled by DDLO. A DDLO is control signal from Battery charger block and is monitoring Battery voltage. When VBAT is under 2.5V (200mV hysteresis from VBAT=2.7V), DDLO minimizes (DDLO enable) current flow from Li-Ion battery. Main LDOs Sub LDOs : LDO1a, LDO2a, LDO3a, LDO6a : LDO1b, LDO2b, LDO3b, LDO6b Table 4a. DDLO status table Status LDO1a LDO1b LDO2a LDO2b LDO3a LDO3b LDO4 REFO Baseband Baseband VDD Coin cell Audio REFO AVDD DDLO Enable OFF OFF OFF OFF OFF OFF OFF OFF DDLO Disable X X X X X ON X X Note REV.PrP 2/6/02 - 22 - LDO5 Vibrator LDO6a LDO6b LDO7 Baseband Core Rx1 OFF OFF OFF OFF X X X X LDO8 LDO9 LDO10 LDO11 RF Tx Rx2 Option Option OFF OFF OFF OFF X X X X PRELIMINARY TECHNICAL DATA ADP3500 1. "X" means a status of LDO depends on other conditions. LDO5 Vibrator LDO6a LDO6b LDO7 Baseband Core ON Rx1 LDO8 LDO9 LDO10 LDO11 RF Tx Rx2 Option Option ON ON/ OFF OFF ON/ OFF OFF OFF OFF OFF OFF OFF ON/ OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF TE Table 4b. LDO Control Event Table Event LDO1a LDO1b LDO2a LDO2b LDO3a LDO3b LDO4 REFO Baseband Baseband VDD Coin cell Audio REFO AVDD POWER ON ON ON ON ON ON (Note 2) TCXO_ON ON/ ON/ ON/ (Note 3) OFF OFF OFF SLEEP(Note 4) RESETINOFF OFF "ALLOFF" bit OFF OFF goes "H" "PWROFF" bit OFF OFF OFF OFF OFF OFF OFF goes "H" LE Notes 1. This table only indicate the change of status caused by an event. Blank cells means "no change" and keep previous status 2. Power ON Event: Indicating a status just after the power ON event. After the event, a status of LDO1a, 2a, 3a, and LDO6a are changed by TCXO_ON signal. 3. TCXO_ON: Hardware control, change all Main-LDO' ON/OFF status. 4. SLEEP-: The LDO7 and LDO9 are able to be controlled by software if SLEEP="H" level. If SLEEP- goes "L", these LDOs are turned OFF immediately. Table 4c. Software Controllability of LDOs LDO1a LDO1b LDO2a LDO2b LDO3a LDO3b LDO4 REFO LDO description Baseband Baseband VDD Coin cell Audio REFO AVDD Software Turn ON B SO Software Turn OFF LDO5 Vibrator LDO6a LDO6b LDO7 Baseband Core Rx1 LDO8 LDO9 LDO10 LDO11 RF Tx Rx2 Option Option (Note1) (Note1) Note 1. LDO7 and LDO9 have a gate with SLEEP-. If SLEEP- is in "L" (active) status, user cannot control and both LDOs are kept to "OFF" status. User may want to use this function as immediate control to get OFF status by using SLEEP- hardware control while set register "1" to the LDO control register. 2.9 RTC BLOCK The Calendar registers are set through serial interface. O 2.9.1 Function * RTC counter using binary * Reading out and writing setting s of Year, Month, Day, Week, Hour, Minute, and second data. * Leap year controls, Number of days in a month control * Alarm function (Weak, Hour, Minute) * Periodic Interrupt function - 2Hz, 1Hz, 1/60Hz, 1/3600Hz, Each month (First day of each month) * Protection of wrong data readout during RTC data update. REV.PrP 2/6/02 - 23 - PRELIMINARY TECHNICAL DATA ADP3500 RTC_CLK32K RTC_SP_ADDR[5:0] RTC_WRITE_ENABLE RTC_WRITE_DATA[7:0] (from serial I/F) RTC Register block Loading Alarm times Alarm Comparator RTC Counter Reset will be asserted when RTC counter is writed. Periodic Interrupt leap year and Date Control Data Select rtc_alarm_int rtc_ctfg_int rtc_data[7:0] Registers for Test mode USEC Counter - Reset to RTC & USEC counters - Write initial data of USEC counter TE RTC_CS Sec counter Increment control LE Figure 15. RTC counter block B SO 2.9.2 Operation Synchronizing with RTC_CLK32K clock, USEC counter generates 1sec timing clock and the clock hits RTC counter. Through the serial interface, CPU can write setting value and read RTC counter value. In case the RTC counter toggles during the serial interface access to RTC counter, the wrong data can be read/write between RTC counter and interface. CS signal stops the clocking to RTC counter until CS signal is released. In case CPU writes data into SEC counter, USEC counter is reset to zero. Note * In case of RTC counter access, the access should be waited approximately 62S, (2 clock cycles of CLK32K) after the CS signal is asserted, to hold the RTC value. * CS signal should never be asserted 1sec or longer, this affects counter operation. 2.9.3 Operation of USEC counter USEC counter counts up synchronizing with RTC_CLK32K clock. It generates 1sec timing signal and it is used as an increment clocking of RTC counter. In case the 1sec signal is generated during CS signal asserted, the increment clock is delayed until CS signal is released. O 2.9.4 Operation of RTC counter RTC counter uses the increment signal from USEC counter to control counting operation including the leap year control and numbers of days in a month control. REV.PrP 2/6/02 - 24 - PRELIMINARY TECHNICAL DATA ADP3500 Enabled signals created by decoding of RTC_SP_ADDR[5:0] addr06h_write 06h Year 100 scale 05h Month 12 scale 04h Date 31 scale 03h Week 7 scale 02h Hour 12 scale 01h Minute 60 scale addr00h_write Leap year & days in month control Initial data To following counters year_count month_count day_count USEC counter inc_enb inc_clk week_count hour_count min_count 00h Second 60 scale TE sec_count Figure 16. RTC counter block diagram "A year which can be divided by 4" Note - LE Definition of Leap year The definition of a leap year is, "a year which can be divided by 4 and can not be divided by 100" and "a year which can be divided by 400." For this device, the following definition is used instead. Year counter = "00" means year 2000, and is a leap year because it can be divided by 400. Actual covered year period is from 1901 to 2099. B SO Number of days of month control Months 1, 3, 5, 7, 8, 10, 12 have 31days. Months 4, 6, 9, 11 have 30days. Month 2 has 28days, but has 29 in leap year. 2.9.5 Alarm Function Comparing the RTC counter value with the seting value in alarm_setting register (07h-09h), alarm condition is detected. Setting of week uses 7bits for each day in a week, and works with multiple days setting. There is a delay of 62S from Alarm detection to setting up to AOUT/BOUT registers. O ALA_EN flag in ALARM CONTROL register (0Dh) sets Enable/Disable of alarm detection. INT register (1Eh) indicates the interrupt signals, alarm_int of ALA or/and ALB. INT MASK register (1Fh) do mask of alarm interrupt signal. Alarm detection state is indicated as AOUT of ALARM CONTROL register (0Dh), and the alarm can be released by writing "1" at the bit. Alarm B is also controlled as same as Alarm A is. Note: User just need to write "1" to release the alarm, and not need to write "0" after "1". User doesn't need to wait 62S from CS assertion. 2.9.6 Periodic Interrupt function This is a function, which generates interrupt periodically. The timing of cycle can be selected from 2Hz (0.5sec clock pulse), 1Hz (1sec clock pulse), 1/60Hz (minutes), 1/3600Hz (hour), and month (first day of each month). The cycle is set using CT2-CT0 value in CTFG CONTROL register (0Eh). The state when interrupt is generated is indicated at INTRA bit of CTFG CONTROL register (0Eh). INT MASK register (1Fh) only does mask of periodic interrupt signal. There are two kinds of pattern of CTFG Interrupt signal output. * * Hold the value when the interrupt is occurred (level). After the interrupt event is happened, assert interrupt signal in certain time period then release it (pulse). REV.PrP 2/6/02 - 25 - PRELIMINARY TECHNICAL DATA ADP3500 In level case, interrupt is occurred at each 0 min (1/60Hz), 0 o'clock (1/3600Hz) or at first day of month. Because they are happened in long cycle, the value is held at register. After the CPU checks the state, it is released by writing "1" at CTFG bit of CTFG CONTROL register. In case of 2Hz and 1Hz, the interrupt is not held because the event happens in short cycle. These event signal output pulse signal of 2Hz or 1Hz in RTC counter directly. Interrupt release operation doesn't affect on the interrupt signal in the case. 2.10 STAY-ALIVE TIMER This is a counter, which increments each 250mS after RTC_RESETIN_N is asserted. It holds its value when the counter counts full up. Signal clk4 is a 4Hz (250mS) clock which generated in USEC counter. The counter can be reset by writing "1" at CLR of Stay-Alive TIMER CONTROL register (0Fh). The RTC_RESETIN_N signal is transferred from a logic input circuit, that is supplied by VBAT, of RESETIN_N. : User just need to write "1" to release the interrupt, and not need to write "0" after "1". clk4 test_reset Stay-Alive Timer RTC_RESETIN_N D TE Note SA[4:0] 5bit counter LE CLRB Register B SO Stay-alive Timer Control register (0Fh): CLR Stay-alive Timer Control register (0Fh): SAx Figure 17. Stay-Alive Timer block diagram rtc_voltage_detect O sa_clear clk4 sa_count[4:0] 0 1 2 3 4 5 Figure 18. Stay-Alive Timer operation timing REV.PrP 2/6/02 - 26 - 30 31 0 PRELIMINARY TECHNICAL DATA ADP3500 2.11 REGISTERS 16h LDO Control 3 17h 18h 19h 1Ah LDO2 Gain Keypad Column/B-light Register Keypad Row GPIO Control Register 1Bh GPIO MASK GPIO Register 1Dh GPIO INT 1Eh D6 D5 S5 M5 Y6 Y5 AM5 AW6 AW5 BM5 BW6 BW5 Y4 AM4 AH4 AW4 BM4 BH4 BW4 CLR SA4 D3 MO3 Y3 AM3 AH3 AW3 BM3 BH3 BW3 ALA_EN CTFG SA3 CHV0 MV4 MV3 MV2 LDO11 D1 S1 M1 H1 W1 D1 MO1 Y1 AM1 AH1 AW1 BM1 BH1 BW1 ALB_EN CT1 SA1 CHI REF0 MV1 LDO5 LDO10 LDO9 LDO8 CHV1 D4 S4 M4 H4 D3 S3 M3 H3 D4 INT Register 1Fh INT MASK 20h DATA IN KI5 Power OFF 3Fh TEST register (option) IN T7 IR ST 7 MS K7 INT6 IRST6 INT5 D0 S0 M0 H0 W0 D0 MO0 Y0 AM0 AH0 AW0 BM0 BH0 BW0 Bout CT0 SA0 CHEN MVEN MV0 LDO4 Comment Note 1,5 Note 1,5 Note 1,5 Note 1,5 Note 1,5 Note 1,5 Note 1,5 Note 5 Note 5 Note 5 Note 5 Note 5 Note 5 Note 5 Note 5 Note 5 Note 4 Note 4 Note 4 Note 4 Note 7 Note 4 GPMSK3 GPMSK2 GPMSK1 GPI3 GPO3 GPINT3 GPRST3 GPI2 GPO2 GPINT2 GPRST2 GPI1 GPO1 GPINT1 GPRST1 INT4 INT3 IRST3 INT2 IRST2 INT1 IRST1 INT0 IRST0 Note 2,6 BL KI4 G23 KO3 KI3 GPC3 G22 KO2 KI2 GPC2 G21 KO1 KI1 GPC1 Note 4 Note 4 Note 6 Note 6 Note 6 Note 6 Note 6 Note 2,6 MSK6 MSK5 MSK4 MSK3 MSK2 MSK1 MSK0 Note 6 DI6 DI5 DI4 DI3 DI2 DI1 Note 6 LDOENB USENB DI0 PWROF F TEST O 21h D2 S2 M2 H2 W2 D2 MO2 Y2 AM2 AH2 AW2 BM2 BH2 BW2 Aout CT2 SA2 LDO7 ALLOF F G20 KO0 KI0 GPC0 GPMSK 0 GPI0 GPO0 GPINT0 GPRST0 B SO 1Ch D7 TE Description Sec. Counter Min. Counter Hour Counter Week Counter Day Counter Month Counter Year Counter Alarm_A Min Register Alarm_A Hour Register Alarm_A Week Register Alarm_B Min Register Alarm_B Hour Register Alarm_B Week Register (Option) Alarm Control Periodic Interrupt Control Stay-Alive Timer Control Charger Control Charger MVBAT Control Charger MVBAT LDO Control 1 Not available LDO Control 2 LE ADDR 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h Note 6 Note 3,5 Notes: 1. For the RTC counter data protection, the access should be waited for certain time (62S) period after CS signal assertion. (Refer to RTC counter section for the wait time). 2. The INT reset operation will be valid at 62S or later after its setting. 3. This is a set register for internal test, and should not be accessed at normal operation. 4. Analog block control registers. They control LDO etc. They are powered by VBAT. 5. Registers regarding RTC counter. They are powered by RTCV. 6. Registers for INT, GPIO, KEYPAD I/F etc. They are powered by VBAT. 7. Not available. REV.PrP 2/6/02 - 27 - PRELIMINARY TECHNICAL DATA ADP3500 Typical Performance Characteristics (Vin = 4.2 V, TA = 25 C) 2.879 2.925 2.879 Output Voltage, V Output Voltage, V 2.920 2.915 2.910 2.905 2.878 2.878 2.877 TE 2.877 2.900 2.876 0 50 100 150 0 Output Current, mA 0.2 0.4 0.6 0.8 1 Output Current, mA TPC1, LDO1a load regulation TPC2, LDO1b load regulation 2.813 LE 2.872 2.813 2.870 Output Voltage, V Output Voltage, V 2.813 2.868 2.866 2.864 2.812 2.812 2.812 B SO 2.812 2.862 2.812 2.860 0 10 20 30 40 2.811 0 50 0.05 0.1 2.915 2.915 2.910 2.910 2.895 2.890 0.25 0.3 0.35 2.905 2.900 2.895 2.890 2.885 2.885 0 50 100 150 200 0 Output Current, mA 50 100 150 Output Current, mA TPC5, LDO4 load regulation REV.PrP 2/6/02 Output Voltage, V 2.920 2.900 0.2 TPC4, LDO6b load regulation 2.920 O Output Voltage, V TPC3, LDO6a load regulation 2.905 0.15 Output Current, mA Output Current, mA TPC6, LDO7 load regulation - 28 - 200 PRELIMINARY TECHNICAL DATA ADP3500 PACKAGE DIMENSION ST-64A 64-Lead Thin Plastic Quad Flatpack [LQFP] 7 X 7mm Body, 1.4mm Thick 0.030 (0.75) 0.024 (0.60) 0.018 (0.45) 0.063 (1.60) MAX 0.354 (9.00) BSC SQ 49 64 1 48 SEATING PLANE 0.276 (7.00) BSC SQ TOP VIEW 0.003 (0.008) MAX LEAD COPLANARITY 16 TE (PINS DOW N) 33 17 0.009 (0.23) 0.007 (0.18) 0.005 (0.13) 0.057 (1.45) 0.055 (1.40) 0.053 (1.35) LE 0.016 (0.4) BSC 32 7 8 0 8 O B SO 0.006 (0.15) 0.002 (0.05) CONTROLLING DIMENSIONS ARE IN MILLIMETERS REV.PrP 2/6/02 - 29 -