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Rev. 7.00 Jan 31, 2006 page ii of xxvi Preface The SH7032 and SH7034 are microprocessors that integrate peripheral functions necessary for system configuration with a 32-bit internal architecture SH1-DSP CPU as its core. The SH7032 and SH7034's on-chip peripheral functions include an interrupt controller, timers, serial communication interfaces, a user break controller (UBC), a bus state controller (BSC), a direct memory access controller (DMAC), and I/O ports, making it ideal for use as a microcomputer in electronic devices that require high speed together with low power consumption. Intended Readership: This manual is intended for users undertaking the design of an application system using the SH7032 and SH7034. Readers using this manual require a basic knowledge of electrical circuits, logic circuits, and microcomputers. Purpose: The purpose of this manual is to give users an understanding of the hardware functions and electrical characteristics of the SH7032 and SH7034. Details of execution instructions can be found in the SH-1, SH-2, SH-DSP Software Manual, which should be read in conjunction with the present manual. Using this Manual: * For an overall understanding of the SH7032 and SH7034's functions Follow the Table of Contents. This manual is broadly divided into sections on the CPU, system control functions, peripheral functions, and electrical characteristics. * For a detailed understanding of CPU functions Refer to the separate publication SH-1, SH-2, SH-DSP Software Manual. Note on bit notation: Related Material: Bits are shown in high-to-low order from left to right. The latest information is available at our Web Site. Please make sure that you have the most up-to-date information available. http://www.renesas.com/ Rev. 7.00 Jan 31, 2006 page iii of xxvi User's Manuals on the SH7032 and SH7034: Manual Title Document No. SH7032 and SH7034 Hardware Manual This manual SH-1, SH-2, SH-DSP Software Manual REJ09B0171-0500 Users manuals for development tools: Manual Title Document No. C/C++ Complier, Assembler, Optimized Linkage Editor User's Manual REJ10B0152-0101 Simulator Debugger Users Manual REJ10B0210-0200 High-performance Embedded Workshop Users Manual REJ10J0886-0300 Application Note: Manual Title Document No. C/C++ Complier REJ05B0463-0300 Rev. 7.00 Jan 31, 2006 page iv of xxvi Organization of This Manual Table 1 describes how this manual is organized. Figure 1 shows the relationships between the sections within this manual. Table 1 Manual Organization Category Section Title Abbreviation Overview 1. Overview -- Features, internal block diagram, pin layout, pin functions CPU 2. CPU CPU Register configuration, data structure. instruction features, instruction types, instruction lists Operating Modes 3. Operating Modes -- MCU mode, PROM mode Internal Modules 4. Exception Handling -- Resets, address errors, interrupts, trap instructions, illegal instructions 5. Interrupt Controller INTC NMI interrupts, user break interrupts, IRQ interrupts, on-chip module interrupts 6. User Break Controller UBC Break address and break bus cycle selection Clock 7. Clock Pulse Generator CPG Crystal pulse generator, duty correction circuit Buses 8. Bus State Controller BSC Division of memory space, DRAM interface, refresh, wait state control, parity control 9. Direct Memory Access Controller DMAC Auto request, external request, on-chip peripheral module request, cycle steal mode, burst mode 10. 16-Bit Integrated Timer Pulse Unit ITU Waveform output mode, input capture function, counter clear function, buffer operation, PWM mode, complementary PWM mode, reset synchronized mode, synchronized operation, phase counting mode, compare match output mode 11. Programmable Timing Pattern Controller TPC Compare match output triggers, nonoverlap operation 12. Watchdog Timer WDT Watchdog timer mode, interval timer mode Timers Contents Rev. 7.00 Jan 31, 2006 page v of xxvi Category Section Title Abbreviation Data Processing 13. Serial Communication Interface SCI Asynchronous mode, synchronous mode, multiprocessor communication function 14. A/D Converter A/D Single mode, scan mode, activation by external trigger 15. Pin Function Controller PFC Pin function selection 16. Parallel I/O Ports I/O I/O ports 17. ROM ROM PROM mode, high-speed programming system 18. RAM RAM On-chip RAM 19. Power-Down State -- Sleep mode, standby mode Electrical Characteristics -- Absolute maximum ratings, AC characteristics, DC characteristics, operation timing Pins Memory Power-Down State Electrical 20. Characteristics Rev. 7.00 Jan 31, 2006 page vi of xxvi Contents 1. Overview 3. Operating modes 2. CPU On-chip modules 4. Exception handling 5. Interrupt controller (INTC) 6. User break controller (UBC) 7. Clock pulse generator (CPG) Timers Buses 8. Bus state controller (BSC) 10. 16-bit integrated timer pulse unit (ITU) 9. Direct memory access controller (DMAC) 11. Programmable timing pattern controller (TPC) 12. Watchdog timer (WDT) Memory Data processing 17. ROM 13. Serial communication interface (SCI) 18. RAM Pins 14. A/D converter 15. Pin function controller (PFC) 16. Parallel I/O ports 19. Power-down state 20. Electrical characteristics Figure 1 Manual Organization Rev. 7.00 Jan 31, 2006 page vii of xxvi Addresses of On-Chip Peripheral Module Registers The on-chip peripheral module registers are located in the on-chip peripheral module space (area 5: H'5000000-H'5FFFFFF), but since the actual register space is only 512 bytes, address bits A23-A9 are ignored. 32k shadow areas in 512 byte units that contain exactly the same contents as the actual registers are thus provided in the on-chip peripheral module space. In this manual, register addresses are specified as though the on-chip peripheral module registers were in the 512 bytes H'5FFFE00-H'5FFFFFF. Only the values of the A27-A24 and A8-A0 bits are valid; the A23-A9 bits are ignored. When area H'5000000-H'50001FF is accessed, for example, the result will be the same as when area H'5FFFE00-H'5FFFFFF is accessed. For more details, see Section 8.3.5, Area Descriptions: Area 5. Rev. 7.00 Jan 31, 2006 page viii of xxvi List of Items Revised or Added for This Version Item Page Revision (See Manual for Details) All * All references to Hitachi, Hitachi, Ltd., Hitachi Semiconductors, and other Hitachi brand names changed to Renesas Technology Corp. * Designation for categories changed from "series" to "group" * Changes due to change in package codes. FP-112 PRQP0112JA-A FP-120 PTQP0120LA-A 1.1 SuperH Microcomputer Features 6 Table amended Product Number On-Chip Operating Operating ROM Voltage Frequency Temperature Range Model Marking Model No.*2 SH7032 ROMless 5.0 V -20 to +75 C HD6417032F20 HD6417032F20 -40 to +85 C HD6417032FI20 HD6417032FI20 2 to 12.5 MHz -20 to +75 C HD6417032VF12 HD6417032VF12 -40 to +85 C HD6417032VFI12 HD6417032VFI12 -20 to +75 C HD6477034F20 HD6477034F20 -40 to +85 C HD6477034FI20 HD6477034FI20 Table 1.2 Product Lineup 3.3 V SH7034 2.3.2 Addressing Modes 27 PROM 5.0 V 2 to 20 MHz 2 to 20 MHz 3.3 V 2 to12.5 MHz -20 to +75 C HD6477034VF12 HD6477034VF12 5.0 V 2 to 20 MHz -20 to +75 C HD6477034X20 HD6477034TE20 Package 112-pin plastic QFP (PRQP0112JA-A) 112-pin plastic QFP (PRQP0112JA-A) 120-pin plastic TQFP (PTQP0120LA-A) Table amended PC relative addressing added to Rn. Table 2.8 Addressing Modes and Effective Addresses 2.3.3 Instruction Formats 28 Table amended m format added to mmmm: PC relative using Rm Table 2.9 Instruction Formats 2.4.1 Instruction 33 Set by Classification Table 2.11 Instruction Code Format Note amended * Scaling (x1, x2, x4) is performed based on the operand size of the instruction. Rev. 7.00 Jan 31, 2006 page ix of xxvi Item Page 2.4.1 Instruction 37 Set by Classification Table 2.13 Arithmetic Instructions 2.4.2 Operation Code Map 42, 43 Table amended Execution Cycles T Bit Signed operation of (Rn) x (Rm) + MAC MAC 16 x 16 + 42 42-bit 3/(2)* -- 0010nnnnmmmm1111 Signed operation of Rn x Rm MAC 16 x 16 32-bit 1-3* -- 0010nnnnmmmm1110 Unsigned operation of Rn x Rm MAC 16 x 16 32-bit 1-3* -- Instruction Instruction Code Operation MAC.W @Rm+,@Rn+ 0100nnnnmmmm1111 MULS Rm,Rn MULU Rm,Rn Table amended Instruction Code MSB Table 2.18 Operation Code Map 8.5.3 Wait State Control Revision (See Manual for Details) 0000 0000 Fx 1001 0000 Rn Fx 1001 0110 Rn 151 Fx: 0000 LSB MD: 00 Rm NOP 10MD SWAP.B Rm,Rn Fx: 0001 Fx: 0010 Fx: 0011-1111 MD: 01 MD: 10 MD: 11 DIV0U MOVT Rn SWAP.W Rm,Rn Rm,Rn NEG Rm,Rn Description amended Regardless of the state of the WAIT signal, when the RW1 bit, the number of wait states selected by CBR refresh wait state insertion bits 1 and 0 (RLW1, RLW0) in the refresh control register (RCR) are inserted into the CAS-before-RAS refresh cycle. 10.4.5 Reset273 Synchronized PWM Mode Description of PFC setting added Figure 10.31 Procedure for Selecting ResetSynchronized PWM Mode 10.4.6 Complementary PWM Mode NEGC 276 Description of PFC setting added Figure 10.33 Procedure for Selecting Complementary PWM Mode Rev. 7. 00 Jan 31, 2006 page x of xxvi Item Page Revision (See Manual for Details) 20.1.3 AC Characteristics 486 Note amended Note 2. For tACC2, use tcyc x (n + 2) - 30 instead of tcyc x (n + 2) - tAD (or tCSD1) - tRDS. (3) Bus Timing Figure 20.9 Basic Bus Cycle: TwoState Access Figure 20.12 (b) 490 DRAM Bus Cycle (Short-Pitch, HighSpeed Page Mode: Write) Figure amended tWSD3 tWSD4 WRH, WRL, WR (Write) tWDD2 tWDH tWPDD2 tWPDH AD15-AD0 DPH, DPL (Write) DPH, DPL (Write) 20.1.3 AC Characteristics 502 (3) Bus Timing Figure 20.22 Basic Bus Cycle: TwoState Access Figure 20.25 (b) 506 DRAM Bus Cycle (Short-Pitch, HighSpeed Page Mode: Write) Note amended Note 2. For tACC2, use tcyc x (n + 2) - 44 instead of tcyc x (n + 2) - tAD (or tCSD1) - tRDS. Figure amended tWSD3 tWSD4 WRH, WRL, WR (Write) tWDD2 tWDH tWPDD2 tWPDH AD15-AD0 DPH, DPL (Write) DPH, DPL (Write) Rev. 7.00 Jan 31, 2006 page xi of xxvi Item Page Revision (See Manual for Details) 20.2.3 AC Characteristics 538 Note amended (3) Bus Timing Note 2. For tACC2, use tcyc x (n + 2) - 30 instead of tcyc x (n + 2) - tAD (or tCSD1) - tRDS. Figure 20.53 Basic Bus Cycle: TwoState Access Figure 20.56 (b) 542 DRAM Bus Cycle (Short-Pitch, HighSpeed Page Mode: Write) Figure amended tWSD3 tWSD4 WRH, WRL, WR (Write) tWDD2 tWDH tWPDD2 tWPDH AD15-AD0 DPH, DPL (Write) DPH, DPL (Write) Rev. 7. 00 Jan 31, 2006 page xii of xxvi Contents Section 1 Overview ............................................................................................................. 1.1 1.2 1.3 1 SuperH Microcomputer Features ...................................................................................... 1 Block Diagram .................................................................................................................. 8 Pin Descriptions ................................................................................................................ 9 1.3.1 Pin Arrangement .................................................................................................. 9 1.3.2 Pin Functions ....................................................................................................... 11 1.3.3 Pin Layout by Mode............................................................................................. 15 Section 2 CPU ...................................................................................................................... 17 2.1 2.2 2.3 2.4 2.5 Register Configuration ...................................................................................................... 2.1.1 General Registers (Rn)......................................................................................... 2.1.2 Control Registers ................................................................................................. 2.1.3 System Registers .................................................................................................. 2.1.4 Initial Values of Registers.................................................................................... Data Formats ..................................................................................................................... 2.2.1 Data Format in Registers...................................................................................... 2.2.2 Data Format in Memory....................................................................................... 2.2.3 Immediate Data Format ....................................................................................... Instruction Features........................................................................................................... 2.3.1 RISC-Type Instruction Set................................................................................... 2.3.2 Addressing Modes ............................................................................................... 2.3.3 Instruction Formats .............................................................................................. Instruction Set ................................................................................................................... 2.4.1 Instruction Set by Classification .......................................................................... 2.4.2 Operation Code Map............................................................................................ CPU State.......................................................................................................................... 2.5.1 State Transitions................................................................................................... 2.5.2 Power-Down State ............................................................................................... 17 17 18 19 19 20 20 20 21 21 21 24 27 31 31 42 45 45 48 Section 3 Operating Modes............................................................................................... 49 3.1 3.2 Types of Operating Modes and Their Selection................................................................ Operating Mode Descriptions ........................................................................................... 3.2.1 Mode 0 (MCU Mode 0) ....................................................................................... 3.2.2 Mode 1 (MCU Mode 1) ....................................................................................... 3.2.3 Mode 2 (MCU Mode 2) ....................................................................................... 3.2.4 Mode 7 (PROM Mode) ........................................................................................ 49 49 49 49 49 50 Rev. 7.00 Jan 31, 2006 page xiii of xxvi Section 4 Exception Handling ......................................................................................... 51 4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.8 Overview........................................................................................................................... 4.1.1 Exception Handling Types and Priorities ............................................................ 4.1.2 Exception Handling Operation............................................................................. 4.1.3 Exception Vector Table ....................................................................................... Resets ................................................................................................................................ 4.2.1 Reset Types.......................................................................................................... 4.2.2 Power-On Reset ................................................................................................... 4.2.3 Manual Reset ....................................................................................................... Address Errors .................................................................................................................. 4.3.1 Address Error Sources ......................................................................................... 4.3.2 Address Error Exception Handling ...................................................................... Interrupts ........................................................................................................................... 4.4.1 Interrupt Sources.................................................................................................. 4.4.2 Interrupt Priority Rankings .................................................................................. 4.4.3 Interrupt Exception Handling............................................................................... Instruction Exceptions....................................................................................................... 4.5.1 Types of Instruction Exceptions .......................................................................... 4.5.2 Trap Instruction.................................................................................................... 4.5.3 Illegal Slot Instruction.......................................................................................... 4.5.4 General Illegal Instructions.................................................................................. Cases in which Exceptions are Not Accepted ................................................................... 4.6.1 Immediately after Delayed Branch Instruction .................................................... 4.6.2 Immediately after Interrupt-Disabling Instruction ............................................... Stack Status after Exception Handling.............................................................................. Notes ................................................................................................................................. 4.8.1 Value of the Stack Pointer (SP) ........................................................................... 4.8.2 Value of the Vector Base Register (VBR) ........................................................... 4.8.3 Address Errors Caused by Stacking During Address Error Exception Handling 51 51 53 54 56 56 57 57 58 58 58 59 59 59 60 61 61 61 62 62 63 63 63 64 65 65 65 65 Section 5 Interrupt Controller (INTC) ........................................................................... 67 5.1 5.2 Overview........................................................................................................................... 5.1.1 Features................................................................................................................ 5.1.2 Block Diagram..................................................................................................... 5.1.3 Pin Configuration................................................................................................. 5.1.4 Registers............................................................................................................... Interrupt Sources ............................................................................................................... 5.2.1 NMI Interrupts ..................................................................................................... 5.2.2 User Break Interrupt ............................................................................................ 5.2.3 IRQ Interrupts ...................................................................................................... Rev. 7.00 Jan 31, 2006 page xiv of xxvi 67 67 67 69 69 70 70 70 70 5.3 5.4 5.5 5.6 5.2.4 On-Chip Interrupts ............................................................................................... 5.2.5 Interrupt Exception Vectors and Priority Rankings ............................................. Register Descriptions ........................................................................................................ 5.3.1 Interrupt Priority Registers A-E (IPRA-IPRE) ................................................... 5.3.2 Interrupt Control Register (ICR) .......................................................................... Interrupt Operation............................................................................................................ 5.4.1 Interrupt Sequence ............................................................................................... 5.4.2 Stack after Interrupt Exception Handling............................................................. Interrupt Response Time ................................................................................................... Usage Notes ...................................................................................................................... 71 71 74 74 75 76 76 79 80 81 Section 6 User Break Controller (UBC) ....................................................................... 83 6.1 6.2 6.3 6.4 6.5 Overview........................................................................................................................... 83 6.1.1 Features ................................................................................................................ 83 6.1.2 Block Diagram ..................................................................................................... 84 6.1.3 Register Configuration......................................................................................... 85 Register Descriptions ........................................................................................................ 86 6.2.1 Break Address Registers (BAR) .......................................................................... 86 6.2.2 Break Address Mask Register (BAMR)............................................................... 87 6.2.3 Break Bus Cycle Register (BBR)......................................................................... 88 Operation........................................................................................................................... 90 6.3.1 Flow of User Break Operation ............................................................................. 90 6.3.2 Break on Instruction Fetch Cycles to On-Chip Memory...................................... 92 6.3.3 Program Counter (PC) Value Saved in User Break Interrupt Exception Processing ............................................................................................................ 92 Setting User Break Conditions.......................................................................................... 93 Notes ................................................................................................................................. 94 6.5.1 On-Chip Memory Instruction Fetch..................................................................... 94 6.5.2 Instruction Fetch at Branches............................................................................... 94 6.5.3 Instruction Fetch Break........................................................................................95 Section 7 Clock Pulse Generator (CPG) ....................................................................... 97 7.1 7.2 7.3 Overview........................................................................................................................... Clock Source ..................................................................................................................... 7.2.1 Connecting a Crystal Resonator........................................................................... 7.2.2 External Clock Input ............................................................................................ Usage Notes ...................................................................................................................... 97 97 97 99 100 Section 8 Bus State Controller (BSC) ........................................................................... 103 8.1 Overview........................................................................................................................... 103 Rev. 7.00 Jan 31, 2006 page xv of xxvi 8.2 8.3 8.4 8.5 8.6 8.7 8.8 8.1.1 Features................................................................................................................ 8.1.2 Block Diagram..................................................................................................... 8.1.3 Pin Configuration................................................................................................. 8.1.4 Register Configuration......................................................................................... 8.1.5 Overview of Areas ............................................................................................... Register Descriptions ........................................................................................................ 8.2.1 Bus Control Register (BCR) ................................................................................ 8.2.2 Wait State Control Register 1 (WCR1)................................................................ 8.2.3 Wait State Control Register 2 (WCR2)................................................................ 8.2.4 Wait State Control Register 3 (WCR3)................................................................ 8.2.5 DRAM Area Control Register (DCR).................................................................. 8.2.6 Refresh Control Register (RCR) .......................................................................... 8.2.7 Refresh Timer Control/Status Register (RTCSR) ................................................ 8.2.8 Refresh Timer Counter (RTCNT)........................................................................ 8.2.9 Refresh Time Constant Register (RTCOR) ......................................................... 8.2.10 Parity Control Register (PCR) ............................................................................. 8.2.11 Notes on Register Access..................................................................................... Address Space Subdivision ............................................................................................... 8.3.1 Address Spaces and Areas ................................................................................... 8.3.2 Bus Width ............................................................................................................ 8.3.3 Chip Select Signals (CS0-CS7) ........................................................................... 8.3.4 Shadows ............................................................................................................... 8.3.5 Area Descriptions................................................................................................. Accessing External Memory Space .................................................................................. 8.4.1 Basic Timing........................................................................................................ 8.4.2 Wait State Control................................................................................................ 8.4.3 Byte Access Control ............................................................................................ DRAM Interface Operation............................................................................................... 8.5.1 DRAM Address Multiplexing.............................................................................. 8.5.2 Basic Timing........................................................................................................ 8.5.3 Wait State Control................................................................................................ 8.5.4 Byte Access Control ............................................................................................ 8.5.5 DRAM Burst Mode.............................................................................................. 8.5.6 Refresh Control.................................................................................................... Address/Data Multiplexed I/O Space Access ................................................................... 8.6.1 Basic Timing........................................................................................................ 8.6.2 Wait State Control................................................................................................ 8.6.3 Byte Access Control ............................................................................................ Parity Check and Generation ............................................................................................ Warp Mode ....................................................................................................................... Rev. 7.00 Jan 31, 2006 page xvi of xxvi 103 104 105 106 107 109 109 111 113 115 117 119 121 122 123 124 126 127 127 129 129 130 132 139 139 141 144 145 145 147 149 151 153 158 162 162 163 164 164 165 8.9 Wait State Control............................................................................................................. 8.10 Bus Arbitration.................................................................................................................. 8.10.1 Operation of Bus Arbitration ............................................................................... 8.10.2 BACK Operation ................................................................................................. 8.11 Usage Notes ...................................................................................................................... 8.11.1 Usage Notes on Manual Reset ............................................................................. 8.11.2 Usage Notes on Parity Data Pins DPH and DPL ................................................. 8.11.3 Maximum Number of States from BREQ Input to Bus Release.......................... 166 169 170 171 172 172 175 175 Section 9 Direct Memory Access Controller (DMAC) ............................................ 179 9.1 Overview........................................................................................................................... 9.1.1 Features ................................................................................................................ 9.1.2 Block Diagram ..................................................................................................... 9.1.3 Pin Configuration................................................................................................. 9.1.4 Register Configuration......................................................................................... Register Descriptions ........................................................................................................ 9.2.1 DMA Source Address Registers 0-3 (SAR0-SAR3) .......................................... 9.2.2 DMA Destination Address Registers 0-3 (DAR0-DAR3).................................. 9.2.3 DMA Transfer Count Registers 0-3 (TCR0-TCR3) ........................................... 9.2.4 DMA Channel Control Registers 0-3 (CHCR0-CHCR3)................................... 9.2.5 DMA Operation Register (DMAOR)................................................................... Operation........................................................................................................................... 9.3.1 DMA Transfer Flow............................................................................................. 9.3.2 DMA Transfer Requests ...................................................................................... 9.3.3 Channel Priority ................................................................................................... 9.3.4 DMA Transfer Types ........................................................................................... 9.3.5 Number of Bus Cycle States and DREQ Pin Sample Timing.............................. 9.3.6 DMA Transfer Ending Conditions....................................................................... Examples of Use ............................................................................................................... 9.4.1 DMA Transfer between On-Chip RAM and Memory-Mapped External Device .................................................................................................................. 9.4.2 Example of DMA Transfer between On-Chip SCI and External Memory .......... 9.4.3 Example of DMA Transfer Between On-Chip A/D Converter and External Memory................................................................................................................ Usage Notes ...................................................................................................................... 179 179 181 182 183 184 184 184 185 185 190 192 192 194 196 201 208 216 217 Section 10 16-Bit Integrated Timer Pulse Unit (ITU) .............................................. 10.1 Overview........................................................................................................................... 10.1.1 Features ................................................................................................................ 10.1.2 Block Diagram ..................................................................................................... 223 223 223 226 9.2 9.3 9.4 9.5 217 218 219 220 Rev. 7.00 Jan 31, 2006 page xvii of xxvi 10.2 10.3 10.4 10.5 10.6 10.1.3 Input/Output Pins ................................................................................................. 10.1.4 Register Configuration......................................................................................... ITU Register Descriptions ................................................................................................ 10.2.1 Timer Start Register (TSTR) ............................................................................... 10.2.2 Timer Synchro Register (TSNC) ......................................................................... 10.2.3 Timer Mode Register (TMDR) ............................................................................ 10.2.4 Timer Function Control Register (TFCR)............................................................ 10.2.5 Timer Output Control Register (TOCR) .............................................................. 10.2.6 Timer Counters (TCNT) ...................................................................................... 10.2.7 General Registers A and B (GRA and GRB)....................................................... 10.2.8 Buffer Registers A and B (BRA, BRB) ............................................................... 10.2.9 Timer Control Register (TCR)............................................................................. 10.2.10 Timer I/O Control Register (TIOR) ..................................................................... 10.2.11 Timer Status Register (TSR)................................................................................ 10.2.12 Timer Interrupt Enable Register (TIER) .............................................................. CPU Interface.................................................................................................................... 10.3.1 16-Bit Accessible Registers ................................................................................. 10.3.2 8-Bit Accessible Registers ................................................................................... Operation .......................................................................................................................... 10.4.1 Overview.............................................................................................................. 10.4.2 Basic Functions.................................................................................................... 10.4.3 Synchronizing Mode............................................................................................ 10.4.4 PWM Mode ......................................................................................................... 10.4.5 Reset-Synchronized PWM Mode......................................................................... 10.4.6 Complementary PWM Mode............................................................................... 10.4.7 Phase Counting Mode .......................................................................................... 10.4.8 Buffer Mode......................................................................................................... 10.4.9 ITU Output Timing .............................................................................................. Interrupts ........................................................................................................................... 10.5.1 Timing of Setting Status Flags............................................................................. 10.5.2 Status Flag Clear Timing ..................................................................................... 10.5.3 Interrupt Sources and DMAC Activation ............................................................ Notes and Precautions....................................................................................................... 10.6.1 Contention between TCNT Write and Clear........................................................ 10.6.2 Contention between TCNT Word Write and Increment ...................................... 10.6.3 Contention between TCNT Byte Write and Increment........................................ 10.6.4 Contention between GR Write and Compare Match............................................ 10.6.5 Contention between TCNT Write and Overflow/Underflow............................... 10.6.6 Contention between General Register Read and Input Capture........................... Rev. 7.00 Jan 31, 2006 page xviii of xxvi 231 232 234 234 235 237 239 241 242 243 244 245 247 249 251 253 253 255 256 256 257 266 268 272 275 282 284 289 290 290 292 293 294 294 295 296 297 298 299 10.6.7 Contention Between Counter Clearing by Input Capture and Counter Increment................................................................................................ 10.6.8 Contention between General Register Write and Input Capture .......................... 10.6.9 Note on Waveform Cycle Setting ........................................................................ 10.6.10 Contention between BR Write and Input Capture................................................ 10.6.11 Note on Writing in Synchronizing Mode............................................................. 10.6.12 Note on Setting Reset-Synchronized PWM Mode/Complementary PWM Mode.......................................................................................................... 10.6.13 Clearing Complementary PWM Mode ................................................................ 10.6.14 Note on Counter Clearing by Input Capture ........................................................ 10.6.15 ITU Operating Modes .......................................................................................... 300 301 301 302 303 303 304 304 305 Section 11 Programmable Timing Pattern Controller (TPC).................................. 313 11.1 Overview........................................................................................................................... 11.1.1 Features ................................................................................................................ 11.1.2 Block Diagram ..................................................................................................... 11.1.3 Input/Output Pins ................................................................................................. 11.1.4 Registers............................................................................................................... 11.2 Register Descriptions ........................................................................................................ 11.2.1 Port B Control Registers 1 and 2 (PBCR1, PCBR2)............................................ 11.2.2 Port B Data Register (PBDR) .............................................................................. 11.2.3 Next Data Register A (NDRA) ............................................................................ 11.2.4 Next Data Register B (NDRB)............................................................................. 11.2.5 Next Data Enable Register A (NDERA).............................................................. 11.2.6 Next Data Enable Register B (NDERB) .............................................................. 11.2.7 TPC Output Control Register (TPCR) ................................................................. 11.2.8 TPC Output Mode Register (TPMR) ................................................................... 11.3 Operation........................................................................................................................... 11.3.1 Overview.............................................................................................................. 11.3.2 Output Timing...................................................................................................... 11.3.3 Examples of Use of Ordinary TPC Output .......................................................... 11.3.4 TPC Output Non-Overlap Operation ................................................................... 11.3.5 TPC Output by Input Capture .............................................................................. 11.4 Usage Notes ...................................................................................................................... 11.4.1 Non-Overlap Operation........................................................................................ 313 313 314 315 316 317 317 318 318 320 322 322 323 325 326 326 327 328 331 335 336 336 Section 12 Watchdog Timer (WDT) .............................................................................. 12.1 Overview........................................................................................................................... 12.1.1 Features ................................................................................................................ 12.1.2 Block Diagram ..................................................................................................... 339 339 339 340 Rev. 7.00 Jan 31, 2006 page xix of xxvi 12.1.3 Pin Configuration................................................................................................. 12.1.4 Register Configuration......................................................................................... 12.2 Register Descriptions ........................................................................................................ 12.2.1 Timer Counter (TCNT)........................................................................................ 12.2.2 Timer Control/Status Register (TCSR)................................................................ 12.2.3 Reset Control/Status Register (RSTCSR) ............................................................ 12.2.4 Notes on Register Access..................................................................................... 12.3 Operation .......................................................................................................................... 12.3.1 Operation in Watchdog Timer Mode ................................................................... 12.3.2 Operation in Interval Timer Mode ....................................................................... 12.3.3 Operation in Standby Mode ................................................................................. 12.3.4 Timing of Overflow Flag (OVF) Setting ............................................................. 12.3.5 Timing of Watchdog Timer Overflow Flag (WOVF) Setting.............................. 12.4 Usage Notes ...................................................................................................................... 12.4.1 TCNT Write and Increment Contention .............................................................. 12.4.2 Changing CKS2-CKS0 Bit Values...................................................................... 12.4.3 Changing Watchdog Timer/Interval Timer Modes.............................................. 12.4.4 System Reset With WDTOVF............................................................................. 12.4.5 Internal Reset With Watchdog Timer .................................................................. 340 341 341 341 342 343 344 346 346 348 348 349 349 350 350 350 350 351 351 Section 13 Serial Communication Interface (SCI) .................................................... 13.1 Overview........................................................................................................................... 13.1.1 Features................................................................................................................ 13.1.2 Block Diagram..................................................................................................... 13.1.3 Input/Output Pins ................................................................................................. 13.1.4 Register Configuration......................................................................................... 13.2 Register Descriptions ........................................................................................................ 13.2.1 Receive Shift Register.......................................................................................... 13.2.2 Receive Data Register.......................................................................................... 13.2.3 Transmit Shift Register ........................................................................................ 13.2.4 Transmit Data Register ........................................................................................ 13.2.5 Serial Mode Register............................................................................................ 13.2.6 Serial Control Register......................................................................................... 13.2.7 Serial Status Register ........................................................................................... 13.2.8 Bit Rate Register (BRR) ...................................................................................... 13.3 Operation .......................................................................................................................... 13.3.1 Overview.............................................................................................................. 13.3.2 Operation in Asynchronous Mode ....................................................................... 13.3.3 Multiprocessor Communication........................................................................... 13.3.4 Synchronous Operation........................................................................................ 353 353 353 354 355 355 356 356 356 357 357 358 360 363 367 376 376 378 389 397 Rev. 7.00 Jan 31, 2006 page xx of xxvi 13.4 SCI Interrupt Sources and the DMAC .............................................................................. 407 13.5 Usage Notes ...................................................................................................................... 407 Section 14 A/D Converter ................................................................................................. 14.1 Overview........................................................................................................................... 14.1.1 Features ................................................................................................................ 14.1.2 Block Diagram ..................................................................................................... 14.1.3 Configuration of Input Pins.................................................................................. 14.1.4 Configuration of A/D Registers ........................................................................... 14.2 Register Descriptions ........................................................................................................ 14.2.1 A/D Data Registers A-D (ADDRA-ADDRD).................................................... 14.2.2 A/D Control/Status Register (ADCSR)................................................................ 14.2.3 A/D Control Register (ADCR)............................................................................. 14.3 CPU Interface.................................................................................................................... 14.4 Operation........................................................................................................................... 14.4.1 Single Mode (SCAN = 0)..................................................................................... 14.4.2 Scan Mode (SCAN = 1) ....................................................................................... 14.4.3 Input Sampling Time and A/D Conversion Time ................................................ 14.4.4 A/D Conversion Start by External Trigger Input ................................................. 14.5 Interrupts and DMA Transfer Requests ............................................................................ 14.6 Definitions of A/D Conversion Accuracy ......................................................................... 14.7 A/D Converter Usage Notes.............................................................................................. 14.7.1 Setting Analog Input Voltage............................................................................... 14.7.2 Handling of Analog Input Pins ............................................................................ 14.7.3 Switchover between Analog Input and General Port Functions........................... 411 411 411 412 413 414 414 414 415 417 418 420 420 422 424 425 425 426 427 427 427 428 Section 15 Pin Function Controller (PFC) ................................................................... 429 15.1 Overview........................................................................................................................... 429 15.2 Register Configuration ...................................................................................................... 431 15.3 Register Descriptions ........................................................................................................ 431 15.3.1 Port A I/O Register (PAIOR)............................................................................... 431 15.3.2 Port A Control Registers (PACR1 and PACR2) .................................................. 432 15.3.3 Port B I/O Register (PBIOR) ............................................................................... 437 15.3.4 Port B Control Registers (PBCR1 and PBCR2)................................................... 438 15.3.5 Column Address Strobe Pin Control Register (CASCR) ..................................... 444 Section 16 I/O Ports (I/O) ................................................................................................. 447 16.1 Overview........................................................................................................................... 447 16.2 Port A................................................................................................................................ 447 16.2.1 Register Configuration......................................................................................... 447 Rev. 7.00 Jan 31, 2006 page xxi of xxvi 16.2.2 Port A Data Register (PADR).............................................................................. 16.3 Port B ................................................................................................................................ 16.3.1 Register Configuration......................................................................................... 16.3.2 Port B Data Register (PBDR) .............................................................................. 16.4 Port C ................................................................................................................................ 16.4.1 Register Configuration......................................................................................... 16.4.2 Port C Data Register (PCDR) .............................................................................. 448 449 449 450 451 451 452 Section 17 ROM .................................................................................................................. 453 17.1 Overview........................................................................................................................... 453 17.2 PROM Mode..................................................................................................................... 454 17.2.1 Setting PROM Mode............................................................................................ 454 17.2.2 Socket Adapter Pin Correspondence and Memory Map ...................................... 454 17.3 PROM Programming ........................................................................................................ 456 17.3.1 Selecting the Programming Mode........................................................................ 456 17.3.2 Write/Verify and Electrical Characteristics ......................................................... 457 17.3.3 Notes on Writing.................................................................................................. 461 17.3.4 Reliability after Writing ....................................................................................... 462 Section 18 RAM .................................................................................................................. 463 18.1 Overview........................................................................................................................... 463 18.2 Operation .......................................................................................................................... 464 Section 19 Power-Down State ......................................................................................... 19.1 Overview........................................................................................................................... 19.1.1 Power-Down Modes ............................................................................................ 19.1.2 Register ................................................................................................................ 19.2 Standby Control Register (SBYCR) ................................................................................. 19.3 Sleep Mode ....................................................................................................................... 19.3.1 Transition to Sleep Mode..................................................................................... 19.3.2 Exiting Sleep Mode ............................................................................................. 19.4 Standby Mode ................................................................................................................... 19.4.1 Transition to Standby Mode................................................................................. 19.4.2 Exiting Standby Mode ......................................................................................... 19.4.3 Standby Mode Application .................................................................................. 465 465 465 466 466 467 467 467 468 468 469 469 Section 20 Electrical Characteristics.............................................................................. 20.1 SH7032 and SH7034 Electrical Characteristics................................................................ 20.1.1 Absolute Maximum Ratings ................................................................................ 20.1.2 DC Characteristics ............................................................................................... 471 471 471 471 Rev. 7.00 Jan 31, 2006 page xxii of xxvi 20.1.3 AC Characteristics ............................................................................................... (1) Clock Timing................................................................................................. (2) Control Signal Timing................................................................................... (3) Bus Timing.................................................................................................... (4) DMAC Timing .............................................................................................. (5) 16-bit Integrated Timer Pulse Unit Timing ................................................... (6) Programmable Timing Pattern Controller and I/O Port Timing.................... (7) Watchdog Timer Timing ............................................................................... (8) Serial Communication Interface Timing ....................................................... (9) A/D Converter Timing .................................................................................. (10) AC Characteristics Test Conditions ............................................................. 20.1.4 A/D Converter Characteristics ............................................................................. 20.2 SH7034B 3.3 V 12.5 MHz Version and 20 MHz Version*1 Electrical Characteristics .... 20.2.1 Absolute Maximum Ratings ................................................................................ 20.2.2 DC Characteristics ............................................................................................... 20.2.3 AC Characteristics ............................................................................................... (1) Clock Timing................................................................................................. (2) Control Signal Timing................................................................................... (3) Bus Timing.................................................................................................... (4) DMAC Timing .............................................................................................. (5) 16-bit Integrated Timer Pulse Unit Timing ................................................... (6) Programmable Timing Pattern Controller and I/O Port Timing.................... (7) Watchdog Timer Timing ............................................................................... (8) Serial Communication Interface Timing ....................................................... (9) A/D Converter Timing .................................................................................. (10) AC Characteristics Test Conditions ............................................................ 20.2.4 A/D Converter Characteristics ............................................................................. 477 477 479 482 512 514 515 516 517 518 520 521 522 522 522 526 526 528 531 549 551 552 553 554 555 557 558 Appendix A On-Chip Supporting Module Registers ................................................ 559 A.1 A.2 List of Registers ................................................................................................................ Register Tables.................................................................................................................. A.2.1 Serial Mode Register (SMR) SCI ........................................................................ A.2.2 Bit Rate Register (BRR) SCI ............................................................................... A.2.3 Serial Control Register (SCR) SCI ...................................................................... A.2.4 Transmit Data Register (TDR) SCI...................................................................... A.2.5 Serial Status Register (SSR) SCI ......................................................................... A.2.6 Receive Data Register (RDR) SCI ....................................................................... A.2.7 A/D Data Register AH-DL (ADDRAH-ADDRL) A/D...................................... A.2.8 A/D Control/Status Register (ADCSR) A/D........................................................ A.2.9 A/D Control Register (ADCR) A/D..................................................................... 559 569 569 570 570 572 572 574 575 575 577 Rev. 7.00 Jan 31, 2006 page xxiii of xxvi A.2.10 A.2.11 A.2.12 A.2.13 A.2.14 A.2.15 A.2.16 A.2.17 A.2.18 A.2.19 A.2.20 A.2.21 A.2.22 A.2.23 A.2.24 A.2.25 A.2.26 A.2.27 A.2.28 A.2.29 A.2.30 A.2.31 A.2.32 A.2.33 A.2.34 A.2.35 A.2.36 A.2.37 A.2.38 A.2.39 A.2.40 A.2.41 A.2.42 A.2.43 A.2.44 A.2.45 A.2.46 A.2.47 A.2.48 A.2.49 Timer Start Register (TSTR) ITU........................................................................ Timer Synchronization Register (TSNC) ITU..................................................... Timer Mode Register (TMDR) ITU .................................................................... Timer Function Control Register (TFCR) ITU.................................................... Timer Control Registers 0-4 (TCR0-TCR4) ITU ............................................... Timer I/O Control Registers 0-4 (TIOR0-TIOR4) ITU...................................... Timer Interrupt Enable Registers 0-4 (TIER0-TIER4) ITU ............................... Timer Status Registers 0-4 (TSR0-TSR4) ITU .................................................. Timer Counter 0-4 (TCNT0-TCNT4) ITU......................................................... General Registers A0-4 (GRA0-GRA4) ITU ..................................................... General Registers B0-4 (GRB0-GRB4) ITU...................................................... Buffer Registers A3, 4 (BRA3, BRA4) ITU........................................................ Buffer Registers B3, 4 (BRB3, BRB4) ITU ........................................................ Timer Output Control Register (TOCR) ITU ...................................................... DMA Source Address Registers 0-3 (SAR0-SAR3) DMAC ............................. DMA Destination Address Registers 0-3 (DAR0-DAR3) DMAC..................... DMA Transfer Count Registers 0-3 (TCR0-TCR3) DMAC .............................. DMA Channel Control Registers 0-3 (CHCR0-CHCR3) DMAC...................... DMA Operation Registers (DMAOR) DMAC .................................................... Interrupt Priority Setting Register A (IPRA) INTC ............................................. Interrupt Priority Setting Register B (IPRB) INTC ............................................. Interrupt Priority Setting Register C (IPRC) INTC ............................................. Interrupt Priority Setting Register D (IPRD) INTC ............................................. Interrupt Priority Setting Register E (IPRE) INTC.............................................. Interrupt Control Register (ICR) INTC................................................................ Break Address Register H (BARH) UBC............................................................ Break Address Register L (BARL) UBC............................................................. Break Address Mask Register H (BAMRH) UBC............................................... Break Address Mask Register L (BAMRL) UBC ............................................... Break Bus Cycle Register (BBR) UBC ............................................................... Bus Control Register (BCR) BSC........................................................................ Wait State Control Register 1 (WCR1) BSC ....................................................... Wait State Control Register 2 (WCR2) BSC ....................................................... Wait State Control Register 3 (WCR3) BSC ....................................................... DRAM Area Control Register (DCR) BSC ......................................................... Parity Control Register (PCR) BSC..................................................................... Refresh Control Register (RCR) BSC.................................................................. Refresh Timer Control/Status Register (RTCSR) BSC ....................................... Refresh Timer Counter (RTCNT) BSC ............................................................... Refresh Timer Constant Register (RTCOR) BSC................................................ Rev. 7.00 Jan 31, 2006 page xxiv of xxvi 577 578 580 581 582 583 584 585 586 587 588 589 590 591 592 593 594 595 598 599 600 601 602 603 604 605 606 607 608 609 610 611 612 614 615 617 618 619 620 621 A.2.50 A.2.51 A.2.52 A.2.53 A.2.54 A.2.55 A.2.56 A.2.57 A.2.58 A.2.59 A.2.60 A.2.61 A.2.62 A.2.63 A.2.64 A.2.65 A.2.66 A.2.67 A.2.68 A.3 Timer Control/Status Register (TCSR) WDT ...................................................... Timer Counter (TCNT) WDT.............................................................................. Reset Control/Status Register (RSTCSR) WDT .................................................. Standby Control Register (SBYCR) Power-Down State ..................................... Port A Data Register (PADR) Port A .................................................................. Port B Data Register (PBDR) Port B ................................................................... Port C Data Register (PCDR) Port C ................................................................... Port A I/O Register (PAIOR) PFC....................................................................... Port B I/O Register (PBIOR) PFC ....................................................................... Port A Control Register 1 (PACR1) PFC............................................................. Port A Control Register 2 (PACR2) PFC............................................................. Port B Control Register 1 (PBCR1) PFC ............................................................. Port B Control Register 2 (PBCR2) PFC ............................................................. Column Address Strobe Pin Control Register (CASCR) PFC............................. TPC Output Mode Register (TPMR) TPC........................................................... TPC Output Control Register (TPCR) TPC......................................................... Next Data Enable Register A (NDERA) TPC ..................................................... Next Data Enable Register B (NDERB) TPC...................................................... Next Data Register A (NDRA) TPC (When the Output Triggers of TPC Output Groups 0 and 1 are the Same).......... A.2.69 Next Data Register A (NDRA) TPC (When the Output Triggers of TPC Output Groups 0 and 1 are the Same).......... A.2.70 Next Data Register A (NDRA) TPC (When the Output Triggers of TPC Output Groups 0 and 1 are Different).......... A.2.71 Next Data Register A (NDRA) TPC (When the Output Triggers of TPC Output Groups 0 and 1 are Different).......... A.2.72 Next Data Register B (NDRB) TPC (When the Output Triggers of TPC Output Groups 2 and 3 are the Same).......... A.2.73 Next Data Register B (NDRB) TPC (When the Output Triggers of TPC Output Groups 2 and 3 are the Same).......... A.2.74 Next Data Register B (NDRB) TPC (When the Output Triggers of TPC Output Groups 2 and 3 are Different).......... A.2.75 Next Data Register B (NDRB) TPC (When the Output Triggers of TPC Output Groups 2 and 3 are Different).......... Register Status in Reset and Power-Down States ............................................................. 621 623 623 624 625 626 627 628 629 630 632 634 636 638 639 640 642 642 643 643 644 644 645 645 646 647 647 Appendix B Pin States ....................................................................................................... 650 Appendix C Package Dimensions................................................................................... 656 Rev. 7.00 Jan 31, 2006 page xxv of xxvi Rev. 7.00 Jan 31, 2006 page xxvi of xxvi Section 1 Overview Section 1 Overview 1.1 SuperH Microcomputer Features SuperH microcomputers (SH7000 series) comprise a new generation of reduced instruction set computers (RISC) in which a Renesas-original CPU and the peripheral functions required for system configuration are integrated onto a single chip. The CPU has a RISC-type instruction set. Most instructions can be executed in one system clock cycle, which strikingly improves instruction execution speed. In addition, the CPU has a 32-bit internal architecture for enhanced data-processing ability. As a result, the CPU enables highperformance systems to be constructed with advanced functionality at low cost, even in applications such as realtime control that require very high speeds, an impossibility with conventional microcomputers. SH microcomputers include peripheral functions such as large-capacity ROM, RAM, a direct memory access controller (DMAC), timers, a serial communication interface (SCI), an A/D converter, an interrupt controller (INTC), and I/O ports. External memory access support functions enable direct connection to SRAM and DRAM. These features can drastically reduce system cost. For on-chip ROM, masked ROM or electrically programmable ROM (PROM) can be selected. The PROM version can be programmed by users with a general-purpose PROM programmer. Table 1.1 lists the features of the SH microcomputers (SH7032 and SH7034). Rev. 7.00 Jan 31, 2006 page 1 of 658 REJ09B0272-0700 Section 1 Overview Table 1.1 Features of the SH7032 and SH7034 Microcomputers Feature Description CPU Original Renesas architecture 32-bit internal data paths General-register machine: Sixteen 32-bit general registers Three 32-bit control registers Four 32-bit system registers RISC-type instruction set: Instruction length: 16-bit fixed length for improved code efficiency Load-store architecture (basic arithmetic and logic operations are executed between registers) Delayed unconditional branch instructions reduce pipeline disruption Instruction set optimized for C language Instruction execution time: one instruction/cycle (50 ns/instruction at 20MHz operation) Address space: 4 Gbytes available in the architecture On-chip multiplier: multiplication operations (16 bits x 16 bits 32 bits) executed in 1-3 cycles, and multiplication/accumulation operations (16 bits x 16 bits + 42 bits 42 bits) executed in 2-3 cycles Five-stage pipeline Operating modes Operating modes: On-chip ROMless mode On-chip ROM mode (SH7034 only) Processing states: Power-on reset state Manual reset state Exception handling state Program execution state Power-down state Bus-released state Power-down states: Sleep mode Software standby mode Rev. 7.00 Jan 31, 2006 page 2 of 658 REJ09B0272-0700 Section 1 Overview Feature Description Interrupt controller (INTC) Nine external interrupt pins (NMI, IRQ0-IRQ7) Thirty-one internal interrupt sources Sixteen programmable priority levels User break controller (UBC) Generates an interrupt when the CPU or DMAC generates a bus cycle with specified conditions Simplifies configuration of an on-chip debugger Clock pulse generator (CPG) On-chip clock pulse generator (maximum operating frequency: 20 MHz): Bus state controller (BSC) Supports external memory access: 20-MHz pulses can be generated from a 20-MHz crystal with a duty cycle correcting circuit Sixteen-bit external data bus Address space divided into eight areas with the following preset features: Bus size (8 or 16 bits) Number of wait cycles can be defined by user. Type of area (external memory area, DRAM area, etc.) Simplifies connection to ROM, SRAM, DRAM, and peripheral I/O When the DRAM area is accessed: RAS and CAS signals for DRAM are output Tp cycles can be generated to assure RAS precharge time Address multiplexing is supported internally, so DRAM can be connected directly Chip select signals (CS0 to CS7) are output for each area DRAM refresh function: Programmable refresh interval Supports CAS-before-RAS refresh and self-refresh modes DRAM burst access function: Supports high-speed access modes for DRAM Wait cycles can be inserted by an external WAIT signal One-stage write buffer improves the system performance Data bus parity can be generated and checked Rev. 7.00 Jan 31, 2006 page 3 of 658 REJ09B0272-0700 Section 1 Overview Feature Description Direct memory access controller (DMAC) (4 channels) Permits DMA transfer between the following modules: External memory External I/O On-chip memory Peripheral on-chip modules (except DMAC) DMA transfer can be requested from external pins, on-chip SCI, on-chip timers, and on-chip A/D converter Cycle-steal mode or burst mode Channel priority level is selectable Channels 0 and 1: dual or single address transfer mode is selectable; external request sources are supported; channels 2 and 3: dual address transfer mode, internal request sources only 16-bit integrated timer pulse unit (ITU) Ten types of waveforms can be output Input pulse width and cycle can be measured PWM mode: pulse output with 0-100% duty cycle (maximum resolution: 50 ns) Complementary PWM mode: can output a maximum of three pairs of non-overlapping PWM waveforms Phase counting mode: can count up or down according to the phase of an external two-phase clock Timing pattern controller (TPC) Maximum 16-bit output (4 bits x 4 channels) can be output Non-overlap intervals can be established between pairs of waveforms Timing-source timer is selectable Watchdog timer (WDT) (1 channel) Can be used as watchdog timer or interval timer Timer overflow can generate an internal reset, external signal, or interrupt Power-on reset or manual reset can be selected as the internal reset Serial communication interface (SCI) (2 channels) Asynchronous or synchronous mode is selectable Can transmit and receive simultaneously (full duplex) On-chip baud rate generator in each channel Multiprocessor communication function A/D converter Ten bits x 8 channels Can be externally triggered Variable reference voltage Rev. 7.00 Jan 31, 2006 page 4 of 658 REJ09B0272-0700 Section 1 Overview Feature Description I/O ports Total of 40 I/O lines (32 input/output lines, 8 input-only lines): Port A: 16 input/output lines (input or output can be selected for each bit) Port B: 16 input/output lines (input or output can be selected for each bit) Port C: 8 input lines Large on-chip memory SH7034 (on-chip ROM version): 64-kbyte electrically programmable ROM or masked ROM, and 4-kbyte RAM SH7032 (ROMless version): 8-kbyte RAM 32-bit data can be accessed in one clock cycle Rev. 7.00 Jan 31, 2006 page 5 of 658 REJ09B0272-0700 Section 1 Overview Table 1.2 Product Lineup Product Number On-Chip Operating Operating ROM Voltage Frequency SH7032 ROMless 5.0 V 3.3 V SH7034 PROM Mask ROM 5.0 V 2 to 20 MHz Temperature Range Model Marking Model No.*2 -20 to +75C HD6417032F20 HD6417032F20 -40 to +85C HD6417032FI20 HD6417032FI20 2 to 12.5 MHz -20 to +75C HD6417032VF12 HD6417032VF12 -40 to +85C HD6417032VFI12 HD6417032VFI12 2 to 20 MHz -20 to +75C HD6477034F20 HD6477034F20 -40 to +85C HD6477034FI20 HD6477034FI20 Package 112-pin plastic QFP (PRQP0112JA-A) 112-pin plastic QFP (PRQP0112JA-A) 3.3 V 2 to12.5 MHz -20 to +75C HD6477034VF12 HD6477034VF12 5.0 V 2 to 20 MHz -20 to +75C HD6477034X20 HD6477034TE20 120-pin plastic TQFP (PTQP0120LA-A) 5.0 V 2 to 20 MHz -20 to +75C HD6437034AF20 HD6437034AF20 -40 to +85C HD6437034AFI20 HD6437034AFI20 112-pin plastic QFP (PRQP0112JA-A) 2 to 12.5 MHz -20 to +75C HD6437034AVF12 HD6437034AF12 -40 to +85C HD6437034AVFI12 HD6437034AFI12 3.3 V 5.0 V 3.3 V ROMless 5.0 V 3.3 V 2 to 20 MHz -20 to +75C HD6437034AX20 -40 to +85C HD6437034AXI20 2 to 12.5 MHz -20 to +75C HD6437034AVX12 HD6437034ATE20 120-pin plastic TQFP (PTQP0120LA-A) HD6437034ATE12 HD6437034ATEI12 HD6437034ATEI20 -40 to +85C HD6437034AVXI12 -20 to +75C HD6417034F20 HD6417034F20 -40 to +85C HD6417034FI20 HD6417034FI20 2 to 12.5 MHz -20 to +75C HD6417034VF12 HD6417034VF12 -40 to +85C HD6417034VFI12 HD6417034VFI12 -20 to +75C HD6417034X20 HD6417034TE20 -40 to +85C 2 to 20 MHz 5.0 V 2 to 20 MHz HD6417034XI20 HD6417034TEI20 3.3 V 2 to 12.5 MHz -20 to +75C HD6417034VX12 HD6417034VTE12 -40 to +85C HD6417034VXI12 HD6417034VTEI12 Rev. 7.00 Jan 31, 2006 page 6 of 658 REJ09B0272-0700 112-pin plastic QFP (PRQP0112JA-A) 120-pin plastic TQFP (PTQP0120LA-A) Section 1 Overview Product Number On-Chip Operating Operating ROM Voltage Frequency SH7034B*1 Mask ROM 3.3 V ROMless 3.3 V Temperature Range Model 4 to 12.5 MHz -20 to +75C Package HD6437034BVF12 6437034B(***)F -20 to +75C HD6437034BVX12 6437034B(***)X -40 to +85C HD6437034BVXW12 6437034B(***)XW -20 to +75C -40 to +85C HD6417034BVF20 HD6417034BVF20 112-pin plastic QFP HD6417034BVFW20 HD6417034BVFW2 (PRQP0112JA-A) 0 -20 to +75C HD6417034BVX20 -40 to +85C HD6417034BVXW20 6417034BVTEW20 -40 to +85C 4 to 20 MHz Marking Model No.*2 112-pin plastic QFP HD6437034BVFW12 6437034B(***)FW (PRQP0112JA-A) 6417034BVTE20 120-pin plastic TQFP (PTQP0120LA-A) 120-pin plastic TQFP (PTQP0120LA-A) Notes: 1. The electrical characteristics of the SH7034B mask ROM version and SH7034 PROM version are different. 2. For mask ROM versions, (***) is the ROM code. Rev. 7.00 Jan 31, 2006 page 7 of 658 REJ09B0272-0700 Section 1 Overview Address RES WDTOVF MD2 MD1 MD0 NMI CPU *2 VCC VCC VCC VCC VCC VCC VCC VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS Serial communication interface (2 channels) Programmable timing pattern controller Port C Direct memory access controller : Peripheral address bus (24 bits) : Peripheral data bus (16 bits) : Internal address bus (24 bits) : Internal upper data bus (16 bits) : Internal lower data bus (16 bits) AD15 AD14 AD13 AD12 AD11 AD10 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 Bus state controller 16-bit integrated timer pulse unit A/D Watchdog converter timer Port B PC7/AN7 PC6/AN6 PC5/AN5 PC4/AN4 PC3/AN3 PC2/AN2 PC1/AN1 PC0/AN0 AVref AVCC AVSS User Interrupt break controller controller A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 (HBS) RAM*1 PB15/TP15/IRQ7 PB14/TP14/IRQ6 PB13/TP13/IRQ5/SCK1 PB12/TP12/IRQ4/SCK0 PB11/TP11/TxD1 PB10/TP10/RxD1 PB9/TP9/TxD0 PB8/TP8/RxD0 PB7/TP7/TOCXB4/TCLKD PB6/TP6/TOCXA4/TCLKC PB5/TP5/TIOCB4 PB4/TP4/TIOCA4 PB3/TP3/TIOCB3 PB2/TP2/TIOCA3 PB1/TP1/TIOCB2 PB0/TP0/TIOCA2 VCC(VPP) Clock pulse generator CK EXTAL XTAL PROM or masked ROM*1 Address Port A Data/address CS3/CASL CS2 CS1/CASH CS0 A21 A20 A19 A18 A17 A16 Block Diagram PA15/IRQ3/DREQ1 PA14/IRQ2/DACK1 PA13/IRQ1/DREQ0/TCLKB PA12/IRQ0/DACK0/TCLKA PA11/DPH/TIOCB1 PA10/DPL/TIOCA1 PA9/AH/IRQOUT/ADTRG PA8/BREQ PA7/BACK PA6/RD PA5/WRH (LBS) PA4/WRL (WR) PA3/CS7/WAIT PA2/CS6/TIOCB0 PA1/CS5/RAS PA0/CS4/TIOCA0 1.2 Notes: 1. The SH7032 has 8 kB of RAM and no PROM or masked ROM. The SH7034 has 4 kB of RAM and 64 kB of PROM or masked ROM. 2. VPP: SH7034 (PROM version) Figure 1.1 Block Diagram Rev. 7.00 Jan 31, 2006 page 8 of 658 REJ09B0272-0700 Section 1 Overview Pin Descriptions 1.3.1 Pin Arrangement Top view (PRQP0112JA-A) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 PA3/CS7/WAIT PA2/CS6/TIOCB0 PA1/CS5/RAS PA0/CS4/TIOCA0 VSS CS3/CASL CS2 CS1/CASH CS0 A21 A20 A19 A18 VCC A17 A16 VSS A15 A14 A13 A12 A11 A10 A9 A8 VSS A7 A6 PB14/TP14/IRQ6 PB15/TP15/ VSS AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 VSS AD8 AD9 VCC AD10 AD11 AD12 AD13 AD14 AD15 VSS A0(HBS) A1 A2 A3 A4 A5 AVCC AVref PC0/AN0 PC1/AN1 PC2/AN2 PC3/AN3 AVSS PC4/AN4 PC5/AN5 PC6/AN6 PC7/AN7 VSS PB0/TP0/TIOCA2 PB1/TP1/TIOCB2 VCC PB2/TP2/TIOCA3 PB3/TP3/TIOCB3 PB4/TP4/TIOCA4 PB5/TP5/TIOCB4 PB6/TP6/TOCXA4/TCLKC PB7/TP7/TOCXB4/TCLKD VSS PB8/TP8/RxD0 PB9/TP9/TxD0 PB10/TP10/RxD1 PB11/TP11/TxD1 PB12/TP12/IRQ4/SCK0 PB13/TP13/IRQ5/SCK1 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 VCC VCC MD2 MD1 MD0 RES WDTOVF VCC (VPP)*1 NMI VCC XTAL EXTAL VSS CK VCC PA15/IRQ3/DREQ1 PA14/IRQ2/DACK1*2 PA13/IRQ1/DREQ0/TCLKB PA12/IRQ0/DACK0*2/TCLKA PA11/DPH/TIOCB1 PA10/DPL/TIOCA1 PA9/AH/IRQOUT/ADTRG PA8/BREQ VSS PA7/BACK PA6/RD PA5/WRH (LBS) PA4/WRL (WR) 1.3 Notes: 1. VPP: SH7034 (PROM version) only 2. Initial value (output) Figure 1.2 Pin Arrangement (PRQP0112JA-A) Rev. 7.00 Jan 31, 2006 page 9 of 658 REJ09B0272-0700 Top view (PTQP0120LA-A) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 NC*3 PB14/TP14/IRQ6 PB15/TP15/IRQ7 VSS AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 VSS AD8 AD9 VCC AD10 AD11 AD12 AD13 AD14 AD15 VSS A0(HBS) A1 A2 A3 A4 A5 NC*3 AVCC AVref PC0/AN0 PC1/AN1 PC2/AN2 PC3/AN3 AVSS PC4/AN4 PC5/AN5 PC6/AN6 PC7/AN7 VSS PB0/TP0/TIOCA2 NC*3 PB1/TP1/TIOCB2 VCC PB2/TP2/TIOCA3 PB3/TP3/TIOCB3 PB4/TP4/TIOCA4 PB5/TP5/TIOCB4 PB6/TP6/TOCXA4/TCLKC PB7/TP7/TOCXB4/TCLKD VSS PB8/TP8/RxD0 PB9/TP9/TxD0 PB10/TP10/RxD1 PB11/TP11/TxD1 PB12/TP12/IRQ4/SCK0 PB13/TP13/IRQ5/SCK1 NC*3 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 NC*3 VCC VCC MD2 MD1 MD0 RES WDTOVF VCC (VPP)*1 NMI VCC XTAL EXTAL VSS CK VCC PA15/IRQ3/DREQ1 PA14/IRQ2/DACK1*2 PA13/IRQ1/DREQ0/TCLKB PA12/IRQ0/DACK0*2/TCLKA PA11/DPH/TIOCB1 PA10/DPL/TIOCA1 PA9/AH/IRQOUT/ADTRG PA8/BREQ VSS PA7/BACK PA6/RD PA5/WRH (LBS) PA4/WRL (WR) NC*3 Section 1 Overview Notes: 1. VPP: SH7034 (PROM version) only 2. Initial value (output) 3. Do not make any connection. Figure 1.3 Pin Arrangement (PTQP0120LA-A) Rev. 7.00 Jan 31, 2006 page 10 of 658 REJ09B0272-0700 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 NC*3 PA3/CS7/WAIT PA2/CS6/TIOCB0 PA1/CS5/RAS PA0/CS4/TIOCA0 VSS CS3/CASL CS2 CS1/CASH CS0 A21 A20 A19 A18 VCC A17 A16 VSS A15 A14 A13 A12 A11 A10 A9 A8 VSS A7 A6 NC*3 Section 1 Overview 1.3.2 Pin Functions Table 1.3 describes the pin functions. Table 1.3 Pin Functions Type Pin No. Pin No. (PRQP0112 (PTQP0120 Symbol JA-A) LA-A) I/O Name and Function Power VCC 15, 43, 70, 16, 46, 75, I 75, 77*, 83, 80, 82*, 88, 84, 99 89, 106 Power: Connected to the power supply. Connect all VCC pins to the system power supply . The chip will not operate if any VCC pin is left unconnected. VSS 3, 12, 22, 31, 40, 52, 61, 72, 96, 106 4, 13, 23, I 34, 43, 55, 66, 77, 102, 113 Ground: Connected to ground. Connect all VSS pins to the system ground. The chip will not operate if any VSS pin is left unconnected. VPP 77* 82* I PROM programming power supply: Connected to the power supply (VCC) during normal operation. Apply +12.5 V when programming the PROM in the SH7034 (PROM version). EXTAL 73 78 I External clock: Connected to a crystal resonator or external clock input having the same frequency as the system clock (CK). XTAL 74 79 I Crystal: Connected to a crystal resonator with the same frequency as the system clock (CK). If an external clock is input at the EXTAL pin, leave XTAL open. CK 71 76 O System clock: Supplies the system clock (CK) to peripheral devices. RES 79 84 I Reset: Low input causes a power-on reset if NMI is high, or a manual reset if NMI is low. WDTOVF 78 83 O Watchdog timer overflow: Overflow output signal from the watchdog timer. BREQ 62 67 I Bus request: Driven low by an external device to request bus ownership. BACK 60 65 O Bus request acknowledge: Indicates that bus ownership has been granted to an external device. By receiving the BACK signal, a device that has sent a BREQ signal can confirm that it has been granted the bus. Clock System control Note: * Pin 77 is VCC in the SH7032 and SH7034 (masked ROM version), and VPP in the SH7034 (PROM version). Rev. 7.00 Jan 31, 2006 page 11 of 658 REJ09B0272-0700 Section 1 Overview Type Pin No. Pin No. (PRQP0112 (PTQP0120 Symbol JA-A) LA-A) I/O Name and Function Operating MD2, mode MD1, control MD0 Interrupts NMI IRQ0- IRQ7 82, 81, 80 76 81 I I 66-69, 111, 71-74, 118, I 112, 1, 2 119, 2, 3 IRQOUT 63 Address bus 87, 86, 85 68 O A21-A0 47-44, 42, 50-47, 45, O 41, 39-32, 44, 42-35, 30-23 33, 32, 29-24 Data bus AD15- AD0 Mode select: Selects the operating mode. Do not change these inputs while the chip is operating. The following table lists the possible operating modes and their corresponding MD2-MD0 values. Bus Operating On-Chip Size in MD2 MD1 MD0 Mode ROM Area 0 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 MCU mode Disabled 8 bits 16 bits 1 Enabled* (Reserved) PROM 2 mode* Nonmaskable interrupt: Nonmaskable interrupt request signal. The rising or falling edge can be selected for signal detection. Interrupt request 0-7: Maskable interrupt request signals. Level input or edge-triggered input can be selected. Slave interrupt request output: Indicates occurrence of an interrupt while the bus is released. Address bus: Outputs addresses. 21-16, 14, 22-17, 15, I/O Data bus: 16-bit bidirectional data bus that is 13, 11-4 14, 12-5 multiplexed with the lower 16 bits of the address bus. DPH 65 70 I/O Upper data bus parity: Parity data for D15-D8. DPL 64 69 I/O Lower data bus parity: Parity data for D7-D0. Notes: 1. Use prohibited in the SH7032 and SH7034 ROM-less versions. 2. Can be used in the SH7034 PROM version. Rev. 7.00 Jan 31, 2006 page 12 of 658 REJ09B0272-0700 Section 1 Overview Type Pin No. Pin No. (PRQP0112 (PTQP0120 Symbol JA-A) LA-A) I/O Name and Function Bus control WAIT (cont) DMAC 16-bit integrated timer pulse unit (ITU) 56 59 I Wait: Requests the insertion of wait states (TW ) into the bus cycle when the external address space is accessed. RAS 54 57 O Row address strobe: DRAM row-address strobe timing signal. CASH 49 52 O Column address strobe high: DRAM columnaddress strobe timing signal. Output to access the upper eight data bits. CASL 51 54 O Column address strobe low: DRAM columnaddress strobe timing. Output to access the lower eight data bits. RD 59 64 O Read: Indicates reading of data from an external device. WRH 58 63 O Upper write: Indicates write access to the upper eight bits of an external device. WRL 57 62 O Lower write: Indicates write access to the lower eight bits of an external device. CS0- CS7 48-51, 53-56 51-54, 56-59 O Chip select 0-7: Chip select signals for accessing external memory and devices. AH 63 68 O Address hold: Address hold timing signal for a device using a multiplexed address/data bus. HBS, LBS 23, 58 24, 63 O Upper/lower byte strobe: Upper and lower byte strobe signals. (Also used as WRH and A0.) WR 57 62 O Write: Brought low during write access. (Also used as WRL.) DREQ0, 67, 69 DREQ1 72, 74 I DMA transfer request (channels 0 and 1): Input pins for external DMA transfer requests. DACK0, 66, 68 DACK1 71, 73 O DMA transfer acknowledge (channels 0 and 1): Indicates that DMA transfer is acknowledged. TIOCA0, 53, 55 TIOCB0 56, 58 I/O ITU input capture/output compare (channel 0): Input capture or output compare pins. TIOCA1, 64, 65 TIOCB1 69, 70 I/O ITU input capture/output compare (channel 1): Input capture or output compare pins. TIOCA2, 97, 98 TIOCB2 103, 105 I/O ITU input capture/output compare (channel 2): Input capture or output compare pins. TIOCA3, 100, 101 TIOCB3 107, 108 I/O ITU input capture/output compare (channel 3): Input capture or output compare pins. Rev. 7.00 Jan 31, 2006 page 13 of 658 REJ09B0272-0700 Section 1 Overview Type 16-bit integrated timer pulse unit (ITU) Pin No. Pin No. (PRQP0112 (PTQP0120 Symbol JA-A) LA-A) I/O Name and Function TIOCA4, 102, 103 TIOCB4 109, 110 I/O ITU input capture/output compare (channel 4): Input capture or output compare pins. TOCXA4, 104, 105 TOCXB4 111, 112 O ITU output compare (channel 4): Output compare pins. TCLKA- 66, 67, 104, 71, 72, 111, I TCLKD 105 112 ITU timer clock input: External clock input pins for ITU counters. TP15- TP0 2, 1, 112-107, 105-100, 98, 97 3, 2, 119-114, 112-107, 105, 103 O Timing pattern output 15-0: Timing pattern output pins. TxD0, Serial comTxD1 munication RxD0, interface RxD1 (SCI) SCK0, SCK1 108, 110 115, 117 O Transmit data (channels 0 and 1): Transmit data output pins for SCI0 and SCI1. 107, 109 114, 116 I Receive data (channels 0 and 1): Receive data input pins for SCI0 and SCI1. 111, 112 118, 119 I/O Serial clock (channels 0 and 1): Clock input/output pins for SCI0 and SCI1. A/D converter 95-92, 90-87 101-98, 96-93 I Analog input: Analog signal input pins. ADTRG 63 68 I A/D trigger input: External trigger input for starting A/D conversion. AVref 86 92 I Analog reference power supply: Input pin for the analog reference voltage. AVCC 85 91 I Analog power supply: Power supply pin for analog circuits. Connect to the VCC potential. AVSS 91 97 I Analog ground: Power supply pin for analog circuits. Connect to the VSS potential. PA15- PA0 69-62, 60-53 74-67, 65-62, 59-56 I/O Port A: 16-bit input/output pins. Input or output can be selected individually for each bit. PB15- PB0 2, 1, 112-107, 105-100, 98, 97 3, 2, 119-114, 112-107, 105, 103 I/O Port B: 16-bit input/output pins. Input or output can be selected individually for each bit. PC7- PC0 95-92, 90-87 101-98, 96-93 I Timing pattern controller (TPC) I/O ports AN7- AN0 Rev. 7.00 Jan 31, 2006 page 14 of 658 REJ09B0272-0700 Port C: 8-bit input pins. Section 1 Overview 1.3.3 Pin Layout by Mode Table 1.4 Pin Layout by Mode Pin No. Pin No. (PRQP0112 (PTQP0120 JA-A) LA-A) MCU Mode PROM Mode (SH7034 PROM Version) Pin No. Pin No. (PRQP0112 (PTQP0120 JA-A) LA-A) MCU Mode PROM Mode (SH7034 PROM Version) -- 1 NC NC 30 33 A7 A7 1 2 PB14/TP14/IRQ6 NC 31 34 VSS VSS 2 3 PB15/TP15/IRQ7 NC 32 35 A8 A8 3 4 VSS VSS 33 36 A9 OE 4 5 AD0 D0 34 37 A10 A10 5 6 AD1 D1 35 38 A11 A11 6 7 AD2 D2 36 39 A12 A12 7 8 AD3 D3 37 40 A13 A13 8 9 AD4 D4 38 41 A14 A14 9 10 AD5 D5 39 42 A15 A15 10 11 AD6 D6 40 43 VSS VSS 11 12 AD7 D7 41 44 A16 A16 12 13 VSS VSS 42 45 A17 VCC 13 14 AD8 NC 43 46 VCC VCC 14 15 AD9 NC 44 47 A18 VCC 15 16 VCC VCC 45 48 A19 NC 16 17 AD10 NC 46 49 A20 NC 17 18 AD11 NC 47 50 A21 NC 18 19 AD12 NC 48 51 CS0 NC 19 20 AD13 NC 49 52 CS1/CASH NC 20 21 AD14 NC 50 53 CS2 NC 21 22 AD15 NC 51 54 CS3/CASL NC 22 23 VSS VSS 52 55 VSS VSS 23 24 A0 (HBS) A0 53 56 PA0/CS4/TIOCA0 NC 24 25 A1 A1 54 57 PA1/CS5/RAS 25 26 A2 A2 55 58 PA2/CS6/TIOCB0 PGM 26 27 A3 A3 56 59 PA3/CS7/WAIT CE 27 28 A4 A4 -- 60 NC NC 28 29 A5 A5 -- 61 NC NC -- 30 NC NC 57 62 PA4/WRL (WR) NC -- 31 NC NC 58 63 PA5/WRH (LBS) NC 29 32 A6 A6 59 64 PA6/RD NC NC Rev. 7.00 Jan 31, 2006 page 15 of 658 REJ09B0272-0700 Section 1 Overview Pin No. Pin No. (PRQP0112 (PTQP0120 JA-A) LA-A) MCU Mode PROM Mode (SH7034 PROM Version) Pin No. Pin No (PRQP0112 (PTQP0120 JA-A) LA-A) MCU Mode PROM Mode (SH7034 PROM Version) 60 65 PA7/BACK NC 87 93 PC0/AN0 VSS 61 66 VSS VSS 88 94 PC1/AN1 VSS 62 67 PA8/BREQ NC 89 95 PC2/AN2 VSS 63 68 PA9/AH/IRQOUT/ NC ADTRG 90 96 PC3/AN3 VSS 64 69 PA10/DPL/ TIOCA1 NC 91 97 AVSS VSS 65 70 PA11/DPH/ TIOCB1 NC 92 98 PC4/AN4 VSS 66 71 PA12/IRQ0/ DACK0/TCLKA NC 93 99 PC5/AN5 VSS 67 72 PA13/IRQ1/ DREQ0/TCLKB NC 94 100 PC6/AN6 VSS 68 73 PA14/IRQ2/ DACK1 NC 95 101 PC7/AN7 VSS 69 74 PA15/IRQ3/ DREQ1 NC 96 102 VSS VSS 70 75 VCC VCC 97 103 PB0/TP0/TIOCA2 NC 71 76 CK NC -- 104 NC 72 77 VSS VSS 98 105 PB1/TP1/TIOCB2 NC 73 78 EXTAL NC 99 106 VCC PB2/TP2/TIOCA3 NC NC VCC 74 79 XTAL NC 100 107 75 80 VCC VCC 101 108 PB3/TP3/TIOCB3 NC 76 81 NMI A9 102 109 PB4/TP4/TIOCA4 NC 77 82 VCC VPP 103 110 PB5/TP5/TIOCB4 NC 78 83 WDTOVF NC 104 111 PB6/TP6/ NC TOCXA4/TCLKC 79 84 RES VSS 105 112 PB7/TP7/ NC TOCXB4/TCLKD 80 85 MD0 VCC 106 113 VSS VSS 81 86 MD1 VCC 107 114 PB8/TP8/RxD0 NC 82 87 MD2 VCC 108 115 PB9/TP9/TxD0 NC 83 88 VCC VCC 109 116 PB10/TP10/RxD1 NC 84 89 VCC VCC 110 117 PB11/TP11/TxD1 NC -- 90 NC NC 111 118 PB12/TP12/IRQ4/ NC SCK0 85 91 AVCC VCC 112 119 PB13/TP13/IRQ5/ NC SCK1 86 92 AVref VCC -- 120 NC Rev. 7.00 Jan 31, 2006 page 16 of 658 REJ09B0272-0700 NC Section 2 CPU Section 2 CPU 2.1 Register Configuration The register set consists of sixteen 32-bit general registers, three 32-bit control registers, and four 32-bit system registers. 2.1.1 General Registers (Rn) General registers Rn consist of sixteen 32-bit registers (R0-R15). General registers are used for data processing and address calculation. Register R0 also functions as an index register. For some instructions, the R0 register must be used. Register R15 functions as a stack pointer to save or restore status registers (SR) and the program counter (PC) during exception handling. 31 0 R0 R1 R2 R3 R4 R0 functions as an index register in the indexed register addressing mode and indirect indexed GBR addressing mode. In some instructions, R0 functions as a source register or a destination register. R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15, SP (hardware stack pointer) R15 functions as a stack pointer (SP) during exception handling. Figure 2.1 General Registers (Rn) Rev. 7.00 Jan 31, 2006 page 17 of 658 REJ09B0272-0700 Section 2 CPU 2.1.2 Control Registers Control registers consist of the 32-bit status register (SR), global base register (GBR), and vector base register (VBR). The status register indicates processing states. The global base register functions as a base address for the indirect GBR addressing mode to transfer data to the registers of on-chip supporting modules. The vector base register functions as the base address of the exception vector area including interrupts. 31 SR 9 8 7 6 5 4 32 1 0 M Q I3 I2 I1 I0 ST SR: Status register T bit: The MOVT, CMP, TAS, TST, BT, BF, SETT, and CLRT instructions use the T bit to indicate true (1) or false (0). The ADDV, ADDC, SUBV, SUBC, DIV0U, DIV0S, DIV1, NEGC, SHAR, SHAL, SHLR, SHLL, ROTR, ROTL, ROTCR and ROTCL instructions also use the T bit to indicate carry/borrow or overflow/underflow S bit: Used by the MAC instruction. Reserved bits. These bits always read 0. The write value should always be 0. Bits I3-I0: Interrupt mask bits. M and Q bits: Used by the DIV0U, DIV0S, and DIV1 instructions. Global base register (GBR): 0 Indicates the base address in indirect GBR addressing mode. The indirect GBR addressing mode is used to transfer data to the on-chip supporting module register area, etc. 31 GBR 31 0 Vector base register (VBR): Stores the base address of the exception vector area. VBR Figure 2.2 Control Registers Rev. 7.00 Jan 31, 2006 page 18 of 658 REJ09B0272-0700 Section 2 CPU 2.1.3 System Registers System registers consist of four 32-bit registers: multiply and accumulate registers high and low (MACH and MACL), procedure register (PR), and program counter (PC). The multiply and accumulate registers store the results of multiply and accumulate operations. The procedure register stores the return address for a subroutine procedure. The program counter stores program addresses to control the flow of the processing. 31 9 (Sign extended) 0 MACH MACL 0 31 PR 0 31 PC Multiply and accumulate (MAC) registers high and low (MACH, MACL): Store the results of multiply and accumulate operations. MACH is sign-extended when read because only the lowest 10 bits are valid. Procedure register (PR): Stores the return address for a subroutine procedure. Program counter (PC): Indicates the fourth byte (second instruction) after the current instruction. Figure 2.3 System Registers 2.1.4 Initial Values of Registers Table 2.1 lists the values of the registers after reset. Table 2.1 Initial Values of Registers Classification Register General registers R0-R14 Control registers System registers Initial Value Undefined R15 (SP) Value of the stack pointer in the vector address table SR Bits I3-I0 are 1111(H'F), reserved bits are 0, and other bits are undefined GBR Undefined VBR H'00000000 MACH, MACL, PR Undefined PC Value of the program counter in the vector address table Rev. 7.00 Jan 31, 2006 page 19 of 658 REJ09B0272-0700 Section 2 CPU 2.2 Data Formats 2.2.1 Data Format in Registers Register operands are always longwords (32 bits). When the memory operand is only a byte (8 bits) or a word (16 bits), it is sign-extended into a longword when stored into a register (figure 2.4). 31 0 Longword Figure 2.4 Data Format in Registers 2.2.2 Data Format in Memory Memory data formats are classified into bytes, words, and longwords. Byte data can be accessed from any address, but an address error will occur if an attempt is made to access word data starting from an address other than 2n or longword data starting from an address other than 4n. In such cases, the data accessed cannot be guaranteed. The hardware stack area, which is referred to by the hardware stack pointer (SP, R15), uses only longword data starting from address 4n because this area stores the program counter and status register (figure 2.5). Address m + 1 Address m 23 31 Address m + 3 Address m + 2 7 15 0 7 Byte 0 7 Byte 0 7 Byte 0 7 Byte 0 Address 2n 15 Address 4n 31 Word 0 15 Word Longword Figure 2.5 Data Format in Memory Rev. 7.00 Jan 31, 2006 page 20 of 658 REJ09B0272-0700 0 0 Section 2 CPU 2.2.3 Immediate Data Format Byte (8-bit) immediate data is located in the instruction code. Immediate data accessed by the MOV, ADD, and CMP/EQ instructions is sign-extended and is handled in registers as longword data. Immediate data accessed by the TST, AND, OR, and XOR instructions is zero-extended and is handled as longword data. Consequently, AND instructions with immediate data always clear the upper 24 bits of the destination register. Word or longword immediate data is not located in the instruction code but rather is stored in a memory table. The memory table is accessed by an immediate data transfer instruction (MOV) using the PC relative addressing mode with displacement. 2.3 Instruction Features 2.3.1 RISC-Type Instruction Set All instructions are RISC type. Their features are as follows: 16-Bit Fixed Length: Every instruction is 16 bits long, making program coding much more efficient. One Instruction/Cycle: Basic instructions can be executed in one cycle using a pipeline system. One-cycle instructions are executed in 50 ns at 20 MHz. Data Length: Longword is the standard data length for all operations. Memory can be accessed in bytes, words, or longwords. Byte or word data accessed from memory is sign-extended and handled as longword data. Immediate data is sign-extended for arithmetic operations or zeroextended for logic operations (handled as longword data). Table 2.2 Sign Extension of Word Data SH7000 Series CPU Description Conventional CPUs MOV.W Data is sign-extended to 32 bits, and R1 becomes H'00001234. It is next operated upon by an ADD instruction. ADD.W @(disp,PC),R1 ADD R1,R0 ........... .DATA.W H'1234 #H'1234,R0 Note: The address of the immediate data is accessed by @(disp, PC). Rev. 7.00 Jan 31, 2006 page 21 of 658 REJ09B0272-0700 Section 2 CPU Load-Store Architecture: Basic operations are executed between registers. For operations that involve memory, data is loaded into to the registers and executed (load-store architecture). Instructions such as AND that manipulate bits, however, are executed directly in memory. Delayed Branch Instructions: Unconditional branch instructions are delayed. Pipeline disruption during branching is reduced by first executing the instruction that follows the branch instruction, and then branching. See the SH-1/SH-2/SH-DSP Software Manual for details. Table 2.3 Delayed Branch Instructions SH7000 Series CPU Description Conventional CPU BRA ADD Executes an ADD before branching to TRGET. ADD.W R1,R0 BRA TRGET TRGET R1,R0 Multiplication/Accumulation Operation: The five-stage pipeline system and the on-chip multiplier enable 16-bit x 16-bit 32-bit multiplication operations to be executed in 1-3 cycles. 16-bit x 16-bit + 42-bit 42-bit multiplication/accumulation operations can be executed in 2-3 cycles. T bit: T bit (in the status register) is set according to the result of a comparison, and in turn is the condition (True/False) that determines if the program will branch. The T bit in the status register is only changed by selected instructions, thus improving the processing speed. Table 2.4 T Bit SH7000 Series CPU Description Conventional CPU CMP/GE R1,R0 BT TRGET0 BF TRGET1 T bit is set when R0 R1. The program branches to TRGET0 when R0 R1 and to TRGET1 when R0<R1. CMP.W R1,R0 BGE TRGET0 BLT TRGET1 ADD TST BT T bit is not changed by ADD. T bit is set when R0 = 0. The program branches if R0 = 0. SUB.W #1,R0 BEQ TRGET #-1,R0 R0,R0 TRGET Immediate Data: Byte (8-bit) immediate data is located in the instruction code. Word or longword immediate data is not located in instruction codes but is stored in a memory table. The memory table is accessed by an immediate data transfer instruction (MOV) using the PC relative addressing mode with displacement. Rev. 7.00 Jan 31, 2006 page 22 of 658 REJ09B0272-0700 Section 2 CPU Table 2.5 Immediate Data Accessing Classification SH7000 Series CPU Conventional CPU 8-bit immediate MOV MOV.B #H'12,R0 16-bit immediate MOV.W @(disp,PC),R0 ......... .DATA.W H'1234 MOV.W #H'1234,R0 32-bit immediate MOV.L @(disp,PC),R0 ......... .DATA.L H'12345678 MOV.L R0 #H'12345678, #H'12,R0 Note: The address of the immediate data is accessed by @(disp, PC). Absolute Address: When data is accessed by absolute address, the value already in the absolute address is placed in the memory table. By loading the immediate data when the instruction is executed, that value is transferred to the register and the data is accessed in the indirect register addressing mode. Table 2.6 Absolute Address Accessing Classification SH7000 Series CPU Conventional CPU Absolute address MOV.L MOV. B ......... .DATA.L MOV.B @(disp,PC),R1 @R1,R0 @H'12345678,R0 H'12345678 Note: The address of the immediate data is accessed by @(disp, PC). 16/32-Bit Displacement: When data is accessed by 16-bit or 32-bit displacement, the pre-existing displacement value is placed in the memory table. By loading the immediate data when the instruction is executed, that value is transferred to the register and the data is accessed in the indirect indexed register addressing mode. Table 2.7 Accessing by Displacement Classification SH7000 Series CPU Conventional CPU 16-bit displacement MOV.W @(disp,PC),R0 MOV.W @(R0,R1),R2 ......... .DATA.W H'1234 MOV.W @(H'1234,R1),R2 Note: The address of the immediate data is accessed by @(disp, PC). Rev. 7.00 Jan 31, 2006 page 23 of 658 REJ09B0272-0700 Section 2 CPU 2.3.2 Addressing Modes Addressing modes and effective address calculation are described in table 2.8. Table 2.8 Addressing Modes and Effective Addresses Addressing Mnemonic Mode Expression Effective Addresses Calculation Equation -- Direct register addressing Rn The effective address is register Rn. (The operand is the contents of register Rn.) Indirect register addressing @Rn The effective address is the contents of register Rn. Rn Post-increment indirect register addressing @Rn + Rn Rn The effective address is the contents of register Rn. A constant is added to the contents of Rn after the instruction is executed. 1 is added for a byte operation, 2 for a word operation, and 4 for a longword operation. Rn Rn Rn + 1/2/4 @-Rn Rn 1/2/4 Rev. 7.00 Jan 31, 2006 page 24 of 658 REJ09B0272-0700 Byte: Rn + 1 Rn Longword: Rn + 4 Rn The effective address is the value obtained by subtracting a constant from Rn. 1 is subtracted for a byte operation, 2 for a word operation, and 4 for a longword operation. Rn - 1/2/4 (After the instruction is executed) Word: Rn + 2 Rn + 1/2/4 Pre-decrement indirect register addressing Rn - Rn - 1/2/4 Byte: Rn - 1 Rn Word: Rn - 2 Rn Longword: Rn - 4 Rn (Instruction executed with Rn after calculation) Section 2 CPU Addressing Mnemonic Mode Expression Indirect register addressing with displacement @(disp:4, Rn) Effective Addresses Calculation Equation The effective address is Rn plus a 4-bit displacement (disp). disp is zero-extended, and remains the same for a byte operation, is doubled for a word operation, and is quadrupled for a longword operation. Byte: Rn + disp Rn disp (zero-extended) Word: Rn + disp x 2 Longword: Rn + disp x 4 Rn + disp x 1/2/4 + x 1/2/4 Indirect indexed register addressing @(R0, Rn) Rn + R0 Rn + Rn + R0 R0 Indirect GBR addressing with displacement @(disp:8, GBR) The effective address is the GBR value plus an 8bit displacement (disp). The value of disp is zeroextended, and remains the same for a byte operation, is doubled for a word operation, and is quadrupled for a longword operation. GBR disp (zero-extended) + GBR + disp x 1/2/4 Byte: GBR + disp Word: GBR + disp x 2 Longword: GBR + disp x 4 x 1/2/4 Indirect indexed GBR addressing @(R0, GBR) The effective address is the GBR value plus the R0 value. GBR + R0 GBR + GBR + R0 R0 Rev. 7.00 Jan 31, 2006 page 25 of 658 REJ09B0272-0700 Section 2 CPU Addressing Mnemonic Mode Expression PC relative addressing with displacement @(disp:8, PC) Effective Addresses Calculation Equation The effective address is the PC value plus an 8-bit displacement (disp). disp is zero-extended, is doubled for a word operation, and is quadrupled for a longword operation. For a longword operation, the lowest two bits of the PC are masked. Word: PC + disp x 2 PC Longword: PC & H'FFFFFFFC + disp x 4 &* H'FFFFFFFC + disp (zero-extended) PC + disp x 2 or PC & H'FFFFFFFC + disp x 4 x 2/4 *: For longword PC relative addressing disp:8 The effective address is the PC value signextended with an 8-bit displacement (disp), doubled, and added to the PC. PC + disp x 2 PC disp (zero-extended) + PC + disp x 2 x 2 disp:12 The effective address is the PC value signextended with a 12-bit displacement (disp), doubled, and added to the PC. PC disp (zero-extended) + x 2 Rev. 7.00 Jan 31, 2006 page 26 of 658 REJ09B0272-0700 PC + disp x 2 PC + disp x 2 Section 2 CPU Addressing Mnemonic Mode Expression PC relative addressing Rn Effective Addresses Calculation Equation The effective address is the PC value plus Rn. PC + Rn PC + PC + Rn Rn Immediate addressing 2.3.3 #imm:8 The 8-bit immediate data (imm) for the TST, AND, OR, and XOR instructions is zero-extended. -- #imm:8 The 8-bit immediate data (imm) for the MOV, ADD, and CMP/EQ instructions is sign-extended. -- #imm:8 Immediate data (imm) for the TRAPA instruction is zero-extended and is quadrupled. -- Instruction Formats The instruction format refers to the source operand and the destination operand. The meaning of the operand depends on the instruction code. Symbols are as follows. xxxx Instruction code mmmm Source register nnnn Destination register iiii Immediate data dddd Displacement Rev. 7.00 Jan 31, 2006 page 27 of 658 REJ09B0272-0700 Section 2 CPU Table 2.9 Instruction Formats Instruction Format 0 format 15 Source Operand Destination Operand Example -- -- NOP -- nnnn: Register direct MOVT Rn Control register or system register nnnn: Register direct STS MACH,Rn Control register or system register nnnn: Register indirect with pre-decrement STC.L mmmm: Register direct Control register or LDC system register Rm,SR mmmm: Register indirect with post-increment Control register or LDC.L system register @Rm+,SR mmmm: Register indirect -- JMP @Rm mmmm: PC relative using Rm -- BRAF Rm 0 xxxx xxxx xxxx xxxx n format 15 0 xxxx nnnn xxxx xxxx m format 15 0 xxxx mmmm xxxx SR,@-Rn xxxx Rev. 7.00 Jan 31, 2006 page 28 of 658 REJ09B0272-0700 Section 2 CPU Instruction Format Source Operand Destination Operand nm format mmmm: Register direct nnnn: Register direct ADD Rm,Rn mmmm: Register direct nnnn: Register indirect MOV.L Rm,@Rn 15 0 xxxx nnnn mmmm xxxx mmmm: Register MACH, MACL indirect with postincrement (multiplyand-accumulate) Example MAC.W @Rm+,@Rn+ nnnn: Register indirect with postincrement (multiplyand-accumulate)* md format 15 0 xxxx xxxx mmmm dddd nd4 format 15 0 xxxx xxxx nnnn dddd nmd format 15 0 xxxx mmmm: Register indirect with post-increment nnnn: Register direct MOV.L @Rm+,Rn mmmm: Register direct nnnn: Register indirect with pre-decrement MOV.L Rm,@-Rn mmmm: Register direct nnnn: Indexed register indirect MOV.L Rm,@(R0,Rn) mmmmdddd: Register indirect with displacement R0 (Register direct) MOV.B @(disp,Rn),R0 R0 (Register direct) nnnndddd: Register indirect with displacement MOV.B R0,@(disp,Rn) mmmm: Register direct nnnndddd: Register indirect with displacement MOV.L Rm,@(disp,Rn) mmmmdddd: Register indirect with displacement nnnn: Register direct MOV.L @(disp,Rm),Rn nnnn mmmm dddd Rev. 7.00 Jan 31, 2006 page 29 of 658 REJ09B0272-0700 Section 2 CPU Instruction Format Source Operand d format 15 0 xxxx xxxx dddd dddd d12 format 15 0 xxxx dddd dddd 15 0 nnnn dddd dddd i format 15 0 xxxx xxxx iiii iiii ni format 15 0 xxxx nnnn iiii Example R0 (Register direct) MOV.L @(disp,GBR),R0 R0 (Register direct) dddddddd: GBR indirect with displacement MOV.L R0,@(disp,GBR) dddddddd: PC relative with displacement R0 (Register direct) MOVA @(disp,PC),R0 dddddddd: PC relative -- BF label dddddddddddd: PC relative -- BRA label (label = disp + PC) dddd nd8 format xxxx dddddddd: GBR indirect with displacement Destination Operand dddddddd: PC relative with displacement nnnn: Register direct MOV.L @(disp,PC),Rn iiiiiiii: Immediate Indexed GBR indirect AND.B #imm,@(R0,GBR) iiiiiiii: Immediate R0 (Register direct) AND #imm,R0 iiiiiiii: Immediate -- TRAPA #imm iiiiiiii: Immediate nnnn: Register direct ADD #imm,Rn iiii Note: * In multiply-and-accumulate instructions, nnnn is the source register. Rev. 7.00 Jan 31, 2006 page 30 of 658 REJ09B0272-0700 Section 2 CPU 2.4 Instruction Set 2.4.1 Instruction Set by Classification Table 2.10 lists instructions by classification. Table 2.10 Classification of Instructions Classification Data transfer Arithmetic operations Logic operations Types Operation Code 5 MOV Data transfer, immediate data transfer, 39 supporting module data transfer, structure data transfer MOVA Effective address transfer MOVT T bit transfer SWAP Swap of upper and lower bytes XTRCT Extraction of the middle of registers connected ADD Binary addition ADDC Binary addition with carry ADDV Binary addition with overflow check CMP/cond Comparison DIV1 Division DIV0S Initialization of signed division DIV0U Initialization of unsigned division EXTS Sign extension 17 6 Number of Instructions Function 28 EXTU Zero extension MAC Multiplication and accumulation MULS Signed multiplication MULU Unsigned multiplication NEG Negation NEGC Negation with borrow SUB Binary subtraction SUBC Binary subtraction with carry SUBV Binary subtraction with underflow check AND Logical AND NOT Bit inversion 14 OR Logical OR TAS Memory test and bit set Rev. 7.00 Jan 31, 2006 page 31 of 658 REJ09B0272-0700 Section 2 CPU Classification Types Operation Code Function Number of Instructions 14 Logic oper- 6 ations (cont) TST Logical AND and T bit set XOR Exclusive OR Shift ROTL One-bit left rotation ROTR One-bit right rotation ROTCL One-bit left rotation with T bit ROTCR One-bit right rotation with T bit SHAL One-bit arithmetic left shift SHAR One-bit arithmetic right shift Branch System control Total 10 7 11 SHLL One-bit logical left shift SHLLn n-bit logical left shift SHLR One-bit logical right shift SHLRn n-bit logical right shift BF Conditional branch (T = 0) BT Conditional branch (T = 1) BRA Unconditional branch BSR Branch to subroutine procedure JMP Unconditional branch JSR Branch to subroutine procedure RTS Return from subroutine procedure CLRT T bit clear CLRMAC MAC register clear LDC Load to control register LDS Load to system register NOP No operation RTE Return from exception handling SETT T bit set SLEEP Shift into power-down mode STC Store control register data STS Store system register data TRAPA Trap exception handling 56 Rev. 7.00 Jan 31, 2006 page 32 of 658 REJ09B0272-0700 14 7 31 133 Section 2 CPU The following tables (arranged by instruction classification) show instruction codes, operations, and execution states, using the format shown below. Table 2.11 Instruction Code Format Item Format Instruction mnemonic OP.Sz Instruction code MSB LSB mmmm: Source register nnnn: Destination register 0000: R0 0001: R1 ........... 1111: R15 iiii: Immediate data dddd: Displacement Operation summary , (xx) M/Q/T & | ^ ~ <<n, >>n Direction of transfer Memory operand Flag bits in SR Logical AND of each bit Logical OR of each bit Exclusive OR of each bit Logical NOT of each bit n-bit shift Execution cycle Explanation SRC,DEST OP: Operation code Sz: Size SRC: Source DEST: Destination Rm: Source register Rn: Destination register imm: Immediate data disp: Displacement* Value when no wait states are inserted Instruction execution cycles: The execution cycles shown in the table are minimums. The actual number of cycles may be increased: 1. When contention occurs between instruction fetches and data access, or 2. When the destination register of the load instruction (memory register) and the register used by the next instruction are the same. T bit Value of T bit after instruction is executed -- No change Notes: * Scaling (x1, x2, x4) is performed based on the operand size of the instruction. Rev. 7.00 Jan 31, 2006 page 33 of 658 REJ09B0272-0700 Section 2 CPU Table 2.12 Data Transfer Instructions Execution Cycles T Bit Instruction Instruction Code Operation MOV #imm,Rn 1110nnnniiiiiiii #imm Sign extension Rn 1 -- MOV.W @(disp,PC),Rn 1001nnnndddddddd (disp x 2 + PC) Sign extension Rn 1 -- MOV.L @(disp,PC),Rn 1101nnnndddddddd (disp x 4 + PC) Rn 1 -- MOV Rm,Rn 0110nnnnmmmm0011 Rm Rn 1 -- MOV.B Rm,@Rn 0010nnnnmmmm0000 Rm (Rn) 1 -- MOV.W Rm,@Rn 0010nnnnmmmm0001 Rm (Rn) 1 -- MOV.L Rm,@Rn 0010nnnnmmmm0010 Rm (Rn) 1 -- MOV.B @Rm,Rn 0110nnnnmmmm0000 (Rm) Sign extension Rn 1 -- MOV.W @Rm,Rn 0110nnnnmmmm0001 (Rm) Sign extension Rn 1 -- MOV.L @Rm,Rn 0110nnnnmmmm0010 (Rm) Rn 1 -- MOV.B Rm,@-Rn 0010nnnnmmmm0100 Rn-1 Rn, Rm (Rn) 1 -- MOV.W Rm,@-Rn 0010nnnnmmmm0101 Rn-2 Rn, Rm (Rn) 1 -- MOV.L Rm,@-Rn 0010nnnnmmmm0110 Rn-4 Rn, Rm (Rn) 1 -- MOV.B @Rm+,Rn 0110nnnnmmmm0100 (Rm) Sign extension Rn, Rm + 1 Rm 1 -- MOV.W @Rm+,Rn 0110nnnnmmmm0101 (Rm) Sign extension Rn, Rm + 2 Rm 1 -- MOV.L @Rm+,Rn 0110nnnnmmmm0110 (Rm) Rn, Rm + 4 Rm 1 -- MOV.B R0,@(disp,Rn) 10000000nnnndddd R0 (disp + Rn) 1 -- MOV.W R0,@(disp,Rn) 10000001nnnndddd R0 (disp x 2 + Rn) 1 -- MOV.L Rm,@(disp,Rn) 0001nnnnmmmmdddd Rm (disp x 4 + Rn) 1 -- MOV.B @(disp,Rm),R0 10000100mmmmdddd (disp + Rm) Sign extension R0 1 -- Rev. 7.00 Jan 31, 2006 page 34 of 658 REJ09B0272-0700 Section 2 CPU Execution Cycles T Bit Instruction Instruction Code Operation MOV.W @(disp,Rm),R0 10000101mmmmdddd (disp x 2 + Rm) Sign extension R0 1 -- MOV.L @(disp,Rm),Rn 0101nnnnmmmmdddd (disp x 4 + Rm) Rn 1 -- MOV.B Rm,@(R0,Rn) 0000nnnnmmmm0100 Rm (R0 + Rn) 1 -- MOV.W Rm,@(R0,Rn) 0000nnnnmmmm0101 Rm (R0 + Rn) 1 -- MOV.L Rm,@(R0,Rn) 0000nnnnmmmm0110 Rm (R0 + Rn) 1 -- MOV.B @(R0,Rm),Rn 0000nnnnmmmm1100 (R0 + Rm) Sign extension Rn 1 -- MOV.W @(R0,Rm),Rn 0000nnnnmmmm1101 (R0 + Rm) Sign extension Rn 1 -- MOV.L @(R0,Rm),Rn 0000nnnnmmmm1110 (R0 + Rm) Rn 1 -- MOV.B R0,@(disp,GBR) 11000000dddddddd R0 (disp + GBR) 1 -- MOV.W R0,@(disp,GBR) 11000001dddddddd R0 (disp x 2 + GBR) 1 -- MOV.L R0,@(disp,GBR) 11000010dddddddd R0 (disp x 4 + GBR) 1 -- MOV.B @(disp,GBR),R0 11000100dddddddd (disp + GBR) Sign extension R0 1 -- MOV.W @(disp,GBR),R0 11000101dddddddd (disp x 2 + GBR) Sign extension R0 1 -- MOV.L @(disp,GBR),R0 11000110dddddddd (disp x 4 + GBR) R0 1 -- MOVA @(disp,PC),R0 11000111dddddddd disp x 4 + PC R0 1 -- MOVT Rn 0000nnnn00101001 T Rn 1 -- SWAP.B Rm,Rn 0110nnnnmmmm1000 Rm Swap the bottom two bytes Rn 1 -- SWAP.W Rm,Rn 0110nnnnmmmm1001 Rm Swap two consecutive words Rn 1 -- XTRCT 0010nnnnmmmm1101 Rm: Center 32 bits of Rn Rn 1 -- Rm,Rn Rev. 7.00 Jan 31, 2006 page 35 of 658 REJ09B0272-0700 Section 2 CPU Table 2.13 Arithmetic Instructions Instruction Instruction Code Operation Execution Cycles T Bit ADD Rm,Rn 0011nnnnmmmm1100 Rn + Rm Rn 1 -- ADD #imm,Rn 0111nnnniiiiiiii Rn + imm Rn 1 -- ADDC Rm,Rn 0011nnnnmmmm1110 Rn + Rm + T Rn, Carry T 1 Carry ADDV Rm,Rn 0011nnnnmmmm1111 Rn + Rm Rn, Overflow T 1 Overflow CMP/EQ #imm,R0 10001000iiiiiiii If R0 = imm, 1 T 1 Comparison result CMP/EQ Rm,Rn 0011nnnnmmmm0000 If Rn = Rm, 1 T 1 Comparison result CMP/HS Rm,Rn 0011nnnnmmmm0010 If Rn Rm with unsigned data, 1 T 1 Comparison result CMP/GE Rm,Rn 0011nnnnmmmm0011 If Rn Rm with signed data, 1 T 1 Comparison result CMP/HI Rm,Rn 0011nnnnmmmm0110 If Rn > Rm with unsigned data, 1 T 1 Comparison result CMP/GT Rm,Rn 0011nnnnmmmm0111 If Rn > Rm with signed data, 1 T 1 Comparison result CMP/PZ Rn 0100nnnn00010001 If Rn 0, 1 T 1 Comparison result CMP/PL Rn 0100nnnn00010101 If Rn > 0, 1 T 1 Comparison result CMP/STR Rm,Rn 0010nnnnmmmm1100 If Rn and Rm have an equivalent byte, 1 T 1 Comparison result DIV1 Rm,Rn 0011nnnnmmmm0100 Single-step division (Rn/Rm) 1 Calculation result DIV0S Rm,Rn 0010nnnnmmmm0111 MSB of Rn Q, MSB of Rm M, M ^ Q T 1 Calculation result DIV0U 0000000000011001 0 M/Q/T 1 0 EXTS.B Rm,Rn 0110nnnnmmmm1110 A byte in Rm is signextended Rn 1 -- Rev. 7.00 Jan 31, 2006 page 36 of 658 REJ09B0272-0700 Section 2 CPU Execution Cycles T Bit A word in Rm is signextended Rn 1 -- 0110nnnnmmmm1100 A byte in Rm is zeroextended Rn 1 -- EXTU.W Rm,Rn 0110nnnnmmmm1101 A word in Rm is zeroextended Rn 1 -- MAC.W @Rm+,@Rn+ 0100nnnnmmmm1111 Signed operation of (Rn) x (Rm) + MAC MAC 16 x 16 + 42 42-bit 3/(2)* -- MULS Rm,Rn 0010nnnnmmmm1111 Signed operation of Rn x Rm MAC 16 x 16 32-bit 1-3* -- MULU Rm,Rn 0010nnnnmmmm1110 Unsigned operation of Rn x Rm MAC 16 x 16 32-bit 1-3* -- NEG Rm,Rn 0110nnnnmmmm1011 0-Rm Rn 1 -- NEGC Rm,Rn 0110nnnnmmmm1010 0-Rm-T Rn, Borrow T 1 Borrow SUB Rm,Rn 0011nnnnmmmm1000 Rn-Rm Rn 1 -- SUBC Rm,Rn 0011nnnnmmmm1010 Rn-Rm-T Rn, Borrow T 1 Borrow SUBV Rm,Rn 0011nnnnmmmm1011 Rn-Rm Rn, Underflow T 1 Underflow Instruction Instruction Code Operation EXTS.W Rm,Rn 0110nnnnmmmm1111 EXTU.B Rm,Rn Note: * The normal minimum number of cycles (numbers in parenthesis represent the number of cycles when there is contention with preceding or following instructions). Rev. 7.00 Jan 31, 2006 page 37 of 658 REJ09B0272-0700 Section 2 CPU Table 2.14 Logic Operation Instructions Execution Cycles T Bit 0010nnnnmmmm1001 Rn & Rm Rn 1 -- 11001001iiiiiiii R0 & imm R0 1 -- AND.B #imm,@(R0,GBR) 11001101iiiiiiii (R0 + GBR) & imm (R0 + GBR) 3 -- NOT Rm,Rn 0110nnnnmmmm0111 ~Rm Rn 1 -- OR Rm,Rn 0010nnnnmmmm1011 Rn | Rm Rn 1 -- OR #imm,R0 11001011iiiiiiii R0 | imm R0 1 -- OR.B #imm,@(R0,GBR) 11001111iiiiiiii (R0 + GBR) | imm 3 (R0 + GBR) -- TAS.B @Rn 0100nnnn00011011 If (Rn) is 0, 1 T; 1 MSB of (Rn) 4 Test result TST Rm,Rn 0010nnnnmmmm1000 Rn & Rm; if the result is 0, 1 T 1 Test result TST #imm,R0 11001000iiiiiiii R0 & imm; if the result is 0, 1 T 1 Test result TST.B #imm,@(R0,GBR) 11001100iiiiiiii (R0 + GBR) & imm; 3 if the result is 0, 1 T Test result XOR Rm,Rn 0010nnnnmmmm1010 Rn ^ Rm Rn 1 -- XOR #imm,R0 11001010iiiiiiii R0 ^ imm R0 1 -- 11001110iiiiiiii (R0 + GBR) ^ imm (R0 + GBR) 3 -- Instruction Instruction Code AND Rm,Rn AND #imm,R0 XOR.B #imm,@(R0,GBR) Rev. 7.00 Jan 31, 2006 page 38 of 658 REJ09B0272-0700 Operation Section 2 CPU Table 2.15 Shift Instructions Instruction Instruction Code Operation Execution Cycles T Bit ROTL Rn 0100nnnn00000100 T Rn MSB 1 MSB ROTR Rn 0100nnnn00000101 LSB Rn T 1 LSB ROTCL Rn 0100nnnn00100100 T Rn T 1 MSB ROTCR Rn 0100nnnn00100101 T Rn T 1 LSB SHAL Rn 0100nnnn00100000 T Rn 0 1 MSB SHAR Rn 0100nnnn00100001 MSB Rn T 1 LSB SHLL Rn 0100nnnn00000000 T Rn 0 1 MSB SHLR Rn 0100nnnn00000001 0 Rn T 1 LSB SHLL2 Rn 0100nnnn00001000 Rn<<2 Rn 1 -- SHLR2 Rn 0100nnnn00001001 Rn>>2 Rn 1 -- SHLL8 Rn 0100nnnn00011000 Rn<<8 Rn 1 -- SHLR8 Rn 0100nnnn00011001 Rn>>8 Rn 1 -- SHLL16 Rn 0100nnnn00101000 Rn<<16 Rn 1 -- SHLR16 Rn 0100nnnn00101001 Rn>>16 Rn 1 -- Table 2.16 Branch Instructions Execution Cycles T Bit If T = 0, disp x 2 + PC PC; if T = 1, nop 3/1* -- 10001001dddddddd If T = 1, disp x 2 + PC PC; if T = 0, nop 3/1* -- BRA label 1010dddddddddddd Delayed branch, disp x 2 + PC PC 2 -- BSR label 1011dddddddddddd Delayed branch, PC PR, disp x 2 + PC PC 2 -- JMP @Rm 0100mmmm00101011 Delayed branch, Rm PC 2 -- JSR @Rm 0100mmmm00001011 Delayed branch, PC PR, Rm PC 2 -- RTS 0000000000001011 Delayed branch, PR PC 2 -- Instruction Instruction Code Operation BF label 10001011dddddddd BT label Note: * The execution state is three cycles when program branches, and one cycle when program does not branch. Rev. 7.00 Jan 31, 2006 page 39 of 658 REJ09B0272-0700 Section 2 CPU Table 2.17 System Control Instructions Instruction Instruction Code Operation Execution Cycles T Bit CLRT 0000000000001000 0T 1 0 CLRMAC 0000000000101000 0 MACH, MACL 1 -- LDC Rm,SR 0100mmmm00001110 Rm SR 1 LSB LDC Rm,GBR 0100mmmm00011110 Rm GBR 1 -- LDC Rm,VBR 0100mmmm00101110 Rm VBR 1 -- LDC.L @Rm+,SR 0100mmmm00000111 (Rm) SR, Rm + 4 Rm 3 LSB LDC.L @Rm+,GBR 0100mmmm00010111 (Rm) GBR, Rm + 4 Rm 3 -- LDC.L @Rm+,VBR 0100mmmm00100111 (Rm) VBR, Rm + 4 Rm 3 -- LDS Rm,MACH 0100mmmm00001010 Rm MACH 1 -- LDS Rm,MACL 0100mmmm00011010 Rm MACL 1 -- LDS Rm,PR 0100mmmm00101010 Rm PR 1 -- LDS.L @Rm+,MACH 0100mmmm00000110 (Rm) MACH, Rm + 4 Rm 1 -- LDS.L @Rm+,MACL 0100mmmm00010110 (Rm) MACL, Rm + 4 Rm 1 -- LDS.L @Rm+,PR 0100mmmm00100110 (Rm) PR, Rm + 4 Rm 1 -- NOP 0000000000001001 No operation 1 -- RTE 0000000000101011 Delayed branch, stack area PC/SR 4 -- SETT 0000000000011000 1T 1 1 SLEEP 0000000000011011 Sleep 3* -- 1 -- STC SR,Rn 0000nnnn00000010 SR Rn STC GBR,Rn 0000nnnn00010010 GBR Rn 1 -- STC VBR,Rn 0000nnnn00100010 VBR Rn 1 -- STC.L SR,@-Rn 0100nnnn00000011 Rn-4 Rn, SR (Rn) 2 -- STC.L GBR,@-Rn 0100nnnn00010011 Rn-4 Rn, GBR (Rn) 2 -- STC.L VBR,@-Rn 0100nnnn00100011 Rn-4 Rn, VBR (Rn) 2 -- STS 0000nnnn00001010 MACH Rn 1 -- MACH,Rn Note: * The number of execution states before the chip enters the sleep state. Rev. 7.00 Jan 31, 2006 page 40 of 658 REJ09B0272-0700 Section 2 CPU Instruction Instruction Code Operation Execution Cycles T Bit STS MACL,Rn 0000nnnn00011010 MACL Rn 1 -- STS PR,Rn 0000nnnn00101010 PR Rn 1 -- STS.L MACH,@-Rn 0100nnnn00000010 Rn-4 Rn, MACH (Rn) 1 -- STS.L MACL,@-Rn 0100nnnn00010010 Rn-4 Rn, MACL (Rn) 1 -- STS.L PR,@-Rn 0100nnnn00100010 Rn-4 Rn, PR (Rn) 1 -- TRAPA #imm 11000011iiiiiiii PC/SR stack area, (imm x 4 + VRR) PC 8 -- Notes: The execution cycles shown in the table are minimums. The actual number of cycles may be increased: 1. When contention occurs between instruction fetches and data access 2. When the destination register of the load instruction (memory register) and the register used by the next instruction are the same. Rev. 7.00 Jan 31, 2006 page 41 of 658 REJ09B0272-0700 Section 2 CPU 2.4.2 Operation Code Map Table 2.18 shows an operation code map. Table 2.18 Operation Code Map Instruction Code MSB Fx: 0000 LSB MD: 00 Fx: 0001 Fx: 0010 Fx: 0011-1111 MD: 01 MD: 10 MD: 11 0000 Rn Fx 0000 0000 Rn Fx 0001 0000 Rn Fx 0010 0000 Rn Fx 0011 0000 Rn Rm 01MD MOV.B Rm, @(R0,Rn) MOV.W Rm, @(R0,Rn) MOV.L Rm, @(R0,Rn) 0000 0000 Fx 1000 CLRT SETT CLRMAC 0000 0000 Fx 1001 NOP DIV0U 0000 0000 Fx 1010 RTS SLEEP 0000 0000 Fx 1011 0000 Rn Fx 1000 0000 Rn Fx 1001 0000 Rn Fx 1010 STC SR,Rn STC GBR,Rn STC VBR,Rn RTE MOVT Rn STS MACH,Rn STS MACL,Rn STS PR,Rn 0000 Rn Rm 1011 0000 Rn Rm 11MD MOV.B @(R0,Rm),Rn 0001 Rn Rm disp 0010 Rn Rm 00MD MOV.B Rm,@Rn MOV.W Rm,@Rn MOV.L Rm,@Rn 0010 Rn Rm 01MD MOV.B Rm,@-Rn MOV.W Rm,@-Rn MOV.L Rm,@-Rn DIV0S Rm,Rn 0010 Rn Rm 10MD TST AND XOR Rm,Rn OR Rm,Rn 0010 Rn Rm 11MD CMP/STR Rm,Rn MULU Rm,Rn MULS Rm,Rn 0011 Rn Rm 00MD CMP/EQ Rm,Rn CMP/HS Rm,Rn CMP/GE Rm,Rn 0011 Rn Rm 01MD DIV1 Rm,Rn CMP/HI Rm,Rn CMP/GT Rm,Rn 0011 Rn Rm 10MD SUB Rm,Rn SUBC Rm,Rn SUBV Rm,Rn 0011 Rn Rm 11MD ADD Rm,Rn ADDC Rm,Rn ADDV Rm,Rn 0100 Rn Fx 0000 SHLL Rn 0100 Rn Fx 0001 SHLR Rn 0100 Rn Fx 0010 STS.L @-Rn MOV.W @(R0,Rm),Rn MOV.L @(R0,Rm),Rn MOV.L Rm,@(disp:4,Rn) Rm,Rn Rm,Rn XTRCT Rm,Rn MACH, Rev. 7.00 Jan 31, 2006 page 42 of 658 REJ09B0272-0700 SHAL Rn CMP/PZ Rn SHAR Rn STS.L MACL, @-Rn STS.L PR, @-Rn Section 2 CPU Instruction Code MSB Fx: 0000 Fx: 0001 Fx: 0010 Fx: 0011-1111 MD: 11 LSB MD: 00 MD: 01 MD: 10 0100 Rn Fx 0011 STC.L SR,@-Rn STC.L GBR,@-Rn STC.L VBR,@-Rn 0100 Rn Fx 0100 ROTL Rn 0100 Rn Fx 0101 ROTR Rn CMP/PL Rn ROTCR Rn 0100 Rm Fx 0110 LDS.L @Rm+,MACH LDS.L @Rm+,MACL LDS.L @Rm+,PR 0100 Rm Fx 0111 LDC.L @Rm+,SR LDC.L @Rm+,GBR LDC.L @Rm+,VBR 0100 Rn Fx 1000 SHLL2 Rn SHLL8 Rn SHLL16 Rn 0100 Rn Fx 1001 SHLR2 Rn SHLR8 Rn SHLL16 Rn 0100 Rm Fx 1010 LDS Rm,MACH LDS LDS Rm,PR 0100 Rm/Rn Fx 1011 JSR @Rm TAS.B @Rn JMP @Rm 0100 Rm Fx 1100 0100 Rm Fx 1101 0100 Rn Fx 1110 LDC Rm,SR LDC LDC Rm,VBR ROTCL Rn Rm,MACL Rm,GBR 0100 Rn Rm 1111 MAC.W @Rm+,@Rn+ 0101 Rn Rm disp MOV.L @(disp:4,Rm),Rn 0110 Rn Rm 00MD MOV.B @Rm,Rn MOV.W @Rm,Rn MOV.L @Rm,Rn MOV Rm,Rn 0110 Rn Rm 01MD MOV.B @Rm+,Rn MOV.W @Rm+,Rn MOV.L @Rm+,Rn NOT Rm,Rn 0110 Rn Rm 10MD SWAP.B Rm,Rn SWAP.W Rm,Rn NEGC NEG Rm,Rn 0110 Rn Rm EXTU.W Rm,Rn EXTS.B Rm,Rn 0111 Rn 11MD EXTU.B Rm,Rn imm ADD Rn disp MOV.B R0, @(disp:4,Rn) MOV.W R0, @(disp:4,Rn) 1000 01MD Rm disp MOV.B @(disp:4, Rm),R0 MOV.W @(disp:4, Rm),R0 1000 10MD imm/disp CMP/EQ #imm:8,R0 BT 1000 11MD imm/disp disp EXTS.W Rm,Rn #imm:8,Rn 1000 00MD 1001 Rn Rm,Rn disp:8 BF disp:8 MOV.W @(disp:8,PC),Rn 1010 disp BRA disp:12 1011 disp BSR disp:12 Rev. 7.00 Jan 31, 2006 page 43 of 658 REJ09B0272-0700 Section 2 CPU Instruction Code Fx: 0000 Fx: 0001 Fx: 0010 Fx: 0011-1111 MSB MD: 00 MD: 01 MD: 10 MD: 11 LSB 1100 00M D imm/disp 1100 01M D disp MOV.B @(disp:8, GBR),R0 MOV.W @(disp:8, GBR),R0 MOV.L @(disp:8, GBR),R0 MOVA @(disp:8, PC),R0 1100 10M D imm TST #imm:8,R0 AND #imm:8,R0 XOR #imm:8,R0 OR #imm:8,R0 1100 11M D imm TST.B #imm:8, @(R0,GBR) AND.B #imm:8, @(R0,GBR) XOR.B #imm:8, @(R0,GBR) OR.B #imm:8, @(R0,GBR) 1101 Rn disp MOV.L @(disp:8,PC),Rn 1110 Rn imm MOV 1111 MOV.B R0,@ MOV.W R0,@ MOV.L R0,@ TRAPA #imm:8 (disp:8,GBR) (disp:8,GBR) (disp:8,GBR) #imm:8,Rn ... Rev. 7.00 Jan 31, 2006 page 44 of 658 REJ09B0272-0700 Section 2 CPU 2.5 CPU State 2.5.1 State Transitions The CPU has five processing states: reset, exception handling, bus-released, program execution and power-down. The transitions between the states are shown in figure 2.6. For more information on the reset and exception handling states, see section 4, Exception Handling. For details on the power-down state, see section 19, Power-Down State. Rev. 7.00 Jan 31, 2006 page 45 of 658 REJ09B0272-0700 Section 2 CPU From any state when RES = 0 and NMI = 1 From any state when RES = 0 and NMI = 0 RES = 0, NMI = 0 Power-on reset state Manual reset state RES = 0, NMI = 1 When an interrupt source or DMA address error occurs RES = 1, NMI = 0 RES = 1, NMI = 1 Reset states Exception handling state Bus request cleared NMI interrupt source occurs Bus request generated Bus-release-state Bus request generated Bus request generated Exception handling source occurs Exception handling ends Bus request cleared Program execution state Bus request cleared Sleep mode SLEEP instruction with SBY bit cleared SLEEP instruction with SBY bit set Standby mode Power-down state Figure 2.6 Transitions Between Processing States Rev. 7.00 Jan 31, 2006 page 46 of 658 REJ09B0272-0700 Section 2 CPU Reset State: In the reset state the CPU is reset. This occurs when the RES pin level goes low. When the NMI pin is high, the result is a power-on reset; when it is low, a manual reset will occur. When turning on the power, be sure to carry out a power-on reset. In a power-on reset, all CPU internal states and on-chip supporting module registers are initialized. In a manual reset, all CPU internal states and on-chip supporting module registers, with the exception of the bus state controller (BSC) and pin function controller (PFC), are initialized. In a manual reset, the BSC is not initialized, so refresh operations will continue. Exception Handling State: Exception handling is a transient state that occurs when the CPU's processing state flow is altered by exception handling sources such as resets or interrupts. In a reset, the initial values of the program counter PC (execution start address) and stack pointer SP are fetched from the exception vector table and stored; the CPU then branches to the execution start address and execution of the program begins. For an interrupt, the stack pointer (SP) is accessed and the program counter (PC) and status register (SR) are saved to the stack area. The exception handling routine start address is fetched from the exception vector table; the CPU then branches to that address and the program starts executing, thereby entering the program execution state. Program Execution State: In the program execution state, the CPU sequentially executes the program. Power-Down State: In the power-down state, CPU operation halts and power consumption decreases. The SLEEP instruction places the CPU in the power-down state. This state has two modes: sleep mode and standby mode. Bus-Released State: In the bus-released state, the CPU releases the bus to the device that has requested it. Rev. 7.00 Jan 31, 2006 page 47 of 658 REJ09B0272-0700 Section 2 CPU 2.5.2 Power-Down State In addition to the ordinary program execution states, the CPU also has a power-down state in which CPU operation halts and power consumption is reduced There are two power-down state modes: sleep mode and standby mode. Sleep Mode: When the standby bit SBY (in the standby control register, SBYCR) is cleared to 0 and a SLEEP instruction is executed, the CPU switches from program execution state to sleep mode. In sleep mode, the CPU halts and the contents of its internal registers and the data in onchip RAM are stored. The on-chip supporting modules other than the CPU do not halt in sleep mode. Sleep mode is cleared by a reset, any interrupt, or a DMA address error; the CPU returns to ordinary program execution state through the exception handling state. Software Standby Mode: To enter standby mode, set standby bit SBY (in the standby control register, SBYCR) to 1 and execute a SLEEP instruction. In standby mode, all CPU, on-chip supporting module and oscillator functions are halted. CPU internal register contents and on-chip RAM data are held. Standby mode is cleared by a reset or an external NMI interrupt. For resets, the CPU returns to the ordinary program execution state through the exception handling state when placed in a reset state during the oscillator settling time. For NMI interrupts, the CPU returns to the ordinary program execution state through the exception handling state after the oscillator settling time has elapsed. In this mode, power consumption drops markedly, since the oscillator stops. Table 2.19 Power-Down State State Mode Conditions Clock CPU Sleep mode Execute SLEEP Run instruction with SBY bit cleared to 0 in SBYCR On-Chip CPU Supporting RegiModules sters RAM Halted Run Held Held Standby Execute SLEEP Halted Halted Halted and Held mode instruction with initialized* SBY bit set to 1 in SBYCR Held Note: * Differs depending on the supporting module and pin. Rev. 7.00 Jan 31, 2006 page 48 of 658 REJ09B0272-0700 I/O Ports Held Canceling 1. Interrupt 2. DMA address error 3. Power-on reset 4. Manual reset Held or 1. NMI high-Z* 2. Power-on (selectreset able) 3. Manual reset Section 3 Operating Modes Section 3 Operating Modes 3.1 Types of Operating Modes and Their Selection The SH7032 microcomputer operates in one of two operating modes (modes 0 and 1) and the SH7034 operates in one of four operating modes (modes 0, 1, 2, and 7). Modes 0 and 1 differ in the bus width of memory area 0. The mode is selected by the mode pins (MD2-MD0) as indicated in table 3.1. Do not change the mode selection while the chip is operating. Table 3.1 Operating Mode Selection Pin Settings Operating Mode MD2 MD1 MD0 Mode Name Bus Width of Area 0 2 Mode 0* 0 0 0 MCU mode 0 8 bits 2 Mode 1* 0 0 1 MCU mode 1 16 bits Mode 2 0 1 0 MCU mode 2 On-chip ROM 1 1 1 PROM mode -- 1 Mode 7* Notes: 1. SH7034 PROM version only 2. Only modes 0 and 1 are available in the SH7032 and SH7034 ROMless version. 3.2 Operating Mode Descriptions 3.2.1 Mode 0 (MCU Mode 0) In mode 0, memory area 0 has an eight-bit bus width. For the memory map, see section 8, Bus State Controller (BSC). 3.2.2 Mode 1 (MCU Mode 1) In mode 1, memory area 0 has a 16-bit bus width. 3.2.3 Mode 2 (MCU Mode 2) In mode 2, memory area 0 is assigned to the on-chip ROM. Mode 2 should only be set for the product is the SH7034. Rev. 7.00 Jan 31, 2006 page 49 of 658 REJ09B0272-0700 Section 3 Operating Modes 3.2.4 Mode 7 (PROM Mode) Mode 7 is a PROM mode. In this mode, the PROM can be programmed. For details, see section 17, ROM. Mode 7 should only be set for the SH7034 (PROM version). Rev. 7.00 Jan 31, 2006 page 50 of 658 REJ09B0272-0700 Section 4 Exception Handling Section 4 Exception Handling 4.1 Overview 4.1.1 Exception Handling Types and Priorities As figure 4.1 indicates, exception handling may be caused by a reset, address error, interrupt, or instruction. Exception sources are prioritized as indicated in figure 4.1. If two or more exceptions occur simultaneously, they are accepted and handled in the priority order shown. Rev. 7.00 Jan 31, 2006 page 51 of 658 REJ09B0272-0700 Section 4 Exception Handling Priority Reset * Power-on reset * Manual reset Address error * CPU address error * DMA address error * NMI * User break * IRQ Interrupt Exception source * On-chip module Instruction High * IRQ0-IRQ7 * Direct memory access controller * 16-bit integrated timer pulse unit * Serial communication interface * Parity control unit (part of the bus controller) * A/D converter * Watchdog timer * DRAM refresh control unit (part of the bus controller) * Trap instruction * TRAPA instruction * General illegal instruction * Illegal slot instruction * Undefined code * Undefined instruction or instruction that rewrites the PC*1 Low placed directly after a delayed branch instruction*2 Notes: 1. The instructions that rewrite the PC are JMP, JSR, BRA, BSR, RTS, RTE, BT, BF, and TRAPA. 2. The delayed branch instructions are JMP, JSR. BRA. BSR, RTS, and RTE. Figure 4.1 Exception Source Types and Priority Rev. 7.00 Jan 31, 2006 page 52 of 658 REJ09BX0272-0700 Section 4 Exception Handling 4.1.2 Exception Handling Operation Exception sources are detected at the times indicated in table 4.1, whereupon handling starts. Table 4.1 Exception Source Detection and Start of Handling Exception Type Source Detection and Start of Handling Reset Power-on Low-to-high transition at RES pin when NMI is high Manual Low-to-high transition at RES pin when NMI is low Address error Detected when instruction is decoded and starts after the instruction that was executing prior to this point is completed. Interrupt Detected when instruction is decoded and starts after the instruction that was executing prior to this point is completed. Instruction Trap instruction Starts when a trap instruction (TRAPA) is executed. General illegal instruction Starts when undefined code is decoded at a position other than directly after a delayed branch instruction (a delay slot). Illegal slot instruction Starts when undefined code or an instruction that rewrites the PC is decoded directly after a delayed branch instruction (in a delay slot). When exception handling begins, the CPU operates as follows: Resets: The initial values of the program counter (PC) and stack pointer (SP) are read from the exception vector table (the respective PC and SP values are H'00000000 and H'00000004 for a power-on reset and H'00000008 and H'0000000C for a manual reset). For more information on the exception vector table, see section 4.1.3, Exception Vector Table. Next, the vector base register (VBR) is cleared to zero and interrupt mask bits (I3-I0) in the status register (SR) are set to 1111. Program execution starts from the PC address read from the exception vector table. Address Errors, Interrupts and Instructions: SR and PC are pushed onto the stack indicated in R15. For interrupts, the interrupt priority level is written in the interrupt mask bits (I3-I0). For address errors and instructions, bits I3-I0 are not affected. Next, the start address is fetched from the exception vector table, and program execution starts from this address. Rev. 7.00 Jan 31, 2006 page 53 of 658 REJ09B0272-0700 Section 4 Exception Handling 4.1.3 Exception Vector Table Before exception handling can execute, the exception vector table must be set in memory. The exception vector table holds the start addresses of exception handling routines (the table for reset exception handling stores initial PC and SP values). Different vector numbers and vector table address offsets are assigned to different exception sources. The vector table addresses are calculated from the corresponding vector numbers and vector address offsets. In exception handling, the exception handling routine start address is fetched from the exception vector table indicated by this vector table address. Table 4.2 lists vector numbers and vector table address offsets. Table 4.3 shows how vector table addresses are calculated. Rev. 7.00 Jan 31, 2006 page 54 of 658 REJ09BX0272-0700 Section 4 Exception Handling Table 4.2 Exception Vector Table Vector Number Vector table Address Offset PC 0 H'00000000-H'00000003 SP 1 H'00000004-H'00000007 PC 2 H'00000008-H'0000000B SP 3 H'0000000C-H'0000000F General illegal instruction 4 H'00000010-H'00000013 (Reserved for system use) 5 H'00000014-H'00000017 Illegal slot instruction 6 H'00000018-H'0000001B (Reserved for system use) 7 H'0000001C-H'0000001F 8 H'00000020-H'00000023 CPU address error 9 H'00000024-H'00000027 DMA address error 10 H'00000028-H'0000002B NMI 11 H'0000002C-H'0000002F User break 12 H'00000030-H'00000033 (Reserved for system use) 13-31 H'00000034-H'00000037 to H'0000007C-H'0000007F Trap instruction (user vectors) 32-63 H'00000080-H'00000083 to H'000000FC-H'000000FF Exception Source Power-on reset Manual reset Interrupts Interrupts IRQ0 64 H'00000100-H'00000103 IRQ1 65 H'00000104-H'00000107 IRQ2 66 H'00000108-H'0000010B IRQ3 67 H'0000010C-H'0000010F IRQ4 68 H'00000110-H'00000113 IRQ5 69 H'00000114-H'00000117 IRQ6 70 H'00000118-H'0000011B IRQ7 71 H'0000011C-H'0000011F On-chip modules* 72-255 H'00000120-H'00000123 to H'000003FC-H'000003FF Note: * See table 5.3, Interrupt Exception Vectors and Rankings, in section 5, Interrupt Controller (INTC), for details on vector numbers and vector table address offsets of individual on-chip supporting module interrupts. Rev. 7.00 Jan 31, 2006 page 55 of 658 REJ09B0272-0700 Section 4 Exception Handling Table 4.3 Calculation of Exception Vector Table Addresses Exception Source Calculation of Vector Table Address Reset (Vector table address) = (vector table address offset) = (vector number) x 4 Address error, interrupt, instructions (Vector table address) = VBR + (vector table address offset) = VBR + (vector number) x 4 Note: VBR: Vector base register. For vector table address offsets and vector numbers, see table 4.2. 4.2 Resets 4.2.1 Reset Types A reset is the highest-priority exception. There are two types of reset: power-on reset and manual reset. As table 4.4 shows, a power-on reset initializes the internal state of the CPU and all registers of the on-chip supporting modules. A manual reset initializes the internal state of the CPU and all registers of the on-chip supporting modules except the bus state controller (BSC), pin function controller (PFC), and I/O ports (I/O). Table 4.4 Reset Types Transition Conditions Reset NMI RES Internal State CPU On-Chip Supporting Modules Power-on Reset High Low Initialized Initialized Manual Reset Low Low Initialized All initialized except BSC, PFC, and I/O Rev. 7.00 Jan 31, 2006 page 56 of 658 REJ09BX0272-0700 Section 4 Exception Handling 4.2.2 Power-On Reset When the NMI pin is high, a low input at the RES pin drives the chip into the power-on reset state. The RES pin should be driven low while the clock pulse generator (CPG) is stopped (or while the CPG is operating during the oscillation settling time) for at least 20 tcyc to assure that the chip is reset. A power-on reset initializes the internal state of the CPU and all registers of the on-chip supporting modules. For pin states in the power-on reset state, see appendix B, Pin States. While the NMI pin remains high, if the RES pin is held low for a certain time then driven high in the power-on state, power-on reset exception handling begins. The CPU then: 1. Reads the start address (initial PC value) from the exception vector table. 2. Reads the initial stack pointer value (SP) from the exception vector table. 3. Clears the vector base register (VBR) to H'00000000, and sets interrupt mask bits I3-I0 in the status register (SR) to H'F (1111). 4. Loads the values read from the exception vector table into the PC and SP and starts program execution. A power-on reset must be executed when turning on power. 4.2.3 Manual Reset When the NMI pin is high, a low input at the RES pin drives the chip into the manual reset state. To ensure that the chip is properly reset, drive the RES pin low for at least 20 tcyc. A manual reset initializes the internal state of the CPU and all registers of the on-chip supporting modules except the bus state controller, pin function controller, and I/O ports. Since a manual reset does not affect the bus state controller, the DRAM refresh control function operates even if the manual reset state continues for a long time. When a manual reset is performed during the bus cycle, manual reset exception handling is deferred until the end of the bus cycle. The manual reset thus cannot be used to abort the bus cycle. For the pin states during the manual reset state, see appendix B, Pin States. While the NMI pin remains low, if the RES pin is held low for a certain time then driven high in the manual reset state, manual reset exception handling begins. The CPU carries out the same operations as for a power-on reset. Rev. 7.00 Jan 31, 2006 page 57 of 658 REJ09B0272-0700 Section 4 Exception Handling 4.3 Address Errors 4.3.1 Address Error Sources Address errors occur during instruction fetches and data reading/writing as shown in table 4.5. Table 4.5 Address Error Sources Bus Cycle Type Instruction fetch Operation Address Error Instruction fetch from even address None (normal) Instruction fetch from odd address Address error Instruction fetch from outside on-chip None (normal) supporting module space Instruction fetch from on-chip supporting Address error module space Data read/write CPU or DMAC Access to word data from even address None (normal) Access to word data from odd address Address error Access to longword data aligned on None (normal) longword boundary Access to longword data not aligned on Address error longword boundary Access to word or byte data in on-chip None (normal) supporting module space* None (normal) Access to longword data in 16-bit onchip supporting module space* Access to longword data in 8-bit on-chip Address error supporting module space* Note: * See section 8, Bus State Controller (BSC), for details on the on-chip supporting module space. 4.3.2 Bus Master CPU Address Error Exception Handling When an address error occurs, address error exception handling starts after both the bus cycle that caused the address error and the instructions that were being executed at that time, have been completed. The CPU then: 1. Pushes SR onto the stack. 2. Pushes the program counter onto the stack. The PC value saved is the start address of the instruction following the last instruction to be executed. 3. Fetches the exception handling routine start address from the exception vector table for the address error that occurred and starts program execution from that address. The branch that occurs here is not a delayed branch. Rev. 7.00 Jan 31, 2006 page 58 of 658 REJ09BX0272-0700 Section 4 Exception Handling 4.4 Interrupts 4.4.1 Interrupt Sources Table 4.6 lists the types of interrupt exception handling sources (NMI, user break, IRQ, on-chip supporting module). Table 4.6 Interrupt Sources Interrupt Requesting Pin or Module Number of Sources NMI NMI pin (external input) 1 User break User break controller 1 IRQ IRQ0-IRQ7 pin (external input) 8 On-chip supporting module Direct Memory Access Controller 4 16-bit integrated timer pulse unit 15 Serial communication interface 8 A/D converter 1 Watchdog timer 1 Bus state controller 2 Each interrupt source has a different vector number and vector address offset value. See table 5.3, Interrupt Exception Vectors and Rankings, in section 5, Interrupt Controller (INTC), for details on vector numbers and vector table address offsets. 4.4.2 Interrupt Priority Rankings Interrupt sources are assigned priorities. When multiple interrupts occur at the same time, the interrupt controller (INTC) ascertains their priorities and starts exception handling based on its findings. Priorities from 16-0 can be assigned, with 0 the lowest level and 16 the highest. NMI has priority level 16 and cannot be masked. NMI is always accepted. The user break priority level is 15. The IRQ and on-chip supporting module interrupt priority levels can be set in interrupt priority level registers A-E (IPRA-IPRE) as shown in table 4.7. Priority levels 0-15 can be set. See section 5.3.1, Interrupt Priority Registers A-E (IPRA-IPRE), for details. Rev. 7.00 Jan 31, 2006 page 59 of 658 REJ09B0272-0700 Section 4 Exception Handling Table 4.7 Interrupt Priority Rankings Type Priority Comments NMI 16 Fixed and unmaskable User break 15 Fixed IRQ and on-chip supporting modules 0-15 Set in interrupt priority level registers A-E (IPRA-IPRE) 4.4.3 Interrupt Exception Handling When an interrupt is generated, the INTC ascertains the interrupt ranking. NMI is always accepted, but other interrupts are only accepted if their ranking is higher than the ranking set in the interrupt mask bits (I3-I0) of SR. When an interrupt is accepted, interrupt exception handling begins. In the interrupt exception handling sequence, the SR and PC values are pushed onto the stack, and the priority level of the accepted interrupt is copied to the interrupt mask level bits (I3-I0) in SR. In NMI exception handling, the priority ranking is 16 but the value 15 (H'F) is stored in I3-I0. The exception handling routine start address for the accepted interrupt is fetched from the exception vector table and the program branches to that address and starts executing. For further information on interrupts, see section 5.4, Interrupt Operation. Rev. 7.00 Jan 31, 2006 page 60 of 658 REJ09BX0272-0700 Section 4 Exception Handling 4.5 Instruction Exceptions 4.5.1 Types of Instruction Exceptions Table 4.8 shows the three types of instruction that start exception handling (trap instructions, illegal slot instructions, and general illegal instructions). Table 4.8 Types of Instruction Exceptions Type Source Instruction Comments Trap instruction TRAPA -- Illegal slot instruction Undefined code or instruction that rewrites the PC located immediately after a delayed branch instruction (delay slot) Delayed branch instructions are: JMP, JSR, BRA, BSR, RTS, RTE. Instructions that rewrite the PC are: JMP, JSR, BRA, BSR, RTS, RTE, BT, BF, and TRAPA General illegal instructions Undefined code in other than delay slot -- 4.5.2 Trap Instruction Trap instruction exception handling is carried out when a trap instruction (TRAPA) is executed. The CPU then: 1. Saves the status register by pushing register contents onto the stack. 2. Pushes the program counter value onto the stack. The PC value saved is the start address of the next instruction after the TRAPA instruction. 3. Reads the exception handling routine start address from the vector table corresponding to the vector number specified in the TRAPA instruction, branches to that address, and starts program execution. The branch is not a delayed branch. Rev. 7.00 Jan 31, 2006 page 61 of 658 REJ09B0272-0700 Section 4 Exception Handling 4.5.3 Illegal Slot Instruction An instruction located immediately after a delayed branch instruction is called an "instruction placed in a delay slot." If an undefined instruction is located in a delay slot, illegal slot instruction exception handling begins executing when the undefined code is decoded. Illegal slot instruction exception handling also begins when the instruction located in the delay slot is an instruction that rewrites the program counter. In this case, exception handling begins when the instruction that rewrites the PC is decoded. The CPU performs illegal slot exception handling as follows: 1. Saves the status register onto the stack. 2. Pushes the program counter value onto the stack. The PC value saved is the branch destination address of the delayed branch instruction immediately before the instruction that contains the undefined code or rewrites the PC. 3. Fetches the exception handling routine start address from the vector table corresponding to the exception that occurred, branches to that address, and starts executing the program. The branch is not a delayed branch. 4.5.4 General Illegal Instructions If an undefined instruction located other than in a delay slot (immediately after a delayed branch instruction) is decoded, general illegal instruction exception handling is executed. The CPU follows the same procedure as for illegal slot exception handling, except that the program counter (PC) value pushed on the stack in general illegal instruction exception handling is the start address of the illegal instruction with the undefined code. Rev. 7.00 Jan 31, 2006 page 62 of 658 REJ09BX0272-0700 Section 4 Exception Handling 4.6 Cases in which Exceptions are Not Accepted In some cases, address errors and interrupts that directly follow a delayed branch instruction or interrupt-disabled instruction are not accepted immediately. Table 4.9 lists these cases. When this occurs, the exception is accepted when an instruction that can accept the exception is decoded. Table 4.9 Cases in which Exceptions are Not Accepted Exception Source Case 1 Immediately after delayed branch instruction* 2 Immediately after interrupt-disabled instruction* Address Error Interrupt X X O X X: Not accepted O: Accepted Notes: 1. Delayed branch instructions: JMP, JSR, BRA, BSR, RTS, RTE 2. Interrupt-disabled instructions: LDC, LDC.L, STC, STC.L, LDS, LDS.L, STS, STS.L 4.6.1 Immediately after Delayed Branch Instruction Address errors and interrupts are not accepted when an instruction in a delay slot immediately following a delayed branch instruction is decoded. The delayed branch instruction and the instruction in the delay slot are therefore always executed one after the other. Exception handling is never inserted between them. 4.6.2 Immediately after Interrupt-Disabling Instruction Interrupts are not accepted when the instruction immediately following an interrupt-disabled instruction is decoded. Address errors are accepted, however. Rev. 7.00 Jan 31, 2006 page 63 of 658 REJ09B0272-0700 Section 4 Exception Handling 4.7 Stack Status after Exception Handling Table 4.10 shows the stack after exception handling. Table 4.10 Stack after Exception Handling Type Address error Stack Status Type Stack Status Interrupt SP Address of instruction Upper 16 bits after instruction that has finished executing SP Address of instruction Upper 16 bits after instruction that has finished executing Lower 16 bits Lower 16 bits SR SR Upper 16 bits Lower 16 bits Lower 16 bits Trap instruction SP Address of instruction Upper 16 bits after TRAPA instruction Illegal slot instrucSP tion Lower 16 bits SR Upper 16 bits Branch destination address of delayed branch instuction Lower 16 bits Upper 16 bits Lower 16 bits Upper 16 bits SR Upper 16 bits Lower 16 bits General illegal instruction SP Start address of illegal instruction Upper 16 bits Lower 16 bits SR Upper 16 bits Lower 16 bits Note: Stack status is based on a bus width of 16 bits. Rev. 7.00 Jan 31, 2006 page 64 of 658 REJ09BX0272-0700 Section 4 Exception Handling 4.8 Notes 4.8.1 Value of the Stack Pointer (SP) An address error occurs if the stack is accessed for exception handling when the value of the stack pointer (SP) is not a multiple of four. Therefore, a multiple of four should always be stored in the SP. 4.8.2 Value of the Vector Base Register (VBR) An address error occurs if the vector table is accessed for exception handling when the value of the vector base register (VBR) is not a multiple of four. Therefore, VBR should always be set to a multiple of four. 4.8.3 Address Errors Caused by Stacking During Address Error Exception Handling If the stack pointer is not a multiple of four, address errors will occur in the exception handling (interrupt, etc.) stacking. After the exception handling ends, the CPU will then shift to address error exception handling. An address error will also occur during the address error exception handling stacking, but the CPU is set up to ignore the address error so that it can avoid an infinite series of address errors. This allows it to shift program control to the address error exception handling routine and handle the error. When an address error does occur in exception handling stacking, the stacking bus cycle (write) is executed. In SR and PC stacking, four is subtracted from each of the SPs so the SP values are not multiples of four after stacking either. Since the address value output during stacking is the SP value, the address that produced the error is exactly what is output. In such cases, the stacked write data will be undefined. Rev. 7.00 Jan 31, 2006 page 65 of 658 REJ09B0272-0700 Section 4 Exception Handling Rev. 7.00 Jan 31, 2006 page 66 of 658 REJ09BX0272-0700 Section 5 Interrupt Controller (INTC) Section 5 Interrupt Controller (INTC) 5.1 Overview The interrupt controller (INTC) determines the priority of interrupt sources and controls interrupt requests to the CPU. INTC has registers for assigning priority levels to interrupt sources. These registers handle interrupt requests according to user-specified priorities. 5.1.1 Features The interrupt controller has the following features: * 16 settable priority levels: Five interrupt priority registers can set 16 levels of interrupt priorities for IRQ and on-chip supporting module interrupt sources. * NMI noise canceller function: INTC has an NMI input level bit that indicates the NMI pin status. By reading this bit in the interrupt exception handling routine, the pin status can be checked for use in a noise canceller function. * The interrupt controller can notify external devices (via the IRQOUT pin) that an on-chip interrupt has occurred. In this way an external device can, for example, be informed if an onchip interrupt occurs while the chip is operating in bus-released mode and the bus has been requested. 5.1.2 Block Diagram Figure 5.1 shows a block diagram of the interrupt controller. Rev. 7.00 Jan 31, 2006 page 67 of 658 REJ09B0272-0700 Section 5 Interrupt Controller (INTC) IRQOUT NMI IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 Input control Priority decision logic Comparator Interrupt request SR UBC DMAC ITU SCI PRT A/D WDT REF (Interrupt request) (Interrupt request) (Interrupt request) (Interrupt request) (Interrupt request) (Interrupt request) (Interrupt request) (Interrupt request) I3 I2 I1 CPU IPR ICR Module bus Bus interface Internal bus IPRA-IPRE INTC UBC: User break controller DMAC: Direct memory access controller ITU: 16-bit integrated timer pulse unit SCI: Serial communication interface PRT: Parity control unit of BSC A/D: A/D converter WDT: Watchdog timer REF: DRAM refresh control unit of BSC ICR: Interrupt control register IPRA-IPRE: Interrupt priority registers A-E SR: Status register Figure 5.1 Block Diagram of Interrupt Controller Rev. 7.00 Jan 31, 2006 page 68 of 658 REJ09B0272-0700 I0 Section 5 Interrupt Controller (INTC) 5.1.3 Pin Configuration INTC pins are summarized in table 5.1. Table 5.1 INTC Pin Configuration Name Abbr. Nonmaskable interrupt input pin NMI I/O Function I Inputs a non-maskable interrupt request signal. Interrupt request input pins IRQ0- IRQ7 I Inputs maskable interrupt request signals. Interrupt request output pin IRQOUT O Outputs a signal indicating an interrupt source has occurred. 5.1.4 Registers The interrupt controller has six registers as listed in table 5.2. These registers are used for setting interrupt priority levels and controlling the detection of external interrupt input signals. Table 5.2 Interrupt Controller Register Configuration 2 Name Abbr. R/W Address* Interrupt priority register A IPRA R/W H'5FFFF84 Initial Value Bus width H'0000 8, 16, 32 Interrupt priority register B IPRB R/W H'5FFFF86 H'0000 8, 16, 32 Interrupt priority register C IPRC R/W H'5FFFF88 H'0000 8, 16, 32 Interrupt priority register D IPRD R/W H'5FFFF8A H'0000 8, 16, 32 Interrupt priority register E IPRE R/W H'5FFFF8C H'0000 8, 16, 32 Interrupt control register ICR R/W H'5FFFF8E 1 * 8, 16, 32 Notes: 1. H'8000 when pin NMI is high, H'0000 when pin NMI is low. 2. Only the values of bits A27-A24 and A8-A0 are valid; bits A23-A9 are ignored. For details on the register addresses, see section 8.3.5, Area Descriptions. Rev. 7.00 Jan 31, 2006 page 69 of 658 REJ09B0272-0700 Section 5 Interrupt Controller (INTC) 5.2 Interrupt Sources There are four types of interrupt sources: NMI, user break, IRQ, and on-chip supporting module interrupts. Interrupt rankings are expressed as priority levels (0-16), with 0 the lowest and 16 the highest. An interrupt set to level 0 is masked. 5.2.1 NMI Interrupts NMI is the highest-priority interrupt (level 16) and is always accepted. Input at the NMI pin is edge-sensed. Either the rising or falling edge can be selected by setting the NMI edge select bit (NMIE) in the interrupt control register (ICR). NMI interrupt exception handling sets the interrupt mask level bits (I3-I0) in the status register (SR) to level 15. 5.2.2 User Break Interrupt A user break interrupt occurs when a break condition is satisfied in the user break controller (UBC). A user break interrupt has priority level 15. User break interrupt exception handling sets the interrupt mask level bits (I3-I0) in the status register (SR) to level 15. For further details on the user break interrupt, see section 6, User Break Controller (UBC). 5.2.3 IRQ Interrupts IRQ interrupts are requested by input from pins IRQ0-IRQ7. IRQ sense select bits 0-7 (IRQ0S- IRQ7S) in the interrupt control register (ICR) can select low-level sensing or falling-edge sensing for each pin independently. Interrupt priority registers A and B (IPRA and IPRB) can select priority levels from 0-15 for each pin. IRQ interrupt exception handling sets the interrupt mask level bits (I3-I0) in the status register (SR) to the priority level value of the IRQ interrupt that was accepted. Rev. 7.00 Jan 31, 2006 page 70 of 658 REJ09B0272-0700 Section 5 Interrupt Controller (INTC) 5.2.4 On-Chip Interrupts On-chip interrupts are interrupts generated by the following 6 on-chip supporting modules: * Direct memory access controller (DMAC) * 16-bit integrated timer pulse unit (ITU) * Serial communication interface (SCI) * Bus state controller (BSC) * A/D converter (A/D) * Watchdog timer (WDT) A different interrupt vector is assigned to each interrupt source, so the exception handling routine does not have to decide which interrupt has occurred. Priority levels 0-15 can be assigned to individual on-chip supporting module in interrupt priority registers C-E (IPRC-IPRE). On-chip interrupt exception handling sets the interrupt mask level bits (I3-I0) in the status register (SR) to the priority level value of the on-chip interrupt that was accepted. 5.2.5 Interrupt Exception Vectors and Priority Rankings Table 5.3 lists the vector numbers, vector table address offsets, and interrupt priority order of the interrupt sources. Each interrupt source is allocated a different vector number and vector table address offset. The vector table address is calculated from this vector number and address offset. In interrupt exception handling, the exception handling routine start address is fetched from the vector table indicated by this vector table address. See table 4.3, Calculation of Exception Vector Table Address, in section 4, Exception Handling, for details on this calculation. Arbitrary interrupt priority levels between 0 and 15 can be assigned to IRQ and on-chip supporting module interrupt sources by setting interrupt priority registers A-E (IPRA-IPRE) for each pin or module. The interrupt sources for IPRC-IPRE, however, must be ranked in the order listed under Priority Within Module in table 5.3 and cannot be changed. A reset assigns priority level 0 to IRQ and on-chip supporting module interrupts. If the same priority level is assigned to two or more interrupt sources, and interrupts from those sources occur simultaneously, their priority order is the default priority order indicated at the right in table 5.3. Rev. 7.00 Jan 31, 2006 page 71 of 658 REJ09B0272-0700 Section 5 Interrupt Controller (INTC) Table 5.3 Interrupt Exception Vectors and Rankings Interrupt Priority Order IPR (Bit Interrupt Source (Initial Value) Numbers) Priority VecWithin tor Address Offset in Module No. Vector Table NMI -- -- 16 11 Default Priority Order H'0000002C-H'0000002F High User break 15 -- -- 12 H'00000030-H'00000033 IRQ0 0-15 (0) IPRA (15-12) -- 64 H'00000100-H'00000103 IRQ1 0-15 (0) IPRA (11-8) -- 65 H'00000104-H'00000107 IRQ2 0-15 (0) IPRA (7-4) -- 66 H'00000108-H'0000010B IRQ3 0-15 (0) IPRA (3-0) -- 67 H'0000010C-H'0000010F IRQ4 0-15 (0) IPRB (15-12) -- 68 H'00000110-H'00000113 IRQ5 0-15 (0) IPRB (11-8) -- 69 H'00000114-H'00000117 IRQ6 0-15 (0) IPRB (7-4) -- 70 H'00000118-H'0000011B IRQ7 0-15 (0) IPRB (3-0) -- 71 H'0000011C-H'0000011F DMAC0 DEI0 0-15 (0) IPRC (15-12) 3 72 H'00000120-H'00000123 2 73 H'00000124-H'00000127 1 74 H'00000128-H'0000012B 0 75 H'0000012C-H'0000012F IPRC (11-8) 3 76 H'00000130-H'00000133 2 77 H'00000134-H'00000137 1 78 H'00000138-H'0000013B 0 79 H'0000013C-H'0000013F 3 80 H'00000140-H'00000143 IMIB0 2 81 H'00000144-H'00000147 OVI0 1 82 H'00000148-H'0000014B Reserved 0 83 H'0000014C-H'0000014F Reserved DMAC1 DEI1 Reserved DMAC2 DEI2 0-15 (0) Reserved DMAC3 DEI3 Reserved ITU0 ITU1 ITU2 IMIA0 IMIA1 0-15 (0) 3 84 H'00000150-H'00000153 IMIB1 2 85 H'00000154-H'00000157 OVI1 1 86 H'00000158-H'0000015B Reserved 0 87 H'0000015C-H'0000015F IPRD (15-12) 3 88 H'00000160-H'00000163 IMIA2 0-15 (0) IPRC (7-4) 0-15 (0) IPRC (3-0) IMIB2 2 89 H'00000164-H'00000167 OVI2 1 90 H'00000168-H'0000016B Reserved 0 91 H'0000016C-H'0000016F Low Rev. 7.00 Jan 31, 2006 page 72 of 658 REJ09B0272-0700 Section 5 Interrupt Controller (INTC) Interrupt Priority Order IPR (Bit Interrupt Source (Initial Value) Numbers) ITU3 IMIA3 ITU4 SCI0 92 H'00000170-H'00000173 High IMIB3 2 93 H'00000174-H'00000177 OVI3 1 94 H'00000178-H'0000017B Reserved 0 95 H'0000017C-H'0000017F 3 96 H'00000180-H'00000183 0-15 (0) IPRD (7-4) IMIB4 2 97 H'00000184-H'00000187 OVI4 1 98 H'00000188-H'0000018B Reserved 0 99 H'0000018C-H'0000018F 3 100 H'00000190-H'00000193 2 101 H'00000194-H'00000197 ERI0 0-15 (0) IPRD (3-0) RxI0 SCI1 TxI0 1 102 H'00000198-H'0000019B TEI0 0 103 H'0000019C-H'0000019F IPRE (15-12) 3 104 H'000001A0-H'000001A3 RxI1 2 105 H'000001A4-H'000001A7 TxI1 1 106 H'000001A8-H'000001AB ERI1 0-15 (0) TEI1 0 107 H'000001AC-H'000001AF IPRE (11-8) 3 108 H'000001B0-H'000001B3 ITI 2 109 H'000001B4-H'000001B7 Reserved 1 110 H'000001B8-H'000001BB Reserved 0 111 H'000001BC-H'000001BF 3 112 H'000001C0-H'000001C3 1 PRT* PEI A/D WDT Default Priority Order IPRD (11-8) 3 IMIA4 0-15 (0) Priority VecWithin tor Address Offset in Module No. Vector Table ITI 0-15 (0) 0-15 (0) IPRE (7-4) 2 REF* CMI 2 113 H'000001C4-H'000001C7 Reserved 1 114 H'000001C8-H'000001CB Reserved 0 115 H'000001CC-H'000001CF -- 116 to 255 H'000001D0-H'000001D3 to H'000003FC-H'000003FF Low Reserved -- -- Notes: 1. PRT: Parity control unit of bus state controller. 2. REF: DRAM refresh control unit of bus state controller. Rev. 7.00 Jan 31, 2006 page 73 of 658 REJ09B0272-0700 Section 5 Interrupt Controller (INTC) 5.3 Register Descriptions 5.3.1 Interrupt Priority Registers A-E (IPRA-IPRE) The five registers IPRA-IPRE are 16-bit read/write registers that assign priority levels from 0-15 to the IRQ and on-chip supporting module interrupt sources. Interrupt request sources are mapped onto IPRA-IPRE as shown in table 5.4. Bit 15 14 13 12 11 10 9 8 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Bit 7 6 5 4 3 2 1 0 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Table 5.4 Interrupt Request Sources and IPRA-IPRE Register Bits 15-12 Bits 11-8 Bits 7-4 Bits 3-0 IPRA IRQ0 IRQ1 IRQ2 IRQ3 IPRB IRQ4 IRQ5 IRQ6 IRQ7 IPRC DMAC0, DMAC1 DMAC2, DMAC3 ITU0 ITU1 IPRD ITU2 ITU3 IPRE SCI1 PRT* , A/D ITU4 1 SCI0 2 WDT, REF* 3 (Reserved)* Notes: 1. PRT: Parity control unit of bus state controller. See section 8, Bus State Controller (BSC), for details. 2. REF: DRAM refresh control unit of bus controller. See section 8, Bus State Controller (BSC), for details. 3. Always read as 0. Always write 0 in reserved bits. As indicated in table 5.4, four IRQ pins or four groups of on-chip supporting modules are assigned to each interrupt priority register. The priority levels for the four pins or groups can be set by setting the corresponding 4-bit groups of bits 15-12, bits 11-8, bits 7-4, and bits 3-0 (of IPRA- IPRE) with values in the range of H'0 (0000) to H'F (1111). Setting H'0 gives interrupt priority level 0 (the lowest). Setting H'F gives level 15 (the highest). When two on-chip supporting modules are assigned to the same bits (DMAC0 and DMAC1, or DMAC2 and DMAC3, or the parity control unit and the A/D converter, or the watchdog timer and DRAM refresh control unit), Rev. 7.00 Jan 31, 2006 page 74 of 658 REJ09B0272-0700 Section 5 Interrupt Controller (INTC) those two modules have the same priority. A reset initializes IPRA-IPRE to H'0000. These registers are not initialized in standby mode. 5.3.2 Interrupt Control Register (ICR) ICR is a 16-bit register that sets the input detection mode of external interrupt input pins NMI and IRQ0-IRQ7, and indicates the input signal level at the NMI pin. A reset initializes ICR but standby mode does not. Bit: 15 14 13 12 11 10 9 8 NMIL -- -- -- -- -- -- NMIE Initial value * 0 0 0 0 0 0 0 Read/Write R -- -- -- -- -- -- R/W Bit Initial value 7 6 5 4 3 2 1 0 IRQ0S IRQ1S IRQ2S IRQ3S IRQ4S IRQ5S IRQ6S IRQ7S 0 0 0 0 0 0 0 0 R/W R/W R/W R/W Read/Write R/W R/W R/W R/W Note: * When NMI input is high: 1; when NMI input is low: 0 Bit 15NMI input level (NMIL): NMIL sets the level of the signal input at the NMI pin. NMIL cannot be modified. The NMI input level can be read to determine the NMI pin level. Bit 15: NMIL Description 0 NMI input level is low 1 NMI input level is high Bits 14-9Reserved: These bits are always read as 0. The write value should always be 0. Bit 8NMI Edge Select (NMIE): NMIE selects whether the falling or rising edge of the interrupt request signal at the NMI pin is sensed. Bit 8: NMIE Description 0 Interrupt is requested on falling edge of NMI input 1 Interrupt is requested on rising edge of NMI input (Initial value) Rev. 7.00 Jan 31, 2006 page 75 of 658 REJ09B0272-0700 Section 5 Interrupt Controller (INTC) Bits 7-0IRQ0-IRQ7 Sense Select (IRQ0S-IRQ7S): IRQ0-IRQ7 select whether the falling edge or low level of the IRQ inputs is sensed at pins IRQ0-IRQ7. Bits 7-0: IRQ0S-IRQ7S Description 0 Interrupt is requested when IRQ input is low 1 Interrupt is requested on falling edge of IRQ input 5.4 Interrupt Operation 5.4.1 Interrupt Sequence (Initial value) The sequence of interrupt operations is described below. Figure 5.2 shows a flowchart of the operations up to acceptance of the interrupt. 1. The interrupt request sources send interrupt request signals to the interrupt controller. 2. The interrupt controller selects the highest-priority interrupt among the interrupt requests sent, following the priority order indicated in table 5.3 and the levels set in interrupt priority registers A-E (IPRA-IPRE). Lower priority interrupts are ignored*. If two interrupts with the same priority level are requested simultaneously, or if there are multiple interrupts occurring within a single module, the interrupt with the highest default priority or priority within module as indicated in table 5.3 is selected. 3. The interrupt controller compares the priority level of the selected interrupt request with the interrupt mask level bits (I3-I0) in the CPU's status register (SR). If the request priority level is equal to or less than the interrupt mask level, the request is ignored. If the request priority level is higher than the interrupt mask level, the interrupt controller accepts the request and sends an interrupt request signal to the CPU. 4. When the interrupt controller accepts an interrupt request, it drives IRQOUT pin low. 5. The CPU detects the interrupt request sent from the interrupt controller when it decodes the next instruction to be executed. Instead of executing that instruction, the CPU starts interrupt exception handling. (See figure 5.4.) 6. In interrupt exception handling, first SR and PC are pushed onto the stack. 7. The priority level of the accepted interrupt is copied to the interrupt mask level bits (I3-I0) in the status register (SR). 8. When the accepted interrupt is level-sensed or from an on-chip supporting module, the IRQOUT pin returns to the high level. If the accepted interrupt is edge-sensed, the IRQOUT pin returns to the high level when the instruction to be executed by the CPU in (5) is replaced by the interrupt exception handling. If the interrupt controller has accepted another interrupt (of a level higher than the current interrupt), however, the IRQOUT pin remains low. Rev. 7.00 Jan 31, 2006 page 76 of 658 REJ09B0272-0700 Section 5 Interrupt Controller (INTC) 9. The CPU accesses the exception vector table at the entry for the vector number of the accepted interrupt, reads the start address of the exception handling routine, branches to that address, and starts executing the program there. This branch is not delayed. Note: * A request for an external interrupt (IRQ) designated as edge-detected is held pending once only. An external interrupt designated as level-detected is held pending as long as the interrupt request continues, but if the request is cleared before the CPU next accepts an interrupt, the interrupt request is regarded as not having been made. Interrupt requests from on-chip supporting modules are level requests. When the status flag in a particular module is set, an interrupt is requested. For details, see the descriptions of the individual modules. Note that the interrupt request will be continued unless an operation described in "Clearing Conditions" is performed. Rev. 7.00 Jan 31, 2006 page 77 of 658 REJ09B0272-0700 Section 5 Interrupt Controller (INTC) Program execution state No Interrupt? Yes No NMI? Yes User break? Yes No Level 15 interrupt? No IRQOUT low*1 Yes Push SR onto stack Yes Level 14 interrupt? I3 to I0 level 14? Yes Level 1 interrupt? I3 to I0 level 13? Yes Push PC onto stack No Yes Copy level of acceptance from I3 to I0 No No Yes IRQOUT high*2 No I3 to I0 = level 0? No Read exception vector table Branch to exception handling routine I3 to I0: Interrupt mask bits of status register Notes: 1. IRQOUT is the same signal as the interrupt request signal to the CPU (figure 5.1). The IRQOUT pin returns to the high level when the interrupt controller has accepted the interrupt of a level higher than that specified by bits I3 to I0 in the CPU's status register. 2. If the accepted interrupt is edge-sensed, the IRQOUT pin returns to the high level when the instruction to be executed by the CPU is replaced by interrupt exception handling (before the status register is saved to the stack ). If the interrupt controller has accepted another interrupt of a level higher than the current interrupt, and has sent an interrupt request to the CPU, however, the IRQOUT pin remains low. Figure 5.2 Flowchart of Interrupt Operation Rev. 7.00 Jan 31, 2006 page 78 of 658 REJ09B0272-0700 Section 5 Interrupt Controller (INTC) 5.4.2 Stack after Interrupt Exception Handling Figure 5.3 shows the stack after interrupt exception handling. Address 4n-8 PC*1 4n-2 SP*2 Lower 16 bits 4n-6 4n-4 Upper 16 bits SR Upper 16 bits Lower 16 bits 4n Notes: Bus width is 16 bits. 1. PC stores the start address of the next instruction (return instruction) after the executed instruction. 2. The value of SP must always be a multiple of four. Figure 5.3 Stack after Interrupt Exception Handling Rev. 7.00 Jan 31, 2006 page 79 of 658 REJ09B0272-0700 Section 5 Interrupt Controller (INTC) 5.5 Interrupt Response Time Table 5.5 shows the interrupt response time, which is the time from the occurrence of an interrupt request until interrupt exception handling starts and fetching of the first instruction of the interrupt handling routine begins. Figure 5.4 shows the pipeline when an IRQ interrupt is accepted. Table 5.5 Interrupt Response Time Number of States NMI or On-Chip Interrupt IRQ Interrupt priority decision and comparison with SR mask bit 2 3 Wait for completion of sequence currently being executed by CPU X ( 0) Time from interrupt exception handling (saving PC and SR and fetching vector address) until fetching of first instruction of interrupt handling routine starts 5 + m1 + m2 + m3 Interrupt response Total 7 + m1 + m2 + m3 8 + m1 + m2 + m3 Minimum 10 11 0.50-0.55 s at 20 MHz Maximum 11 + 2(m1 + m2 + m3) + m4 12 + 2(m1 + m2 + m3) + m4 (m1 = m2 = m3 = m4 = 1) 0.90-0.95 s at 20 MHz Item Notes The longest sequence is the interrupt or address error exception handling sequence: X = 4 + m1 + m2 + m3 + m4. If an interruptmasking instruction follows, however, the time may be longer. Notes: m1-m4 are the number of states needed for the following memory accesses: m1: SR save cycle (longword write) m2: PC save cycle (longword write) m3: Vector address read cycle (longword read) m4: Fetch start instruction of interrupt handling routine Rev. 7.00 Jan 31, 2006 page 80 of 658 REJ09B0272-0700 Section 5 Interrupt Controller (INTC) Interrupt accepted 5 + m1 + m2 + m3 3 m1 m2 1 m3 1 3 IRQ Instruction (instruction replaced by interrupt exception handling) F D E E M M E M E E Overrun fetch Interrupt service routine-- first instruction F F D E IRQOUT (edge) (level) When m1 = m2 = m3, the interrupt response time is 11 cycles. F (Instruction fetch) D (Instruction decoding) E (Instruction execution) M (Memory access) Instruction fetched from memory where program is stored. The fetched instruction is decoded. Data operations and address calculations are performed according to the decoded results. Data in memory is accessed. Note: For the interrupt acceptance timing, see table 4.1, Exception Source Detection and Start of Handling, in section 4.1.2, Exception Handling Operation. Figure 5.4 Example of Pipelining in IRQ Interrupt Acceptance 5.6 Usage Notes When the following operations are performed in the order shown when a pin to which IRQ input is assigned is designated as a general input pin by the pin function controller (PFC) and inputs a lowlevel signal, the IRQ falling edge is detected, and an interrupt request is detected, immediately after the setting in (b) is performed: * An interrupt control register (ICR) setting is made so that an interrupt is detected at the falling edge of IRQ. ...(a) * The function of pins to which IRQ input is assigned is switched from general input to IRQ input by a pin function controller (PFC) setting. ...(b) Therefore, when switching the pin function from general input pin to IRQ input, the pin function controller (PFC) setting should be changed to IRQ input while the pin to which IRQ input is assigned is high. Rev. 7.00 Jan 31, 2006 page 81 of 658 REJ09B0272-0700 Section 5 Interrupt Controller (INTC) Rev. 7.00 Jan 31, 2006 page 82 of 658 REJ09B0272-0700 Section 6 User Break Controller (UBC) Section 6 User Break Controller (UBC) 6.1 Overview The user break controller (UBC) simplifies the debugging of user programs. Break conditions are set in the UBC and a user break interrupt request is sent to the CPU in response to the contents of a CPU or DMAC bus cycle. This function can implement an effective self-monitoring debugger, enabling a program to be debugged by itself without using a large in-circuit emulator. 6.1.1 Features * The following break conditions can be set: Address CPU cycle or DMA cycle Instruction fetch or data access Read or write Operand size (longword access, word access, or byte access) * When break conditions are met, a user break interrupt is generated. A user-created user break interrupt exception routine can then be executed. * When a break is set to a CPU instruction fetch, the break occurs just before the fetched instruction. Rev. 7.00 Jan 31, 2006 page 83 of 658 REJ09B0272-0700 Section 6 User Break Controller (UBC) 6.1.2 Block Diagram Figure 6.1 shows a block diagram of the user break controller. BBR BAMRH BARH BAMRL BARL Internal bus Bus interface Module bus Break condition comparator User break interrupt generating circuit UBC Interrupt request Interrupt controller BARH, BARL: Break address registers H and L BAMRH, BAMRL: Break address mask registers H and L BBR: Break bus cycle register Figure 6.1 Block Diagram of User Break Controller Rev. 7.00 Jan 31, 2006 page 84 of 658 REJ09B0272-0700 Section 6 User Break Controller (UBC) 6.1.3 Register Configuration The user break controller has five registers as listed in table 6.1. These registers are used for setting break conditions. Table 6.1 User Break Controller Registers Name Abbr. R/W Address* Initial Value Bus width Break address register high BARH R/W H'5FFFF90 H'0000 8, 16, 32 Break address register low BARL R/W H'5FFFF92 H'0000 8, 16, 32 Break address mask register high BAMRH R/W H'5FFFF94 H'0000 8, 16, 32 Break address mask register low BAMRL R/W H'5FFFF96 H'0000 8, 16, 32 Break bus cycle register BBR R/W H'5FFFF98 H'0000 8, 16, 32 Note: * Only the values of bits A27-A24 and A8-A0 are valid; bits A23-A9 are ignored. For details on the register addresses, see section 8.3.5, Area Descriptions. Rev. 7.00 Jan 31, 2006 page 85 of 658 REJ09B0272-0700 Section 6 User Break Controller (UBC) 6.2 Register Descriptions 6.2.1 Break Address Registers (BAR) There are two break address registers--break address register H (BARH) and break address register L (BARL)--that together form a single group. Both are 16-bit read/write registers. BARH stores the upper bits (bits 31-16) of the address of the break condition. BARL stores the lower bits (bits 15-0) of the address of the break condition. A reset initializes both BARH and BARL to H'0000. They are not initialized in standby mode. BARH: Break address register H. Bit 15 14 13 12 11 10 9 8 BA31 BA30 BA29 BA28 BA27 BA26 BA25 BA24 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 BA23 BA22 BA21 BA20 BA19 BA18 BA17 BA16 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Bit BARH Bits 15-0--Break Address 31-16 (BA31-BA16): BA31-BA16 store the upper bit values (bits 31-16) of the address of the break condition. BARL: Break address register L. Bit Initial value Read/Write Bit Initial value Read/Write 15 BA15 0 R/W 14 BA14 0 R/W 13 BA13 0 R/W 12 BA12 0 R/W 11 BA11 0 R/W 10 BA10 0 R/W 9 BA9 0 R/W 8 BA8 0 R/W 7 BA7 0 R/W 6 BA6 0 R/W 5 BA5 0 R/W 4 BA4 0 R/W 3 BA3 0 R/W 2 BA2 0 R/W 1 BA1 0 R/W 0 BA0 0 R/W BARL Bits 15-0--Break Address 15-0 (BA15-BA0): BA15-BA0 store the lower bit values (bits 15-0) of the address of the break condition. Rev. 7.00 Jan 31, 2006 page 86 of 658 REJ09B0272-0700 Section 6 User Break Controller (UBC) 6.2.2 Break Address Mask Register (BAMR) The two break address mask registers--break address mask register H (BAMRH) and break address mask register L (BARML)--together form a single group. Both are 16-bit read/write registers. BAMRH determines which of the bits in the break address set in BARH are masked. BAMRL determines which of the bits in the break address set in BARL are masked. A reset initializes BAMRH and BARML to H'0000. They are not initialized in standby mode. BAMRH: Break address mask register H. Bit Initial value Read/Write Bit Initial value Read/Write 15 BAM31 0 R/W 14 BAM30 0 R/W 13 BAM29 0 R/W 12 BAM28 0 R/W 11 BAM27 0 R/W 10 BAM26 0 R/W 9 BAM25 0 R/W 8 BAM24 0 R/W 7 BAM23 0 R/W 6 BAM22 0 R/W 5 BAM21 0 R/W 4 BAM20 0 R/W 3 BAM19 0 R/W 2 BAM18 0 R/W 1 BAM17 0 R/W 0 BAM16 0 R/W BAMRH bits 15-0--Break Address Mask 31-16 (BAM31-BAM16): BAM31-BAM16 specify whether bits BA31-BA16 of the break address set in BARH are masked or not. BAMRL: Break address mask register L. Bit Initial value Read/Write Bit Initial value Read/Write 15 BAM15 0 R/W 14 BAM14 0 R/W 13 BAM13 0 R/W 12 BAM12 0 R/W 11 BAM11 0 R/W 10 BAM10 0 R/W 9 BAM9 0 R/W 8 BAM8 0 R/W 7 BAM7 0 R/W 6 BAM6 0 R/W 5 BAM5 0 R/W 4 BAM4 0 R/W 3 BAM3 0 R/W 2 BAM2 0 R/W 1 BAM1 0 R/W 0 BAM0 0 R/W BAMRL bits 15-0--Break Address Mask 15-0 (BAM15-BAM0)): BAM15-BAM0 specify whether bits BA15-BA0 of the break address set in BARH are masked or not. Bits 15-0: BAMn 0 1 n = 31-0 Description Break address bit BAn is included in the break condition Break address bit BAn is not included in the break condition (Initial value) Rev. 7.00 Jan 31, 2006 page 87 of 658 REJ09B0272-0700 Section 6 User Break Controller (UBC) 6.2.3 Break Bus Cycle Register (BBR) The break bus cycle register (BBR) is a 16-bit read/write register that selects the following four break conditions: * CPU cycle or DMA cycle * Instruction fetch or data access * Read or write * Operand size (byte, word, longword) A reset initializes BBR to H'0000. It is not initialized in standby mode. Bit 15 14 13 12 11 10 9 8 -- -- -- -- -- -- -- -- Initial value 0 0 0 0 0 0 0 0 Read/Write -- -- -- -- -- -- -- -- Bit 7 6 5 4 3 2 1 0 CD1 CD0 ID1 ID0 RW1 RW0 SZ1 SZ0 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Bits 15-8--Reserved: These bits are always read as 0. The write value should always be 0. Bits 7 and 6--CPU Cycle/DMA Cycle Select (CD1 and CD0): CD1 and CD0 select whether to break on CPU and/or DMA bus cycles. Bit 7: CD1 Bit 6: CD0 Description 0 0 No break interrupt occurs 1 Break only on CPU cycles 0 Break only on DMA cycles 1 Break on both CPU and DMA cycles 1 Rev. 7.00 Jan 31, 2006 page 88 of 658 REJ09B0272-0700 (Initial value) Section 6 User Break Controller (UBC) Bits 5 and 4--Instruction Fetch/Data Access Select (ID1, ID0): ID1 and ID0 select whether to break on instruction fetch and/or data access bus cycles. Bit 5: ID1 Bit 4: ID0 Description 0 0 No break interrupt occurs 1 Break only on instruction fetch cycles 0 Break only on data access cycles 1 Break on both instruction fetch and data access cycles 1 (Initial value) Bits 3 and 2--Read/Write Select (RW1, RW0): RW1 and RW0 select whether to break on read and/or write access cycles. Bit 3: RW1 Bit 2: RW0 Description 0 0 No break interrupt occurs 1 Break only on read cycles 0 Break only on write cycles 1 Break on both read and write cycles 1 (Initial value) Bits 1 and 0 --Operand Size Select (SZ1, SZ0): SZ1 and SZ0 select the bus cycle operand size as a break condition. Bit 1: SZ1 Bit 0: SZ0 Description 0 0 Operand size is not a break condition 1 Break on byte access 0 Break on word access 1 Break on longword access 1 (Initial value) Note: When setting a break on an instruction fetch, clear the SZ0 bit to 0. All instructions will be considered to be accessed as words (even those instructions in on-chip memory for which two instructions can be fetched simultaneously in a single bus cycle). Instruction fetch is by word access and CPU/DMAC data access is by the specified operand size. The access is not determined by the bus width of the space being accessed. Rev. 7.00 Jan 31, 2006 page 89 of 658 REJ09B0272-0700 Section 6 User Break Controller (UBC) 6.3 Operation 6.3.1 Flow of User Break Operation The flow from setting of break conditions to user break interrupt exception handling is described below. 1. Break conditions are set in the break address register (BAR), break address mask register (BAMR), and break bus cycle register (BBR). Set the break address in BAR, the address bits to be masked in BAMR and the type of break bus cycle in BBR. When even one of the BBR groups (CPU cycle/DMA cycle select bits (CD1, CD0), instruction fetch/data access select bits (ID1, ID0), read/write select bits (RW1, RW0)) is set to 00 (no user break interrupt), there will be no user break even when all other conditions are consistent. To use a user break interrupt, set conditions for all three pairs. 2. The UBC checks to see if the set conditions are satisfied, using the system shown in figure 6.2. When the break conditions are satisfied, the UBC sends a user break interrupt request to the interrupt controller. 3. On receiving the user break interrupt request, the interrupt controller checks its priority level. The user break interrupt has priority level 15, so it is accepted only if the interrupt mask level in bits I3-I0 in the status register (SR) is 14 or lower. When the I3-I0 bit level is 15, the user break interrupt cannot be accepted, but is held pending until user break interrupt exception handling is carried out. NMI exception handling sets I3-I0 to level 15, so a user break cannot occur during the NMI handling routine unless the NMI handling routine itself begins by reducing I3-I0 to level 14 or lower. Section 5, Interrupt Controller (INTC), describes the handling of priority levels in greater detail. 4. INTC sends a request signal for a user break interrupt to the CPU. When the CPU receives it, it starts user break interrupt exception handling. Section 5.4, Interrupt Operation, describes interrupt exception handling in more detail. Rev. 7.00 Jan 31, 2006 page 90 of 658 REJ09B0272-0700 Section 6 User Break Controller (UBC) BARH/BARL BAMRH/BAMRL 32 32 Internal address bits 31-0 32 32 32 CD1 CD0 ID1 ID0 CPU cycle DMA cycle Instruction fetch User break interrupt Data access RW1 RW0 SZ1 SZ0 Read cycle Write cycle Byte size Word size Longword size Figure 6.2 Break Condition Logic Rev. 7.00 Jan 31, 2006 page 91 of 658 REJ09B0272-0700 Section 6 User Break Controller (UBC) 6.3.2 Break on Instruction Fetch Cycles to On-Chip Memory On-chip memory (on-chip ROM (SH7034 only) and RAM) is always accessed 32 bits each bus cycle. Two instructions are therefore fetched in a bus cycle from on-chip memory . Although only a single bus cycle occurs for the two-instruction fetch, a break can be set on either instruction by placing the corresponding address in the break address registers (BAR). In other words, to break the second of the two instructions fetched, set its start address in the BAR. The break will then occur after the first instruction executes. 6.3.3 Program Counter (PC) Value Saved in User Break Interrupt Exception Processing Break on Instruction Fetch: The program counter (PC) value saved in user break interrupt exception processing for an instruction fetch is the address set as the break condition. The user break interrupt is generated before the fetched instruction is executed. If a break condition is set on the fetch cycle of a delayed slot instruction immediately following a delayed branch instruction or on the fetch cycle of an instruction that follows an interrupt-disabling instruction, however, the user break interrupt is not accepted immediately, so the instruction is executed. The user break interrupt is not accepted until immediately after that instruction. The PC value that will be saved is the start address of the next instruction that is able to accept the interrupt. Break on Data Access (CPU/DMAC): The program counter (PC) value is the top address of the next instruction after the last executed instruction at the time when the user break exception processing is activated. When data access (CPU/DMAC) is set as a break condition, the place where the break will occur cannot be specified exactly. The break will occur at the instruction fetched close to where the data access that is to receive the break occurs. Rev. 7.00 Jan 31, 2006 page 92 of 658 REJ09B0272-0700 Section 6 User Break Controller (UBC) 6.4 Setting User Break Conditions CPU Instruction Fetch Bus Cycle: * Register settings: BARH = H'0000, BARL = H'0404, BBR = H'0054 Conditions set: Address = H'00000404, bus cycle = CPU, instruction fetch, read (operand size not included in conditions) A user break interrupt will occur immediately before the instruction at address H'00000404. If the instruction at address H'00000402 can accept an interrupt, the user break exception handling will be executed after that instruction is executed. The instruction at H'00000404 will not be executed. The value saved to the PC is H'00000404. * Register settings: BARH = H'0015, BARL = H'389C, BBR = H'0058 Conditions set: Address = H'0015389C, bus cycle = CPU, instruction fetch, write (operand size not included in conditions) No user break interrupt occurs, because no instruction fetch cycle is ever a write cycle. * Register settings: BARH = H'0003, BARL = H'0147, BBR = H'0054 Conditions set: Address = H'00030147, bus cycle = CPU, instruction fetch, read (operand size not included in conditions) No user break interrupt occurs, because instructions are always fetched from even addresses. If the first fetched address after a branch is odd and a user break is set on this address, however, user break exception handling will be carried out after address error exception handling. CPU Data Access Bus Cycle: * Register settings: BARH = H'0012, BARL = H'3456, BBR = H'006A Conditions set: Address = H'00123456, bus cycle = CPU, data access, write, word A user break interrupt occurs when word data is written to address H'00123456. * Register settings: BARH = H'00A8, BARL = H'0391, BBR = H'0066 Conditions set: Address = H'00A80391, bus cycle = CPU, data access, read, word No user break interrupt occurs, because word data access is always to an even address. DMA Cycle: * Register setting: BARH = H'0076, BARL = H'BCDC, BBR = H'00A7 Conditions set: Address = H'0076BCDC, bus cycle = DMA, data access, read, longword A user break interrupt occurs when longword data is read from address H'0076BCDC. * Register setting: BARH = H'0023, BARL = H'45C8, BBR = H'0094 Conditions set: Address = H'002345C8, bus cycle = DMA, instruction fetch, read (operand size not included) No user break interrupt occurs, because a DMA cycle includes no instruction fetch. Rev. 7.00 Jan 31, 2006 page 93 of 658 REJ09B0272-0700 Section 6 User Break Controller (UBC) 6.5 Notes 6.5.1 On-Chip Memory Instruction Fetch Two instructions are simultaneously fetched from on-chip memory. If a break condition is set on the second of these two instructions but the contents of the UBC break condition registers are changed so as to alter the break condition immediately after the first of the two instructions is fetched, a user break interrupt will still occur when the second instruction is fetched. 6.5.2 Instruction Fetch at Branches When a conditional branch instruction or TRAPA instruction causes a branch, instructions are fetched and executed as follows: 1. Conditional branch instruction, branch taken: BT, BF Instruction fetch cycles: Conditional branch fetch Next-instruction overrun fetch Nextbut-one-instruction overrun fetch Branch destination fetch Instruction execution: Conditional branch instruction execution Branch destination instruction execution 2. TRAPA instruction, branch taken: TRAPA Instruction fetch cycles: TRAPA instruction fetch Next-instruction overrun fetch Nextbut-one-instruction overrun fetch Branch destination fetch Instruction execution: TRAPA instruction execution Branch destination instruction execution When a conditional branch instruction or TRAPA instruction causes a branch, the branch destination will be fetched after the next instruction or the one after that does an overrun fetch. When the next instruction or the one after that is set as a break condition, a branch will result in the generation of a user break interrupt at the next instruction or the instruction after that, neither of which instructions will be executed. Rev. 7.00 Jan 31, 2006 page 94 of 658 REJ09B0272-0700 Section 6 User Break Controller (UBC) 6.5.3 Instruction Fetch Break If a break is attempted at the task A return destination instruction fetch, task B is activated before the UBC interrupt by interrupt B generated during task A processing, and the UBC interrupt is handled after the interrupt B exception handling. 1. Cause The SH7032/SH7034 chip operates as follows. Interrupt B accepted UBC interrupt accepted Interrupt exception handling F D E E M M E M E E Interrupt exception handling F <Address> <Description> F D E 0x00011a0a Instruction replaced by interrupt exception handling Break condition E M M E M E E f 0x00011a0c Overrun fetch 0xf000974 Task B first instruction fetch (instruction replaced by interrupt exception handling) F (0xf000978 Overrun fetch) 0x02000030 UBC first instruction fetch Figure 6.3 UBC Operation It actually takes at least two cycles for the UBC interrupt generated by the address 0x00011a0c instruction fetch cycle to be sent to the interrupt controller and interrupt exception handling to begin. However, as shown in figure 6.3, when the UBC interrupt is generated, previously generated interrupt B initiated by task B is accepted first, and the UBC interrupt is accepted after completion of the interrupt B exception handling. 2. Remedy There is no way of preventing this operation by hardware. A software solution, such as the use of a flag, must be employed. Rev. 7.00 Jan 31, 2006 page 95 of 658 REJ09B0272-0700 Section 6 User Break Controller (UBC) Rev. 7.00 Jan 31, 2006 page 96 of 658 REJ09B0272-0700 Section 7 Clock Pulse Generator (CPG) Section 7 Clock Pulse Generator (CPG) 7.1 Overview The SuperH microcomputer has a built-in clock pulse generator (CPG) that supplies the chip and external devices with a clock pulse. The CPG makes the chip run at the oscillation frequency of the crystal resonator. The CPG consists of an oscillator and a duty cycle correction circuit (figure 7.1). The CPG can be made to generate a clock signal by connecting it to a crystal resonator or by inputting an external clock. (The CPG is halted in standby mode.) CPG XTAL Oscillator Duty cycle correction circuit EXTAL Internal clock () CK System clock Figure 7.1 Block Diagram of Clock Pulse Generator 7.2 Clock Source Clock pulses can be supplied from a connected crystal resonator or an external clock. 7.2.1 Connecting a Crystal Resonator Circuit Configuration: A crystal resonator can be connected as shown in figure 7.2. Use the damping resistance Rd shown in table 7.1. Use an AT-cut parallel resonating crystal with a frequency equal to the system clock (CK) frequency. Connect load capacitors (CL1 and C L2) as shown in the figure. The clock pulse produced by the crystal resonator and internal pulse generator is sent to the duty cycle correction circuit where its duty cycle is corrected. It is then supplied to the chip and to external devices. Rev. 7.00 Jan 31, 2006 page 97 of 658 REJ09B0272-0700 Section 7 Clock Pulse Generator (CPG) CL1 EXTAL CL1 = CL2 =10-22 pF Rd CL2 XTAL Figure 7.2 Connection of Crystal Resonator (Example) Table 7.1 Damping Resistance Frequency [MHz] 2 4 8 12 16 20 Rd [] 1k 500 200 0 0 0 Crystal Resonator: Figure 7.3 shows an equivalent circuit of the crystal resonator. Use a crystal resonator with the characteristics listed in table 7.2. CL L Rs XTAL EXTAL C0 Figure 7.3 Crystal Resonator Equivalent Circuit Table 7.2 Crystal Resonator Parameters Frequency (MHz) Parameter 2 4 8 12 16 20 Rs max [] 500 120 80 60 50 40 Co max [pF] 7 7 7 7 7 7 Rev. 7.00 Jan 31, 2006 page 98 of 658 REJ09B0272-0700 Section 7 Clock Pulse Generator (CPG) 7.2.2 External Clock Input An external clock signal can be input at the EXTAL pin as shown in figure 7.4. The XTAL pin should be left open. The frequency must be equal to the system clock (CK) frequency. The specifications for the waveform of the external clock input are given below. Make the external clock frequency the same as the system clock (CK). Open XTAL External clock input EXTAL Figure 7.4 External Clock Input Method tcyc tEXH 1/2 Vcc tEXL VIH VIL tEXr tEXf Figure 7.5 Input Clock Waveform Table 7.3 Input Clock Specifications 5 V Specifications 1 (fmax = 20 MHz)* 3.3 V Specifications 3.3 V Specifications 2 (fmax = 12.5 MHz) (fmax = 20 MHz)* Unit tEXr/f (VIL-VIH) Max = 5 Max = 10 Max = 5 ns tEXH/L Min = 10 Min = 20 Min = 15 ns Notes: 1. Except SH7034B 2. SH7034B only Rev. 7.00 Jan 31, 2006 page 99 of 658 REJ09B0272-0700 Section 7 Clock Pulse Generator (CPG) 7.3 Usage Notes Board Design: When designing the board, place the crystal resonator and its load capacitors as close as possible to the XTAL and EXTAL pins. Route no other signal lines near the XTAL and EXTAL pin signal lines to prevent induction from interfering with correct oscillation. See figure 7.6. No crossing signal lines CL1 CL2 XTAL EXTAL Figure 7.6 Precaution on Oscillator Circuit Board Design Duty Cycle Correction Circuit: Duty cycle corrections are conducted for an input clock over 5 MHz. Duty cycles may not be corrected for a clock of under 5 MHz, but AC characteristics for the high-level pulse width (tCH) and low-level pulse width (tCL) of the clock are satisfied, and the chip will operate normally. Figure 7.7 shows the standard characteristics of duty cycle correction. This duty cycle correction circuit is not for correcting transient fluctuations and jitter in the input clock. Thus, it takes several tens of microseconds to obtain a stable clock after duty cycle correction is performed. Rev. 7.00 Jan 31, 2006 page 100 of 658 REJ09B0272-0700 Section 7 Clock Pulse Generator (CPG) Output duty 70 60 Input duty* 70 60 50 40 30 50 40 30 1 2 5 Input frequency 10 20 (MHz) Note: * With the SH7034B, compensation is performed in the input duty range of 60% to 40%. Figure 7.7 Duty Cycle Correction Circuit Standard Characteristics Rev. 7.00 Jan 31, 2006 page 101 of 658 REJ09B0272-0700 Section 7 Clock Pulse Generator (CPG) Rev. 7.00 Jan 31, 2006 page 102 of 658 REJ09B0272-0700 Section 8 Bus State Controller (BSC) Section 8 Bus State Controller (BSC) 8.1 Overview The bus state controller (BSC) divides address space and outputs control signals for all kinds of memory and peripheral chips. BSC functions enable the chip to be connected directly to DRAM, SRAM, ROM, and peripheral chips without the use of external circuits, simplifying system design and allowing high-speed data transfer in a compact system. 8.1.1 Features The BSC has the following features: * Address space is divided into eight areas A maximum 4-Mbyte linear address space for each of eight areas, 0-7 (area 1 can be up to 16-Mbyte linear space when set for DRAM). (The space that can actually be used varies with the type of memory connected.) Bus width (8 bits or 16 bits) can be selected by access address On-chip ROM and RAM is accessed in one cycle (32 bits wide) Wait states can be inserted using the WAIT pin Wait state insertion can be controlled by software. Register settings can be used to specify the insertion of 1-4 cycles for areas 0, 2, and 6 (long wait function) The type of memory connected can be specified for each area Outputs control signals for accessing the memory and peripheral chips connected to the area * Direct interface to DRAM Multiplexes row/column addresses according to DRAM capacity Two types of byte access signals (dual-CAS system and dual-WE system) Supports burst operation (high-speed page mode) Supports CAS-before-RAS refresh and self-refresh * Access control for all memory and peripheral chips Address/data multiplex function * Parallel execution of external writes etc. with internal access (warp mode) * Supports parity check and generation for data bus Odd parity/even parity selectable Interrupt request generated for parity error (PEI interrupt request signal) Rev. 7.00 Jan 31, 2006 page 103 of 658 REJ09B0272-0700 Section 8 Bus State Controller (BSC) * Refresh counter can be used as an interval timer Interrupt request generated at compare match (CMI interrupt request signal) 8.1.2 Block Diagram Bus interface WCR1 Wait control unit WAIT WCR2 WCR3 RD WRH, WRL BCR DCR RCR CASH, CASL DRAM control unit RAS Module bus Area control unit HBS, LBS AH CS7 to CS0 RTCSR CMI interrupt request RTCNT Comparator DPH, DPL Interrupt controller Peripheral bus PEI interrupt request Parity control unit RTCOR PCR BSC WCR: Wait state control register BCR: Bus control register DCR: DRAM area control register RCR: Refresh control register RTCSR: Refresh timer control/status register RTCNT: Refresh timer counter RTCOR: Refresh time constant register PCR: Parity control register Figure 8.1 Block Diagram of BSC Rev. 7.00 Jan 31, 2006 page 104 of 658 REJ09B0272-0700 Internal bus Figure 8.1 shows a block diagram of the bus state controller. Section 8 Bus State Controller (BSC) 8.1.3 Pin Configuration Table 8.1 shows the BSC pin configuration. Table 8.1 Pin Configuration Name Abbreviation I/O Function Chip select 7-0 CS7-CS0 O Chip select signal that indicates the area being accessed Read RD O Strobe signal that indicates the read cycle High write WRH O Strobe signal that indicates write cycle to upper 8 bits Low write WRL O Strobe signal that indicates write cycle to lower 8 bits Write WR* O Strobe signal that indicates write cycle High byte strobe 2 HBS* O Strobe signal that indicates access to upper 8 bits Low byte strobe LBS* 3 O Strobe signal that indicates access to lower 8 bits O DRAM row address strobe signal 1 Row address strobe RAS High column address strobe CASH O Column address strobe signal for accessing the upper 8 bits of the DRAM Low column address strobe CASL O Column address strobe signal for accessing the lower 8 bits of the DRAM Address hold AH O Signal for holding the address for address/data multiplexing Wait WAIT I Wait state request signal Address bus A21-A0 O Address output Data bus AD15-AD0 I/O Data I/O. During address/data multiplexing, address output and data input/output Data bus parity high DPH I/O Parity data I/O for upper byte Data bus parity low I/O Parity data I/O for lower byte DPL Notes: 1. Doubles with the WRL pin. (Selected by the BAS bit in BCR. See section 8.2.1, Bus Control Register (BCR), for details.) 2. Doubles with the A0 pin. (Selected by the BAS bit in BCR. See section 8.2.1, Bus Control Register (BCR), for details.) 3. Doubles with the WRH pin. (Selected by the BAS bit in BCR. See section 8.2.1, Bus Control Register (BCR), for details.) Rev. 7.00 Jan 31, 2006 page 105 of 658 REJ09B0272-0700 Section 8 Bus State Controller (BSC) 8.1.4 Register Configuration The BSC has ten registers (listed in table 8.2) which control space division, wait states, DRAM interface, and parity check. Table 8.2 Register Configuration 1 Name Abbr. R/W Initial Value Address* Bus control register BCR R/W H'0000 H'5FFFFA0 8,16,32 Wait state control register 1 WCR1 R/W H'FFFF H'5FFFFA2 8,16,32 Wait state control register 2 WCR2 R/W H'FFFF H'5FFFFA4 8,16,32 Wait state control register 3 WCR3 R/W H'F800 H'5FFFFA6 8,16,32 DRAM area control register DCR R/W H'0000 H'5FFFFA8 8,16,32 Parity control register PCR R/W H'0000 H'5FFFFAA 8,16,32 Refresh control register RCR R/W H'0000 H'5FFFFAC 8,16,32* Refresh timer control/status register RTCSR R/W H'0000 H'5FFFFAE 8,16,32* Refresh timer counter RTCNT R/W H'0000 H'5FFFFB0 8,16,32* Refresh time constant register RTCOR R/W H'00FF H'5FFFFB2 8,16,32* Bus width 2 2 2 2 Notes: 1. Only the values of bits A27-A24 and A8-A0 are valid; bits A23-A9 are ignored. For details on the register addresses, see section 8.3.5, Area Descriptions. 2. Write only with word transfer instructions. See section 8.2.11, Notes on Register Access, for details on writing. Rev. 7.00 Jan 31, 2006 page 106 of 658 REJ09B0272-0700 Section 8 Bus State Controller (BSC) 8.1.5 Overview of Areas The SH microprocessors have a 32-bit address space in the architecture, but the upper 4 bits are ignored. Table 8.3 outlines the space divisions. As shown, the space is divided into areas 0-7 according to the value of the upper addresses. Each area is allocated a specific type of space. When the area is accessed, a strobe signal that matches the type of area space is generated. This allocates peripheral chips and memory devices according to the type of the area spaces and allows them to be directly linked to this chip. Some areas are of a fixed type based on their address while others can be selected in registers. Area 0 can be used as an on-chip ROM space or external memory space in the SH7034. In the SH7032, it can only be used as external memory space. Area 1 can be used as DRAM space or external memory space. DRAM space enables direct connection to DRAM and outputs RAS, CAS and multiplexed addresses. Areas 2-4 can only be used as external memory space. Area 5 can be used as on-chip supporting module space or external memory space. Area 6 can be used as address/data multiplexed I/O space or external memory space. For address/data multiplexed I/O space, an address and data are multiplexed and input/output from pins AD15-AD0. Area 7 can be used as on-chip RAM space or external memory space. The bus width of the data bus is basically switched between 8 bits and 16 bits according to the value of address bit A27. For the following areas, however, the bus width is determined by conditions other than the A27 bit value. * On-chip ROM space in area 0: Always 32 bits * External memory space in area 0: 8 bits when MD0 pin is 0, 16 bits when the pin is 1 * On-chip supporting module space in area 5: 8 bits when the A8 address bit is 0, 16 bits when it is 1 * Area 6: If A27 = 0, area 6 is 8 bits when the A14 address bit is 0, 16 bits when A14 is 1 * On-chip RAM space in area 7: Always 32 bits See table 8.6 in section 8.3, Address Space Subdivision, for more information on how the space is divided. Rev. 7.00 Jan 31, 2006 page 107 of 658 REJ09B0272-0700 Section 8 Bus State Controller (BSC) Table 8.3 Area 0 Overview of Space Divisions Address H'0000000-H'0FFFFFF Assignable Memory 1 On-chip ROM* H'1000000-H'1FFFFFF CS Output -- 64 kB 32 External memory* 4 MB 8/16* CS0 External memory 4 DRAM* 4 MB 8 CS1 16 MB 8 RAS CAS 2 1 Capacity Bus (Linear Space) Width 3 2 H'2000000-H'2FFFFFF External memory 4 MB 8 CS2 3 H'3000000-H'3FFFFFF External memory 4 MB 8 CS3 4 H'4000000-H'4FFFFFF External memory 4 MB 8 CS4 On-chip supporting modules 7 External memory* 512 B 5 8/16* -- 4 MB 8/16* CS6 Multiplexed I/O 4 MB H'7000000-H'7FFFFFF External memory 4 MB 8 CS7 H'8000000-H'8FFFFFF 1 On-chip ROM* 5 H'5000000-H'5FFFFFF 6 H'6000000-H'6FFFFFF 7 0 64 kB 32 External memory* 4 MB 8/16* CS0 External memory 4 DRAM* 4 MB 16 CS1 16 MB 16 RAS CAS 2 1 H'9000000-H'9FFFFFF 6 -- 3 2 H'A000000-H'AFFFFFF External memory 4 MB 16 CS2 3 H'B000000-H'BFFFFFF External memory 4 MB 16 CS3 4 H'C000000-H'CFFFFFF External memory 4 MB 16 CS4 5 H'D000000-H'DFFFFFF External memory 4 MB 16 CS5 6 H'E000000-H'EFFFFFF External memory 16 CS6 7 H'F000000-H'FFFFFFF On-chip RAM 4 MB 8 9 8 kB* , 4 kB* 32 -- Notes: 1. 2. 3. 4. 5. 6. 7. 8. 9. When MD2-MD0 pins are 010 (SH7034) When MD2-MD0 pins are 000 or 001 Select with MD0 pin Select with DRAME bit in BCR Divided into 8-bit and 16-bit space according to value of address bit A8. (Longword accesses are inhibited, however, for on-chip supporting modules with bus widths of 8 bits. Some on-chip supporting modules with bus widths of 16 bits also have registers that are only byte-accessible and registers for which byte access is inhibited. For details, see the sections on the individual modules.) Divided into 8-bit space and 16-bit space by value of address bit A14 Select with IOE bit in BCR For SH7032 For SH7034 Rev. 7.00 Jan 31, 2006 page 108 of 658 REJ09B0272-0700 Section 8 Bus State Controller (BSC) 8.2 Register Descriptions 8.2.1 Bus Control Register (BCR) The bus control register (BCR) is a 16-bit read/write register that selects the functions of areas and status of bus cycles. It is initialized to H'0000 by a power-on reset, but is not initialized by a manual reset or in standby mode. Bit 15 14 13 12 11 10 9 8 DRAME IOE WARP RDDTY BAS -- -- -- Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W -- -- -- 7 6 5 4 3 2 1 0 -- -- -- -- -- -- -- -- Initial value 0 0 0 0 0 0 0 0 Read/Write -- -- -- -- -- -- -- -- Bit Bit 15--DRAM Enable Bit (DRAME): DRAME selects whether area 1 is used as an external memory space or DRAM space. 0 sets it as external memory space and 1 sets it as DRAM space. The setting of the DRAM area control register is valid only when this bit is set to 1. Bit 15: DRAME Description 0 Area 1 is external memory space 1 Area 1 is DRAM space (Initial value) Bit 14--Multiplexed I/O Enable Bit (IOE): IOE selects whether area 6 is used as external memory space or an address/data multiplexed I/O area. 0 sets it as external memory space and 1 sets it as address/data multiplexed I/O space. With address/data multiplexed I/O space, the address and data are multiplexed and input/output is from AD15-AD0. Bit 14: IOE Description 0 Area 6 is external memory space 1 Area 6 is an address/data multiplexed I/O area (Initial value) Rev. 7.00 Jan 31, 2006 page 109 of 658 REJ09B0272-0700 Section 8 Bus State Controller (BSC) Bit 13--Warp Mode Bit (WARP): WARP selects warp or normal mode. 0 sets normal mode and 1 sets warp mode. In warp mode, some external accesses are carried out in parallel with internal access. Bit 13: WARP Description 0 Normal mode: External and internal accesses are not performed simultaneously (Initial value) 1 Warp mode: External and internal accesses are performed simultaneously Bit 12--RD Duty (RDDTY): RDDTY selects 35% or 50% of the T1 state as the high-level duty cycle ratio of signal RD. 0 sets 50%, 1 sets 35%. Bit 12: RDDTY Description 0 RD signal high-level duty cycle is 50% of T1 state 1 RD signal high-level duty cycle is 35% of T1 state (Initial value) Bit 11--Byte Access Select (BAS): BAS selects whether byte access control signals are WRH, WRL, and A0, or LBS, WR and HBS during word space accesses. When this bit is cleared to 0, WRH, WRL, and A0 signals are valid; when set to 1, LBS, WR, and HBS signals are valid. Bit 11: BAS Description 0 WRH, WRL, and A0 enabled 1 LBS, WR, and HBS enabled (Initial value) Bits 10-0--Reserved: These bits are always read as 0. The write value should always be 0. Rev. 7.00 Jan 31, 2006 page 110 of 658 REJ09B0272-0700 Section 8 Bus State Controller (BSC) 8.2.2 Wait State Control Register 1 (WCR1) Wait state control register 1 is a 16-bit read/write register that controls the number of states for accessing each area and whether wait states are used. WCR1 is initialized to H'FFFF by a poweron reset. It is not initialized by a manual reset or in standby mode. Bit 15 14 13 12 11 10 9 8 RW7 RW6 RW5 RW4 RW3 RW2 RW1 RW0 Initial value 1 1 1 1 1 1 1 1 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 -- -- -- -- -- -- WW1 -- Initial value 1 1 1 1 1 1 1 1 Read/Write -- -- -- -- -- -- R/W -- Bit Bits 15-8--Wait State Control During Read (RW7-RW0): RW7-RW0 determine the number of states in read cycles for each area and whether or not to sample the signal input from the WAIT pin. Bits RW7-RW0 correspond to areas 7-0, respectively. If a bit is cleared to 0, the WAIT signal is not sampled during the read cycle for the corresponding area. If it is set to 1, sampling takes place. For the external memory spaces of areas 1, 3-5, and 7, read cycles are completed in one state when the corresponding bits are cleared to 0. When they are set to 1, the number of wait states is 2 plus the WAIT signal value. For the external memory space of areas 0, 2, and 6, read cycles are completed in one state plus the number of long wait states (set in wait state controller 3 (WCR3)) when the corresponding bits are cleared to 0. When they are set to 1, the number of wait states is 1 plus the long wait state; when the WAIT signal is low as well, a wait state is inserted. The DRAM space (area 1) finishes the column address output cycle in one state (short pitch) when the RW1 bit is 0, and in 2 states plus the WAIT signal value (long pitch) when RW1 is 1. When RW1 is set to 1, the number of wait states selected in wait state insertion bits 1 and 0 (RLW0 and RLW1) for CAS-before-RAS (CBR) refresh in the refresh control register (RCR) are inserted during the CBR refresh cycle, regardless of the status of the WAIT signal. The read cycle of the address/data multiplexed I/O space (area 6) is 4 states plus the wait states from the WAIT signal, regardless of the setting of the RW6 bit. The read cycle of the on-chip supporting module space (area 5) finishes in 3 states, regardless of the setting of the RW5 bit, and the WAIT signal is not sampled. The read cycles of on-chip ROM (area 0) and on-chip RAM (area Rev. 7.00 Jan 31, 2006 page 111 of 658 REJ09B0272-0700 Section 8 Bus State Controller (BSC) 7) finish in 1 state, regardless of the settings of bits RW0 and RW7. The WAIT signal is not sampled for either. Table 8.4 summarizes read cycle state information. Table 8.4 Read Cycle States Read Cycle States External Memory Space WAIT Pin Bits 15-8: Input RW7-RW0 Signal External Memory Space 0 Not sampled during read 1 cycle* Areas 1, 3-5,7: 1 state, fixed 1 Sampled during read cycle (Initial value) Areas 1, 3-5, 7: 2 states + wait states from WAIT Internal Space Multiplexed DRAM Space I/O Column address cycle: 1 Areas 0, 2, 6: 1 state state, fixed (short pitch) + long wait state 4 states + wait states from WAIT On-Chip On-Chip Supporting ROM and Modules RAM 3 states, fixed 1 state, fixed Column address cycle: 2 states + wait Areas 0, 2, 6: 1 state state from WAIT (long + long wait state + *2 wait state from WAIT pitch) Notes: 1. Sampled in the address/data multiplexed I/O space 2. During a CBR refresh, the WAIT signal is ignored and the wait state from the RLW1 and RLW0 bits in RCR is inserted. Bits 7-2--Reserved: These bits are always read as 1. The write value should always be 1. Bit 1--Wait State Control During Write (WW1): WW1 determines the number of states in write cycles for the DRAM space (area 1) and whether or not to sample the WAIT signal. When the DRAM enable bit (DRAME) in BCR is set to 1 and area 1 is being used as DRAM space, clearing WW1 to 0 makes the column address output cycle finish in 1 state (short pitch). When WW1 is set to 1, it finishes in 2 states plus the wait states from the WAIT signal (long pitch). Note: Write 0 to WW1 only when area 1 is used as DRAM space (DRAME bit in BCR is 1). Never write 0 to WW1 when area 1 is used as external memory space (DRAME is 0). Bit 1: WW1 DRAM Space (DRAME = 1) Area 1 External Memory Space (DRAME = 0) 0 Column address cycle: 1 state (short pitch) Setting inhibited 1 Column address cycle: 2 states + wait state from WAIT (long pitch) (Initial value) 2 states + wait state from WAIT Rev. 7.00 Jan 31, 2006 page 112 of 658 REJ09B0272-0700 Section 8 Bus State Controller (BSC) Bit 0--Reserved: This bit is always read as 1. The write value should always be 1. 8.2.3 Wait State Control Register 2 (WCR2) Wait state control register 2 is a 16-bit read/write register that controls the number of states for accessing each area with a DMA single address mode transfer and whether wait states are used. WCR2 is initialized to H'FFFF by a power-on reset. It is not initialized by a manual reset or in standby mode. Bit 15 14 13 12 11 10 9 8 DRW7 DRW6 DRW5 DRW4 DRW3 DRW2 DRW1 DRW0 Initial value 1 1 1 1 1 1 1 1 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 DWW7 DWW6 DWW5 DWW4 DWW3 DWW2 DWW1 DWW0 Bit Initial value 1 1 1 1 1 1 1 1 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Bits 15-8--Wait State Control During Single-Mode DMA Transfer (DRW7-DRW0): DRW7-DRW0 determine the number of states in single-mode DMA memory read cycles for each area and whether or not to sample the WAIT signal. Bits DRW7-DRW0 correspond to areas 7-0, respectively. If a bit is cleared to 0, the WAIT signal is not sampled during the single-mode DMA memory read cycle for the corresponding area. If it is set to 1, sampling takes place. For the external memory spaces of areas 1, 3-5, and 7, single-mode DMA memory read cycles are completed in one state when the corresponding bits are cleared to 0. When they are set to 1, the number of wait states is 2 plus the wait states from the WAIT signal. For the external memory space of areas 0, 2, and 6, single-mode DMA memory read cycles are completed in one state plus the long wait state number (set in wait state controller 3 (WCR3)) when the corresponding bits are cleared to 0. When they are set to 1, the number of wait states is 1 plus the long wait state; when the WAIT signal is low as well, a wait state is inserted. The DRAM space (area 1) finishes the column address output cycle in one state (short pitch) when the DRW1 bit is 0, and in 2 states plus the wait states from the WAIT signal (long pitch) when DRW1 is 1. The single-mode DMA memory read cycle of the address/data multiplexed I/O space (area 6) is 4 states plus the wait states from the WAIT signal, regardless of the setting of the DRW6 bit. Rev. 7.00 Jan 31, 2006 page 113 of 658 REJ09B0272-0700 Section 8 Bus State Controller (BSC) Table 8.5 Single-Mode DMA Memory Read Cycle States (External Memory Space) Single-Mode DMA Memory Read Cycle States (External Memory Space) Bits 15-8: WAIT Pin Input DRW7-DRW0 Signal External Memory Space DRAM Space Multiplexed I/O 0 Not sampled during Areas 1, 3-5,7: 1 state, fixed Column address 4 states + single-mode DMA cycle: 1 state, wait states Areas 0, 2, 6: 1 state + memory read cycle* long wait state fixed (short pitch) from WAIT 1 Sampled during single-mode DMA memory read cycle (Initial value) Areas 1, 3-5, 7: 2 states + wait states from WAIT Areas 0, 2, 6: 1 state + long wait state + wait state from WAIT Column address cycle: 2 states + wait state from WAIT (long pitch) Note: * Sampled in the address/data multiplexed I/O space. Bits 7-0--Single-Mode DMA Memory Write Wait State Control (DWW7-DWW0): DWW7- DWW0 determine the number of states in single-mode DMA memory write cycles for each area and whether or not to sample the WAIT signal. Bits DWW7-DWW0 correspond to areas 7-0, respectively. If a bit is cleared to 0, the WAIT signal is not sampled during the single-mode DMA memory write cycle for the corresponding area. If it is set to 1, sampling takes place. The number of states for areas accesses based on bit settings is the same as indicated for singlemode DMA memory read cycles. See bits 15-8, Wait State Control During Single-Mode DMA Memory Transfer (DRW7-DRW0), for details. Table 8.6 summarizes single-mode DMA memory write cycle state information. Rev. 7.00 Jan 31, 2006 page 114 of 658 REJ09B0272-0700 Section 8 Bus State Controller (BSC) Table 8.6 Single-Mode DMA Memory Write Cycle States (External Memory Space) Single-Mode DMA Memory Write Cycle States (External Memory Space) Bits 15-8: WAIT Pin Input DWW7-DWW0 Signal External Memory Space Multiplexed I/O DRAM Space 0 Not sampled Areas 1, 3-5,7: 1 state, fixed during single-mode Areas 0, 2, 6: 1 state + long DMA memory write wait state cycle* Column address 4 states + cycle: 1 state, wait state fixed (short from WAIT pitch) 1 Sampled during single-mode DMA memory write cycle (Initial value) Column address cycle: 2 states + wait state from WAIT (long pitch) Areas 1, 3-5, 7: 2 states + wait state from WAIT Areas 0, 2, 6: 1 state + long wait state + wait state from WAIT Note: * Sampled in the address/data multiplexed I/O space. 8.2.4 Wait State Control Register 3 (WCR3) Wait state control register 3 is a 16-bit read/write register that controls WAIT pin pull-up and the insertion of long wait states. WCR3 is initialized to H'F800 by a power-on reset. It is not initialized by a manual reset or in standby mode. Bit 15 WPU 14 13 12 A02LW1 A02LW0 A6LW1 11 10 9 8 A6LW0 -- -- -- Initial value 1 1 1 1 1 0 0 0 Read/Write R/W R/W R/W R/W R/W -- -- -- Bit 7 6 5 4 3 2 1 0 -- -- -- -- -- -- -- -- Initial value 0 0 0 0 0 0 0 0 Read/Write -- -- -- -- -- -- -- -- Bit 15--Wait Pin Pull-Up Control (WPU): WPU controls whether the WAIT pin is pulled up or not. When cleared to 0, the pin is not pulled up; when set to 1, it is pulled up. Bit 15: WPU Description 0 WAIT pin is not pulled up 1 WAIT pin is pulled up (Initial value) Rev. 7.00 Jan 31, 2006 page 115 of 658 REJ09B0272-0700 Section 8 Bus State Controller (BSC) Bits 14 and 13--Long Wait Insertion in Areas 0 and 2, Bits 1, 0 (A02LW1 and A02LW0): A02LW1 and A02LW0 select the long wait states to be inserted (1-4 states) when accessing external memory space of areas 0 and 2. Bit 14: A02LW1 Bit 13: A02LW0 Description 0 0 1 state inserted 1 2 states inserted 0 3 states inserted 1 4 states inserted 1 (Initial value) Bits 12 and 11--Long Wait Insertion in Area 6, Bits 1, 0 (A6LW1 and A6LW0): A6LW1 and A6LW0 select the long wait states to be inserted (1-4 states) when accessing external memory space of area 6. Bit 12: A6LW1 Bit 11: A6LW0 Description 0 0 1 state inserted 1 2 states inserted 0 3 states inserted 1 4 states inserted 1 (Initial value) Bits 10-0--Reserved: These bits are always read as 0. The write value should always be 0. Rev. 7.00 Jan 31, 2006 page 116 of 658 REJ09B0272-0700 Section 8 Bus State Controller (BSC) 8.2.5 DRAM Area Control Register (DCR) The DRAM area control register (DCR) is a 16-bit read/write register that selects the type of DRAM control signal, the number of precharge cycles, the burst operation mode, and the use of address multiplexing. DCR settings are valid only when the DRAME bit in BCR is set to 1. It is initialized to H'0000 by a power-on reset, but is not initialized by a manual reset or in standby mode. Bit 15 14 13 12 11 10 9 8 CW2 RASD TPC BE CDTY MXE MXC1 MXC0 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 -- -- -- -- -- -- -- -- Initial value 0 0 0 0 0 0 0 0 Read/Write -- -- -- -- -- -- -- -- Bit Bit 15--Dual-CAS or Dual-WE Select Bit (CW2): When accessing a 16-bit bus width space, CW2 selects the dual-CAS or the dual-WE method. When cleared to 0, the CASH, CASL, and WRL signals are valid ; when set to 1, the CASL, WRH, and WRL signals are valid. When accessing an 8-bit space, only CASL and WRL signals are valid, regardless of the CW2 setting. Bit 15L: CW2 Description 0 Dual-CAS: CASH, CASL, and WRL signals are valid 1 Dual-WE: CASL, WRH, and WRL signals are valid (Initial value) Bit 14--RAS Down (RASD): When DRAM access pauses, RASD determines whether to keep RAS low while waiting for the next DRAM access (RAS down mode) or return it to high (RAS up mode). When cleared to 0, the RAS signal returns to high; when set to 1, it stays low. Bit 14: RASD Description 0 RAS up mode: Return RAS signal to high and wait for the next DRAM access (Initial value) 1 RAS down mode: Keep RAS signal low and wait for the next DRAM access Rev. 7.00 Jan 31, 2006 page 117 of 658 REJ09B0272-0700 Section 8 Bus State Controller (BSC) Bit 13--RAS Precharge Cycle Count (TPC): TPC selects whether the RAS signal precharge cycle (TP) will be 1 state or 2. When TPC is cleared to 0, a 1-state precharge cycle is inserted; when 1 is set, a 2-state precharge cycle is inserted. Bit 13: TPC Description 0 1-state precharge cycle inserted 1 2-state precharge cycle inserted (Initial value) Bit 12--Burst Operation Enable (BE): BE selects whether or not to perform burst operation, a high-speed page mode. When burst operation is not selected (0), the row address is not compared but instead is transferred to the DRAM every time and full access is performed. When burst operation is selected (1), row addresses are compared and burst operation with the same row address as previously is performed (in this access, no row address is output and the column address and CAS signal alone are output) (high-speed page mode). Bit 12: BE Description 0 Normal mode: full access 1 Burst operation: high-speed page mode (Initial value) Bit 11--CAS Duty (CDTY): CDTY selects 35% or 50% of the TC state as the high-level duty ratio of the signal CAS in short-pitch access. When cleared to 0, the CAS signal high level duty is 50%; when set to 1, it is 35%. Bit 11: CDTY Description 0 CAS signal high level duty cycle is 50% of the TC state 1 CAS signal high level duty cycle is 35% of the TC state (Initial value) Bit 10--Multiplex Enable Bit (MXE): MXE determines whether or not DRAM row and column addresses are multiplexed. When cleared to 0, addresses are not multiplexed; when set to 1, they are multiplexed. Bit 10: MXE Description 0 1 Multiplexing of row and column addresses disabled Multiplexing of row and column addresses enabled Rev. 7.00 Jan 31, 2006 page 118 of 658 REJ09B0272-0700 (Initial value) Section 8 Bus State Controller (BSC) Bits 9 and 8--Multiplex Shift Count 1 and 0 (MXC1 and MXC0): Shift row addresses downward by a certain number of bits (8-10) when row and column addresses are multiplexed (MXE = 1). Regardless of the MXE bit setting, these bits also select the range of row addresses compared in burst operation. Bit 9: MXC1 Bit 8: MXC0 Row Address Shift (MXE = 1) Row Address Bits Compared (in Burst Operation) (MXE = 0 or 1) 0 0 1 0 1 8 bits 9 bits 10 bits Reserved A8-A27 A9-A27 A10-A27 Reserved 1 (Initial value) (Initial value) Bits 7-0--Reserved: These bits are always read as 0. The write value should always be 0. 8.2.6 Refresh Control Register (RCR) The refresh control register (RCR) is a 16-bit read/write register that controls the start of refreshing and selects the refresh mode and the number of wait states during refreshing. It is initialized to H'0000 by a power-on reset, but is not initialized by a manual reset or in standby mode. To prevent RCR from being written incorrectly, it must be written by a different method from most other registers. A word transfer operation is used, H'5A is written in the upper byte, and the actual data is written in the lower byte. For details, see section 8.2.11, Notes on Register Access. Bit 15 14 13 12 11 10 9 8 -- -- -- -- -- -- -- -- Initial value Read/Write 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- Bit 7 6 5 4 3 2 1 0 RLW1 RLW0 -- -- -- -- 0 R/W 0 R/W 0 -- 0 -- 0 -- 0 -- RFSHE RMODE Initial value Read/Write 0 R/W 0 R/W Bit 15-8--Reserved: These bits are always read as 0. Rev. 7.00 Jan 31, 2006 page 119 of 658 REJ09B0272-0700 Section 8 Bus State Controller (BSC) Bit 7--Refresh Control (RFSHE): RFSHE determines whether or not to perform DRAM refresh operations. When this bit is cleared to 0, no DRAM refresh control is performed and the refresh timer counter (RTCNT) can be used as an 8-bit interval timer. When set to 1, DRAM refresh control is performed. Bit 7: RFSHE Description 0 Refresh control disabled. RTCNT can be used as an 8-bit interval timer (Initial value) 1 Refresh control enabled Bit 6--Refresh Mode (RMODE): When DRAM refresh control is selected (RFSHE = 1), RMODE selects whether to perform CAS-before-RAS (CBR) refresh or self-refresh. When this bit is cleared to 0, a CBR refresh is performed at the cycle set in the refresh timer control/status register (RTCSR) and refresh time constant register (RTCOR). When set to 1, the DRAM performs a self-refresh. When refresh control is not selected (RFSHE = 0), the RMODE bit setting is not valid. When canceling self-refresh, set RMODE to 0 with RFSHE set to 1. Bit 6: RMODE Description 0 CAS-before-RAS refresh 1 Self-refresh (Initial value) Bits 5 and 4--CBR Refresh Wait State Insertion Bits 1 and 0 (RLW1, RLW0): These bits select the number of wait states to be inserted (1-4) during CAS-before-RAS refreshing. When CBR refresh is performed and the RW1 bit in WCR1 is set to 1, the number of wait states selected by RLW1 and RLW0 is inserted regardless of the WAIT signal. When the RW1 bit is cleared to 0, the RLW1 and RLW0 bit settings are ignored and no wait states are inserted. Bit 5: RLW1 Bit 4: RLW0 Description 0 0 1 state inserted 1 2 states inserted 0 3 states inserted 1 4 states inserted 1 (Initial value) Bits 3-0--Reserved: These bits are always read as 0. The write value should always be 0. Rev. 7.00 Jan 31, 2006 page 120 of 658 REJ09B0272-0700 Section 8 Bus State Controller (BSC) 8.2.7 Refresh Timer Control/Status Register (RTCSR) The refresh timer control/status register (RTCSR) is a 16-bit read/write register that selects the clock input to the refresh timer counter (RTCNT) and controls compare match interrupts (CMI). It is initialized to H'0000 by a power-on reset, but is not initialized by a manual reset or in standby mode. To prevent RTCSR from being written incorrectly, it must be written by a different method from most other registers. A word transfer operation is used, H'A5 is written in the upper byte, and the actual data is written in the lower byte. For details, see section 8.2.11, Notes on Register Access. Bit 15 14 13 12 11 10 9 8 -- -- -- -- -- -- -- -- Initial value 0 0 0 0 0 0 0 0 Read/Write -- -- -- -- -- -- -- -- Bit 7 6 5 4 3 2 1 0 CMF CMIE CKS2 CKS1 CKS0 -- -- -- Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W -- -- -- Bits 15-8--Reserved: These bits are always read as 0. Bit 7--Compare Match Flag (CMF): Indicates whether the values of RTCNT and the refresh time constant register (RTCOR) match. When 0, the value of RTCNT and RTCOR do not match; when 1, the value of RTCNT and RTCOR match. Bit 7: CMF Description 0 RTCNT value does not equal RTCOR value (Initial value) To clear CMF, the CPU must read CMF after it has been set to 1, then write a 0 in this bit 1 RTCNT value is equal to RTCOR value Rev. 7.00 Jan 31, 2006 page 121 of 658 REJ09B0272-0700 Section 8 Bus State Controller (BSC) Bit 6--Compare Match Interrupt Enable (CMIE): Enables or disables the compare match interrupt (CMI) generated when CMF is set to 1 in RTCSR (RTCNT value = RTCOR value). When cleared to 0, the CMI interrupt is disabled; when set to 1, it is enabled. Bit 6: CMIE Description 0 Compare match interrupt request (CMI) is disabled 1 Compare match interrupt request (CMI) is enabled (Initial value) Bits 5-3--Clock Select Bits 2-0 (CKS2-CKS0): These bits select the clock input to RTCNT from among the seven types of clocks created by dividing the system clock (). When the input clock is selected with the CKS2-CKS0 bits, RTCNT starts to increment. Bit 5: CKS2 Bit 4: CKS1 Bit 3: CKS0 Description 0 0 0 Clock input disabled 1 /2 0 /8 1 /32 0 /128 1 /512 0 /2048 1 /4096 1 1 0 1 (Initial value) Bits 2-0--Reserved: These bits are always read as 0. The write value should always be 0. 8.2.8 Refresh Timer Counter (RTCNT) The refresh timer counter (RTCNT) is a 16-bit read/write register that is used as an 8-bit upcounter that generates refresh or interrupt requests. When the input clock is selected by clock select bits 2- 0 (CKS2-CKS0) in RTCSR, that clock makes the RTCNT start incrementing. When the values of RTCNT and the refresh time constant register (RTCOR) match, RTCNT is cleared to H'0000 and the CMF flag in RTCSR is set to 1. When the RFSHE bit in RCR is also set to 1, a CAS-beforeRAS refresh is performed. When the CMIE bit in RTCSR is also set to 1, a compare match interrupt (CMI) is generated. Bits 15-8 are reserved and are not incremented. These bits are always read as 0. RTCNT is initialized to H'0000 by a power-on reset, but is not initialized by a manual reset or in standby mode. Rev. 7.00 Jan 31, 2006 page 122 of 658 REJ09B0272-0700 Section 8 Bus State Controller (BSC) To prevent RTCSR from being written incorrectly, it must be written by a different method from most other registers. A word transfer operation is used, H'69 is written in the upper byte, and the actual data is written in the lower byte. For details, see section 8.2.11, Notes on Register Access. Bit 15 14 13 12 11 10 9 8 -- -- -- -- -- -- -- -- Initial value 0 0 0 0 0 0 0 0 Read/Write -- -- -- -- -- -- -- -- Bit 7 6 5 4 3 2 1 0 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W 8.2.9 Refresh Time Constant Register (RTCOR) The refresh time constant register (RTCOR) is a 16-bit read/write register that sets the compare match cycle used with RTCNT. The values in RTCOR and RTCNT are constantly compared. When they match, the compare match flag (CMF) is set in RTCNT and RTCSR is cleared to H'0000. If the RFSHE bit in RCR is set to 1 when this happens, a CAS-before-RAS (CBR) refresh is performed. When the CMIE bit in RTCSR is also set to 1, a compare match interrupt (CMI) is generated. Bits 15-8 are reserved and cannot be used to set the cycle. These bits are always read as 0. RTCOR is initialized to H'00FF by a power-on reset, but is not initialized by a manual reset or in standby mode. To prevent RTCOR from being written incorrectly, it must be written by a different method from most other registers. A word transfer operation is used, H'96 is written in the upper byte, and the actual data is written in the lower byte. For details, see section 8.2.11, Notes on Register Access. Bit 15 14 13 12 11 10 9 8 -- -- -- -- -- -- -- -- Initial value 0 0 0 0 0 0 0 0 Read/Write -- -- -- -- -- -- -- -- Rev. 7.00 Jan 31, 2006 page 123 of 658 REJ09B0272-0700 Section 8 Bus State Controller (BSC) Bit 7 6 5 4 3 2 1 0 Initial value 1 1 1 1 1 1 1 1 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W 8.2.10 Parity Control Register (PCR) The parity control register (PCR) is a 16-bit read/write register that selects the parity polarity and space to be parity checked. PCR is initialized to H'0000 by a power-on reset, but is not initialized by a manual reset or in standby mode. Bit 15 14 13 12 11 10 9 8 PEF PFRC PEO PCHK1 PCHK0 -- -- -- Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W -- -- -- 7 6 5 4 3 2 1 0 Bit -- -- -- -- -- -- -- -- Initial value 0 0 0 0 0 0 0 0 Read/Write -- -- -- -- -- -- -- -- Bit 15--Parity Error Flag (PEF): When a parity check is carried out, PEF indicates whether a parity error has occurred. 0 indicates that no parity error has occurred; 1 indicates that a parity error has occurred. Bit 15: PEF Description 0 No parity error 1 Parity error has occurred (Initial value) Cleared by reading PEF after it has been set to 1, then writing 0 in PEF Rev. 7.00 Jan 31, 2006 page 124 of 658 REJ09B0272-0700 Section 8 Bus State Controller (BSC) Bit 14--Parity Output Force (PFRC): PFRC selects whether to produce a forced parity output for testing the parity error check function. When cleared to 0, there is no forced output; when set to 1, it produces a forced high-level output from the DPH and DPL pins when data is output, regardless of the parity. Bit 14: PFRC Description 0 Parity output not forced 1 High output forced (Initial value) Bit 13--Parity Polarity (PEO): PEO selects even or odd parity. When cleared to 0, parity is even; when set to 1, parity is odd. Bit 13: PEO Description 0 Even parity 1 Odd parity (Initial value) Bits 12 and 11--Parity Check Enable Bits 1 and 0 (PCHK1 and PCHK0): These bits determine whether or not parity is checked and generated, and select the check and generation spaces. Bit 12: PCHK1 Bit 11: PCHK0 Description 0 0 Parity not checked and not generated 1 Parity checked and generated only in DRAM area 0 Parity checked and generated in DRAM area and area 2 1 Reserved 1 (Initial value) Bits 10-0--Reserved: These bits are always read as 0. The write value should always be 0. Rev. 7.00 Jan 31, 2006 page 125 of 658 REJ09B0272-0700 Section 8 Bus State Controller (BSC) 8.2.11 Notes on Register Access RCR, RTCSR, RTCNT, and RTCOR differ from other registers in being more difficult to write. Data requires a password when it is written. This prevents data from being mistakenly overwritten by program overruns and so on. Writing to RCR, RTCSR, RTCNT, and RTCOR: Use only word transfer instructions. It is not possible to write with byte transfer instructions. As figure 8.2 shows, when writing to RCR, place H'5A in the upper byte and the write data in the lower byte. When writing to RTCSR, place H'A5 in the upper byte and the write data in the lower byte. When writing to RTCNT, place H'69 in the upper byte and the write data in the lower byte. When writing to RTCOR, place H'96 in the upper byte and the write data in the lower byte. These transfers write data in the lower byte of the respective registers. If the upper byte differs from the above passwords, no writing occurs. 15 RCR 8 7 H'5A 15 RTCSR 8 7 15 0 Write data 8 7 H'69 15 RTCOR Write data H'A5 RTCNT 0 0 Write data 8 7 H'96 0 Write data Figure 8.2 Writing to RCR, RTCSR, RTCNT, and RTCOR Reading from RCR, RTCSR, RTCNT, and RTCOR: These registers are read like other registers. They can be read by byte and word transfer instructions. If read by word transfer, the value of the upper eight bits is H'00. Rev. 7.00 Jan 31, 2006 page 126 of 658 REJ09B0272-0700 Section 8 Bus State Controller (BSC) 8.3 Address Space Subdivision 8.3.1 Address Spaces and Areas Figure 8.3 shows the address format used in this chip. 4-Gbyte space 128-Mbyte space 16-Mbyte space 4-Mbyte space A31-A28 A27 A26-A24 A23,A22 A21 A0 Output address: Output from address pins A21-A0 Ignored: Only valid when the address multiplex function is being used in the DRAM space (area 1); not output in other cases. When not output, becomes shadow. Area selection: Decoded to become chip select signals CS0-CS7 for areas 0-7 Basic bus width selection: Not output externally, but used for basic bus width selection When 0, (H'0000000-H'7FFFFFF), the basic bus width is 8 bits. When 1, (H'8000000-H'FFFFFFF), the basic bus width is 16 bits. Ignored: Always ignored, not output externally Figure 8.3 Address Format Since this chip uses a 32-bit address, 4 Gbytes of space can be accessed in the architecture; however, the upper 4 bits (A31-A28) are always ignored and not output. Bit A27 is basically only used for switching the bus width. When the A27 bit is 0 (H'0000000-H'7FFFFFF), the bus width is 8 bits; when the A27 bit is 1 (H'8000000-H'FFFFFFF), the bus width is 16 bits. With the remaining 27 bits (A26-A0), a total of 128 Mbytes can thus be accessed. The 128-Mbyte space is subdivided into 8 areas (areas 0-7) of 16 Mbytes each according to the values of bits A26-A24. The space with bits A26-A24 as 000 is area 0 and the space with bits A26-A24 as 111 is area 7. The A26-A24 bits are decoded and are output as the chip select signals (CS0-CS7) of the corresponding areas 0-7. Table 8.7 shows how the space is divided. Rev. 7.00 Jan 31, 2006 page 127 of 658 REJ09B0272-0700 Section 8 Bus State Controller (BSC) Table 8.7 Area 0 How Space is Divided Address Assignable Memory H'0000000-H'0FFFFFF 1 On-chip ROM* H'1000000-H'1FFFFFF CS Output -- 64 kB 32 External memory* 4 MB 8/16* CS0 External memory 4 MB 8 CS1 2 1 Capacity Bus (Linear Space) Width 4 DRAM* 3 16 MB 8 RAS CAS 2 H'2000000-H'2FFFFFF External memory 4 MB 8 CS2 3 H'3000000-H'3FFFFFF External memory 4 MB 8 CS3 4 H'4000000-H'4FFFFFF External memory 4 MB 8 5 H'5000000-H'5FFFFFF On-chip supporting modules 512 B 8/16* 6 H'6000000-H'6FFFFFF External memory* 4 MB Multiplexed I/O 4 MB External memory 7 0 1 H'7000000-H'7FFFFFF H'8000000-H'8FFFFFF H'9000000-H'9FFFFFF 7 1 On-chip ROM* CS4 5 -- 8/16* 6 CS6 4 MB 8 CS7 -- 64 kB 32 2 External memory* 4 MB 3 8/16* CS0 External memory 4 MB 16 CS1 4 DRAM* 16 MB 16 RAS CAS 2 H'A000000-H'AFFFFFF External memory 4 MB 16 CS2 3 H'B000000-H'BFFFFFF External memory 4 MB 16 CS3 4 H'C000000-H'CFFFFFF External memory 4 MB 16 CS4 5 H'D000000-H'DFFFFFF External memory 4 MB 16 CS5 6 H'E000000-H'EFFFFFF External memory 4 MB 16 CS6 32 -- 7 H'F000000-H'FFFFFFF Notes: 1. 2. 3. 4. 5. 6. 7. 8. 9. On-chip RAM 8 9 8 kB* , 4 kB* When MD2-MD0 pins are 010 (SH7034) When MD2-MD0 pins are 000 or 001 Select with MD0 pin Select with DRAME bit in BCR Divided into 8-bit and 16-bit space according to value of address bit A8. (Longword accesses are inhibited, however, for on-chip supporting modules with bus widths of 8 bits. Some on-chip supporting modules with bus widths of 16 bits also have registers that are only byte-accessible and registers for which byte access is inhibited. For details, see the sections on the individual modules.) Divided into 8-bit space and 16-bit space by value of address bit A14 Select with IOE bit in BCR For SH7032 For SH7034 Rev. 7.00 Jan 31, 2006 page 128 of 658 REJ09B0272-0700 Section 8 Bus State Controller (BSC) As table 8.7 shows, specific spaces such as DRAM space and address/data multiplexed I/O space are allocated to the 8 areas. Each of the spaces is equipped with the necessary interfaces. The control signals needed by DRAM and peripheral chips will be output by the chip to devices connected to an area allocated to the appropriate type of space. 8.3.2 Bus Width The primary bus width selection for this chip is made by switching between 8 bits and 16 bits using the A27 bit. When A27 is 0, the bus width is 8 bits and data is input/output through the AD7-AD0 pins; when A27 is 1, the size is 16 bits and data is input/output through the AD15- AD0 pins for word accesses. For byte access, the upper byte is input/output through AD15-AD8 and the lower byte through AD7-AD0. When the bus width is 8 bits or byte access is being performed with a 16-bit bus width, the status of the eight AD pins that are not inputting/outputting data is as shown in appendix B, Pin States. Bus widths are also determined by conditions other than the A27 bit for specific areas: * Area 0 is an 8-bit external memory space when the MD2-MD0 pins are 000, a 16-bit external memory space when these bits are 001, and a 32-bit on-chip ROM space when they are 010 (the on-chip ROM is available only in the SH7034). * Area 5 is an 8-bit on-chip supporting module space when the A27 bit and A8 bit are both 0 and a 16-bit on-chip supporting module space when the A27 bit is 0 and the A8 bit is 1. When the A27 bit is 1, it is a 16-bit external memory space. * Area 6 has an 8-bit bus width when the A27 bit and A14 bit are both 0 and a 16-bit bus width when the A27 bit is 0 and the A14 bit is 1. When the A27 bit is 1, it is a 16-bit space. * Area 7 is a 32-bit on-chip RAM space when the A27 bit is 1 and an 8-bit external memory space when the A27 bit is 0. Word (16-bit) data accessed from 8-bit bus areas and longword (32-bit) data accessed from 16-bit bus areas require two consecutive accesses. Longword (32-bit) data accessed from 8-bit bus areas requires four consecutive accesses. 8.3.3 Chip Select Signals (CS0 CS0-CS7 CS0 CS7) CS7 When the A26-A24 bits of the address are decoded, they become chip select signals (CS0-CS7) for areas 0-7. When an area is accessed, the corresponding chip select pin is driven low. Table 8.8 shows the relationship between the A26-A24 bits and the chip select signals. Rev. 7.00 Jan 31, 2006 page 129 of 658 REJ09B0272-0700 Section 8 Bus State Controller (BSC) Table 8.8 A26 0 1 A26-A24 Bits and Chip Select Signals Address A25 A24 0 0 1 1 0 1 0 0 1 1 0 1 Area Selected Area 0 Area 1 Area 2 Area 3 Area 4 Area 5 Area 6 Area 7 Chip Select Pin Driven Low CS0 CS1 CS2 CS3 CS4 CS5 CS6 CS7 The chip select signal is output only for external accesses. When accessing the on-chip ROM (area 0), on-chip supporting modules (area 5), and on-chip RAM (area 7), the CS0, CS5, and CS7 pins are not driven low. When accessing DRAM space (area 1), select the RAS and CAS signals with the pin function controller. 8.3.4 Shadows The size of each area is 16 Mbytes, which can be specified with the 24 address bits A23-A0 for 8bit spaces and 16-bit spaces alike. Bits A23 and A22, however, output externally only when the address multiplex function is used in DRAM space (area 1); in all other cases, there is no output, so the actually accessible area for all areas is the 4 Mbytes that can be specified with the 22 bits A21-A0. Regardless of the values of A23 and A22, the same 4 Mbytes of actual space is accessed. As illustrated in figure 8.4 (a), the A23 and A22 bit regions 00, 01, 10 and 11 are called shadows of actual areas. Shadows are allocated in 4-Mbyte units for both 8-bit and 16-bit bus widths. When the same addresses H'3200000, H'3600000, H'3A00000 and H'3E00000 are specified for values A21-A0, as shown in figure 8.4 (b), the same actual space is accessed regardless of the A23 and A22 bits. In areas whose bus widths are switchable using the A27 address bit, the shadow of the same actual space is allocated to both A27 = 0 spaces and A27 = 1 spaces (figure 8.4(a)). When the value of A27 is changed, the valid AD pins switch from AD15-AD0 to AD7-AD0, but the actual space accessed remains the same. The spaces of on-chip ROM (area 0), DRAM (area 1), on-chip supporting modules (area 5), and on-chip RAM (area 7) have shadows of different sizes from those mentioned above. See section 8.3.5, Area Descriptions, for details. Rev. 7.00 Jan 31, 2006 page 130 of 658 REJ09B0272-0700 Section 8 Bus State Controller (BSC) Logical address space H'B000000 H'3000000 H'B3FFFFF H'B400000 H'33FFFFF Shadow (A23, A22 = 00) H'3400000 H'B7FFFFF H'B800000 H'37FFFFF Shadow (A23, A22 = 01) H'BBFFFFF H'BC00000 H'BFFFFFF H'3800000 H'3BFFFFF H'3C00000 H'3FFFFFF 16-bit space Actual space Area accessible with A21-A0 Shadow (A23, A22 = 10) 4 Mbytes Shadow (A23, A22 = 11) 8-bit space a. Shadow allocation Logical address space H'3000000 H'3200000 H'33FFFFF Location indicated by address H'3400000 H'3600000 H'37FFFFF H'3800000 H'3A00000 H'3BFFFFF H'3C00000 H'3E00000 H'3FFFFFF Actual space Location indicated by address Location actually accessed Location indicated by address Location indicated by address 8-bit space b. Actual space accessed when addresses are specified Figure 8.4 Shadows Rev. 7.00 Jan 31, 2006 page 131 of 658 REJ09B0272-0700 Section 8 Bus State Controller (BSC) 8.3.5 Area Descriptions Area 0: Area 0 is an area with address bits A26-A24 set to 000 and an address range of H'0000000-H'0FFFFFF and H'8000000-H'8FFFFFF. Figure 8.5 shows a memory map of area 0. Area 0 can be set for use as on-chip ROM space or external memory space with the mode pins (MD2-MD0). The MD2-MD0 pins also determine the bus width, regardless of the A27 address bit. When MD2-MD0 are 000, area 0 is an 8-bit external memory space; when they are 001, area 0 is a 16-bit external memory space; and when they are 010, it is a 32-bit on-chip ROM space. In the SH7032, area 0 can only be used as external memory space since there is no on-chip ROM, and this last setting is meaningless. The capacity of the on-chip ROM is 64 kbytes, so bits A23-A16 are ignored in on-chip ROM space and the shadow is in 64-kbyte units. The CS0 signal is disabled. In external memory space, the A23 and A22 bits are not output and the shadow is in 4-Mbyte units. When external memory space is accessed, the CS0 signal is valid. The external memory space has a long wait function, so between 1 and 4 states can be selected for the number of long waits inserted into the bus cycle using the area 0 and 2 long wait insertion bits (A02LW1, A02LW0) of wait state controller 3 (WCR3). Rev. 7.00 Jan 31, 2006 page 132 of 658 REJ09B0272-0700 Section 8 Bus State Controller (BSC) Logical address space Logical address space H'8000000 H'800FFFF H'8010000 H'0000000 H'000FFFF H'0010000 H'8000000 H'0000000 Shadow Shadow Shadow H'83FFFFF H'8400000 Shadow H'03FFFFF H'0400000 Actual space On-chip ROM (64 kbytes) H'8FF0000 Shadow H'8FFFFFF H'0FF0000 H'0FFFFFF Shadow Shadow 32-bit space 32-bit space MD2-MD0 = 010 Note: * Valid addresses A15-A0 (A23-A16 ignored) * CS0 not valid * On-chip ROM space valid in SH7034 only Shadow H'87FFFFF H'8800000 Actual space External memory space (4 Mbytes) H'07FFFFF H'0800000 Shadow H'8BFFFFF H'8C00000 H'0BFFFFF H'0C00000 Shadow H'8FFFFFF H'0FFFFFF 8 or 16 bit space 8 or 16 bit space * MD2-MD0 = 000: 8-bit access, 001: 16-bit access * Valid addresses A21-A0 (A23 and A22 not output) * CS0 valid * Long wait function MD2-MD0 = 000 or 001 The bus width of area 0 is determined by the MD2-MD0 pins regardless of the A27 bit setting. Figure 8.5 Memory Map of Area 0 Area 1: Area 1 is an area with address bits A26-A24 set to 001 and an address range of H'1000000-H'1FFFFFF and H'9000000-H'9FFFFFF. Figure 8.6 shows a memory map of area 1. Area 1 can be set for use as DRAM space or external memory space with the DRAM enable bit (DRAME) in the bus control register (BCR). When the DRAME bit is 0, area 1 is external memory space; when DRAME is 1, it is DRAM space. In external memory space, the bus width is 8 bits when the A27 bit is 0 and 16 bits when it is 1. Bits A23 and A22 are not output and the shadow is in 4-Mbyte units. When external memory is accessed, the CS1 signal is valid. DRAM space is a type of external memory space, but it is configured especially to be connected to DRAM, so it outputs strobe signals required for this purpose. The access size is 8 bits when Rev. 7.00 Jan 31, 2006 page 133 of 658 REJ09B0272-0700 Section 8 Bus State Controller (BSC) address bit A27 is 0 and 16 bits when A27 is 1. When the multiplex enable bit (MXE) in the DRAM control register (DCR) is set to 1 to use the address multiplex function, bits A23-A0 are multiplexed and output from pins A15-A0, so a maximum 16-Mbyte space can be used. When DRAM space is accessed, the CS1 signal is not valid and the pin function controller should be set for access with CAS (CASH and CASL) and RAS signals. Logical address space Logical address space H'9000000 H'9000000 Actual space H'1000000 H'1000000 Shadow H'93FFFFF H'9400000 H'13FFFFF H'1400000 Actual space Shadow H'97FFFFF H'9800000 H'17FFFFF H'1800000 Shadow H'9BFFFFF H'9C00000 H'1BFFFFF H'1C00000 H'9FFFFFF H'1FFFFFF A27 = 1: 16-bit space Shadow External memory space (4 Mbytes) Shadow DRAM space (maximum 16 Mbytes) * Valid address A21-A0 (A23 and A22 not output) * CS1 H'9FFFFFF valid H'1FFFFFF A27 = 0: 8-bit space A27 = 1: A27 = 0: 16-bit space 8-bit space DRAME = 0 or DRAME = 1, MXE = 0 * Multiplexed (MXE = 1): 16-bit space * Not multiplexed (MXE = 0): 4-Mbyte space * CS1 not valid (CAS, RAS output) DRAME = 1 Figure 8.6 Memory Map of Area 1 Areas 2-4: Areas 2-4 are areas with address bits A26-A24 set to 010, 011, and 100, respectively, and address ranges of H'2000000-H'2FFFFFF and H'A000000-H'AFFFFFF (area 2), H'3000000- H'3FFFFFF and H'B000000-H'BFFFFFF (area 3), and H'4000000-H'4FFFFFF and H'C000000- H'CFFFFFF (area 4). Figure 8.7 shows a memory map of area 2, which is representative of areas 2-4. Rev. 7.00 Jan 31, 2006 page 134 of 658 REJ09B0272-0700 Section 8 Bus State Controller (BSC) Areas 2-4 are always used as external memory space. The bus width is 8 bits when the A27 bit is 0 and 16 bits when it is 1. A23 and A22 bits are not output and the shadow is in 4-Mbyte units. When areas 2-4 are accessed, the CS2, CS3, and CS4 signals are valid. Area 2 has a long wait function, so between 1 and 4 states can be selected for the number of long waits inserted into the bus cycle using bits A02LW1 and A02LW0 in WCR3. Logical address space H'A000000 H'2000000 Shadow H'A3FFFFF H'A400000 H'23FFFFF H'2400000 Actual space Shadow H'A7FFFFF H'A800000 External memory space (4 Mbytes) H'27FFFFF H'2800000 Shadow H'ABFFFFF H'AC00000 H'2BFFFFF H'2C00000 * Valid addresses A21-A0 (A23 and A22 not output) * CS2 valid * Long wait function Shadow H'AFFFFFF H'2FFFFFF 16-bit space 8-bit space Figure 8.7 Memory Map of Area 2 Rev. 7.00 Jan 31, 2006 page 135 of 658 REJ09B0272-0700 Section 8 Bus State Controller (BSC) Area 5: Area 5 is an area with address bits A26-A24 set to 101 and an address range of H'5000000-H'5FFFFFF and H'D000000-H'DFFFFFF. Figure 8.8 shows a memory map of area 5. Area 5 is allocated to on-chip supporting module space when the A27 address bit is 0 and external memory space when A27 is 1. In on-chip supporting module space, bits A23-A9 are ignored and the shadows are in 512-byte units. The bus width is 8 bits when the A8 bit is 0 and 16 bits when A8 is 1. When on-chip supporting module space is accessed, the CS5 signal is not valid. In external memory space, the A23 and A22 bits are not output and the shadow is in 4-Mbyte units. The bus width is always 16 bits. When external memory space is accessed, the CS5 signal is valid. Logical address space H'D000000 Logical address space H'5000000 H'50001FF Shadow Shadow Shadow Shadow H'D3FFFFF H'D400000 Actual space On chip peripheral module space (512 bytes) Shadow Shadow H'5FFFE00 H'5FFFFFF Shadow 8 or 16-bit space Actual space Shadow H'D7FFFFF H'D800000 Shadow A8 = 0: H'DBFFFFF H'DC00000 8-bit space A8 = 1: 16-bit space* * Ignored Shadow addresses: A23-A9 (Valid addresses H'DFFFFFF 16-bit space A8-A0) * CS5 not valid External memory space (4 Mbytes) * Valid addresses A21-A0 A23 and A22 not output) * CS5 valid Note: * Some on-chip supporting module registers can only be accessed as 8-bit registers even though they occupy 16 bits (see Appendix A). Figure 8.8 Memory Map of Area 5 Rev. 7.00 Jan 31, 2006 page 136 of 658 REJ09B0272-0700 Section 8 Bus State Controller (BSC) Area 6: Area 6 is an area with address bits A26-A24 set to 110 and an address range of H'6000000-H'6FFFFFF and H'E000000-H'EFFFFFF. Figure 8.9 shows a memory map of area 6. In area 6, a space for which address bit A27 is 0 is allocated to address/data multiplexed I/O space when the multiplexed I/O enable bit (IOE) of the bus control register (BCR) is 1, and to external memory space when the IOE bit is 0. When A27 is 1, it is always external memory space. The multiplexed I/O space is a type of external memory space but the address and data are multiplexed and output from AD15-AD0 or AD7-AD0. The bus width is 8 bits when the A14 bit is 0 and 16 bits when the A14 bit is 1. The A23 and A22 bits are not output and the shadow is in 4Mbyte units. When multiplexed I/O space is accessed, the CS6 signal is valid. In external memory space, the bus width is 8 bits when both the A27 and A14 bits are 0 and 16 bits when the A27 bit is 0 and the A14 bit is 1. When the A27 bit is 1, it is always a 16-bit space. The A23 and A22 bits are not output and the shadow is in 4-Mbyte units. When external memory is accessed, the CS6 signal is valid. The external memory space has a long wait function so between 1 and 4 states can be selected for the number of long waits inserted into the bus cycle using the area 6 long wait insertion bits (A6LW1 and A6LW0) in WCR3. Logical address space H'6000000 Logical address space H'E000000 Shadow H'63FFFFF H'6400000 Shadow Actual space Shadow H'67FFFFF H'6800000 Shadow H'6BFFFFF H'6C00000 Shadow H'6FFFFFF 8 or 16-bit space Multiplexed I/O space or external memory space (4 Mbytes) H'E3FFFFF H'E400000 Actual space Shadow H'E7FFFFF H'E800000 External memory space (4 Mbytes) Shadow * Valid * IOE = 1: addresses address/data A21-A0 (A23 multiplexed I/O H'EBFFFFF H'EC00000 and A22 not space; output) IOE = 0: external * CS6 valid memory space Shadow * Long wait * A14 = 0: 8-bit space function A14 = 1: 16-bit space * Valid addresses H'EFFFFFF A21-A0 (A23 and 16-bit space A22 not output) * CS6 valid * Long wait function Figure 8.9 Memory Map of Area 6 Rev. 7.00 Jan 31, 2006 page 137 of 658 REJ09B0272-0700 Section 8 Bus State Controller (BSC) Area 7: Area 7 is an area with address bits A26-A24 set to 111 and an address range of H'7000000-H'7FFFFFF and H'F000000-H'FFFFFFF. Figure 8.10 shows a memory map of area 7. Area 7 is allocated to external memory space when A27 is 0 and on-chip RAM space when A27 is 1. In external memory space, the bus width is 8 bits. The A23 and A22 bits are not output and the shadow is in 4-Mbyte units. When external memory is accessed, the CS7 signal is valid. The on-chip RAM space has a bus width of 32 bits. In the SH7032, the on-chip RAM capacity is 8 kbytes, so A23-A13 are ignored and the shadows are in 8-kbyte units. In the SH7034, the on-chip RAM capacity is 4 kbytes, so A23-A12 are ignored and the shadows are in 4-kbyte units. During on-chip RAM access, the CS7 signal is not valid. Logical address space H'7000000 Logical address space H'F000000 H'F000FFF (SH7034) Shadow H'F001FFF (SH7032) Shadow Shadow Shadow H'73FFFFF H'7400000 Actual space Shadow H'77FFFFF H'7800000 Shadow H'7BFFFFF H'7C00000 Actual space External memory space (4 Mbytes) * Valid addresses A21-A0 (A23 and A22 not output) * CS7 valid Shadow H'FFFE000 (SH7032) H'FFFF000 (SH7034) H'FFFFFFF H'7FFFFFF 8-bit space Shadow Shadow Shadow 32-bit space Figure 8 10 Memory Map of Area 7 Rev. 7.00 Jan 31, 2006 page 138 of 658 REJ09B0272-0700 * On-chip RAM space SH7032: 8 kbytes, SH7034: 4 kbytes * Valid addresses SH7032: A12-A0 (A23-A13 not output) SH7034: A11-A0 (A23-A12 not output) * CS7 not valid Section 8 Bus State Controller (BSC) 8.4 Accessing External Memory Space In external memory space, a strobe signal is output based on the assumption of a directly connected SRAM. The external memory space is allocated to the following areas: * Area 0 (when MD2-MD0 are 000 or 001) * Area 1 (when the DRAM enable bit (DRAME) in BCR is 0) * Areas 2-4 * Area 5 (space where address bit A27 is 1) * Area 6 (when the multiplexed I/O enable bit (IOE) bit in BCR is 0, or space where address bit A27 is 1) * Area 7 (space where address bit A27 is 0) 8.4.1 Basic Timing The bus cycle for external memory space access is 1 or 2 states. The number of states is controlled with wait states by the settings of wait state control registers 1-3 (WCR1-WCR3). For details, see section 8.4.2, Wait State Control. Figures 8.11 and 8.12 illustrate the basic timing of external memory space access. T1 CK A21-A0 CSn RD (Read) AD15-AD0 (Read) Figure 8.11 Basic Timing of External Memory Space Access (1-State Read Timing) Rev. 7.00 Jan 31, 2006 page 139 of 658 REJ09B0272-0700 Section 8 Bus State Controller (BSC) T1 T2 CK A21-A0 CSn When RDDTY = 0 RD Read When RDDTY = 1 AD15-AD0 WRH, WRL Write AD15-AD0 Figure 8.12 Basic Timing of External Memory Space Access (2-State Read Timing) High-level duties of 35% and 50% can be selected for the RD signal using the RD duty bit (RDDTY) in BCR. When RDDTY is set to 1, the high-level duty is 35% of the T1 state, enabling longer access times for external devices. Only set to 1 when the operating frequency is a minimum of 10 MHz. Rev. 7.00 Jan 31, 2006 page 140 of 658 REJ09B0272-0700 Section 8 Bus State Controller (BSC) 8.4.2 Wait State Control The number of external memory space access states and the insertion of wait states can be controlled using the WCR1-WCR3 bits. The bus cycles that can be controlled are the CPU read cycle and the DMAC dual mode read cycle. The bus cycle that can be controlled using the WCR2 is the DMAC single-mode read/write cycle. Table 8.9 shows the number of states and number of wait states in access cycles to external memory spaces. Table 8.9 Number of States and Number of Wait States in Access Cycles to External Memory Spaces CPU Read Cycle, DMAC Dual Mode Read Cycle, DMAC Single Mode Read/Write Cycle CPU Write Cycle and DMAC Dual Mode Write Cycle (Cannot be 2 controlled by WCR1)* Corresponding Bits in WCR1 and WCR2 = 0 Corresponding Bits in WCR1 and WCR2 = 1 1, 3-5, 7 1 cycle fixed; WAIT signal ignored 2 cycles fixed + wait state from WAIT signal* 0, 2, 6 (long wait available) 1 cycle + long wait state, WAIT signal ignored 1 cycle + long wait state* + wait state from WAIT signal Area 3 1 Notes: 1. The number of long wait states is set by WCR3. 2. When DRAME = 1, short pitch/long pitch is selected with the WW1 bit in WCR1. 3. Pin wait cannot be used for the CS7 and WAIT pins of area 3 because they are multiplexed. For the CPU read cycle, DMAC dual mode read cycle, and DMAC single mode read/write cycle, the access cycle is completed in 1 state when the corresponding bits of WCR1 and WCR2 for areas 1, 3-5, and 7 are cleared to 0 and the WAIT pin input signal is not sampled. When the bits are set to 1, the WAIT signal is sampled and the number of states is 2 plus the number of wait states set by the WAIT signal. The WAIT signal is sampled at the rise of the system clock (CK) directly preceding the second state of the bus cycle and the wait states are inserted as long as the level is low. When a high level is detected, it shifts to the second state (final state). Figure 8.13 shows the wait state timing when accessing the external memory spaces of areas 1, 3, 4, 5, and 7. Rev. 7.00 Jan 31, 2006 page 141 of 658 REJ09B0272-0700 Section 8 Bus State Controller (BSC) T1 Tw (wait state) T2 CK A21-A0 CSn RD Read AD15-AD0 WRH, WRL Write AD15-AD0 WAIT Figure 8.13 Wait State Timing for External Memory Space Access (2 States Plus Wait States from WAIT Signal) Areas 0, 2, and 6 have long wait functions. When the corresponding bits in WCR1 and WCR2 are cleared to 0, the access cycle is 1 state plus the number of long wait states (set in WCR3, selectable between 1 and 4) and the WAIT pin input signal is not sampled. When the bits are set to 1, the WAIT signal is sampled and the number of states is 1 plus the number of long wait states plus the number of wait states set by the WAIT signal. The WAIT signal is sampled at the rise of the system clock (CK) directly preceding the last long wait state and the wait states are inserted as long as the level is low. When a high level is detected, it shifts to the final long wait state. Figure 8.14 shows the wait state timing when accessing the external memory spaces of areas 0, 2, and 6. Rev. 7.00 Jan 31, 2006 page 142 of 658 REJ09B0272-0700 Section 8 Bus State Controller (BSC) Wait state Wait from WAIT states set signal input in WCR3 Wait states set in WCR3 T1 TLW1 TLW2 TW TLW3 CK A21-A0 CSn RD Read AD15-AD0 WRH, WRL Write AD15-AD0 WAIT Figure 8.14 Wait State Timing for External Memory Space Access (1 State Plus Long Wait State (When Set to Insert 3 States) Plus Wait States from WAIT Signal) For CPU write cycles and DMAC dual mode write cycles to external memory space, the number of states and wait state insertion cannot be controlled by WCR1. In areas 1, 3, 4, 5, and 7, the WAIT signal is sampled and the number of states is 2 plus the number of wait states set by the WAIT signal (figure 8.13). In areas 0, 2 and 6, the number of states is 1 state plus the number of long wait states plus the number of wait states set by the WAIT signal (figure 8.14). Do not write 0 in bits 7-2 and 0 of WCR1; only write 1. When area 1 is being used as external memory space, do not write 0 in bit 1 (WW1); always write 1. Rev. 7.00 Jan 31, 2006 page 143 of 658 REJ09B0272-0700 Section 8 Bus State Controller (BSC) 8.4.3 Byte Access Control The upper byte and lower byte control signals when 16-bit bus width space is being accessed can be selected from (WRH, WRL, A0) or (WR, HBS, LBS). When the byte access select bit (BAS) in BCR is set to 1, the WRH, WRL, and A0 pins output WR, LBS, and HBS signals. Figure 8.15 illustrates the control signal output timing in the byte write cycle. Upper byte access T1 T2 Lower byte access T1 T2 CK A0 BAS = 0 WRH WRL HBS BAS = 1 LBS WR Figure 8.15 Byte Access Control Timing For External Memory Space Access (Write Cycle) The WRH, WRL system and the HBS, LBS system are available as byte access signals for 16-bit space in address/data multiplexing space and external memory space. These strobe signals are assigned to pins in the manner: A0/HBS, WRH/LBS, WRL/WR, and the BAS bit in the bus control register (BCR) is used to switch specify signal sending. Note that the byte access signals are strobe signals specifically for byte access to a 16-bit space and are not to be used for byte access to an 8-bit space. When making an access to an 8-bit space, use the A0/HBS pin as A0 irrespective of the BAS bit value to use the WRL/WR pin as the WR pin, and avoid using the WRH/LBS pin. Rev. 7.00 Jan 31, 2006 page 144 of 658 REJ09B0272-0700 Section 8 Bus State Controller (BSC) 8.5 DRAM Interface Operation When the DRAM enable bit (DRAME) in BCR is set to 1, area 1 becomes DRAM space and the DRAM interface function is available, which permits direct connection of this chip to DRAMs. 8.5.1 DRAM Address Multiplexing When the multiplex enable bit (MXE) in the DRAM area control register (DCR) is set to 1, row addresses and column addresses are multiplexed. This allows DRAMs that require multiplexing of row and column addresses to be connected directly to an SH microprocessor without additional multiplexing circuits. When addresses are multiplexed (MXE = 1), setting of the DCR's multiplex shift bits (MXC1, MXC0) allows selection of eight, nine and ten-bit row address shifting. Table 8.10 illustrates the relationship between the MXC1/MXC0 bits and address multiplexing. Rev. 7.00 Jan 31, 2006 page 145 of 658 REJ09B0272-0700 Section 8 Bus State Controller (BSC) Table 8.10 Relationship between Multiplex Shift Count Bits (MXC1, MXC0) and Address Multiplexing 8-Bit Shift 9-Bit Shift 10-Bit Shift Output Pin Output Row Address Output Column Address Output Row Address Output Column Address Output Row Address Output Column Address A21 Undefined A21 Undefined A21 Undefined A21 A20 Value A20 Value A20 Value A20 A19 A19 A19 A19 A18 A18 A18 A18 A17 A17 A17 A17 A16 A16 A16 A16 A15 A15 A15 A15 A23 A14 A22 A14 A23 A14 A13 A21 A13 A22 A13 A23 A13 A12 A20 A12 A21 A12 A22 A12 A11 A19 A11 A20 A11 A21 A11 A10 A18 A10 A19 A10 A20 A10 A9 A17 A9 A18 A9 A19 A9 A8 A16 A8 A17 A8 A18 A8 A7 A15 A7 A16 A7 A17 A7 A6 A14 A6 A15 A6 A16 A6 A5 A13 A5 A14 A5 A15 A5 A4 A12 A4 A13 A4 A14 A4 A3 A11 A3 A12 A3 A13 A3 A2 A10 A2 A11 A2 A12 A2 A1 A9 A1 A10 A1 A11 A1 A0 A8 A0 A9 A0 A10 A0 Note: The MXC1=1, MX0=1 setting is reserved, and must not be used. Rev. 7.00 Jan 31, 2006 page 146 of 658 REJ09B0272-0700 A14 Section 8 Bus State Controller (BSC) For example, when MXC1 and MXC0 are set to 00 and an 8-bit shift is selected, the A23-A8 address bit values are output to pins A15-A0 the row address. The values for A21-A16 are undefined. The values of bits address A21-A0 are output to pins A21-A0 as the column address. Figure 8.16 depicts address multiplexing with an 8-bit shift. RAS = Low Internal address A23 Address pin A8 A7 A21 A16 A15 A0 A0 Undefined output CAS = Low Internal address A23 A22 A21 Address pin A0 A21 A0 Figure 8.16 Address Multiplexing States (8-Bit Shift) 8.5.2 Basic Timing There are two types of DRAM accesses: short pitch and long pitch. Short pitch or long pitch can be selected for the respective bus cycles using the RW1 and WW1 bits in WCR1 and the DRW1 and DWW1 bits in WCR2. When the corresponding bits are cleared to 0, DRAM access is short pitch and column address output occurs in 1 state. When these bits are 1, DRAM access is long pitch and column address output occurs in 2 states. Figure 8.17 shows short pitch timing; figure 8.18 shows long pitch timing. The high-level duty of the CAS signal can also be selected between 50% and 35% of the Tc state when access is short pitch. By setting the CDTY bit to 1, the high level duty becomes 35% and the DRAM access time can be lengthened. Only set to 1 when the operating frequency is a minimum of 10 MHz. Rev. 7.00 Jan 31, 2006 page 147 of 658 REJ09B0272-0700 Section 8 Bus State Controller (BSC) Tp Tr Tc CK Row address A21-A0 Column address RAS CDTY =0 CAS CDTY =1 WRH, WRL Read AD15-AD0 WRH, WRL Write AD15-AD0 Figure 8.17 Short Pitch Access Timing Rev. 7.00 Jan 31, 2006 page 148 of 658 REJ09B0272-0700 Section 8 Bus State Controller (BSC) Tp Tr Tc1 Tc2 CK Row address A21-A0 Column address RAS CAS WRH, WRL Read AD15-AD0 WRH, WRL Write AD15-AD0 Figure 8.18 Long Pitch Access Timing 8.5.3 Wait State Control Precharge State Control: When the microprocessor clock frequency is raised and the cycle period shortened, 1 cycle may not always be sufficient for the precharge time for the RAS signal when the DRAM is accessed. The BSC allows the precharge cycle to be set to 1 state or 2 states using the RAS signal precharge cycles bit (TPC) in DCR. When the TPC bit is 0, the precharge cycle is 1 state; when TPC is 1, the precharge cycle is 2 states. Figure 8.19 shows the timing when the precharge cycle is 2 states. Rev. 7.00 Jan 31, 2006 page 149 of 658 REJ09B0272-0700 Section 8 Bus State Controller (BSC) Tp 1 Tp2 Tr Tc1 Tc2 CK Row address A21-A0 Column address RAS CAS Figure 8.19 Precharge Timing (Long Pitch) Control of Insertion of Wait States Using the WAIT Pin Input Signal: The number of wait states inserted into the DRAM access cycle can be controlled by setting WCR1 and WCR2. When the corresponding bits in WCR1 and WCR2 are cleared to 0, the column address output cycle ends in 1 state and no wait states are inserted. When the bit is 1, the WAIT pin input signal is sampled on the rise of the system clock (CK) directly preceding the second state of the column address output cycle and the wait state is inserted as long as the level is low. When a high level is detected, it shifts to the second state. Figure 8.20 shows the wait state timing in a long pitch bus cycle. Tp Tr Tc1 Tcw (wait state) Tc2 CK A21-A0 Row address Column address RAS CAS WAIT Figure 8.20 Wait State Timing during DRAM Access (Long Pitch) Rev. 7.00 Jan 31, 2006 page 150 of 658 REJ09B0272-0700 Section 8 Bus State Controller (BSC) Regardless of the state of the WAIT signal, when the RW1 bit, the number of wait states selected by CBR refresh wait state insertion bits 1 and 0 (RLW1, RLW0) in the refresh control register (RCR) are inserted into the CAS-before-RAS refresh cycle. 8.5.4 Byte Access Control 16-bit width and 18-bit width DRAMs require different types of byte control signals for access. By setting the dual CAS signals/dual WE signals select bit (CW2) in DCR, the BSC allows selection of either the dual CAS signal or dual WE signal system of control signals. When 16-bit space is being accessed and the CW2 bit is cleared to 0 for dual CAS signals, CASH, CASL, and WRL signals are output; when CW2 is set to 1 for dual WE signals, the CASL, WRH, and WRL signals are output. When accessing 8-bit space, WRL and CASL are output regardless of the CW2 setting. Figure 8.21 shows the control timing of the upper byte write cycle (short pitch) in 16-bit space. Rev. 7.00 Jan 31, 2006 page 151 of 658 REJ09B0272-0700 Section 8 Bus State Controller (BSC) Tp Tr Tc Row address Column address CK A21-A0 RAS Byte control CASH CASL High WRH Fixed high WRL (a) Dual CAS signals (CW2 = 0) Tp Tr Tc CK Row address A21-A0 Column address RAS CASH Fixed high CASL Byte control WRH High WRL (b) Dual WE signals (CW2 = 1) Figure 8.21 Byte Access Control Timing for DRAM Access (Upper Byte Write Cycle, Short Pitch) Rev. 7.00 Jan 31, 2006 page 152 of 658 REJ09B0272-0700 Section 8 Bus State Controller (BSC) 8.5.5 DRAM Burst Mode In addition to the normal mode of DRAM access, in which row addresses are output at every access and data then accessed (full access), the DRAM also has a high-speed page mode for use when continuously accessing the same row. The high speed page mode enables fast access of data simply by changing the column address after the row address is output (burst mode). Select between full access and burst operation by setting the burst enable bit (BE) in DCR. When the BE bit is set to 1, burst operation is performed when the row address matches the previous DRAM access row address. Figure 8.22 shows a comparison between full access and burst operation. RAS CAS Column address 2 Column address 1 A21-A0 AD15- AD0 Row address 1 Row address 2 Data 1 Data 2 (a) Full access (read cycle) RAS CAS Column Column Column Column address 1 address 2 address 3 address 4 A21-A0 AD15- AD0 Row address 1 Data 1 Data 2 Data 3 Data 4 (b) Burst operation (read cycle) Figure 8.22 Full Access and Burst Operation Short pitch high-speed page mode or long pitch high-speed page mode burst transfers can be selected independently for DRAM read/write cycles even when burst operation is selected by using the bits corresponding to area 1 in WCR1 and WCR2 (RW1, WW1, DRW1, DWW1). RAS down mode or RAS up mode can be selected by setting the RAS down bit (RASD) in DCR when there is an access outside the DRAM space during burst operation. Rev. 7.00 Jan 31, 2006 page 153 of 658 REJ09B0272-0700 Section 8 Bus State Controller (BSC) Short-Pitch, High-Speed Page Mode and Long-Pitch High-Speed Page Mode: When burst operation is selected by setting the BE bit to 1 in DCR, short pitch high-speed page mode or long pitch high-speed page mode can be selected by setting the RW1, WW1, DRW1, and DWW1 bits in WCR1 and WCR2. * Short-pitch, high-speed page mode: When the RW1, WW1, DRW1, and DWW1 bits in WCR1 and WCR2 are cleared to 0, and the corresponding DRAM access cycle is continuing, the CAS signal and column address output cycles continue as long as the row addresses continue to match. The column address output cycle is performed in 1 state and the WAIT signal is not sampled. Figure 8.23 shows the read cycle timing for short-pitch, high-speed page mode. Tp Tr Tc Tc Tc Column address 1 Column address 2 Tc CK Column Column address 3 address 4 A21- A0 Row address 1 RAS CAS WR AD15- A0 Data 1 Data 2 Data 3 Data 4 Figure 8.23 Short-Pitch, High-Speed Page Mode (Read Cycle) When the write cycle continues for the same row address in short-pitch, high-speed page mode, an open cycle (silent cycle) is produced for 1 cycle only. This timing is shown in figure 8.24. Likewise, when a write cycle continues after the read cycle for the same row address, a silent cycle is produced for 1 cycle. This timing is shown in figure 8.25. Note also that when DRAM is written to in short-pitch, high-speed page mode when using DMAC single address mode, a silent cycle is inserted in each transfer. The details of timing are discussed in sections 20.1.3 (3) and 20.2.3 (3), Bus Timing. Rev. 7.00 Jan 31, 2006 page 154 of 658 REJ09B0272-0700 Section 8 Bus State Controller (BSC) Access A Tp Tr Tc Access B Silent cycle Tc Tc Tc CK Column Column address A-1 address A-2 Column Column address B-1 address B-2 A21- A0 Row address RAS CAS WR AD15- AD0 Note: Data A-1 Data A-2 Data B-1 Data B-2 Accesses A and B are examples of 32-bit data accesses in their respective 16-bit bus width spaces. Figure 8.24 Short-Pitch, High-Speed Page Mode (Write Cycle) Access A (read) Tp Tr Tc Access B (write) Tc Silent cycle Tc Tc CK Column Column address A-1 address A-2 Column Column address B-1 address B-2 A21- A0 Row address RAS CAS WR AD15- AD0 Read data A-1 Read data A-2 Write data B-1 Write data B-2 Note: Accesses A and B are examples of 32-bit data accesses in their respective 16-bit bus width spaces. Figure 8.25 Short-Pitch, High-Speed Page Mode (Read and Write Cycles Continuing with Same Row Address) Rev. 7.00 Jan 31, 2006 page 155 of 658 REJ09B0272-0700 Section 8 Bus State Controller (BSC) The high-level duty of the CAS signal can be selected in short-pitch, high-speed page mode using the CAS duty bit (CDTY) in DCR. When the CDTY bit is cleared to 0, the high-level duty is 50% of the TC state; when CDTY is set to 1, it is 35% of the TC state. * Long-pitch, high-speed page mode: When the RW1, WW1, DRW1, and DWW1 bits in WCR1 and WCR2 are set to 1, and the corresponding DRAM access cycle is continuing, the CAS signal and column address output cycles (2 states) continue as long as the row addresses continue to match. When the WAIT signal is detected at the low level, the second cycle of the column address output cycle is repeated as the wait state. Figure 8.26 shows the timing for long-pitch, high-speed page mode. See sections 20.1.3 (3) and 20.2.3 (3), Bus Timing, for more information about the timing. Tp Tr Tc1 Tc2 Tc1 Tc2 CK Column address 1 Column address 2 A21-AD0 Row address 1 RAS CAS Read WR AD15-AD0 Data 1 Data 2 WR Write AD15-AD0 Data 1 Data 2 Figure 8.26 Long-Pitch, High-Speed Page Mode (Read/Write Cycle) RAS Down Mode and RAS Up Mode: Sometimes access to another area can occur between accesses to the DRAM even though burst operation has been selected. Keeping the RAS signal low while this other access is occurring allows burst operation to continue the next time the same row of the DRAM is accessed. The RASD bit in DCR selects RAS down mode when set to 1 and RAS up mode when cleared to 0. In both RAS down mode and RAS up mode, burst operation is continued while the same row address continues to be accessed, even if the bus master is changed. * RAS down mode: When the RASD bit in DCR is set to 1, the DRAM access pauses and the RAS signal is held low throughout the access of the other space while waiting for the next Rev. 7.00 Jan 31, 2006 page 156 of 658 REJ09B0272-0700 Section 8 Bus State Controller (BSC) access to the DRAM area. When the row address for the next DRAM access is the same as the previous DRAM access, burst operation continues. Figure 8.27 shows the timing of RAS down mode when external memory space is accessed during burst operation. The RAS signal can be held low in the DRAM for a limited time; the RAS signal must be returned to high within the specified limits even when RAS down mode is selected since the critical low level period is set. In this chip, even when RAS down mode is selected, the RAS signal automatically reverts to high when the DRAM is refreshed, so the BSC's refresh control function can be employed to set a CAS-before-RAS refresh that will keep operation within specifications. See section 8.5.6, Refresh Control, for details. External memory space access DRAM access Tp Tr Tc Tc T1 DRAM access Tc Tc CK Column Column address 1 address 2 External Column Column memory address 3 address 4 A21- A0 Row address RAS CAS WR AD15- AD0 Data 1 Data 2 Data 3 Data 4 External memory data Figure 8.27 RAS Down Mode Rev. 7.00 Jan 31, 2006 page 157 of 658 REJ09B0272-0700 Section 8 Bus State Controller (BSC) * RAS up mode: When the RASD bit is cleared to 0, the RAS signal reverts to high whenever a DRAM access pauses for access to another space. Burst operation continues only while DRAM access is continuous. Figure 8.28 shows the timing when an external memory space access occurs during burst operation in RAS up mode. External memory space access DRAM access Tp Tr Tc Tc T1 DRAM access Tp Tr Tc CK Column Column External memory address 1 address 2 address Column address 3 A21- A0 Row address Row address RAS CAS AD15- AD0 Data 1 Data 2 Data 3 External memory data Figure 8.28 RAS Up Mode 8.5.6 Refresh Control The BSC has a function for controlling DRAM refreshing. By setting the refresh mode bit (RMODE) in the refresh control register (RCR), either CAS-before-RAS refresh (CBR) or selfrefresh can be selected. When no refresh is performed, the refresh timer counter (RTCNT) can be used as an 8-bit interval timer. CAS-Before-RAS Refresh (CBR): A refresh is performed at an interval determined by the input clock selected with clock select bits 2-0 (CKS2-CKS0) in the refresh timer control/status register (RTCSR) and the value set in the refresh time constant register (RTCOR). Set the values of RTCOR and CKS2-CKS0 so they satisfy the refresh interval specifications of the DRAM being used. To perform a CBR refresh, clear the RMODE bit in RCR to 0 and then set the refresh control bit (RFSHE) bit to 1. Also write the required values to RTCNT and RTCOR. When the clock is subsequently selected with the CKS2-CKS0 bits in RTCSR, RTCNT will begin to increment from its current value. The RTCNT value is constantly compared with the RTCOR value and a CBR Rev. 7.00 Jan 31, 2006 page 158 of 658 REJ09B0272-0700 Section 8 Bus State Controller (BSC) refresh is performed when they match. RTCNT is simultaneously cleared to H'00 and incrementing begins again. When the clock is selected with the CKS2-CKS0 bits, RTCNT immediately begins to increment from its current value. This means that when the RTCOR cycle is set after the CKS2-CKS0 bits are set, the RTCNT count may already be higher than the RTCOR cycle. When this occurs, the RTCNT will overflow once (from H'FF to H'00) and incrementing will start again. Since the CBR refresh will not be performed until the RTCNT again matches the RTCOR value, the initial refresh interval will be rather long. It is thus advisable to set the RTCOR cycle prior to setting the CKS2- CKS0 bits and start it incrementing. When CBR refresh control is being performed after use as an 8-bit interval timer, the RTCNT count value may be in excess of the refresh cycle. For this reason, clear RTCNT by writing H'00 before starting refresh control to assure a correct refresh interval. When the RW1 bit in WCR1 is set to 1 and the read cycle is set to long pitch, the number of wait states selected by the RLW1 and RLW0 bits in RCR will be inserted into the CBR refresh cycle, regardless of the status of the WAIT signal. Figure 8.29 shows RTCNT operation and figure 8.30 shows the timing of the CBR refresh. For details on timing, see sections 20.1.3 (3) and 20.2.3 (3), Bus Timing. RTCNT value RTCOR value Compare match with RTCOR Compare match with RTCOR Compare match with RTCOR Compare match with RTCOR H'00 Time Clock CBR selected with CKS2-CKS0 CBR CBR CBR CBR: CAS-before-RAS refresh Figure 8.29 Refresh Timer Counter (RTCNT) Operation TRp TRr TRc CK RAS CAS Figure 8.30 Output Timing for CAS-Before-RAS Refresh Signal Rev. 7.00 Jan 31, 2006 page 159 of 658 REJ09B0272-0700 Section 8 Bus State Controller (BSC) Self-Refresh Mode: Some DRAMs have a self-refresh mode (battery back-up mode). This is a type of a standby mode in which the refresh timing and refresh addresses are generated inside the DRAM chip. When the RFSHE and RMODE bits in RCR are both set to 1, the DRAM will enter self-refresh mode when the CAS and RAS signals are output as shown in figure 8.31. See sections 20.1.3 (3) and 20.2.3 (3), Bus Timing, for details. DRAM self-refresh mode is cleared when the RMODE bit in RCR is cleared to 0 (figure 8.31). The RFSHE bit should be left at 1 when this is done. Some DRAM vendors recommend that after exiting self-refresh mode, all row addresses should be refreshed again. This can be done using the BSC's CBR refresh function to set all row addresses for refresh in software. To access a DRAM area while in self-refresh mode, first clear the RMODE bit to 0 and exit selfrefresh mode. The chip can be kept in the self-refresh state and shifted to standby mode by setting it to selfrefresh mode, setting the standby bit (SBY) in the standby control register (SBYCR) to 1, and then executing a SLEEP instruction. TRp TRr TRc TRcc CK RAS CAS Figure 8.31 Output Timing for Self-Refresh Signal Refresh Requests and Bus Cycle Requests: When a CAS-before-RAS refresh or self-refresh is requested during bus cycle execution, parallel execution is sometimes possible. Table 8.11 summarizes the operation when refresh and bus cycles are in contention. Rev. 7.00 Jan 31, 2006 page 160 of 658 REJ09B0272-0700 Section 8 Bus State Controller (BSC) Table 8.11 Refresh and Bus Cycle Contention Type of Bus Cycle External Space Access External Memory Space, Multiplexed I/O Space DRAM Space Type of Refresh Read Cycle Write Cycle Read Cycle Write Cycle On-Chip ROM, On-Chip RAM, On-Chip Supporting Module Access CAS-beforeRAS refresh Yes No No No Yes Self-refresh Yes Yes No No Yes Yes: Can be executed in parallel No: Cannot be executed in parallel When parallel execution is possible, the RAS and CAS signals are output simultaneously during bus cycle execution and the refresh is executed. When parallel execution is not possible, the refresh occurs after the bus cycle has ended. Using RTCNT as an 8-Bit Interval Timer: When not performing refresh control, RTCNT can be used as an 8-bit interval timer. Simply set the RFSHE bit in RCR to 0. To produce a compare match interrupt (CMI), set the compare match interrupt enable bit (CMIE) to 1 and set the interrupt generation timing in RTCOR. When the input clock is selected with the CKS2-CKS0 bits in RTCSR, RTCNT starts incrementing as an 8-bit interval timer. Its value is constantly compared with RTCOR, and when a match occurs, the CMF bit in RTCSR is set to 1 and a CMI interrupt is produced. RTCNT is cleared to H'00. When the clock is selected with the CKS2-CKS0 bits, RTCNT starts incrementing immediately. This means that when the RTCOR cycle is set after the CKS2-CKS0 bits are set, the RTCNT count may already be higher than the RTCOR cycle. When this occurs, the RTCNT will overflow once (H'FF goes to H'00) and the count up will start again. No interrupt will be generated until the RTCNT again matches the RTCOR value. It is thus advisable to set the RTCOR cycle prior to setting the CKS2-CKS0 bits. After its use as an 8-bit interval timer, the RTCNT count value may be in excess of the set cycle. For this reason, write H'00 to the RTCNT to clear it before starting to use it again with new settings. RTCNT can then be restarted and an interrupt obtained after the correct interval. Rev. 7.00 Jan 31, 2006 page 161 of 658 REJ09B0272-0700 Section 8 Bus State Controller (BSC) 8.6 Address/Data Multiplexed I/O Space Access The BSC is equipped with a function that multiplexes address and data input/output on pins AD15-AD0 in area 6. This allows the SH microprocessor to be directly connected to peripheral chips that require address/data multiplexing. 8.6.1 Basic Timing When the multiplexed I/O enable bit (IOE) in BCR is set to 1, the area 6 space with address bit A27 as 0 (H'6000000-H'6FFFFFF) becomes an address/data multiplexed I/O space that, when accessed, multiplexes addresses and data. When the A14 address bit is 0, the bus width is 8 bits and address output and data input/output are performed on the AD7-AD0 pins. When the A14 address bit is 1, the bus width is 16 bits and address output and data input/output are performed on the AD15-AD0 pins. In the address/data multiplexed I/O space, access is controlled with the AH, RD, and WR signals. Accesses in the address/data multiplexed I/O space are performed in 4 states, regardless of the WCR settings. Figure 8.32 shows the timing when the address/data multiplexed I/O space is accessed. T1 T2 T3 T4 CK A21-A0 CS AH RD Read AD15-AD0 Address Data (input) Address Data (output) WRH, WRL Write AD15-AD0 Figure 8.32 Access Timing For Address/Data Multiplexed I/O Space Rev. 7.00 Jan 31, 2006 page 162 of 658 REJ09B0272-0700 Section 8 Bus State Controller (BSC) A high-level duty of 35% or 50% can be selected for the RD signal using the RD duty bit (RDDTY) in BCR. When RDDTY is 1, the high-level duty is 35% of the T3 or Tw state, lengthening the access time for external devices. 8.6.2 Wait State Control When the address/data multiplexed I/O space is accessed, the WAIT pin input signal is sampled and a wait state inserted whenever a low level is detected, regardless of the WCR setting. Figure 8.33 shows an example in which a WAIT signal causes one wait state to be inserted. T1 T2 T3 Tw (wait state) T4 CK A21-A0 CS AH RD Read AD15-AD0 Address Data (input) WRH, WRL Write AD15-AD0 Address Data (output) WAIT Figure 8.33 Wait State Timing For Address/Data Multiplexed I/O Space Access Rev. 7.00 Jan 31, 2006 page 163 of 658 REJ09B0272-0700 Section 8 Bus State Controller (BSC) 8.6.3 Byte Access Control The byte access control signals when the address/data multiplexed I/O space is being accessed are of two types (WRH, WRL, A0, or WR, HBS, LBS), just as for byte access control of external memory space access. These types can be selected using the BAS bit in BCR. See section 8.4.3, Byte Access Control, for details. 8.7 Parity Check and Generation The BSC can check and generate parity for data input and output to or from the DRAM space of area 1 and the external memory space of area 2. To check and generate parity, select the space (DRAM space only, or DRAM space and area 2) for which parity is to be checked and generated using the parity check enable bits (PCHK1 and PCHK0) in the parity control register, and select odd or even parity with the parity polarity bit (PEO). When data is input from the space selected with the PCHK1 and PCHK0 bits, the BSC checks the PEO bit to see if the polarity of the DPH pin input (upper byte parity data) is accurate for the AD15-AD8 pin input (upper byte data) or if the DPL pin input (lower byte parity data) is accurate for the AD7-AD0 pin input (lower byte data). If the check indicates that either the upper or lower byte parity is incorrect, a parity error interrupt is produced (PEI). When outputting data to the space selected with the PCHK1 and PCHK0 bits, the BSC outputs parity data output of the polarity set in the PEO bit from the DPH pin for the AD15-AD8 pin output (upper byte data) or from the DPL pin for the AD7-AD0 pin input (lower byte data) using the same timing as the data output. The BSC is also able to force parity output for use in testing the system's parity error check function. When the parity force output bit (PFRC) in PCR is set to 1, a high level is forcibly output from the DPH and DPL pins when data is output to the space selected with the PCHK1 and PCHK0 bits. Rev. 7.00 Jan 31, 2006 page 164 of 658 REJ09B0272-0700 Section 8 Bus State Controller (BSC) 8.8 Warp Mode In warp mode, an external write cycle or DMA single address mode transfer cycle and an internal access cycle (read/write to on-chip memory or on-chip supporting modules) operate independently and in parallel. Warp mode is entered by setting the warp mode bit (WARP) in BCR to 1. This allows the chip to be operated at high speed. When, in warp mode, an external write cycle or DMA single address mode transfer cycle continues for at least 2 states and there is an internal access, only the external write cycle will be performed in the initial state. The external write cycle and internal access cycle will be performed in parallel from the next state on, without waiting for the end of the external write cycle. Figure 8.34 shows the timing when an access to an on-chip supporting module and an external write cycle are performed in parallel. Rev. 7.00 Jan 31, 2006 page 165 of 658 REJ09B0272-0700 Section 8 Bus State Controller (BSC) External space writing On-chip peripheral module read/write T1 T2 T3 T4 T5 CK A21- A0 External space write External space address CSn WR AD15- AD0 Write data External space address Internal address On-chip supporting module write On-chip supporting module read On-chip supporting module address Internal write strobe Internal data bus Write data Internal read strobe Internal data bus Read data Figure 8.34 Warp Mode Timing (Access to On-Chip Supporting Module and External Write Cycle) 8.9 Wait State Control The WCR1-WCR3 registers of the BSC can be set to control sampling of the WAIT signal when accessing various areas, and the number of bus cycle states. Table 8.12 shows the number of bus cycle states when accessing various areas. Rev. 7.00 Jan 31, 2006 page 166 of 658 REJ09B0272-0700 Section 8 Bus State Controller (BSC) Table 8.12 Bus Cycle States when Accessing Address Spaces CPU Read Cycle, DMAC Dual Mode Read Cycle, DMAC Single Mode Memory Read/Write Cycle Address Space Corresponding Bits in WCR1 and WCR2 = 0 External memory (areas 1, 3-5, 7) 1 state fixed; WAIT signal ignored Corresponding Bits in WCR1 and WCR2 = 1 2 states + wait states from WAIT signal External memory (Areas 0, 2, 6; long wait avail-able) 1 state + long wait state*, WAIT signal ignored 1 state + long wait state* + wait states from WAIT signal DRAM space (area 1) Column address cycle: 1 state, WAIT signal ignored (short pitch) Column address cycle: 2 states + wait states from WAIT signal (long pitch) Multiplexed I/O space (area 6) 4 states + wait states from WAIT signal On-chip supporting module space (area 5) 3 states fixed, WAIT signal ignored On-chip ROM (area 0) 1 state fixed, WAIT signal ignored On-chip RAM (area 7) 1 state fixed, WAIT signal ignored CPU Write Cycle, DMAC Dual Mode Memory Write Cycle (WW1 of WCR1) Address Space WW1 of WCR1=0 WW1 of WCR1=1 External memory (area 1) Setting prohibited 2 states + wait state from WAIT signal External memory (areas 3-5, 7) 2 states + wait states from WAIT signal External memory (Areas 0, 2, 6; long wait available) 1 state + long wait state* + wait states from WAIT signal DRAM space (area 1) Column address cycle: 1 state, WAIT signal ignored (short pitch) Multiplexed I/O space (area 6) 4 states + wait states from WAIT signal On-chip peripheral module space (area 5) 3 states fixed, WAIT signal ignored On-chip ROM (area 0) 1 state fixed, WAIT signal ignored On-chip RAM (area 7) 1 state fixed, WAIT signal ignored Column address cycle: 2 states + wait states from WAIT signal (long pitch) Note: * The number of long wait states (1 to 4) is set in WCR3. Rev. 7.00 Jan 31, 2006 page 167 of 658 REJ09B0272-0700 Section 8 Bus State Controller (BSC) For details on bus cycles when external spaces are accessed, see section 8.4, Accessing External Memory Space, section 8.5, DRAM Interface Operation, and section 8.6, Address/Data Multiplexed I/O Space Access. Accesses to on-chip spaces are as follows: On-chip supporting module spaces (area 5 when address bit A27 is 1) are always 3-state access spaces, regardless of WCR, with no WAIT signal sampling. Accesses to on-chip ROM (area 0 when MD2-MD0 are 010) and on-chip RAM (area 7 when address bit A27 is 0) are always performed in 1 state, regardless of WCR, with no WAIT signal sampling. If the bus timing specifications (tWTS and tWTH) are not observed when the WAIT signal is input in external space access, this will simply mean that WAIT signal assertion and negation will not be detected, but will not result in misoperation. Note, however, that the inability to detect WAIT signal assertion may result in a problem with memory access due to insertion of an insufficient number of waits. Rev. 7.00 Jan 31, 2006 page 168 of 658 REJ09B0272-0700 Section 8 Bus State Controller (BSC) 8.10 Bus Arbitration The SuperH microcomputer can release the bus to external devices when they request the bus. It has two internal bus masters, the CPU and the DMAC. Priorities for releasing the bus for these two are as follows. Bus request from external device > refresh > DMAC > CPU Thus, an external device has priority when it generates a bus request, even when the DMAC is carrying out a burst transfer. Note that when a refresh request is generated while the bus is released to an external device, BACK goes high and the bus can be acquired to perform refreshing upon receipt of a BREQ = high response from the external device. Input all bus requests from external devices to the BREQ pin. The signal indicating that the bus has been released is output from the BACK pin. Figure 8.35 illustrates the bus release procedure. External device SuperH BREQ = low Bus request BREQ received Strobe pin: High-level output Address, data, strobe pin: High impedance Bus release response BACK = low BACK acknowledge Bus acquisition Bus released Figure 8.35 Bus Release Procedure Rev. 7.00 Jan 31, 2006 page 169 of 658 REJ09B0272-0700 Section 8 Bus State Controller (BSC) 8.10.1 Operation of Bus Arbitration If there is conflict between bus arbitration and refreshing, the operation is as follows. 1. If DRAM refreshing is requested in this chip when the bus is released and BACK is low, BACK goes high and the occurrence of the refresh request can be indicated externally. At this time, the external device may generate a bus cycle when BREQ is low even if BACK is high. Therefore, the bus remains released to the external device. Then, when BREQ goes high, this chip acquires bus ownership, and executes a refresh and the bus cycle of the CPU or DMAC. After the external device acquires bus ownership and BACK is low, a refresh is requested when BACK goes high even if BREQ input is low. Therefore, drive BREQ high immediately to release the bus for this chip to hold DRAM data (see figure 8.36). 2. When BREQ changes from high to low and an internal refresh is requested at the timing of bus release by this chip, BACK may remain high. The bus is released to the external device since BREQ input is low. This operation is based on the above specification (1). To hold DRAM data, drive BREQ high and release the bus to this chip immediately when the external device detects that BACK does not change to low during a fixed time (see figure 8.37). When a refresh request is generated and BACK returns to high, as shown in figure 8.37, a momentary narrow pulse-shaped spike may be output where BACK was originally supposed to go low. BREQ BACK Refresh execution Refresh demand Figure 8.36 BACK Operation in Response to Refresh Demand (1) Rev. 7.00 Jan 31, 2006 page 170 of 658 REJ09B0272-0700 Section 8 Bus State Controller (BSC) If BACK has not gone low after waiting for the maximum number of states* before the SuperH releases the bus, return BREQ to the high level. BREQ BACK BACK does not go low. Refresh request Note: * For details see section 8.11.3, Maximum Number of States from BREQ Input to Bus Release. Figure 8.37 BACK Operation in Response to Refresh Request (2) 3. If a refresh request is generated during DMA transfer in burst mode, the DMA transfer is halted and a refresh is executed. 8.10.2 BACK Operation 1. BACK operation When an internal refresh is requested during an attempt to assert the BACK signal and BACK is not asserted but remains high, a momentary narrow pulse-shaped spike may be output, as shown below. BREQ BACK Spike pulse width is approx. 2 to 5 ns. Refresh demand 2. Preventing spikes in the BACK signal The following measures should be taken to prevent spikes in the BACK signal: a. When BREQ is input to release the bus, make sure that a conflict with a refresh operation does not occur. Stop the refresh operation or operate the refresh timer counter (RTCNT) or the refresh time constant register (RTCOR) of the bus controller (BSC) to shift the refresh timing. b. A spike in the BACK signal has a narrow pulse width of approximately 2 to 5 ns, which can be eliminated by using a capacitor as shown in the figure below. Rev. 7.00 Jan 31, 2006 page 171 of 658 REJ09B0272-0700 Section 8 Bus State Controller (BSC) For example, adding a capacitance of 220 pF can raise the minimum voltage of the spike above 2.0 V. Note that delay of the BACK signal increases in units of approximately 0.1 ns/pF. (When a capacitance of 220 pF is added, the delay increases by approximately 22 ns.) BACK C SuperH Microcomputer Circuit with capacitor for eliminating spikes c. Latching the BACK signal by using a flip-flop or triggering the flip-flop may or may not be successful due to the narrow pulse width of the spike. Implement a circuit configuration which will cause no problems when latching BACK or using BACK as a trigger signal. When splitting the BACK signal into two signals and latching each of them using a flipflop or triggering the flip-flop, the flip-flop may operate for one signal but not for the other. To capture the BACK signal using a flip-flop, receive the BACK signal using a single flipflop then distribute the signal (see figure below). Trigger OK D Q BACK Q Trigger NG D Q BACK Q D Q Q 8.11 Usage Notes 8.11.1 Usage Notes on Manual Reset Condition: When DRAM (long-pitch mode) is used and a manual reset is performed. Rev. 7.00 Jan 31, 2006 page 172 of 658 REJ09B0272-0700 Section 8 Bus State Controller (BSC) The low width of RAS output may be shorter than usual in a reset (2.5 tcyc 1.5 tcyc), preventing the specified value (tRAS) of DRAM from being satisfied. Corresponding DRAM conditions: Long-pitch/normal mode Long-pitch/high-speed page mode There are no problems regarding operations except for the above conditions. There are the following four cases (figures 8.38 to 8.41) for the output states of DRAM control signals (RAS, CAS, and WR) corresponding to RES latch timing. Actual output levels are shown by solid lines (not by dashed lines). Tp RES latch timing Tr Tc1 Tc2 CK RES Manual reset A0-A21 Row address Column address FFFF RAS CAS WR AD0-AD15 Data output Figure 8.38 Long-Pitch Mode Write (1) RES latch timing Tp Tr Tc1 Tc2 CK RES A0-A21 Manual reset Row address FFFF RAS CAS WR AD0-AD15 Data output Figure 8.39 Long-Pitch Mode Write (2) Rev. 7.00 Jan 31, 2006 page 173 of 658 REJ09B0272-0700 Section 8 Bus State Controller (BSC) Tp RES latch timing Tr Tc1 Tc2 CK RES Manual reset A0-A21 Row address Column address FFFF RAS CAS RD Figure 8.40 Long-Pitch Mode Read (1) Tp RES latch timing Tr Tc1 Tc2 CK RES Manual reset A0-A21 Row address FFFF RAS CAS RD Figure 8.41 Long-Pitch Mode Read (2) For the signal output shown by solid lines, DRAM data may not be held. Therefore, when DRAM data must be held after a reset, take one of the measures described below. 1. When resetting manually, use the watchdog timer (WDT) reset function. 2. Even if the low width of RAS becomes as short as 1.5 tcyc as shown above, use with a frequency that satisfies the DRAM standard (tRAS). 3. Even if the low width of RAS is 1.5 tcyc, use an external circuit so that a RAS signal with a low width of 2.5 tcyc is input in the DRAM (if the low width of RAS is higher than 2.5 tcyc, operate so that the current waveform is input in the DRAM). These measures are not required when DRAM data is initialized or loaded again after a manual reset. Rev. 7.00 Jan 31, 2006 page 174 of 658 REJ09B0272-0700 Section 8 Bus State Controller (BSC) 8.11.2 Usage Notes on Parity Data Pins DPH and DPL The following specifies the setup time, tDS, of parity data DPH and DPL with respect to the fall of the CAS signal when parity data DPH and DPL are written to DRAM in long-pitch mode (early write). Table 8.13 Setup Time of Parity Data DPH and DPL Item Symbol Min Data setup time with respect to CAS (for only DPH and DPL in long-pitch mode) tDS -5ns Therefore, when writing parity data DPH and DPL to the DRAM in long-pitch mode, delay the WRH and WRL signals of this chip and used delayed writing. Normal data is also delay-written, but this is not a problem. SuperH Microcomputer RAS RAS CAS CAS OE RD WRH or WRL *1 *1 CK Notes: 1. 2. DRAM D *2 Q DWRH or DWRL WE Q To prevent signal racing Negative edge latch Figure 8.42 Delayed-Write Control Circuit 8.11.3 Maximum Number of States from BREQ Input to Bus Release The maximum number of states from BREQ input to bus release is: Maximum number of states for which bus is not released + approx. 4.5 states Note: Breakdown of approx. 4.5 states: 1.5 states: Until BACK output after end of bus cycle 1 state (min.): tBACD1 1 state (max.): tBRQS 1 state: Sampling in 1 state before end of bus cycle BREQ is sampled one state before the bus cycle. If BREQ is input without satisfying tBRQS, the bus is released after executing cycle B following the end of bus cycle A, as shown in figure 8.43. Rev. 7.00 Jan 31, 2006 page 175 of 658 REJ09B0272-0700 Section 8 Bus State Controller (BSC) The maximum number of states from BREQ input to bus release are used when B is a cycle comprising the maximum number of states for which the bus is not released; the number of states is the maximum number of states for which bus is not released + approx. 4.5 states. The maximum number of states for which the bus is not released requires careful investigation. CK Bus cycle A B BREQ tBACD1 tBRQS BACK Bus release Figure 8.43 When BREQ is Input without Satisfying tBRQS 1. Cycles in which bus is not released a. One bus cycle The bus is never released during one bus cycle. For example, in the case of a longword read (or write) in 8-bit ordinary space, one bus cycle consists of 4 memory accesses to 8-bit ordinary space, as shown in figure 8.44. The bus is not released between these accesses. Assuming one memory access to require 2 states, the bus is not released for a period of 8 states. 8 bits 8 bits 8 bits 8 bits Cycle during which bus is not released Figure 8.44 One Bus Cycle b. TAS instruction read cycle and write cycle The bus is never released during a TAS instruction read cycle and write cycle (figure 8.45). The TAS instruction read cycle and write cycle should be regarded as one bus cycle during which the bus is not released. Read cycle Write cycle Cycle during which bus is not released (1 bus cycle) Figure 8.45 TAS Instruction Read Cycle and Write Cycle Rev. 7.00 Jan 31, 2006 page 176 of 658 REJ09B0272-0700 Section 8 Bus State Controller (BSC) c. Refresh cycle + bus cycle The bus is never released during a refresh cycle and the following bus cycle ((a) or (b) above)) (figure 8.46). Refresh cycle 1 bus cycle Cycle during which bus is not released Figure 8.46 Refresh Cycle and Following Bus Cycle 2. Bus release procedure The bus release procedure is shown in figure 8.47. Figure 8.47 shows the case where BREQ is input one state before the break between bus cycles so that tBRQS is satisfied. In the SH7032 and SH7034, the bus is released after the bus cycle in which BREQ is input (if BREQ is input between bus cycles, after the bus cycle starting next). CK tBRQS tBRQS BREQ tBACD1 tBACD2 BACK tBZD RD, WR RAS, CAS CSn tBZD A21 to A0 Bus cycle Bus release Strobe pin: high-level output Bus cycle Address & data strobe pins: high impedance The bus is released after the bus cycle in which BREQ is input (if BREQ is input between bus cycles, after the bus cycle starting next). Bus cycle restart Figure 8.47 Bus Release Procedure Rev. 7.00 Jan 31, 2006 page 177 of 658 REJ09B0272-0700 Section 8 Bus State Controller (BSC) Rev. 7.00 Jan 31, 2006 page 178 of 658 REJ09B0272-0700 Section 9 Direct Memory Access Controller (DMAC) Section 9 Direct Memory Access Controller (DMAC) 9.1 Overview The SuperH microcomputer chip includes a four-channel direct memory access controller (DMAC). The DMAC can be used in place of the CPU to perform high speed transfers between external devices that have DACK (transfer request acknowledge signal), external memory, memory-mapped external devices, on-chip memory, and on-chip supporting modules (excluding the DMAC itself). Using the DMAC reduces the burden on the CPU and increases overall operating efficiency. 9.1.1 Features The DMAC has the following features. * Four channels * Four Gbytes of address space in the architecture * Byte or word selectable as data transfer unit * 65536 transfers (maximum) * Single address mode transfers (channels 0 and 1): Either the transfer source or transfer destination (peripheral device) is accessed by a DACK signal (selectable) while the other is accessed by address. One transfer unit of data is transferred in each bus cycle. Device combinations for which transfer is possible: External device with DACK and memory-mapped external device (including external memories) External device with DACK and memory-mapped external memory * Dual address mode transfer (channels 0-3): Both the transfer source and transfer destination are accessed by address. One transfer unit of data is transferred in 2 bus cycles. Device combinations for which transfer is possible: Two external memories External memory and memory-mapped external device Two memory-mapped devices External memory and on-chip memory Memory-mapped external device and on-chip supporting module (excluding the DMAC) External memory and on-chip memory Memory-mapped external device and on-chip supporting module (excluding the DMAC) Two on-chip memories Rev. 7.00 Jan 31, 2006 page 179 of 658 REJ09B0272-0700 Section 9 Direct Memory Access Controller (DMAC) On-chip memory and on-chip supporting module (excluding the DMAC) Two on-chip supporting modules (excluding the DMAC) * Transfer requests External request (From DREQ pins (channels 0 and 1 only). DREQ can be detected either by edge or by level) Requests from on-chip supporting modules (serial communication interface (SCI), A/D converter (A/D), and 16-bit integrated timer pulse unit (ITU)) Auto-request (the transfer request is generated automatically within the DMAC) * Selectable bus modes: Cycle-steal mode or burst mode * Selectable channel priority levels: Fixed, round-robin, or external-pin round-robin modes * CPU can be asked for interrupt when data transfer ends * Maximum transfer rate 20 M words/s (320 MB/s) For 5 V and 20 MHz Bus mode: Burst mode Transmission size: Word Rev. 7.00 Jan 31, 2006 page 180 of 658 REJ09B0272-0700 Section 9 Direct Memory Access Controller (DMAC) 9.1.2 Block Diagram Figure 9.1 shows a block diagram of the DMAC. On-chip ROM On-chip RAM On-chip supporting module SARn Register control DREQ0, DREQ1 ITU SCI A/D converter Start-up control TCRn CHCRn DMAC module bus Iteration control Internal bus Peripheral bus DARn DMAOR Request priority control DACK0, DACK1 DEIn External RAM External device (memorymapped) External device (with acknowledge) External bus External ROM Bus interface DMAC Bus controller DMAOR: DMA operation register SARn: DMA source address register DARn: DMA destination address register TCRn: DMA transfer count register CHCRn: DMA channel control register DEIn: DMA transfer-end interrupt request to CPU n: 0-3 Figure 9.1 Block Diagram of DMAC Rev. 7.00 Jan 31, 2006 page 181 of 658 REJ09B0272-0700 Section 9 Direct Memory Access Controller (DMAC) 9.1.3 Pin Configuration Table 9.1 shows the DMAC pins. Table 9.1 Pin Configuration Channel Name Symbol I/O Function 0 DMA transfer request DREQ0 I DMA transfer request input from external device to channel 0 DMA transfer request acknowledge DACK0 O DMA transfer request acknowledge output from channel 0 to external device DMA transfer request DREQ1 I DMA transfer request input from external device to channel 1 DMA transfer request acknowledge DACK1 O DMA transfer request acknowledge output from channel 1 to external device 1 Rev. 7.00 Jan 31, 2006 page 182 of 658 REJ09B0272-0700 Section 9 Direct Memory Access Controller (DMAC) 9.1.4 Register Configuration Table 9.2 summarizes the DMAC registers. The DMAC has a total of 17 registers. Each channel has four control registers. One other control register is shared by all channels. Table 9.2 DMAC Registers Channel Name Abbreviation R/W 0 SAR0* 1 2 3 DMA source address register 0 Initial Value Address* Access Size 4 3 R/W Undefined H'5FFFF40 16, 32 3 R/W Undefined H'5FFFF44 16, 32 DMA destination address register 0 DAR0* DMA transfer count register 0 TCR0* R/W Undefined H'5FFFF4A 16, 32 DMA channel control register 0 CHCR0 R/(W)* H'0000 H'5FFFF4E 8, 16, 32 DMA source address register 1 3 R/W Undefined H'5FFFF50 16, 32 3 R/W Undefined H'5FFFF54 16, 32 3 SAR1* 1 DMA destination address register 1 DAR1* DMA transfer count register 1 TCR1* R/W Undefined H'5FFFF5A 16, 32 DMA channel control register 1 CHCR1 R/(W)* H'0000 H'5FFFF5E 8, 16, 32 DMA source address register 2 3 R/W Undefined H'5FFFF60 16, 32 3 R/W Undefined H'5FFFF64 16, 32 3 SAR2* 1 DMA destination address register 2 DAR2* DMA transfer count register 2 TCR2* R/W Undefined H'5FFFF6A 16, 32 DMA channel control register 2 CHCR2 R/(W)* H'0000 H'5FFFF6E 8, 16, 32 DMA source address register 3 3 R/W Undefined H'5FFFF70 16, 32 3 R/W Undefined H'5FFFF74 16, 32 3 SAR3* 1 DMA destination address register 3 DAR3* DMA transfer count register 3 TCR3* R/W DMA channel control register 3 CHCR3 R/(W)* Shar- DMA operation register ed 3 DMAOR Undefined H'5FFFF7A 16, 32 1 H'0000 H'5FFFF7E 8, 16, 32 2 H'0000 H'5FFFF48 8, 16, 32 R/(W)* Notes: 1. Only 0 can be written in bit 1 of CHCR0-CHCR3, to clear flags. 2. Only 0 can be written in bits 1 and 2 of DMAOR, to clear flags. 3. Access SAR0-SAR3, DAR0-DAR3, and TCR0-TCR3 by longword or word. If byte access is used when writing, the value of the register contents will be undefined; if used when reading, the value read will be undefined. 4. Only the values of bits A27-A24 and A8-A0 are valid; bits A23-A9 are ignored. For details on the register addresses, see section 8.3.5, Area Descriptions. Rev. 7.00 Jan 31, 2006 page 183 of 658 REJ09B0272-0700 Section 9 Direct Memory Access Controller (DMAC) 9.2 Register Descriptions 9.2.1 DMA Source Address Registers 0-3 (SAR0-SAR3) DMA source address registers 0-3 (SAR0-SAR3) are 32-bit read/write registers that specify the source address of a DMA transfer. During a DMA transfer, these registers indicate the next source address (in single-address mode, SAR is ignored in transfers from external devices with DACK to memory-mapped external devices or external memory). The initial value after a reset or in standby mode is undefined. Bit 31 30 29 28 27 26 25 24 Initial value -- -- -- -- -- -- -- -- Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Bit 23 22 21 Initial value -- -- -- ... -- Read/Write R/W R/W R/W ... R/W ... 0 ... 9.2.2 DMA Destination Address Registers 0-3 (DAR0-DAR3) DMA destination address registers 0-3 (DAR0-DAR3) are 32-bit read/write registers that specify the destination address of a DMA transfer. During a DMA transfer, these registers indicate the next destination address (in single-address mode, DAR is ignored in transfers from memorymapped external devices or external memory to external devices with DACK). The initial value after a reset or in standby mode is undefined. Bit 31 30 29 28 27 26 25 24 Initial value -- -- -- -- -- -- -- -- Read/Write R/W R/W R/W R/W R/W R/W R/W R/W 23 22 21 Bit ... 0 ... Initial value -- -- -- ... -- Read/Write R/W R/W R/W ... R/W Rev. 7.00 Jan 31, 2006 page 184 of 658 REJ09B0272-0700 Section 9 Direct Memory Access Controller (DMAC) 9.2.3 DMA Transfer Count Registers 0-3 (TCR0-TCR3) DMA transfer count registers 0-3 (TCR0-TCR3) are 16-bit read/write registers that specify the DMA transfer count (bytes or words). The number of transfers is 1 when the setting is H'0001, 65535 when the setting is H'FFFF, and 65536 (the maximum) when H'0000 is set. During a DMA transfer, these registers indicate the remaining transfer count. The initial value after a reset or in standby mode is undefined. Bit 15 14 13 12 11 10 9 8 Initial value -- -- -- -- -- -- -- -- Read/Write R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 Bit Initial value -- -- -- -- -- -- -- -- Read/Write R/W R/W R/W R/W R/W R/W R/W R/W 9.2.4 DMA Channel Control Registers 0-3 (CHCR0-CHCR3) DMA channel control registers 0-3 (CHCR0-CHCR3) are 16-bit read/write registers that control the DMA transfer mode. They also indicate the DMA transfer status. They are initialized to H'0000 by a reset and in standby mode. Bit 15 14 13 12 11 10 9 8 DM1 DM0 SM1 SM0 RS3 RS2 RS1 RS0 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Bit Initial value Read/Write 7 6 5 4 3 2 1 0 AM AL DS TM TS IE TE DE 0 0 0 0 0 0 2 R/(W)* 0 2 R/(W)* 2 R/(W)* R/W R/W R/W 0 1 R/(W)* R/W Notes: 1. Only 0 can be written, to clear the flag. 2. Writing is valid only for CHCR0 and CHCR1. Rev. 7.00 Jan 31, 2006 page 185 of 658 REJ09B0272-0700 Section 9 Direct Memory Access Controller (DMAC) Bits 15 and 14--Destination Address Mode Bits 1 and 0 (DM1 and DM0): DM1 and DM0 select whether the DMA destination address is incremented, decremented, or left fixed (in the single address mode, DM1 and DM0 are ignored when transfers are made from memory-mapped external devices or external memory to external devices with DACK). DM1 and DM0 are initialized to 00 by a reset and in standby mode. Bit 15: DM1 Bit 14: DM0 Description 0 0 Fixed destination address 0 1 Destination address is incremented (+1 or +2 depending on whether the transfer size is word or byte) 1 0 Destination address is decremented (-1 or -2 depending on whether the transfer size is word or byte) 1 1 Reserved (illegal setting) (Initial value) Bits 13 and 12--source address mode bits 1, 0 (SM1 and SM0): SM1 and SM0 select whether the DMA source address is incremented, decremented, or left fixed (in the single address mode, SM1 and SM0 are ignored when transfers are made from external devices with DACK to memorymapped external devices or external memory). SM1 and SM0 are initialized to 00 by resets or in standby mode. Bit 13: SM1 Bit 12: SM0 Description 0 0 Fixed source address 0 1 Source address is incremented (+1 or +2 depending on if the transfer size is word or byte) 1 0 Source address is decremented (-1 or -2 depending on if the transfer size is word or byte) 1 1 Reserved (illegal setting) (Initial value) Bits 11-8--Resource Select Bits 3-0 (RS3-RS0): RS3-RS0 specify which transfer requests will be sent to the DMAC. Do not change the transfer request source unless the DMA enable bit (DE) is 0. The RS3-RS0 bits are initialized to 0000 by a reset and in standby mode. Rev. 7.00 Jan 31, 2006 page 186 of 658 REJ09B0272-0700 Section 9 Direct Memory Access Controller (DMAC) Bit 11: Bit 10: Bit 9: RS3 RS2 RS1 Bit 8: RS0 Description 0 0 0 0 DREQ (External request* , dual address mode) (Initial value) 0 0 0 1 Reserved (illegal setting) 0 0 1 0 DREQ (External request* , single address mode* ) 0 0 1 1 DREQ (External request* , single address mode* ) 0 1 0 0 RXI0 (On-chip serial communication interface 0 receive data 4 full interrupt transfer request)* 0 1 0 1 TXI0 (On-chip serial communication interface 0 transmit data 4 empty interrupt transfer request)* 0 1 1 0 RXI1 (On-chip serial communication interface 1 receive data 4 full interrupt transfer request)* 0 1 1 1 TXI1 (On-chip serial communication interface 1 transmit data 4 empty interrupt transfer request)* 1 0 0 0 IMIA0 (On-chip ITU0 input capture/compare match A interrupt 4 transfer request)* 1 0 0 1 IMIA1 (On-chip ITU1 input capture/compare match A interrupt 4 transfer request)* 1 0 1 0 IMIA2 (On-chip ITU2 input capture/compare match A interrupt 4 transfer request)* 1 0 1 1 IMIA3 (On-chip ITU3 input capture/compare match A interrupt 4 transfer request)* 1 1 0 0 Auto-request (Transfer requests automatically generated 4 within DMAC)* 1 1 0 1 ADI (A/D conversion end interrupt request of on-chip A/D 4 converter)* 1 1 1 0 Reserved (illegal setting) 1 1 1 1 Reserved (illegal setting) 1 1 2 1 3 SCI0, SCI1: Serial communication interface channels 0 and 1 ITU0-ITU3: Channels 0-3 of the 16-bit integrated timer pulse unit Notes: 1. These bits are valid only in channels 0 and 1. None of these request sources can be selected in channels 2 and 3. 2. Transfer from memory-mapped external device or external memory to external device with DACK. 3. Transfer from external device with DACK to memory-mapped external device or external memory. 4. Dual address mode. Rev. 7.00 Jan 31, 2006 page 187 of 658 REJ09B0272-0700 Section 9 Direct Memory Access Controller (DMAC) Bit 7--Acknowledge Mode Bit (AM): In dual address mode, AM selects whether the DACK signal is output during the data read cycle or write cycle. This bit is valid only in channels 0 and 1. The AM bit is initialized to 0 by a reset and in standby mode. The AM bit is not valid in single address mode. Bit 7: AM Description 0 DACK is output in read cycle 1 DACK is output in write cycle (Initial value) Bit 6--Acknowledge Level Bit (AL): AL selects active-high or active-low for the DACK signal. This bit is valid only in channels 0 and 1. The AL bit is initialized to 0 by a reset and in standby mode. Bit 6: AL Description 0 DACK is active-high 1 DACK is active-low (Initial value) Bit 5--DREQ DREQ Select Bit (DS): DS selects the DREQ input detection method used. This bit is valid only in channels 0 and 1. The DS bit is initialized to 0 by a reset and in standby mode. Bit 5: DS Description 0 DREQ detected by low level 1 DREQ detected by falling edge (Initial value) Bit 4--Transfer Bus Mode Bit (TM): TM selects the bus mode for DMA transfers. The TM bit is initialized to 0 by a reset and in standby mode. When the source of the transfer request is an onchip supporting module, see table 9.4, Selecting On-Chip Peripheral Module Request Modes with the RS Bits. Bit 4: TM Description 0 Cycle-steal mode 1 Burst mode Rev. 7.00 Jan 31, 2006 page 188 of 658 REJ09B0272-0700 (Initial value) Section 9 Direct Memory Access Controller (DMAC) Bit 3--Transfer Size Bit (TS): TS selects the transfer unit size. If the on-chip supporting module that is the source or destination of the transfer can only be accessed in bytes, byte must be selected with this bit. The TS bit is initialized to 0 by a resets and in standby mode. Bit 3: TS Description 0 Byte (8 bits) 1 Word (16 bits) (Initial value) Bit 2--Interrupt Enable Bit (IE): IE determines whether or not to request a CPU interrupt at the end of a DMA transfer. When the IE bit is set to 1, an interrupt (DEI) request is sent to the CPU when the TE bit is set. The IE bit is initialized to 0 by a reset and in standby mode. Bit 2: IE Description 0 Interrupt request disabled 1 Interrupt request enabled (Initial value) Bit 1--Transfer End Flag Bit (TE): TE indicates that the transfer has ended. When a DMA transfer ends normally and the value in the DMA transfer count register (TCR) becomes 0, the TE bit is set to 1. This flag is not set if the transfer ends because of an NMI interrupt or address error, or because the DE bit or the DME bit in the DMA operation register (DMAOR) was cleared. To clear the TE bit, read 1 from it and then write 0. When this flag is set, setting the DE bit to 1 does not enable a DMA transfer. The TE bit is initialized to 0 by a reset and in standby mode. Bit 1: TE Description 0 DMA has not ended or was aborted (Initial value) To clear TE, the CPU must read TE after it has been set to 1, then write a 0 in this bit 1 DMA has ended normally Bit 0--DMA Enable Bit (DE): DE enables or disables DMA transfers. In auto-request mode, the transfer starts when this bit or the DME bit in DMAOR is set to 1. The TE bit and the NMIF and AE bits in DMAOR must be all cleared to 0. In external request mode or on-chip supporting module request mode, the transfer begins when the DMA transfer request is received from a device or on-chip supporting module, provided this bit and the DME bit are set to 1. As with auto request mode, the TE bit and the NMIF and AE bits must be all cleared to 0. The transfer can be stopped by clearing this bit to 0. Rev. 7.00 Jan 31, 2006 page 189 of 658 REJ09B0272-0700 Section 9 Direct Memory Access Controller (DMAC) The DE bit is initialized to 0 by a reset and in standby mode. Bit 0: DE Description 0 DMA transfer disabled 1 DMA transfer enabled 9.2.5 (Initial value) DMA Operation Register (DMAOR) The DMA operation register (DMAOR) is a 16-bit read/write register that controls the DMA transfer mode. It also indicates the DMA transfer status. It is initialized to H'0000 by a reset and in standby mode. Bit 15 14 13 12 11 10 9 8 ---- -- -- -- -- -- PR1 PR0 Initial value 0 0 0 0 0 0 0 0 Read/Write R R R R R R R/W R/W Bit 7 6 5 4 3 2 1 0 -- -- -- -- -- AE NMIF DME Initial value 0 0 0 0 0 0 0 0 Read/Write R R R R R R/(W)* R/(W)* R/W Note: * Write only 0 to clear the flag. Bits 15-10--Reserved: These bits are always read as 0. The write value should always be 0. Bits 9 and 8--Priority Mode Bits 1 and 0 (PR1 and PR0): PR1 and PR0 select the priority level between channels when there are simultaneous transfer requests for multiple channels. Bit 9: PR1 Bit 8: PR0 Description 0 0 Fixed priority order (Ch. 0 > Ch. 3 > Ch. 2 > Ch. 1) (Initial value) 0 1 Fixed priority order (Ch. 1 > Ch. 3 > Ch. 2 > Ch. 0) 1 0 Round-robin mode priority order (the priority order immediately after a reset is Ch. 0 > Ch. 3 > Ch. 2 > Ch. 1) 1 1 External-pin round-robin mode priority order (the priority order immediately after a reset is Ch. 3 > Ch. 2 > Ch. 1 > Ch. 0) Bits 7-3--Reserved: These bits are always read as 0. The write value should always be 0. Rev. 7.00 Jan 31, 2006 page 190 of 658 REJ09B0272-0700 Section 9 Direct Memory Access Controller (DMAC) Bit 2--Address Error Flag Bit (AE): AE indicates that an address error has occurred in the DMAC. When this flag is set to 1, the channel cannot be enabled even if the DE bit in the DMA channel control register (CHCR) and the DME bit are set to 1. To clear the AE bit, read 1 from it and then write 0. It is initialized to 0 by a reset and in standby mode. Bit 2: AE Description 0 No DMAC address error (Initial value) To clear the AE bit, read 1 from it and then write 0 1 Address error by DMAC Bit 1--NMI Flag Bit (NMIF): NMIF indicates that an NMI interrupt has occurred. When this flag is set to 1, the channel cannot be enabled even if the DE bit in CHCR and the DME bit are set to 1. To clear the NMIF bit, read 1 from it and then write 0. It is initialized to 0 by a reset and in standby mode. Bit 1: NMIF Description 0 No NMI interrupt (Initial value) To clear the NMIF bit, read 1 from it and then write 0 1 NMI has occurred Bit 0--DMA Master Enable Bit (DME): DME enables or disables DMA transfers on all channels. A channel becomes enabled for a DMA transfer when the DE bit in each DMA's CHCR and the DME bit are set to 1. For this to be effective, however, the TE bit of each CHCR and the NMIF and AE bits must all be 0. When the DME bit is cleared, all channel DMA transfers are aborted. Bit 0: DME Description 0 DMA transfers disabled on all channels 1 DMA transfers enabled on all channels (Initial value) Rev. 7.00 Jan 31, 2006 page 191 of 658 REJ09B0272-0700 Section 9 Direct Memory Access Controller (DMAC) 9.3 Operation When there is a DMA transfer request, the DMAC starts the transfer according to the predetermined channel priority order; when the transfer end conditions are satisfied, it ends the transfer. Transfers can be requested in three modes: auto-request, external request, and on-chip module request. Transfer can be in either single address mode or dual address mode. The bus mode can be either burst or cycle steal. 9.3.1 DMA Transfer Flow After the DMA source address registers (SAR), DMA destination address registers (DAR), DMA transfer count registers (TCR), DMA channel control registers (CHCR), and DMA operation register (DMAOR) are set, the DMAC transfers data according to the following procedure: 1. Checks to see if transfer is enabled (DE = 1, DME = 1, TE = 0, NMIF = 0, AE = 0). 2. When a transfer request arrives and transfer is enabled, the DMAC transfers one transfer unit of data. (For an auto-request, the transfer begins automatically when the DE bit and DME bit are set to 1. The TCR value will be decremented by 1.) The actual transfer flows vary by address mode and bus mode. 3. When the specified number of transfer have been completed (when TCR reaches 0), the transfer ends normally. If the IE bit in CHCR is set to 1 at this time, a DEI interrupt is sent to the CPU. 4. When an address error occurs in the DMAC or an NMI interrupt is generated, the transfer is aborted. Transfers are also aborted when the DE bit in CHCR or the DME bit in DMAOR changes to 0. Figure 9.2 shows a flowchart of this procedure. Rev. 7.00 Jan 31, 2006 page 192 of 658 REJ09B0272-0700 Section 9 Direct Memory Access Controller (DMAC) Start Initial settings (SAR, DAR, TCR, CHCR, DMAOR) DE, DME = 1 and NMIF, AE, TE = 0? No Yes Transfer request occurs?*1 Yes *3 Transfer (1 transfer unit); TCR-1 TCR, SAR and DAR updated TCR = 0? Yes DEI interrupt request (when IE = 1) No Normal end Notes: *2 No No Bus mode, transfer request mode, DREQ detection selection system Does NMIF = 1, AE = 1, DE = 0, or DME = 0? Yes No Transfer aborted Does NMIF = 1, AE = 1, DE = 0, and DME = 0? Yes Transfer ends 1. In auto-request mode, transfer begins when NMIF, AE, and TE are all 0 and the DE and DME bits are set to 1. 2. DREQ = level detection in burst mode (external request), or cycle steal mode. 3. DREQ = edge detection in burst mode (external request), or auto request mode in burst mode. Figure 9.2 DMA Transfer Flowchart Rev. 7.00 Jan 31, 2006 page 193 of 658 REJ09B0272-0700 Section 9 Direct Memory Access Controller (DMAC) 9.3.2 DMA Transfer Requests DMA transfer requests are basically generated in either the data transfer source or destination, but they can also be generated by devices and on-chip supporting modules that are neither the source nor the destination. Transfers can be requested in three modes: auto-request, external request, and on-chip module request. The request mode is selected with the RS3-RS0 bits in the DMA channel control registers 0-3 (CHCR0-CHCR3). Auto-Request Mode: When there is no transfer request signal from an external source, as in a memory-to-memory transfer or a transfer between memory and an on-chip supporting module unable to request a transfer, the auto-request mode allows the DMAC to automatically generate a transfer request signal internally. When the DE bits in CHCR0-CHCR3 and the DME bit in DMAOR are set to 1, the transfer begins (so long as the TE bits in CHCR0-CHCR3 and the NMIF and AE bits in DMAOR are all 0). External Request Mode: In this mode a transfer is performed in response to a request signal (DREQ) of an external device. Choose one of the modes shown in table 9.3 according to the application system. When this mode is selected, if DMA transfer is enabled (DE = 1, DME = 1, TE = 0, NMIF = 0, AE = 0), a transfer is performed upon a request at the DREQ input. Choose to detect DREQ by either the falling edge or low level of the signal input with the DS bit in CHCR0- CHCR3 (DS = 0 specifies level detection, DS = 1 specifies edge detection). The source of the transfer request does not have to be the data transfer source or destination. Table 9.3 Selecting External Request Modes with the RS Bits RS3 RS2 RS1 RS0 Address Mode Source Destination 0 0 0 0 Dual address mode Any* Any* 0 0 1 0 Single address mode External memory or memory-mapped external device External device with DACK 0 0 1 1 Single address mode External device with DACK External memory or memory-mapped external device Note: * External memory, memory-mapped external device, on-chip memory, on-chip supporting module (excluding DMAC) On-Chip Module Request: In this mode a transfer is performed in response to a transfer request signal (interrupt request signal) of an on-chip module. The transfer request signals include the receive data full interrupt (RXI) of the serial communication interface (SCI), the transmit data empty interrupt (TXI) of the SCI, the input capture A/compare match A interrupt request (IMIA) of the 16-bit integrated pulse timer (ITU), and the A/D conversion end interrupt (ADI) of the A/D Rev. 7.00 Jan 31, 2006 page 194 of 658 REJ09B0272-0700 Section 9 Direct Memory Access Controller (DMAC) converter (table 9.4). When this mode is selected, if DMA transfer is enabled (DE = 1, DME = 1, TE = 0, NMIF = 0, AE = 0), a transfer is performed upon input of a transfer request signal. The source of the transfer request does not have to be the data transfer source or destination. When RXI is set as the transfer request, however, the transfer source must be the SCI's receive data register (RDR). Likewise, when TXI is set as the transfer request, the transfer source must be the SCI's transmit data register (TDR). If the transfer request is from the A/D converter, the data transfer source must be an A/D converter register. Table 9.4 RS 3 RS 2 Selecting On-Chip Peripheral Module Request Modes with the RS Bits RS 1 RS 0 DMA Transfer Request Source DMA Transfer Request Signal RXI0 (SCI0 receive data full interrupt transfer request) Source Destination Bus Mode RDR0 Any* Cycle steal 0 1 0 0 SCI0 receiver 0 1 0 1 SCI0 TXI0 (SCI0 transmit data transmitter empty interrupt transfer request) Any TDR0 Cycle steal 0 1 1 0 SCI1 receiver RDR1 Any* Cycle steal 0 1 1 1 SCI1 TXI1 (SCI1 transmit data transmitter empty interrupt transfer request) Any* TDR1 Cycle steal 1 0 0 0 ITU0 IMIA0 (ITU0 input capture A/ compare match A) Any* Any* Burst/Cycl e steal 1 0 0 1 ITU1 IMIA1 (ITU1 input capture A/ compare match A) Any* Any* Burst/Cycl e steal 1 0 1 0 ITU2 IMIA2 (ITU2 input capture A/ compare match A) Any* Any* Burst/Cycl e steal 1 0 1 1 ITU3 IMIA3 (ITU3 input capture A/ compare match A) Any* Any* Burst/Cycl e steal 1 1 0 1 A/D converter ADI (A/D conversion end interrupt) ADDR Any Burst/Cycl e steal RXI1 (SCI1 receive data full interrupt transfer request) SCI0, SCI1: Serial communication interface channels 0 and 1 ITU0-ITU3: Channels 0-3 of the 16-bit integrated timer pulse unit RDR0, RDR1: Receive data registers 0, 1 of SCI TDR0, TDR1: Transmit data registers 0, 1 of SCI ADDR: A/D data register of A/D converter Note: * External memory, memory-mapped external device, on-chip memory, on-chip supporting module (excluding DMAC) Rev. 7.00 Jan 31, 2006 page 195 of 658 REJ09B0272-0700 Section 9 Direct Memory Access Controller (DMAC) When outputting transfer requests from on-chip supporting modules, the appropriate interrupt enable bits must be set to output the interrupt signals. Note that transfer request signals from onchip supporting modules (interrupt request signals) are sent not just to the DMAC but to the CPU as well. When an on-chip supporting module is specified as the transfer request source, set the priority level values in the interrupt priority level registers (IPRC-IPRE) of the interrupt controller (INTC) at or below the levels set in the I3-I0 bits of the CPU's status register (SR) so that the CPU does not acknowledge the interrupt request signal. The DMA transfer request signals in table 9.4 are automatically withdrawn when the corresponding DMA transfer is performed. If cycle steal mode is being used, the DMA transfer request (interrupt request) will be cleared at the first transfer; if burst mode is being used, it will be cleared at the last transfer. 9.3.3 Channel Priority When the DMAC receives simultaneous transfer requests on two or more channels, it selects a channel according to a predetermined priority order. The three modes (fixed mode, round-robin mode, and external-pin round-robin mode) are selected by priority bits PR1 and PR0 in the DMA operation register. Fixed Mode: In this mode, the priority levels among the channels remain fixed. When the PR1 and PR0 bits are set to 00, the priority order, high to low, is Ch. 0 > Ch. 3 > Ch. 2 > Ch. 1. When the PR1 and PR0 bits are set to 01, the priority order, high to low, is Ch. 1 > Ch. 3 > Ch. 2 > Ch. 0. Round-Robin Mode: Each time one word or byte is transferred on one channel, the priority order is rotated. The channel on which the transfer just finished rotates to the bottom of the priority order. When necessary, the priority order of channels other than the one that just finished the transfer can also be shifted to keep the relationship between the channels from changing (figure 9.3). The priority order immediately after a reset is channel 0 > channel 3 > channel 2 > channel 1. Rev. 7.00 Jan 31, 2006 page 196 of 658 REJ09B0272-0700 Section 9 Direct Memory Access Controller (DMAC) (1) When channel 0 transfers Initial priority order ch0 > ch3 > ch2 > ch1 Channel 0 becomes bottom priority Priority order after transfer ch3 > ch2 > ch1 > ch0 (2) When channel 3 transfers Initial priority order ch0 > ch3 > ch2 > ch1 Priority order after transfer Channel 3 becomes bottom priority. The priority of channel 0, which was higher than channel 3, is also shifted. ch2 > ch1 > ch0 > ch3 (3) When channel 2 transfers Initial priority order Priority order after transfer ch0 > ch3 > ch2 > ch1 ch1 > ch0 > ch3 > ch2 Priority order after transfer when there is an immediate transfer request for channel 3 only ch2 > ch1 > ch0 > ch3 Channel 2 becomes bottom priority. The priority of channels 0 and 3, which were higher than channel 2, are also shifted. If immediately thereafter there is a transfer request for channel 3 only, channel 3 becomes bottom priority and the priority of channels 0 and 1, which were higher than channel 3, are also shifted. (4) When channel 1 transfers Initial priority order ch0 > ch3 > ch2 > ch1 Priority order does not change Priority order after transfer ch0 > ch3 > ch2 > ch1 Figure 9.3 Round-Robin Mode Figure 9.4 shows how the priority order changes when channel 0 and channel 1 transfers are requested simultaneously and a channel 3 transfer is requested during the channel 0 transfer. The DMAC operates as follows: Rev. 7.00 Jan 31, 2006 page 197 of 658 REJ09B0272-0700 Section 9 Direct Memory Access Controller (DMAC) 1. Transfer requests are generated simultaneously for channels 1 and 0. 2. Channel 0 has a higher priority, so the channel 0 transfer begins first (channel 1 waits for transfer). 3. A channel 3 transfer request occurs during the channel 0 transfer (channels 1 and 3 are both waiting) 4. When the channel 0 transfer ends, channel 0 becomes the lowest priority. 5. At this point, channel 3 has a higher priority than channel 1, so the channel 3 transfer begins (channel 1 waits for transfer). 6. When the channel 3 transfer ends, channel 3 becomes the lowest priority. 7. The channel 1 transfer begins. 8. When the channel 1 transfer ends, channels 1 and 2 shift downward in priority so that channel 1 becomes the lowest priority. Transfer request Waiting channel(s) (1) Channels 0 and 1 DMAC operation Channel priority (2) Channel 0 transfer starts 0>3>2>1 1 (3) Channel 3 1, 3 (4) Channel 0 transfer ends Priority order changes 3>2>1>0 (5) Channel 3 transfer starts 1 (6) Channel 3 transfer ends Priority order changes 2>1>0>3 (7) Channel 1 transfer starts None (8) Channel 1 transfer ends Priority order changes 0>3>2>1 Figure 9.4 Changes in Channel Priority in Round-Robin Mode Rev. 7.00 Jan 31, 2006 page 198 of 658 REJ09B0272-0700 Section 9 Direct Memory Access Controller (DMAC) External-Pin Round-Robin Mode: External-pin round-robin mode switches the priority levels of channel 0 and channel 1, which are the channels that can receive transfer requests from external pins DREQ0 and DREQ1. The priority levels are changed after each (byte or word) transfer on channel 0 or channel 1 is completed. The channel which just finished the transfer rotates to the bottom of the priority order. The priority levels of channels 2 and 3 do not change. The initial priority order after a reset is channel 3 > channel 2 > channel 1 > channel 0. Figure 9.5 shows how the priority order changes when channel 0 and channel 1 transfers are requested simultaneously and a channel 0 transfer is requested again after both channels finish their transfers. The DMAC operates as follows: 1. Transfer requests are generated simultaneously for channels 1 and 0. 2. Channel 1 has a higher priority, so the channel 1 transfer begins first (channel 0 waits for transfer). 3. When the channel 1 transfer ends, channel 1 becomes the lowest priority. 4. The channel 0 transfer begins. 5. When the channel 0 transfer ends, channel 0 becomes the lowest priority. 6. A channel 0 transfer request occurs again. 7. The channel 0 transfer begins. 8. When the channel 0 transfer ends, the priority order does not change, because channel 0 is already the lowest priority. Rev. 7.00 Jan 31, 2006 page 199 of 658 REJ09B0272-0700 Section 9 Direct Memory Access Controller (DMAC) Transfer request Waiting channel(s) (1) Channels 0 and 1 DMAC operation Channel priority (2) Channel 1 transfer starts 3>2>1>0 0 (3) Channel 1 transfer ends Priority order changes 3>2>0>1 (4) Channel 0 transfer starts None (5) Channel 0 transfer ends (7) Channel 0 transfer starts (6) Channel 0 None (8) Channel 0 transfer ends Priority order changes 3>2>1>0 Waiting for transfer request Priority order does not change 3>2>1>0 Figure 9.5 Example of Changes in Priority in External-Pin Round-Robin Mode Rev. 7.00 Jan 31, 2006 page 200 of 658 REJ09B0272-0700 Section 9 Direct Memory Access Controller (DMAC) 9.3.4 DMA Transfer Types The DMAC supports the transfers shown in table 9.5. It can operate in single address mode or dual address mode, which are defined by how many bus cycles the DMAC takes to access the transfer source and transfer destination. The actual transfer operation timing varies with the bus mode. The DMAC has two bus modes: cycle-steal mode and burst mode. Table 9.5 Supported DMA Transfers Destination External Memory MemoryMapped External Device On-Chip Memory On-Chip Supporting Module Not available Single Single Not available Not available External memory Single Dual Dual Dual Dual Memory-mapped external device Single Dual Dual Dual Dual On-chip memory Not available Dual Dual Dual Dual On-chip supporting module Not available Dual Dual Dual Dual External Device with DACK External device with DACK Source Single: Single address mode Dual: Dual address mode Address Modes: * Single Address Mode In single address mode, both the transfer source and destination are external; one (selectable) is accessed by a DACK signal while the other is accessed by an address. In this mode, the DMAC performs the DMA transfer in 1 bus cycle by simultaneously outputting a transfer request acknowledge DACK signal to one external device to access it while outputting an address to the other end of the transfer. Figure 9.6 shows an example of a transfer between an external memory and an external device with DACK in which the external device outputs data to the data bus while that data is written in external memory in the same bus cycle. Rev. 7.00 Jan 31, 2006 page 201 of 658 REJ09B0272-0700 Section 9 Direct Memory Access Controller (DMAC) External address bus External data bus SuperH microcomputer External memory DMAC Read Write 1 2 External device with DACK DACK DREQ : Data flow Note: The read/write direction is decided by the RS3-RS0 bits in the CHCRn registers. If RS3-RS0 = 0010, the direction is as shown in case 1 (circled number above); if RS3RS0 = 0011, the direction is as shown in case 2. In the Electrical Characteristics section, DACK output (read) indicates case 1, and DACK output (write) indicates case 2. Figure 9.6 Data Flow in Single Address Mode Two types of transfers are possible in single address mode: 1) transfers between external devices with DACK and memory-mapped external devices, and 2) transfers between external devices with DACK and external memory. The only transfer request for either of these is the external request (DREQ). Figure 9.7 shows the DMA transfer timing for single address mode. The DACK output when a transfer occurs from an external device with DACK to a memorymapped external device is the write waveform. The DACK output when a transfer occurs from a memory-mapped external device to an external device with DACK is the read waveform. The settings of the acknowledge mode (AM) bits in the channel control registers (CHCR0, CHCR1) have no effect. Rev. 7.00 Jan 31, 2006 page 202 of 658 REJ09B0272-0700 Section 9 Direct Memory Access Controller (DMAC) CK A21-A0 Address output to external memory space CSn Data output from external device with DACK D15-D0 DACK signal to external device with DACK (active-low) DACK WRH WRL WR signal to external memory space (a) External device with DACK to external memory space CK A21-A0 Address output to external memory space CSn Data output from external memory space D15-D0 RD RD signal to external memory space DACK DACK signal to external device with DACK (active-low) (b) External memory space to external device with DACK Figure 9.7 Examples of DMA Transfer Timing in Single Address Mode * Dual Address Mode In dual address mode, both the transfer source and destination are accessed (selectable) by an address. The source and destination can be located externally or internally. The source is accessed in the read cycle and the destination in the write cycle, so the transfer is performed in two separate bus cycles. The transfer data is temporarily stored in the DMAC. Figure 9.8 shows an example of a transfer between two external memories in which data is read from one memory in the read cycle and written to the other memory in the following write cycle. Rev. 7.00 Jan 31, 2006 page 203 of 658 REJ09B0272-0700 Section 9 Direct Memory Access Controller (DMAC) External data bus SuperH microcomputer 2 DMAC External memory External memory 1 : Data flow 1: Read cycle 2: Write cycle Figure 9.8 Data Flow in Dual Address Mode In dual address mode transfers, external memory, memory-mapped external devices, on-chip memory and on-chip supporting modules can be mixed without restriction. Specifically, this enables the following transfer types: 1. Between external memory and a external memory 2. Between external memory and a memory-mapped external device 3. Between a memory-mapped external devices 4. Between external memory and on-chip memory 5. Between external memory and an on-chip supporting module (excluding the DMAC) 6. Between memory-mapped external device and on-chip memory 7. Between memory-mapped external device and an on-chip supporting module (excluding the DMAC) 8. On-chip memory to on-chip memory 9. Between on-chip memory and an on-chip supporting module (excluding the DMAC) 10. Between on-chip supporting modules (excluding the DMAC) Transfer requests can be auto requests, external requests, or on-chip supporting module requests. When the transfer request source is either the SCI or A/D converter, however, either the data destination or source must be the SCI or A/D converter (table 9.4). In dual address mode, DACK is output in read or write cycles other than for internal memory and external supporting modules. CHCR controls the cycle in which DACK is output. Figure 9.9 shows the DMA transfer timing in dual address mode. Rev. 7.00 Jan 31, 2006 page 204 of 658 REJ09B0272-0700 Section 9 Direct Memory Access Controller (DMAC) CK A21-A0 Source address Destination address CSn D15-D0 RD WRH WRL DACK Figure 9.9 DMA Transfer Timing in Dual Address Mode (External Memory Space to External Memory Space Transfer with DACK Output in Read Cycle) Bus Modes: There are two bus modes: cycle-steal and burst. Select the mode with the TM bits in CHCR0-CHCR3. * Cycle-Steal Mode In cycle-steal mode, the bus is given to another bus master after a one-transfer-unit (word or byte) DMA transfer. When another transfer request occurs, the bus is obtained from the other bus master and a transfer is performed for one transfer unit. When that transfer ends, the bus is passed to the other bus master. This is repeated until the transfer end conditions are satisfied. Cycle-steal mode can be used with all categories of transfer destination, transfer source and transfer request. Figure 9.10 shows an example of DMA transfer timing in cycle-steal mode. Transfer conditions shown in the figure are: Dual address mode DREQ level detection DREQ Bus returned to CPU Bus cycle CPU CPU CPU DMAC DMAC Read Write CPU DMAC DMAC Read Write CPU Figure 9.10 Transfer Example in Cycle-Steal Mode (Dual Address Mode, DREQ Level Detection) Rev. 7.00 Jan 31, 2006 page 205 of 658 REJ09B0272-0700 Section 9 Direct Memory Access Controller (DMAC) * Burst Mode Once the bus is obtained, the transfer is performed continuously until the transfer end condition is satisfied. In external request mode with low-level detection at the DREQ pin, however, when the DREQ pin is driven high, the bus passes to the other bus master after the bus cycle of the DMAC that currently has an acknowledged request ends, even if the transfer end conditions have not been satisfied. Burst mode cannot be used when the serial communication interface (SCI) is the transfer request source. Figure 9.11 shows an example of DMA transfer timing in burst mode. The transfer conditions shown in the figure are: Single address mode DREQ level detection DREQ Bus cycle CPU CPU CPU DMAC DMAC DMAC DMAC DMAC DMAC CPU Figure 9.11 Transfer Example in Burst Mode (Single Address Mode, DREQ Level Detection) Relationship between Request Modes and Bus Modes by DMA Transfer Category: Table 9.6 shows the relationship between request modes and bus modes by DMA transfer category. Rev. 7.00 Jan 31, 2006 page 206 of 658 REJ09B0272-0700 Section 9 Direct Memory Access Controller (DMAC) Table 9.6 Address Mode Single Dual Relationship of Request Modes and Bus Modes by DMA Transfer Category Request Mode Bus Mode Transfer Size (bits) Usable Channels External device with DACK and external memory External B/C 8/16 0,1 External device with DACK and memory-mapped external device External B/C 8/16 0, 1 External memory and external memory All* 1 B/C 8/16 0-3* External memory and memorymapped external device All* 1 B/C 8/16 0-3* 1 B/C 8/16 0-3* 1 B/C 8/16 0-3* 2 B/C* 8/16* 0-3* 1 B/C 8/16 0-3* 2 B/C* 8/16* 0-3* 1 B/C 8/16 0-3* 2 B/C* 2 B/C* Transfer Category Memory-mapped external device and All* memory-mapped external device External memory and on-chip memory All* External memory and on-chip supporting module All* Memory-mapped external device and All* on-chip memory Memory-mapped external device and All* on-chip supporting module On-chip memory and on-chip memory All* On-chip memory and on-chip supporting module All* On-chip supporting module and onchip supporting module All* 3 3 5 5 5 5 4 5 5 4 5 5 3 8/16* 4 0-3* 3 8/16* 5 4 0-3* 5 B: Burst, C: Cycle steal Notes: 1. External requests, auto requests and on-chip supporting module requests are all available. For on-chip supporting module requests, however, SCI and A/D converter cannot be specified as the transfer request source. 2. External requests, auto requests and on-chip supporting module requests are all available. When the SCI or A/D converter is also the transfer request source, however, the transfer destination or transfer source must be the SCI or A/D converter, respectively. 3. If the transfer request source is the SCI, cycle-steal only. 4. The access size permitted when the transfer destination or source is an on-chip supporting module register. 5. If the transfer request is an external request, channels 0 and 1 only. Rev. 7.00 Jan 31, 2006 page 207 of 658 REJ09B0272-0700 Section 9 Direct Memory Access Controller (DMAC) Bus Mode and Channel Priority Order: When a given channel (1) is transferring in burst mode and there is a transfer request to a channel (2) with a higher priority, the transfer of the channel with higher priority (2) will begin immediately. When channel 2 is also operating in burst mode, the channel 1 transfer will continue when the channel 2 transfer has completely finished. When channel 2 is in cycle-steal mode, channel 1 will begin operating again after channel 2 completes the transfer of one transfer unit, but the bus will then switch between the two in the order channel 1, channel 2, channel 1, channel 2. Since channel 1 is in burst mode, it will not give the bus to the CPU. This example is illustrated in figure 9.12. Bus status CPU CPU DMAC ch1 DMAC ch1 DMAC ch2 DMAC ch1 DMAC ch2 ch2 ch1 ch2 DMAC ch1 Burst mode DMAC ch1 and ch2 Cycle-steal mode DMAC ch1 DMAC ch1 DMAC ch1 Burst mode CPU CPU Priority order is ch0 > ch3 > ch2 > ch1 (ch1 is in burst mode and ch2 is in cycle-steal mode) Figure 9.12 Bus Handling when Multiple Channels are Operating 9.3.5 Number of Bus Cycle States and DREQ Pin Sample Timing Number of States in Bus Cycle: The number of states in the bus cycle when the DMAC is the bus master is controlled by the bus state controller just as it is when the CPU is the bus master. The bus cycle in dual address mode is controlled by wait state control register 1 (WCR1) while the single address mode bus cycle is controlled by wait state control register 2 (WCR2). For details, see section 8.9, Wait State Control. DREQ Pin Sampling Timing: Normally, when DREQ input is detected immediately prior to the rise edge of the clock pulse (CK) in external request mode, a DMAC bus cycle will be generated and the DMA transfer performed two states later at the earliest. The sampling timing after DREQ input detection differs by bus mode, address mode, and method of DREQ input detection. Rev. 7.00 Jan 31, 2006 page 208 of 658 REJ09B0272-0700 Section 9 Direct Memory Access Controller (DMAC) * DREQ pin sampling timing in cycle-steal mode In cycle-steal mode, the sampling timing is the same regardless of whether DREQ is detected by edge or level. With edge detection, however, once the signal is sampled it will not be sampled again until the next edge detection. Once DREQ input is detected, the next sampling is not performed until the first state, among those DMAC bus cycles thereby produced, in which a DACK signal is output (including the detection state itself). The next sampling occurs immediately prior to the rising edge of the clock pulse (CK) of the third state after the bus cycle previous to the bus cycle in which the DACK signal is output. Figures 9.13 to 9.22 show the sampling timing of the DREQ pin in cycle-steal mode for each bus cycle. When no DREQ input is detected at the sampling after the aforementioned DREQ detection, the next sampling occurs in the next state in which a DACK signal is output. If no DREQ input is detected at this time, sampling occurs at every subsequent state. CK DREQ Bus cycle CPU CPU CPU DMAC CPU CPU CPU CPU DACK Figure 9.13 DREQ Sampling Timing in Cycle-Steal Mode (Output with DREQ Level Detection and DACK Active-Low) (Single Address Mode, Bus Cycle = 1 State) Rev. 7.00 Jan 31, 2006 page 209 of 658 REJ09B0272-0700 Section 9 Direct Memory Access Controller (DMAC) CK DREQ Bus cycle CPU CPU CPU DMAC (R) DMAC (W) CPU CPU CPU DACK DMAC (R): DMAC read cycle DMAC (W): DMAC write cycle Note: Illustrates the case when DACK is output during the DMAC read cycle. Figure 9.14 DREQ Sampling Timing in Cycle-Steal Mode (Output with DREQ Level Detection and DACK Active-Low) (Dual Address Mode, Bus Cycle = 1 State) CK DREQ Bus cycle CPU CPU CPU DMAC CPU CPU CPU CPU DACK Figure 9.15 DREQ Sampling Timing in Cycle-Steal Mode (Output with DREQ Level Detection and DACK Active-Low) (Single Address Mode, Bus Cycle = 2 States) Rev. 7.00 Jan 31, 2006 page 210 of 658 REJ09B0272-0700 Section 9 Direct Memory Access Controller (DMAC) CK DREQ Bus cycle CPU CPU CPU DMAC (R) DMAC (W) CPU CPU CPU DACK DMAC (R): DMAC read cycle DMAC (W): DMAC write cycle Note: Illustrates the case when DACK is output during the DMAC write cycle. Figure 9.16 DREQ Sampling Timing in Cycle-Steal Mode (Output with DREQ Level Detection and DACK Active-Low) (Dual Address Mode, Bus Cycle = 2 States) T1 Tw T2 T1 Tw T2 CK DREQ Bus cycle CPU CPU CPU DMAC CPU DMAC CPU DACK Note: When DREQ is negated at the third state of the DMAC cycle, the next DMA transfer will be executed because the sampling is performed at the second state of the DMAC cycle. Figure 9.17 DREQ Sampling Timing in Cycle-Steal Mode (Output with DREQ Level Detection and DACK Active-Low) (Single Address Mode, Bus Cycle = 2 States + 1 Wait State) Rev. 7.00 Jan 31, 2006 page 211 of 658 REJ09B0272-0700 Section 9 Direct Memory Access Controller (DMAC) T1 Tw T2 T1 Tw T2 CK DREQ Bus cycle CPU CPU CPU DMAC (R) DMAC (W) CPU CPU DACK DMAC (R): DMAC read cycle DMAC (W): DMAC write cycle Figure 9.18 DREQ Sampling Timing in Cycle-Steal Mode (Output with DREQ Level Detection and DACK Active-Low) (Dual Address Mode, Bus Cycle = 2 States + 1 Wait State) Tp Tr Tc Tc Tp Tr Tc Tc CK DREQ Bus cycle CPU CPU CPU DMAC CPU DMAC CPU DACK Note: When DREQ is negated at the fourth state of the DMAC cycle, the next DMA transfer will be executed because the sampling is performed at the second state of the DMAC cycle. Figure 9.19 DREQ Sampling Timing in Cycle-Steal Mode (Output with DREQ Level Detection and DACK Active-Low) (Single Address Mode, Bus Cycle = DRAM Bus Cycle (Long Pitch Normal Mode)) Rev. 7.00 Jan 31, 2006 page 212 of 658 REJ09B0272-0700 Section 9 Direct Memory Access Controller (DMAC) Tp Tr Tc Tc Tp Tr Tc Tc CK DREQ Bus cycle CPU CPU CPU DMAC(R) DMAC (W) CPU DMAC (R) DMAC (W) CPU DACK DMAC (R): DMAC read cycle DMAC (W): DMAC write cycle Note: When DREQ is negated at the fourth state of the DMAC cycle, the next DMA transfer will be executed because the sampling is performed at the second state of the DMAC cycle. Figure 9.20 DREQ Sampling Timing in Cycle-Steal Mode (Output with DREQ Level Detection and DACK Active-Low) (Dual Address Mode, Bus Cycle = DRAM Bus Cycle (Long Pitch Normal Mode)) T1 T2 T3 T4 T1 T2 T3 T4 CK DREQ Bus cycle CPU CPU CPU DMAC CPU DMAC CPU DACK Note: When DREQ is negated at the fourth state of the DMAC cycle, the next DMA transfer will be executed because the sampling is performed at the second state of the DMAC cycle. Figure 9.21 DREQ Sampling Timing in Cycle-Steal Mode (Output with DREQ Level Detection and DACK Active-Low) (Single Address Mode, Bus Cycle = Address/Data Multiplex I/O Bus Cycle) Rev. 7.00 Jan 31, 2006 page 213 of 658 REJ09B0272-0700 Section 9 Direct Memory Access Controller (DMAC) T1 T2 T3 T4 T1 T2 T3 T4 CK DREQ Bus cycle CPU CPU CPU DMAC(R) DMAC (W) CPU DMAC (R) DMAC (W) CPU DACK DMAC (R): DMAC read cycle DMAC (W): DMAC write cycle Note: When DREQ is negated at the fourth state of the DMAC cycle, the next DMA transfer will be executed because the sampling is performed at the second state of the DMAC cycle. Figure 9.22 DREQ Sampling Timing in Cycle-Steal Mode (Output with DREQ Level Detection and DACK Active-Low) (Dual Address Mode, Bus Cycle = Address/Data Multiplex I/O Bus Cycle) * DREQ pin sampling timing in burst mode In burst mode, the sampling timing differs depending on whether DREQ is detected by edge or level. When DREQ input is being detected by edge, once the falling edge of the DREQ signal is detected, the DMA transfer continues until the transfer end conditions are satisfied, regardless of the status of the DREQ pin. No sampling happens during this time. After the transfer ends, sampling occurs every state until the TE bit of CHCR is cleared. When DREQ input is being detected by level, once the DREQ input is detected, subsequent sampling is performed at the end of every CPU or DMAC bus cycle in single address mode. In dual address mode, subsequent sampling is performed at the start of every DMAC read cycle. In both single address mode and dual address mode, if no DREQ input is detected at this time, subsequent sampling occurs at every state. Figures 9.23 and 9.24 show the DREQ pin sampling timing in burst mode when DREQ input is detected by low level. Rev. 7.00 Jan 31, 2006 page 214 of 658 REJ09B0272-0700 Section 9 Direct Memory Access Controller (DMAC) CK DREQ Bus cycle CPU CPU CPU DMAC DMAC DMAC CPU DACK Figure 9.23 DREQ Pin Sampling Timing in Burst Mode (Single Address DREQ Level Detection, DACK Active-Low, 1 Bus Cycle = 2 States) CK DREQ Bus cycle CPU CPU DMAC(R) DMAC(W) DMAC(R) DMAC(W) CPU DACK Figure 9.24 DREQ Pin Sampling Timing in Burst Mode (Dual Address DREQ Level Detection, DACK Active-Low, DACK Output in Read Cycle, 1 Bus Cycle = 2 States) Rev. 7.00 Jan 31, 2006 page 215 of 658 REJ09B0272-0700 Section 9 Direct Memory Access Controller (DMAC) 9.3.6 DMA Transfer Ending Conditions The DMA transfer ending conditions differ for individual channel ending and ending on all channels together. Individual Channel Ending Conditions: There are two ending conditions. A transfer ends when the value of the channel's DMA transfer count register (TCR) is 0, or when the DE bit in the channel's CHCR is cleared to 0. * When TCR is 0: When the TCR value becomes 0 and the corresponding channel's DMA transfer ends, the transfer end flag bit (TE) is set in CHCR. If the IE (interrupt enable) bit has been set, a DMAC interrupt (DEI) request is sent to the CPU. * When DE in CHCR is 0: Software can halt a DMA transfer by clearing the DE bit in the channel's CHCR. The TE bit is not set when this happens. Conditions for Ending All Channels Simultaneously: Transfers on all channels end when 1) the NMIF (NMI flag) bit or AE (address error flag) bit is set to 1 in DMAOR, or 2) when the DME bit in DMAOR is cleared to 0. * Transfers ending when the NMIF or AE bit is set to 1 in DMAOR: When an NMI interrupt or DMAC address error occurs, the NMIF or AE bit is set to 1 in DMAOR and all channels stop their transfers. SAR, DAR, and TCR are all updated by the transfer immediately preceding the halt. The TE bit is not set. To resume transfer after NMI interrupt exception handling or address error exception handling, clear the appropriate flag bit to 0. When a channel's DE bit is then set to 1, the transfer on that channel will restart. To avoid restarting transfer on a particular channel, keep its DE bit cleared to 0. In dual address mode, DMA transfer will be halted after the completion of the write cycle that follows the initial read cycle in which the address error occurs. SAR, DAR, and TCR are updated by the final transfer. * Transfers ending when DME is cleared to 0 in DMAOR: Clearing the DME bit to 0 in DMAOR forcibly aborts transfer on all channels at the end of the current cycle. The TE bit is not set. Rev. 7.00 Jan 31, 2006 page 216 of 658 REJ09B0272-0700 Section 9 Direct Memory Access Controller (DMAC) 9.4 Examples of Use 9.4.1 DMA Transfer between On-Chip RAM and Memory-Mapped External Device In the following example, data is transferred from on-chip RAM to a memory-mapped external device with an input capture A/compare match A interrupt (IMIA0) from channel 0 of the 16-bit integrated timer pulse unit (ITU) as the transfer request signal. The transfer is performed by DMAC channel 3. Table 9.7 shows the transfer conditions and register values. Table 9.7 Transfer Conditions and Register Settings for Transfer Between On-Chip RAM and Memory-Mapped External Device Transfer Conditions Register Setting Transfer source: on-chip RAM SAR3 H'FFFFE00 Transfer destination: memory-mapped external device DAR3 Destination address Number of transfers: 8 TCR3 H'0008 Transfer destination address: fixed CHCR3 H'1805 DMAOR H'0001 Transfer source address: incremented Transfer request source (transfer request signal): ITU channel 0 (IMIA0) Bus mode: cycle-steal Transfer unit: byte DEI interrupt request generated at end of transfer (channel 3 enabled for transfer) Channel priority order: fixed (0 > 3 > 2 > 1) (all channels enabled for transfer) Rev. 7.00 Jan 31, 2006 page 217 of 658 REJ09B0272-0700 Section 9 Direct Memory Access Controller (DMAC) 9.4.2 Example of DMA Transfer between On-Chip SCI and External Memory In this example, receive data of on-chip serial communication interface (SCI) channel 0 is transferred to external memory using DMAC channel 3. Table 9.8 shows the transfer conditions and register settings. Table 9.8 Transfer Conditions and Register Settings for Transfer between On-Chip SCI and External Memory Transfer Conditions Register Setting Transfer source: RDR0 of on-chip SCI0 SAR3 H'FFFFEC5 Transfer destination: external memory DAR3 Destination address Number of transfers: 64 TCR3 H'0040 Transfer destination address: incremented CHCR3 H'4405 DMAOR H'0001 Transfer source address: fixed Transfer request source (transfer request signal): SCI0 (RXI0) Bus mode: cycle-steal Transfer unit: byte DEI interrupt request generated at end of transfer (channel 3 enabled for transfer) Channel priority order: fixed (0 > 3 > 2 > 1) (all channels enabled for transfer) Rev. 7.00 Jan 31, 2006 page 218 of 658 REJ09B0272-0700 Section 9 Direct Memory Access Controller (DMAC) 9.4.3 Example of DMA Transfer Between On-Chip A/D Converter and External Memory In this example, the results of an A/D conversion by the on-chip A/D converter are transferred to external memory using DMAC channel 3. Input from channel 0 (AN0) is A/D-converted using scan mode. Table 9.9 shows the transfer conditions and register settings. Table 9.9 Transfer Conditions and Register Settings for Transfer Between On-Chip A/D Converter and External Memory Transfer Conditions Register Setting Transfer source: ADDRA of on-chip A/D converter SAR3 H'FFFFEE0 (ADDRAH register address) Transfer destination: external memory DAR3 Destination address Number of transfers: 16 TCR3 H'0010 Transfer destination address: incremented CHCR3 H'4D0D DMAOR H'0001 Transfer source address: fixed Transfer request source (transfer request signal): A/D converter (ADI) Bus mode: cycle-steal Transfer unit: word DEI interrupt request generated at end of transfer (channel 3 enabled for transfer) Channel priority order: fixed (0 > 3 > 2 > 1) (all channels enabled for transfer) Rev. 7.00 Jan 31, 2006 page 219 of 658 REJ09B0272-0700 Section 9 Direct Memory Access Controller (DMAC) 9.5 Usage Notes 1. All registers other than the DMA operation register (DMAOR) and DMA channel control registers 0-3 (CHCR0-CHCR3) should be accessed in word or longword units. 2. Before rewriting the RS0-RS3 bits in CHCR0-CHCR3, first clear the DE bit to 0 (when rewriting CHCR with a byte access, be sure to set the DE bit to 0 in advance). 3. Even when an NMI interrupt is input when the DMAC is not operating, the NMIF bit in DMAOR will be set. 4. Interrupt during DMAC transfer When an interrupt occurs during DMAC transfer, the following operation takes place. a. When an NMI interrupt is input, the DMAC stops operation and returns the bus to the CPU. The CPU then executes the interrupt handling. b. When an interrupt other than an NMI occurs * When the DMAC is in burst mode The DMAC does not return the bus to the CPU in burst mode. Therefore, even when an interrupt is requested in DMAC operation, the CPU cannot acquire the bus with, the result that interrupt handling is not executed. When the DMAC completes the transfer and the CPU acquires the bus, the CPU executes interrupt handling if the interrupt requested during DMAC transfer is not cleared.* Note: * Clear conditions for an interrupt request: When an interrupt is requested from an on-chip supporting module, and the interrupt source flag is cleared When an interrupt is requested by IRQ (edge detection), and the CPU begins interrupt handling for the IRQ request source When an interrupt is requested by IRQ (level detection), and the IRQ interrupt request signal returns to the high level * When the DMAC is in cycle-steal mode The DMAC returns the bus to the CPU every time the DMAC completes a transfer unit in cycle-steal mode. Therefore, the CPU executes the requested interrupt handling when it acquires the bus. 5. The CPU and DMAC leave the bus released and the operation of the chip is stopped when the following conditions are satisfied * The warp bit (WARP) in the bus control register (BCR) of the bus controller (BSC) is set * The DMAC is in cycle-steal transfer mode * The CPU accesses (reads/writes) the on-chip I/O space Remedy: Clear the warp bit in BCR to 0 to set normal mode. Rev. 7.00 Jan 31, 2006 page 220 of 658 REJ09B0272-0700 Section 9 Direct Memory Access Controller (DMAC) 6. Notes on use of the SLEEP instruction a. Operation contents When a DMAC bus cycle is entered immediately after executing a SLEEP instruction, there are cases when DMA transfer is not carried out correctly. b. Remedy * Stop operation (for example, by clearing the DMA enable bit (DE) in the DMA channel control register (CHCRn)) before entering sleep mode. * To use the DMAC when in sleep mode, first exit sleep mode by means of an interrupt. In cases when the CPU is not carrying out any other processing but is waiting for the DMAC to end its transfer during DMAC operation, do not use the SLEEP instruction, but use the transfer end flag bit (TE) in the channel DMA control register and a polling software loop. 7. Sampling of DREQ If DREQ is set to level detection in DMA cycle-steal mode, sampling of DREQ may take place before DACK is output. Note that some system configurations involve unnecessary DMA transfers. Operation: As shown in Figure 9.25, sampling of DREQ is carried out immediately before the rising edge of the third-state clock (CK) after completion of the bus cycle preceding the DMA bus cycle where DACK is output. If DACK is output after the third state of the DMA bus cycle, sampling of DREQ must be carried out before DACK is output. Number of states of DMAC bus cycle 1 2 3 4 : DMAC bus cycle Sampling point Figure 9.25 DREQ Sampling Points Rev. 7.00 Jan 31, 2006 page 221 of 658 REJ09B0272-0700 Section 9 Direct Memory Access Controller (DMAC) Especially, if, as shown in figure 9.26, the DMA bus cycle is a full access to DRAM or if a refresh request is generated, sampling of DREQ takes place before DACK is output as mentioned above. This phenomenon is found when one of the following transfers is made with DREQ set to level detection in DMA cycle-steal mode, in a system which employs DRAM (refresh enabled). CK Tp Tr Tc Refresh T1 T2 DACK Sampling point DRAM bus cycle (Full access) Sampling point When refresh operation is entered Sampling point of DREQ for DACK output position differs with presence/absence of the refresh operation. Figure 9.26 Example of DREQ Sampling before Output of DACK * Transfer from a device with DACK to memory in single address mode (not restricted to DRAM) * Transfer from DRAM to a device with DACK in single address mode * Output at DACK write in dual address mode * Output at DACK read in dual address mode and DMA transfer using DRAM as the source Remedy: To prevent unnecessary DMA transfers, configure the system so that DREQ is edge-detected and the edge corresponding to the next transfer request occurs after DACK output. 8. When the following operations are performed in the order shown when the pin to which DREQ input is assigned is designated as a general input pin by the pin function controller (PFC) and inputs a low-level signal, the DREQ falling edge is detected, and a DMA transfer request accepted, immediately after the setting in (b) is performed: a. A channel control register (CHCRn) setting is made so that an interrupt is detected at the falling edge of DREQ. b. The function of the pin to which DREQ input is assigned is switched from general input to DREQ input by a pin function controller (PFC) setting. Therefore, when switching the pin function from general input pin to DREQ input, the pin function controller (PFC) setting should be changed to DREQ input while the pin to which DREQ input is assigned is high. Rev. 7.00 Jan 31, 2006 page 222 of 658 REJ09B0272-0700 Section 10 16-Bit Integrated Timer Pulse Unit (ITU) Section 10 16-Bit Integrated Timer Pulse Unit (ITU) 10.1 Overview The SuperH microcomputer has an on-chip 16-bit integrated timer pulse unit (ITU) with five 16bit timer channels. 10.1.1 Features ITU features are listed below: * Can process a maximum of twelve different pulse outputs and ten different pulse inputs. * Has ten general registers (GR), two per channel, that can be set to function independently as output compare or input capture registers. * Selection of eight counter input clock sources for all channels Internal clock: , /2, /4, /8, External clock: TCLKA, TCLKB, TCLKC, TCLKD * All channels can be set for the following operating modes: Compare match waveform output: 0 output/1 output/selectable toggle output (0 output/1 output for channel 2) Input capture function: Selectable rising edge, falling edge, or both rising and falling edges Counter clearing function: Counters can be cleared by a compare match or input capture. Synchronizing mode: Two or more timer counters (TCNT) can be written to simultaneously. Two or more timer counters can be simultaneously cleared by a compare match or input capture. Counter synchronization functions enable synchronized input/output. PWM mode: PWM output can be provided with any duty cycle. When combined with the counter synchronizing function, enables up to five-phase PWM output. * Channel 2 can be set to phase counting mode: Two-phase encoder output can be counted automatically. * Channels 3 and 4 can be set in the following modes: Reset-synchronized PWM mode: By combining channels 3 and 4, 3-phase PWM output is possible with positive and negative waveforms . Complementary PWM mode: By combining channels 3 and 4, 3-phase PWM output is possible with non-overlapping positive and negative waveforms. * Buffer operation: Input capture registers can be double-buffered. Output compare registers can be updated automatically. Rev. 7.00 Jan 31, 2006 page 223 of 658 REJ09B0272-0700 Section 10 16-Bit Integrated Timer Pulse Unit (ITU) * High-speed access via internal 16-bit bus: The TCNT, GR, and buffer register (BR) 16-bit registers can be accessed at high speed via a 16-bit bus. * Fifteen interrupt sources: Ten compare match/input capture interrupts (2 sources per channel) and five overflow interrupts are vectored independently for a total of 15 sources. * Can activate DMAC: The compare match/input capture interrupts of channels 0-3 can start the DMAC (one for each of four channels). * Output trigger can be generated for the programmable timing pattern controller (TPC): The compare match/input capture signals of channel 0-3 can be used as output triggers for the TPC. Table 10.1 summarizes the ITU functions. Rev. 7.00 Jan 31, 2006 page 224 of 658 REJ09B0272-0700 Section 10 16-Bit Integrated Timer Pulse Unit (ITU) Table 10.1 ITU Functions Item Channel 0 Channel 1 Channel 2 Channel 3 Channel 4 Counter clocks Internal: , /2, /4, /8 External: Independently selectable from TCLKA, TCLKB, TCLKC, and TCLKD General registers (output compare/ input capture dual registers) GRA0, GRB0 GRA1, GRB1 GRA2, GRB2 GRA3, GRB3 GRA4, GRB4 Buffer registers No No No BRA3, BRB3 BRA4, BRB4 Input/output pins TIOCA0, TIOCB0 TIOCA1, TIOCB1 TIOCA2, TIOCB2 TIOCA3, TIOCB3 TIOCA4, TIOCB4 Output pins No No No No TOCXA4, TOCXB4 Counter clear func- GRA0/GRB0 tion (compare match or input capture) GRA1/GRB1 GRA2/GRB2 GRA3/GRB3 GRA4/GRB4 Compare match output Yes Yes 0 Yes Yes Yes 1 Yes Yes Yes Yes Yes Toggle output Yes Yes No Yes Yes Input capture function Yes Yes Yes Yes Yes Synchronization Yes Yes Yes Yes Yes PWM mode Yes Yes Yes Yes Yes Reset-synchronized No PWM mode No No Yes Yes Complementary PWM mode No No No Yes Yes Phase counting mode No No Yes No No Buffer operation No No No Yes Yes DMAC activation GRA0 comGRA1 comGRA2 comGRA3 comNo pare match or pare match or pare match or pare match or input capture input capture input capture input capture Interrupt sources (three) * Compare * match/input capture A0 Compare * match/input capture A1 Compare * match/input capture A2 Compare * match/input capture A3 Compare match/input capture A4 * Compare * match/input capture B0 Compare * match/input capture B1 Compare * match/input capture B2 Compare * match/input capture B3 Compare match/input capture B4 * Overflow * Overflow * Overflow * Overflow * Overflow Rev. 7.00 Jan 31, 2006 page 225 of 658 REJ09B0272-0700 Section 10 16-Bit Integrated Timer Pulse Unit (ITU) 10.1.2 Block Diagram ITU Block Diagram (Overall Diagram): Figure 10.1 shows a block diagram of the ITU. Control logic IMIA0-IMIA4 IMIB0-IMIB4 OVI0-OVI4 TOCR TSTR TSNC TMDR TFCR Module data bus TOCR: Timer output control register (8 bits) TSTR: Timer start register (8 bits) TSNC: Timer synchronization register (8 bits) TMDR: Timer mode register (8 bits) TFCR: Timer function control register (8 bits) Figure 10.1 Block Diagram of ITU Rev. 7.00 Jan 31, 2006 page 226 of 658 REJ09B0272-0700 Bus interface 16-bit timer channel 0 16-bit timer channel 4 16-bit timer channel 1 Counter control and pulse I/O control unit TOCXA4, TOCXB4 TIOCA0-TIOCA4 TIOCB0-TIOCB4 16-bit timer channel 2 , /2, /4, /8 Clock selection 16-bit timer channel 3 TCLKA-TCLKD Internal data bus Section 10 16-Bit Integrated Timer Pulse Unit (ITU) Block Diagram of Channels 0 and 1: ITU channels 0 and 1 have the same function. Figure 10.2 shows a block diagram of channels 0 and 1. Clock selection IMIAn IMIBn OVIn TSRn Control logic TCRn GRBn GRAn TCNTn Comparator TIERn , /2, /4, /8 TIOCAn TIOCBn TIORn TCLKA- TCLKD Module data bus TCNTn: Timer counter n (16 bits) GRAn, GRBn: General registers An, Bn (input capture/output compare dual use) (16 bits x 2) TCRn: Timer control register n (8 bits) TIORn: Timer I/O control register n (8 bits) TIERn: Timer interrupt enable register n (8 bits) TSRn: Timer status register n (8 bits) (n = 0 or 1) Figure 10.2 Block Diagram of Channels 0 and 1 (One Channel Shown) Rev. 7.00 Jan 31, 2006 page 227 of 658 REJ09B0272-0700 Section 10 16-Bit Integrated Timer Pulse Unit (ITU) Block Diagram of Channel 2: Figure 10.3 shows a block diagram of channel 2. Channel 2 is capable of 0 output/1 output only. Clock selection IMIA2 IMIB2 OVI2 TSR2 Control logic TCR2 GRB2 GRA2 TCNT2 Comparator TIER2 , /2, /4, /8 TIOCA2 TIOCB2 TIOR2 TCLKA- TCLKD Module data bus TCNT2: Timer counter 2 (16 bits) GRA2, GRB2: General registers A2, B2 (input capture/output compare dual use) (16 bits x 2) TCR2: Timer control register 2 (8 bits) TIOR2: Timer I/O control register 2 (8 bits) TIER2: Timer interrupt enable register 2 (8 bits) TSR2: Timer status register 2 (8 bits) Figure 10.3 Block Diagram of Channel 2 Rev. 7.00 Jan 31, 2006 page 228 of 658 REJ09B0272-0700 Section 10 16-Bit Integrated Timer Pulse Unit (ITU) Block Diagrams of Channels 3 and 4: Figure 10.4 shows a block diagram of channel 3; figure 10.5 shows a block diagram of channel 4. TCLKA- TCLKD Clock selection TIOCA3 TIOCB3 IMIA3 IMIB3 OVI3 TSR3 TIER3 TIOR3 GRB3 Control logic BRB3 GRA3 BRA3 TCNT3 Comparator TCR3 , /2, /4, /8 Module data bus TCNT3: Timer counter 3 (16 bits) GRA3, GRB3: General registers A3, B3 (input capture/output compare dual use) (16 bits x 2) BRA3, BRB3: Buffer registers A3, B3 (input capture/output compare dual use) (16 bits x 2) TCR3: Timer control register 3 (8 bits) TIOR3: Timer I/O control register 3 (8 bits) TIER3: Timer interrupt enable register 3 (8 bits) TSR3: Timer status register 3 (8 bits) Figure 10.4 Block Diagram of Channel 3 Rev. 7.00 Jan 31, 2006 page 229 of 658 REJ09B0272-0700 Section 10 16-Bit Integrated Timer Pulse Unit (ITU) TCLKA- TCLKD TOCXA4 TOCXB4 Clock selection TIOCA4 TIOCB4 IMIA4 IMIB4 OVI4 TSR4 TIER4 TIOR4 GRB4 Control logic BRB4 GRA4 BRA4 GCNT4 Comparator TCR4 , /2, /4, /8 Module data bus TCNT4: Timer counter 4 (16 bits) GRA4, GRB4: General registers A4, B4 (input capture/output compare dual use) (16 bits x 2) BRA4, BRB4: Buffer registers A4, B4 (input capture/output compare dual use) (16 bits x 2) TCR4: Timer control register 4 (8 bits) TIOR4: Timer I/O control register 4 (8 bits) TIER4: Timer interrupt enable register 4 (8 bits) TSR4: Timer status register 4 (8 bits) Figure 10.5 Block Diagram of Channel 4 Rev. 7.00 Jan 31, 2006 page 230 of 658 REJ09B0272-0700 Section 10 16-Bit Integrated Timer Pulse Unit (ITU) 10.1.3 Input/Output Pins Table 10.2 summarizes the ITU pins. External pin functions should be set with the pin function controller to match to the ITU setting. See section 15, Pin Function Controller, for details. ITU pins need to be set using the pin function controller (PFC) after the chip is set to ITU mode. Table 10.2 Pin Configuration Channel Name Pin Name I/O Function Shared Clock input A TCLKA Clock input B TCLKB Clock input C Clock input D Input capture/output compare A0 Input capture/output compare B0 Input capture/output compare A1 Input capture/output compare B1 Input capture/output compare A2 Input capture/output compare B2 Input capture/output compare A3 TCLKC TCLKD TIOCA0 0 1 2 3 TIOCB0 TIOCA1 TIOCB1 TIOCA2 TIOCB2 TIOCA3 Input capture/output TIOCB3 compare B3 4 Input capture/output TIOCA4 compare A4 Input capture/output TIOCB4 compare B4 Output compare XA4 TOCXA4 Output compare XB4 TOCXB4 I External clock A input pin (A-phase input pin in phase counting mode) I External clock B input pin (B-phase input pin in phase counting mode) I External clock C input pin I External clock D input pin I/O GRA0 output compare/GRA0 input capture/PWM output pin (in PWM mode) I/O GRB0 output compare/GRB0 input capture I/O GRA1 output compare/GRA1 input capture/PWM output pin (in PWM mode) I/O GRB1 output compare/GRB1 input capture I/O GRA2 output compare/GRA2 input capture/PWM output pin (in PWM mode) I/O GRB2 output compare/GRB2 input capture I/O GRA3 output compare/GRA3 input capture/PWM output pin (in PWM mode, complementary PWM mode, or reset-synchronized PWM mode) I/O GRB3 output compare/GRB3 input capture/PWM output pin (in complementary PWM mode or resetsynchronized PWM mode) I/O GRA4 output compare/GRA4 input capture/PWM output pin (in PWM mode, complementary PWM mode or reset-synchronized PWM mode) I/O GRB4 output compare/GRB4 input capture/PWM output pin (in complementary PWM mode or resetsynchronized PWM mode) O PWM output pin (in complementary PWM mode or reset-synchronized PWM mode) O PWM output pin (in complementary PWM mode or reset-synchronized PWM mode) Rev. 7.00 Jan 31, 2006 page 231 of 658 REJ09B0272-0700 Section 10 16-Bit Integrated Timer Pulse Unit (ITU) 10.1.4 Register Configuration Table 10.3 summarizes the ITU register configuration. Table 10.3 Register Configuration Access Size Channel Name Abbreviation R/W Initial Value Shared Timer start register TSTR R/W H'E0/H'60 H'5FFFF00 8 Timer synchro register TSNC R/W H'E0/H'60 H'5FFFF01 8 0 1 Timer mode register TMDR R/W H'80/H'00 H'5FFFF02 8 Timer function control register TFCR R/W H'C0/H'40 H'5FFFF03 8 Timer output control register TOCR R/W H'FF/H'7F H'5FFFF31 8 Timer control register 0 TCR0 R/W H'80/H'00 H'5FFFF04 8 Timer I/O control register 0 TIOR0 R/W H'88/H'08 H'5FFFF05 8 Timer interrupt enable register 0 TIER0 R/W H'F8/H'78 H'5FFFF06 8 Timer status register 0 TSR0 R/(W)* H'F8/H'78 H'5FFFF07 8 Timer counter 0 TCNT0 R/W H'5FFFF08 8, 16, 32 H'5FFFF09 8, 16, 32 H'5FFFF0A 8, 16, 32 H'5FFFF0B 8, 16, 32 H'5FFFF0C 8, 16 H'5FFFF0D 8, 16 General register A0 General register B0 1 Address* GRA0 GRB0 2 R/W R/W H'00 H'FF H'FF Timer control register 1 TCR1 R/W H'80/H'00 H'5FFFF0E 8 Timer I/O control register 1 TIOR1 R/W H'88/H'08 H'5FFFF0F 8 Timer interrupt enable register 1 TIER1 R/W H'F8/H'78 H'5FFFF10 8 Timer status register 1 TSR1 2 R/(W)* H'F8/H'78 H'5FFFF11 8 Timer counter 1 TCNT1 R/W H'5FFFF12 8, 16 H'5FFFF13 8, 16 H'5FFFF14 8, 16, 32 H'5FFFF15 8, 16, 32 H'5FFFF16 8, 16, 32 H'5FFFF17 8, 16, 32 General register A1 General register B1 Rev. 7.00 Jan 31, 2006 page 232 of 658 REJ09B0272-0700 GRA1 GRB1 R/W R/W H'00 H'FF H'FF Section 10 16-Bit Integrated Timer Pulse Unit (ITU) Channel Name Abbreviation R/W Initial Value Address* 2 Timer control register 2 TCR2 H'80/H'00 H'5FFFF18 Timer I/O control register 2 8 TIOR2 R/W H'88/H'08 H'5FFFF19 8 R/W H'F8/H'78 H'5FFFF1A 8 Timer status register 2 TSR2 R/(W)* H'F8/H'78 H'5FFFF1B 8 Timer counter 2 TCNT2 R/W H'5FFFF1C 8, 16, 32 H'5FFFF1D 8, 16, 32 H'5FFFF1E 8, 16, 32 H'5FFFF1F 8, 16, 32 H'5FFFF20 8, 16 H'5FFFF21 8, 16 H'5FFFF22 8 General register B2 GRA2 GRB2 Timer control register 3 TCR3 Timer I/O control register 3 2 H'00 R/W H'FF R/W H'FF R/W H'80/H'00 TIOR3 R/W H'88/H'08 H'5FFFF23 8 Timer interrupt enable register 3 TIER3 R/W H'F8/H'78 H'5FFFF24 8 Timer status register 3 TSR3 R/(W)* H'F8/H'78 H'5FFFF25 8 Timer counter 3 TCNT3 R/W H'5FFFF26 8, 16 H'5FFFF27 8, 16 8, 16, 32 2 H'00 General register A3 GRA3 R/W H'FF H'5FFFF28 H'5FFFF29 8, 16, 32 General register B3 GRB3 R/W H'FF H'5FFFF2A 8, 16, 32 H'5FFFF2B 8, 16, 32 H'5FFFF2C 8, 16, 32 H'5FFFF2D 8, 16, 32 Buffer register A3 Buffer register B3 4 Access Size Timer interrupt enable register 2 TIER2 General register A2 3 R/W 1 BRA3 BRB3 R/W R/W H'FF H'FF H'5FFFF2E 8, 16, 32 H'5FFFF2F 8, 16, 32 Timer control register 4 TCR4 R/W H'80/H'00 H'5FFFF32 8 Timer I/O control register 4 TIOR4 R/W H'88/H'08 H'5FFFF33 8 Timer interrupt enable register 4 TIER4 R/W H'F8/H'78 H'5FFFF34 8 Timer status register 4 TSR4 2 R/(W)* H'F8/H'78 H'5FFFF35 8 Timer counter 4 TCNT4 R/W H'5FFFF36 8, 16 H'5FFFF37 8, 16 H'5FFFF38 8, 16, 32 H'5FFFF39 8, 16, 32 General register A4 GRA4 R/W H'00 H'FF Rev. 7.00 Jan 31, 2006 page 233 of 658 REJ09B0272-0700 Section 10 16-Bit Integrated Timer Pulse Unit (ITU) Channel Name Abbreviation R/W Initial Value Address* 4 General register B4 GRB4 R/W H'FF H'5FFFF3A Buffer register A4 BRA4 R/W H'FF Buffer register B4 BRB4 R/W H'FF 1 Access Size 8, 16, 32 H'5FFFF3B 8, 16, 32 H'5FFFF3C 8, 16, 32 H'5FFFF3D 8, 16, 32 H'5FFFF3E 8, 16, 32 H'5FFFF3F 8, 16, 32 Notes: 1. Only the values of bits A27-A24 and A8-A0 are valid; bits A23-A9 are ignored. For details on the register addresses, see section 8.3.5, Area Descriptions. 2. Only 0 can be written to clear flags. 10.2 ITU Register Descriptions 10.2.1 Timer Start Register (TSTR) The timer start register (TSTR) is an eight-bit read/write register that starts and stops the timer counters (TCNT) of channels 0-4. TSTR is initialized to H'E0 or H'60 by a reset and in standby mode. Bit 7 6 5 4 3 2 1 0 -- -- -- STR4 STR3 STR2 STR1 STR0 Initial value * 1 1 0 0 0 0 0 Read/Write -- -- -- R/W R/W R/W R/W R/W Note: * Undefined Bits 7-5--Reserved: Cannot be modified. Bit 7 is read as undefined. Bits 6 and 5 are always read as 1. The write value to bit 7 should be 0 or 1, and the write value to bits 6 and 5 should always be 1. Bit 4--Count Start 4 (STR4): STR4 starts and stops TCNT4. Bit 4: STR4 Description 0 TCNT4 is halted 1 TCNT4 is counting Rev. 7.00 Jan 31, 2006 page 234 of 658 REJ09B0272-0700 (Initial value) Section 10 16-Bit Integrated Timer Pulse Unit (ITU) Bit 3--Count Start 3 (STR3): STR3 starts and stops TCNT3. Bit 3: STR3 Description 0 TCNT3 is halted 1 TCNT3 is counting (Initial value) Bit 2--Count Start 2 (STR2): STR2 starts and stops TCNT2. Bit 2: STR2 Description 0 TCNT2 is halted 1 TCNT2 is counting (Initial value) Bit 1--Count Start 1 (STR1): STR1 starts and stops TCNT1. Bit 1: STR1 Description 0 TCNT1 is halted 1 TCNT1 is counting (Initial value) Bit 0--Count Start 0 (STR0): STR0 starts and stops TCNT0. Bit 0: STR0 Description 0 TCNT0 is halted 1 TCNT0 is counting 10.2.2 (Initial value) Timer Synchro Register (TSNC) The timer synchro register (TSNC) is an eight-bit read/write register that selects timer synchronizing modes for channels 0-4. Channels for which 1 is set in the corresponding bit will be synchronized. TSNC is initialized to H'E0 or H'60 by a reset and in standby mode. Bit 7 6 5 4 3 2 1 0 -- -- -- SYNC4 SYNC3 SYNC2 SYNC1 SYNC0 Initial value * 1 1 0 0 0 0 0 Read/Write -- -- -- R/W R/W R/W R/W R/W Note: * Undefined Rev. 7.00 Jan 31, 2006 page 235 of 658 REJ09B0272-0700 Section 10 16-Bit Integrated Timer Pulse Unit (ITU) Bits 7-5 Reserved: Bit 7 is read as undefined. Bits 6 and 5 are always read as 1. The write value to bit 7 should be 0 or 1, and the write value to bits 6 and 5 should always be 1. Bit 4--Timer Synchro 4 (SYNC4): SYNC4 selects synchronizing mode for channel 4. Bit 4: SYNC4 Description 0 The timer counter for channel 4 (TCNT4) operates independently (Preset/clear of TCNT4 is independent of other channels) (Initial value) 1 Channel 4 operates synchronously. Synchronized preset/clear of TNCT4 enabled. Bit 3--Timer Synchro 3 (SYNC3): SYNC3 selects synchronizing mode for channel 3. Bit 3: SYNC3 Description 0 The timer counter for channel 3 (TCNT3) operates independently (Preset/clear of TCNT3 is independent of other channels) (Initial value) 1 Channel 3 operates synchronously. Synchronized preset/clear of TNCT3 enabled. Bit 2--Timer Synchro 2 (SYNC2): SYNC2 selects synchronizing mode for channel 2. Bit 2: SYNC2 Description 0 The timer counter for channel 2 (TCNT2) operates independently (Preset/clear of TCNT2 is independent of other channels) (Initial value) 1 Channel 2 operates synchronously. Synchronized preset/clear of TNCT2 enabled. Bit 1--Timer Synchro 1 (SYNC1): SYNC1 selects synchronizing mode for channel 1. Bit 1: SYNC1 Description 0 The timer counter for channel 1 (TCNT1) operates independently (Preset/clear of TCNT1 is independent of other channels) (Initial value) 1 Channel 1 operates synchronously. Synchronized preset/clear of TNCT1 enabled. Rev. 7.00 Jan 31, 2006 page 236 of 658 REJ09B0272-0700 Section 10 16-Bit Integrated Timer Pulse Unit (ITU) Bit 0--Timer Synchro 0 (SYNC0): SYNC0 selects synchronizing mode for channel 0. Bit 0: SYNC0 Description 0 The timer counter for channel 0 (TCNT0) operates independently (Preset/clear of TCNT0 is independent of other channels) (Initial value) 1 Channel 0 operates synchronously. Synchronized preset/clear of TNCT0 enabled. 10.2.3 Timer Mode Register (TMDR) The timer mode register (TMDR) is an eight-bit read/write register that selects PWM mode for channels 0-4, sets phase counting mode for channel 2, and sets the conditions for the overflow flag (OVF). TMDR is initialized to H'80 or H'00 by a reset and in standby mode. Bit 7 6 5 4 3 2 1 0 -- MDF FDIR PWM4 PWM3 PWM2 PWM1 PWM0 Initial value * 0 0 0 0 0 0 0 Read/Write -- R/W R/W R/W R/W R/W R/W R/W Note: * Undefined Bit 7--Reserved: Bit 7 is read as undefined. The write value should be 0 or 1. Bit 6--Phase Counting Mode (MDF): MDF selects phase counting mode for channel 2. Bit 6: MDF Description 0 Channel 2 operates normally 1 Channel 2 operates in phase counting mode (Initial value) When the MDF bit is set to 1 to select phase counting mode, the timer counter (TCNT2) becomes an up/down-counter and the TCLKA and TCLKB pins become count clock input pins. TCNT2 counts on both the rising and falling edges of TCLKA and TCLKB, with increment/decrement chosen as follows: Count Direction Decrement TCLKA pin Rising High Falling Low Rising High Falling Low TCLKB pin Low Rising High Falling High Falling Low Rising Increment Rev. 7.00 Jan 31, 2006 page 237 of 658 REJ09B0272-0700 Section 10 16-Bit Integrated Timer Pulse Unit (ITU) In phase counting mode, selections for external clock edge made with the CKEG1 and CKEG0 bits in timer control register 2 (TCR2) and the counter clock selection made in the TPSC2-TPSC0 bits are ignored. The phase counting mode described above takes priority. Settings for counter clear conditions in the CCLR1 and CCLR0 bits in TCR2 and settings for timer I/O control register 2 (TIOR2), timer interrupt enable register (TIER2), and timer status register 2 (TSR2) compare match/input capture functions and interrupts, however, are valid even in phase counting mode. Bit 5--Flag Direction (FDIR): FDIR selects the setting condition for the overflow flag (OVF) in timer status register 2 (TSR2). This bit is valid no matter which mode channel 2 is operating in. Bit 5: FDIR Description 0 OVF of TSR2 is set to 1 when TCNT2 overflows or underflows 1 OVF of TSR2 is set to 1 when TCNT2 overflows (Initial value) Bit 4--PWM Mode 4 (PWM4): PWM4 selects PWM mode for channel 4. When the PWM4 bit is set to 1 and PWM mode is entered, the TIOCA4 pin becomes a PWM output pin. 1 is output on a compare match of general register A4 (GRA4); 0 is output on a compare match of general register B4 (GRB4). When complementary PWM mode or reset-synchronized PWM mode is set by the CMD1 and CMD0 bits in the timer function control register (TFCR), the setting of this bit is ignored in favor of the settings of CMD1 and CMD0. Bit 4: PWM4 Description 0 Channel 4 operates normally 1 Channel 4 operates in PWM mode (Initial value) Bit 3--PWM Mode 3 (PWM3): PWM3 selects the PWM mode for channel 3. When the PWM3 bit is set to 1 and PWM mode is entered, the TIOCA3 pin becomes a PWM output pin. 1 is output on a compare match of general register A3 (GRA3); 0 is output on a compare match of general register B3 (GRB3). When complementary PWM mode or reset-synchronized PWM mode is set by the CMD1 and CMD0 bits in the timer function control register (TFCR), the setting of this bit is ignored in favor of the settings of CMD1 and CMD0. Bit 3: PWM3 Description 0 Channel 3 operates normally 1 Channel 3 operates in PWM mode (Initial value) Bit 2--PWM Mode 2 (PWM2): PWM2 selects the PWM mode for channel 2. When the PWM2 bit is set to 1 and PWM mode is entered, the TIOCA2 pin becomes a PWM output pin. 1 is output Rev. 7.00 Jan 31, 2006 page 238 of 658 REJ09B0272-0700 Section 10 16-Bit Integrated Timer Pulse Unit (ITU) on a compare match of general register A2 (GRA2); 0 is output on a compare match of general register B2 (GRB2). Bit 2: PWM2 Description 0 Channel 2 operates normally 1 Channel 2 operates in PWM mode (Initial value) Bit 1--PWM Mode 1 (PWM1): PWM1 selects the PWM mode for channel 1. When the PWM1 bit is set to 1 and PWM mode is entered, the TIOCA1 pin becomes a PWM output pin. 1 is output on a compare match of general register A1 (GRA1); 0 is output on a compare match of general register B1 (GRB1). Bit 1: PWM1 Description 0 Channel 1 operates normally 1 Channel 1 operates in PWM mode (Initial value) Bit 0--PWM Mode 0 (PWM0): PWM0 selects the PWM mode for channel 0. When the PWM0 bit is set to 1 and PWM mode is entered, the TIOCA0 pin becomes a PWM output pin. 1 is output on a compare match of general register A0 (GRA0); 0 is output on a compare match of general register B0 (GRB0). Bit 0: PWM0 Description 0 Channel 0 operates normally 1 Channel 0 operates in PWM mode 10.2.4 (Initial value) Timer Function Control Register (TFCR) The timer function control register (TFCR) is an 8-bit read/write register that selects complementary PWM/reset-synchronized PWM for channels 3 and 4 and sets the buffer operation. TFCR is initialized to H'C0 or H'40 by a reset and in standby mode. Bit 7 6 5 4 3 2 1 0 -- -- CMD1 CMD0 BFB4 BFA4 BFB3 BFA3 Initial value * 1 0 0 0 0 0 0 Read/Write -- -- R/W R/W R/W R/W R/W R/W Note: * Undefined Rev. 7.00 Jan 31, 2006 page 239 of 658 REJ09B0272-0700 Section 10 16-Bit Integrated Timer Pulse Unit (ITU) Bits 7 and 6--Reserved: Bit 7 is read as undefined. Bit 6 is always read as 1. The write value to bit 7 should be 0 or 1. The write value to bit 6 should always be 1. Bits 5 and 4--Combination Mode 1 and 0 (CMD1 and CMD0): CMD1 and CMD0 select complementary PWM mode or reset-synchronized mode for channels 3 and 4. Set the complementary PWM/reset-synchronized PWM mode while the timer counter (TCNT) being used is off. When these bits are used to set complementary PWM/reset-synchronized PWM mode, they take priority over the PWM4 and PWM3 bits in TMDR. While the complementary PWM/resetsynchronized PWM mode settings and the SYNC4 and SYNC3 bit settings of the timer synchro register (TSNC) are valid simultaneously, when complementary PWM mode is set, channels 3 and 4 should not be set to operate simultaneously (the SYNC 4 and SYNC 3 bits in TSNC should not both be set to 1). Bit 5: CMD1 Bit 4: CMD0 Description 0 0 1 Channels 3 and 4 operate normally 1 0 Channels 3 and 4 operate together in complementary PWM mode 1 Channels 3 and 4 operate together in reset-synchronized PWM mode Channels 3 and 4 operate normally (Initial value) Bit 3--Buffer Mode B4 (BFB4): BFB4 selects buffer mode for GRB4 and BRB4 in channel 4. Bit 3: BFB4 Description 0 GRB4 operates normally in channel 4 1 GRB4 and BRB4 operate in buffer mode in channel 4 (Initial value) Bit 2--Buffer Mode A4 (BFA4): BFA4 selects buffer mode for GRA4 and BRA4 in channel 4. Bit 2: BFA4 Description 0 GRA4 operates normally in channel 4 1 GRA4 and BRA4 operate in buffer mode in channel 4 (Initial value) Bit 1--Buffer Mode B3 (BFB3): BFB3 selects buffer mode for GRB3 and BRB3 in channel 3. Bit 1: BFB3 Description 0 GRB3 operates normally in channel 3 1 GRB3 and BRB3 operate in buffer mode in channel 3 Rev. 7.00 Jan 31, 2006 page 240 of 658 REJ09B0272-0700 (Initial value) Section 10 16-Bit Integrated Timer Pulse Unit (ITU) Bit 0--Buffer Mode A3 (BFA3): BFA3 selects buffer mode for GRA3 and BRA3 in channel 3. Bit 0: BFA3 Description 0 GRA3 operates normally in channel 3 1 GRA3 and BRA3 operate in buffer mode in channel 3 10.2.5 (Initial value) Timer Output Control Register (TOCR) The timer output control register (TOCR) is an eight-bit read/write register that inverts the output level in complementary PWM mode/reset-synchronized PWM mode. Setting bits OLS3 and OLS4 is valid only in complementary PWM mode and reset-synchronized PWM mode. In other output situations, these bits are ignored. TOCR is initialized to H'FF or H'7F by a reset and in standby mode. Bit 7 6 5 4 3 2 1 0 -- -- -- -- -- -- OLS4 OLS3 Initial value * 1 1 1 1 1 1 1 Read/Write -- -- -- -- -- -- R/W R/W Note: * Undefined Bits 7-2--Reserved: Bit 7 is read as undefined. Bits 6-2 are always read as 1. The write value to bit 7 should be 0 or 1. The write value to bits 6-2 should always be 1. Bit 1--Output Level Select 4 (OLS4): OLS4 selects the output level for complementary PWM mode or reset-synchronized PWM mode. Bit 1: OLS4 Description 0 TIOCA3, TIOCA4, and TIOCB4 are inverted and output 1 TIOCA3, TIOCA4, and TIOCB4 are output directly (Initial value) Bit 0--Output Level Select 3 (OLS3): OLS3 selects the output level for complementary PWM mode or reset-synchronized PWM mode. Bit 0: OLS3 Description 0 TIOCB3, TOCXA4, and TOCXB4 are inverted and output 1 TIOCB3, TOCXA4, and TOCXB4 are output directly (Initial value) Rev. 7.00 Jan 31, 2006 page 241 of 658 REJ09B0272-0700 Section 10 16-Bit Integrated Timer Pulse Unit (ITU) 10.2.6 Timer Counters (TCNT) The ITU has five 16-bit timer counters (TCNT), one for each channel. Each TCNT is a 16-bit read/write counter that counts by input from a clock source. The clock source is selected by timer prescaler bits 2-0 (TPSC2-TPSC0) in the timer control register (TCR). TCNT0 and TCNT 1 are strictly up-counters. Up/down-counting occurs for TCNT2 when phase counting mode is selected, or for TCNT3 and TCNT 4 when complementary PWM mode is selected. In other modes, they are up-counters. TCNT can be cleared to H'0000 by compare match with the corresponding general register A or B (GRA, GRB) or input capture to GRA or GRB (counter clear function). When TCNT overflows (changes from H'FFFF to H'0000), the overflow flag (OVF) in the timer status register (TSR) is set to 1. The OVF of the corresponding channel TSR is also set to 1 when TCNT underflows (changes from H'0000 to H'FFFF). TCNT is connected to the CPU by a 16-bit bus, so it can be written or read by either word access or byte access. TCNT is initialized to H'0000 by a reset and in standby mode. Table 10.4 Timer Counters (TCNT) Channel Abbreviation Function 0 TCNT0 Increment counter 1 TCNT1 2 TCNT2 Phase counting mode: Increment/decrement All others: Increment 3 TCNT3 4 TCNT4 Complementary PWM mode: Increment/decrement All others: Increment Bit 15 14 13 12 11 10 9 8 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Bit 7 6 5 4 3 2 1 0 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Rev. 7.00 Jan 31, 2006 page 242 of 658 REJ09B0272-0700 Section 10 16-Bit Integrated Timer Pulse Unit (ITU) 10.2.7 General Registers A and B (GRA and GRB) Each of the five ITU channels has two 16-bit general registers (GR) for a total of ten registers. Each GR is a 16-bit read/write register that can function as either an output compare register or an input capture register. The function is selected by settings in the timer I/O control register (TIOR). When a general register (GRA/GRB) is used as an output compare register, its value is constantly compared with the timer counter (TCNT) value. When the two values match (compare match), the IMFA/IMFB bit is set to 1 in the timer status register (TSR). If compare match output is selected in TIOR, a specified value is output at the output compare pin. When a general register is used as an input capture register, an external input capture signal is detected and the TCNT value is stored. The IMFA/IMFB bit in the corresponding TSR is set to 1 at the same time. The valid edge or edges of the input capture signal are selected in TIOR. The TIOR setting is ignored when set for PWM mode, complementary PWM mode, or resetsynchronized PWM mode. General registers are connected to the CPU by a 16-bit bus, so general registers can be written or read by either word access or byte access. General registers are initialized as output compare registers (no pin output) by a reset and in standby mode. The initial value is H'FFFF. Table 10.5 General Registers A and B (GRA and GRB) Channel Abbreviation Function 0 GRA0, GRB0 1 GRA1, GRB1 2 GRA2, GRB2 3 GRA3, GRB3 Output compare/input capture dual register. Can also be set for buffer 4 GRA4, GRB4 operation in combination with the buffer registers (BRA, BRB) Bit 15 14 13 12 11 10 9 8 Initial value 1 1 1 1 1 1 1 1 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 Bit Output compare/input capture dual register Initial value 1 1 1 1 1 1 1 1 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Rev. 7.00 Jan 31, 2006 page 243 of 658 REJ09B0272-0700 Section 10 16-Bit Integrated Timer Pulse Unit (ITU) 10.2.8 Buffer Registers A and B (BRA, BRB) Each buffer register is a 16-bit read/write register that is used in buffer mode. The ITU has four buffer registers, two each for channels 3 and 4. Buffer operation can be set independently by the timer function control register (TFCR) bits BFB4, BFA4, BFB3, and BFB3. The buffer registers are paired with the general registers and their function changes automatically to match the function of corresponding general register. The buffer registers are connected to the CPU by a 16-bit bus, so they can be written or read by either word or byte access. Buffer registers are initialized to H'FFFF by a reset and in standby mode. Table 10.6 Buffer Registers A and B (BRA, BRB) Channel Abbreviation Function 3 BRA3, BRB3 4 BRA4, BRB4 When used for buffer operation: When the corresponding GRA and GRB are output compare registers, the buffer registers function as output compare buffer registers that can automatically transfer the BRA and BRB values to GRA and GRB upon a compare match. When the corresponding GRA and GRB are input capture registers, the buffer registers function as input capture buffer registers that can automatically transfer the values stored until an input capture in the GRA and GRB to the BRA and BRB. Bit 15 14 13 12 11 10 9 8 Initial value 1 1 1 1 1 1 1 1 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 Bit Initial value 1 1 1 1 1 1 1 1 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Rev. 7.00 Jan 31, 2006 page 244 of 658 REJ09B0272-0700 Section 10 16-Bit Integrated Timer Pulse Unit (ITU) 10.2.9 Timer Control Register (TCR) The ITU has five 8-bit timer control registers (TCR), one for each channel. TCR is an 8-bit read/write register that selects the timer counter clock, the edges of the external clock source, and the counter clear source. TCR is initialized to H'80 or H'00 by a reset and in standby mode. Table 10.7 Timer Control Register (TCR) Channel Abbreviation 0 TCR0 1 TCR1 2 TCR2 3 TCR3 4 TCR4 Bit Function TCR controls the TCNTs. The TCRs have the same functions on all channels. When channel 2 is set for phase counting mode, setting the CKEG1, CKEG2, and TPSC2-TPSC0 bits will have no effect. 7 6 5 4 3 2 1 0 -- CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0 Initial value * 0 0 0 0 0 0 0 Read/Write -- R/W R/W R/W R/W R/W R/W R/W Note: * Undefined Bit 7--Reserved: Bit 7 is read as undefined. The write value should be 0 or 1. Rev. 7.00 Jan 31, 2006 page 245 of 658 REJ09B0272-0700 Section 10 16-Bit Integrated Timer Pulse Unit (ITU) Bits 6 and 5--Counter Clear 1 and 0 (CCLR1 and CCLR0): CCLR1 and CCLR0 select the counter clear source. Bit 6: CCLR1 Bit 5: CCLR0 Description 0 0 TCNT is not cleared 1 TCNT is cleared by general register A (GRA) compare match or input 1 capture* 0 TCNT is cleared by general register B (GRB) compare match or input 1 capture* 1 Synchronizing clear: TCNT is cleared in synchronization with clear of other 2 timer counters operating in sync* 1 (Initial value) Notes: 1. When GR is functioning as an output compare register, TCNT is cleared upon a compare match. When functioning as an input capture register, TCNT is cleared upon input capture. 2. The timer synchro register (TSNC) sets the synchronization. Bits 4 and 3--External Clock Edge 1/0 (CKEG1 and CKEG0): CKEG1 and CKEG0 select external clock input edge. When channel 2 is set for phase counting mode, settings of the CKEG1 and CKEG0 bits in TCR are ignored and the phase counting mode operation takes priority. Bit 4: Bit 3: CKEG1 CKEG0 Description 0 0 Count rising edges 1 Count falling edges -- Count both rising and falling edges 1 Rev. 7.00 Jan 31, 2006 page 246 of 658 REJ09B0272-0700 (Initial value) Section 10 16-Bit Integrated Timer Pulse Unit (ITU) Bits 2-0--Timer Prescaler 2-0 (TPS2-TPS0): TPS2-TPS0 select the counter clock source. When TPSC2 = 0 and an internal clock source is selected, the timer counts only falling edges. When TPSC2 = 1 and an external clock is selected, the count edge is as set by CKEG1 and CKEG0. When phase counting mode is selected for channel 2 (the MDF bit in the timer mode register is 1), the settings of TPSC2-TPSC0 in TCR2 are ignored and the phase counting operation takes priority. Bit 2: TPSC2 Bit 1: TPSC1 Bit 0: TPSC0 Counter Clock (and Cycle when = 10 MHz) 0 0 0 Internal clock 1 Internal clock /2 1 0 Internal clock /4 1 Internal clock /8 0 External clock A (TCLKA) 1 External clock B (TCLKB) 0 External clock C (TCLKC) 1 External clock D (TCLKD) 1 0 1 (Initial value) 10.2.10 Timer I/O Control Register (TIOR) The timer I/O control register (TIOR) is an eight-bit read/write register that selects the output compare or input capture function for general registers GRA and GRB. It also selects the function of the TIOCA and TIOCB pins. If output compare is selected, TIOR also selects the output settings. If input capture is selected, TIOR also selects the input capture edge. TIOR is initialized to H'88 or H'08 by a reset and in standby mode. Each ITU channel has one TIOR. Table 10.8 Timer I/O Control Register (TIOR) Channel Abbreviation 0 TIOR0 1 TIOR1 2 TIOR2 3 TIOR3 4 TIOR4 Function TIOR controls the GRs. Some functions vary during PWM. When channels 3 and 4 are set for complementary PWM mode/resetsynchronized PWM mode, TIOR3 and TIOR4 settings are not valid. Rev. 7.00 Jan 31, 2006 page 247 of 658 REJ09B0272-0700 Section 10 16-Bit Integrated Timer Pulse Unit (ITU) Bit 7 6 5 4 3 2 1 0 -- IOB2 IOB1 IOB0 -- IOA2 IOA1 IOA0 Initial value * 0 0 0 1 0 0 0 Read/Write -- R/W R/W R/W -- R/W R/W R/W Note: * Undefined Bit 7--Reserved: Bit 7 is read as undefined. The write value should be 0 or 1. Bits 6-4--I/O Control B2-B0 (IOB2-IOB0): IOB2-IOB0 selects the GRB function. Bit 6: IOB2 Bit 5: IOB1 Bit 4: IOB0 GRB Function 0 0 0 GRB is an output compare register 1 1 0 1 1 0 0 1 1 0 Compare match with pin output disabled (Initial value) 1 0 output at GRB compare match* 1 1 output at GRB compare match* Output toggles at GRB compare match (1 output for 1 2 channel 2 only)* * GRB is an GRB captures rising edge of input input capture GRB captures falling edge of input register GRB captures both edges of input 1 Notes: 1. After reset, the value output is 0 until the first compare match occurs. 2. Channel 2 has no compare-match driven toggle output function. If it is set for toggle, 1 is automatically selected as the output. Bit 3--Reserved: Bit 3 always is read as 1. The write value should always be 1. Rev. 7.00 Jan 31, 2006 page 248 of 658 REJ09B0272-0700 Section 10 16-Bit Integrated Timer Pulse Unit (ITU) Bits 2-0--I/O Control A2-A0 (IOA2-IOA0): IOA2-IOA0 select the GRB function. Bit 2: IOA2 Bit 1: IOA1 Bit 0: IOA0 GRA Function 0 0 0 GRA is an output compare register 1 1 0 1 1 0 1 0 output at GRA compare match* 1 1 output at GRA compare match* Output toggles at GRA compare match (1 output for 1 2 channel 2 only)* * GRA is an input capture register 0 1 1 Compare match with pin output disabled (Initial value) 0 GRA captures rising edge of input GRA captures falling edge of input GRA captures both edges of input 1 Notes: 1. After reset, the value output is 0 until the first compare match occurs. 2. Channel 2 has no compare-match driven toggle output function. If it is set for toggle, 1 is automatically selected as the output. 10.2.11 Timer Status Register (TSR) The timer status register (TSR) is an eight-bit read/write register containing flags that indicate timer counter (TCNT) overflow/underflow and general register (GRA/GRB) compare match or input capture. These flags are interrupt sources. If the interrupt is enabled by the corresponding bit in the timer interrupt enable register (TIER), an interrupt request is sent to the CPU. TSR is initialized to H'F8 or H'78 by a reset and in standby mode. Each ITU channel has one TSR. Table 10.9 Timer Status Register (TSR) Channel Abbreviation Function 0 TSR0 1 TSR1 TSR indicates input capture, compare match and overflow status. 2 TSR2 3 TSR3 4 TSR4 Rev. 7.00 Jan 31, 2006 page 249 of 658 REJ09B0272-0700 Section 10 16-Bit Integrated Timer Pulse Unit (ITU) Bit 7 6 5 4 3 2 1 0 -- -- -- -- -- OVF IMFB IMFA Initial value *1 1 1 1 1 0 Read/Write -- -- -- -- -- R/(W)* 0 2 0 2 R/(W)* 2 R/(W)* Notes: 1. Undefined 2. Only 0 can be written, to clear the flag. Bits 7-3--Reserved: Bit 7 is read as undefined. Bits 6-3 are always read as 1. The write value to bit 7 should be 0 or 1. The write value to bits 6-3 should always be 1. Bit 2--Overflow Flag (OVF): OVF indicates that a TCNT overflow/underflow has occurred. Bit 2: OVF Description 0 Clearing condition: Read OVF when OVF = 1, then write 0 in OVF (Initial value) 1 Setting condition: TCNT overflow from H'FFFF to H'0000 or underflow from H'0000 to H'FFFF Note: A TCNT underflow occurs when the TCNT up/down-counter is functioning. It may occur in the following cases: (1) When channel 2 is set to phase counting mode (MDF bit in TMDR is 1), or (2) when channel 3 and 4 are set to complementary PWM mode (CMD1 bit in TFCR is 1 and CMD0 bit is 0). Bit 1--Input Capture/Compare Match B (IMFB): IMFB indicates a GRB compare match or input capture. Bit 1: IMFB Description 0 Clearing condition: Read IMFB when IMFB = 1, then write 0 in IMFB (Initial value) 1 Setting conditions: * GRB is functioning as an output compare register and TCNT = GRB * GRB is functioning as an input capture register and the value of TCNT is transferred to GRB by an input capture signal Rev. 7.00 Jan 31, 2006 page 250 of 658 REJ09B0272-0700 Section 10 16-Bit Integrated Timer Pulse Unit (ITU) Bit 0--Input Capture/Compare Match A (IMFA): IMFA indicates a GRA compare match or input capture. Bit 0: IMFA Description 0 Clearing condition: Read IMFA when IMFA = 1, then write 0 in IMFA (Initial value) DMAC is activated by an IMIA interrupt (only channels 0-3) 1 Setting conditions: * GRA is functioning as an output compare register and TCNT = GRA * GRA is functioning as an input capture register and the value of TCNT is transferred to GRA by an input capture signal 10.2.12 Timer Interrupt Enable Register (TIER) The timer status interrupt enable register (TIER) is an eight-bit read/write register that controls enabling/disabling of overflow interrupt requests and general register compare match/input capture interrupt requests. TIER is initialized to H'F8 or H'78 by a reset and in standby mode. Each ITU channel has one TIER. Table 10.10 Timer Interrupt Enable Register (TIER) Channel Abbreviation Function 0 TIER0 TIER controls interrupt enabling/disabling 1 TIER1 2 TIER2 3 TIER3 4 TIER4 Bit 7 6 5 4 3 2 1 0 -- -- -- -- -- OVIE IMIEB IMIEA Initial value * 1 1 1 1 0 0 0 Read/Write -- -- -- -- -- R/W R/W R/W Note: * Undefined Bits 7-3--Reserved: Bit 7 is read as undefined. Bits 6-3 are always read as 1. The write value to bit 7 should be 0 or 1. The write value to bits 6-3 should always be 1. Rev. 7.00 Jan 31, 2006 page 251 of 658 REJ09B0272-0700 Section 10 16-Bit Integrated Timer Pulse Unit (ITU) Bit 2--Overflow Interrupt Enable (OVIE): When the TSR overflow flag (OVF) is set to 1, OVIE enables or disables interrupt requests from OVF. Bit 2: OVIE Description 0 Disables interrupt requests by OVF 1 Enables interrupt requests from OVF (Initial value) Bit 1--Input Capture/Compare Match Interrupt Enable B (IMIEB): When the IMFB bit in TSR is set to 1, IMIEB enables or disables interrupt requests by IMFB. Bit 1: IMIEB Description 0 Disables interrupt requests by IMFB (IMIB) 1 Enables interrupt requests by IMFB (IMIB) (Initial value) Bit 0--Input Capture/Compare Match Interrupt Enable A (IMIEA): When the IMFA bit in TSR is set to 1, IMIEA enables or disables interrupt requests by IMFA. Bit 0: IMIEA Description 0 Disables interrupt requests by IMFA (IMIA) 1 Enables interrupt requests by IMFA (IMIA) Rev. 7.00 Jan 31, 2006 page 252 of 658 REJ09B0272-0700 (Initial value) Section 10 16-Bit Integrated Timer Pulse Unit (ITU) 10.3 CPU Interface 10.3.1 16-Bit Accessible Registers The timer counters (TCNT), general registers A and B (GRA, GRB), and buffer registers A and B (BRA, BRB) are 16-bit registers. The SH CPU can access these registers a word at a time using a 16-bit data bus. Byte access is also possible. Read and write operations performed on TCNT in word units are shown in figures 10.6 and 10.7. Byte-unit read and write operations on TCNTH and TCNTL are shown in figures 10.8 to 10.11. Internal data bus H H CPU Bus interface L L TCNTH Module data bus TCNTL Figure 10.6 TCNT Access (CPU to TCNT (Word)) Internal data bus H H CPU Bus interface L L TCNTH Module data bus TCNTL Figure 10.7 TCNT Access (TCNT to CPU (Word)) Internal data bus H H CPU L Bus interface L TCNTH Module data bus TCNTL Figure 10.8 TCNT Access (CPU to TCNT (Upper Byte)) Rev. 7.00 Jan 31, 2006 page 253 of 658 REJ09B0272-0700 Section 10 16-Bit Integrated Timer Pulse Unit (ITU) Internal data bus H H CPU Bus interface L L TCNTH Module data bus TCNTL Figure 10.9 TCNT Access (CPU to TCNT (Lower Byte)) Internal data bus H H CPU Bus interface L L TCNTH Module data bus TCNTL Figure 10.10 TCNT Access (TCNT to CPU (Upper Byte)) Internal data bus H H CPU L Bus interface L TCNTH TCNTL Figure 10.11 TCNT Access (TCNT to CPU (Lower Byte)) Rev. 7.00 Jan 31, 2006 page 254 of 658 REJ09B0272-0700 Module data bus Section 10 16-Bit Integrated Timer Pulse Unit (ITU) 10.3.2 8-Bit Accessible Registers All registers other than the TCNT register, general registers, and buffer registers are 8-bit registers. These are connected to the CPU by an 8-bit data bus. Figures 10.12 and 10.13 illustrate reading and writing in byte units with the timer control register (TCR). These registers must be accessed by byte access. Internal data bus Module data bus Bus interface CPU TCR Figure 10.12 TCR Access (CPU to TCR) Internal data bus CPU Module data bus Bus interface TCR Figure 10.13 TCR Access (TCR to CPU ) Rev. 7.00 Jan 31, 2006 page 255 of 658 REJ09B0272-0700 Section 10 16-Bit Integrated Timer Pulse Unit (ITU) 10.4 Operation 10.4.1 Overview The operation modes are described below. Ordinary Operation: Each channel has a timer counter (TCNT) and general register (GR). The TCNT is an up-counter and can also operate as a free-running counter, periodic counter, or external event counter. General registers A and B (GRA and GRB) can be used as output compare registers or input capture registers. Synchronized Operation: The TCNT of a channel set for synchronized operation perform synchronized presetting. When any TCNT of a channel operating in the synchronized mode is rewritten, the TCNTs in other channels are simultaneously rewritten as well. The CCLR1 and CCLR0 bits of the timer control register of multiple channels set for synchronous operation can be set to clear the TCNTs simultaneously. PWM Mode: In PWM mode, a PWM waveform is output from the TIOCA pin. Output becomes 1 upon compare match A and 0 upon compare match B. GRA and GRB can be set so that the PWM waveform output has a duty cycle between 0% and 100%. When set for PWM mode, the GRA and GRB automatically become output compare registers. Reset-Synchronized PWM Mode: Three pairs of positive and negative PWM waveforms can be obtained using channels 3 and 4 (the three phases of the PWM waveform share a transition point on one side). When set for reset-synchronized PWM mode, GRA3, GRB3, GRA4, and GRB4 automatically become output compare registers. The TIOCA3, TIOCB3, TIOCA4, TOCXA4, TIOCB4, and TOCXB4 pins also become PWM output pins and TCNT3 becomes an up-counter. TCNT4 functions independently (although GRA and GRB are isolated from TCNT4). Complementary PWM Mode: Three pairs of complementary positive and negative PWM waveforms whose positive and negative phases do not overlap can be obtained using channels 3 and 4. When set for complementary PWM mode, GRA3, GRB3, GRA4, and GRB4 automatically become output compare registers. The TIOCA3, TIOCB3, TIOCA4, TOCXA4, TIOCB4, and TOCXB4 pins also become PWM output pins while TCNT3 and TCNT4 become up-counters. Phase Counting Mode: In phase counting mode, the phase differential between two clocks input from the TCLKA and TCLKB pins is detected and the TCNT2 operates as an up/down-counter. In phase counting mode, the TCLKA and TCLKB pins become clock inputs and TCNT2 functions as an up/down-counter. Rev. 7.00 Jan 31, 2006 page 256 of 658 REJ09B0272-0700 Section 10 16-Bit Integrated Timer Pulse Unit (ITU) Buffer Mode: * When GR is an output compare register: The BR value of each channel is transferred to GR when a compare match occurs. * When GR is an input capture register: The TCNT value is transferred to GR when an input capture occurs and simultaneously the value previously stored in GR is transferred to BR. * Complementary PWM mode: When TCNT3 and TCNT4 change count directions, the BR value is transferred to GR. * Reset-synchronized PWM mode: The BR value is transferred to GR upon a GRA3 compare match. 10.4.2 Basic Functions Counter Operation: When a start bit (STR0-STR4) in the timer start register (TSTR) is set to 1, the corresponding timer counter (TCNT) starts counting. There are two counting modes: a freerunning mode and a periodic mode. * Procedure for selecting counting mode (figure 10.14): 1. Set bits TPSC2-TPSC0 in TCR to select the counter clock source. If an external clock source is selected, set bits CKEG1 and CKEG0 in TCR to select the desired edge of the external clock signal. 2. To operate as a periodic counter, set CCLR1 and CCLR0 in TCR to select whether to clear TCNT at GRA compare match or GRB compare match. 3. Set GRA or GRB selected in step 2 as an output compare register using the timer I/O control register (TIOR). 4. Write the desired cycle value in GRA or GRB selected in step 1. 5. Set the STR bit in TSTR to 1 to start counting. Rev. 7.00 Jan 31, 2006 page 257 of 658 REJ09B0272-0700 Section 10 16-Bit Integrated Timer Pulse Unit (ITU) Counting mode selection Select counter clock Counting? (1) No Yes Free-running counter Periodic counter Select counter clear source (2) Select output compare register (3) Set period (4) Start counting (5) Periodic counter Start counting (5) Free-running counter Figure 10.14 Procedure for Selecting the Counting Mode * Free-running count and periodic count A reset of the counters for channels 0-4 leaves them all in free-running mode. When a corresponding bit in TSTR is set to 1, the corresponding timer counter operates as a freerunning counter and begins to increment. When the count wraps around from H'FFFF to H'0000, the overflow flag (OVF) in the timer status register (TSR) is set to 1. If the OVIE bit in the timer's corresponding interrupt enable register (TIER) is set to 1, an interrupt request will be sent to the CPU. After TCNT overflows, counting continues from H'0000. Figure 10.15 shows an example of free-running counting. Periodic counter operation is obtained for a given channel's TCNT by selecting compare match as a TCNT clear source. (Set GRA or GRB for period setting to output compare register and select counter clear upon compare match using the CCLR1 and CCLR0 bits in the timer control register (TCR).) After setting, TCNT begins incrementing as a periodic counter when the corresponding bit in TSTR is set to 1. When the count matches GRA or GRB, the IMFA/IMFB bit in TSR is set to 1 and the counter is automatically cleared to H'0000. If the IMIEA/IMIEB bit of the corresponding TIER is set to 1 at this point, an interrupt request will be sent to the CPU. After the compare match, TCNT continues counting from H'0000. Figure 10.16 shows an example of periodic counting. Rev. 7.00 Jan 31, 2006 page 258 of 658 REJ09B0272-0700 Section 10 16-Bit Integrated Timer Pulse Unit (ITU) TCNT value H'FFFF H'0000 Time STR0-STR4 OVF Figure 10.15 Free-Running Counter Operation TCNT value Counter cleared by GR compare match GR H'0000 Time STR0-STR4 IMF Figure 10.16 Periodic Counter Operation * TCNT counter timing Internal clock source: Bits TPSC2-TPSC0 in TCR select the system clock (CK) or one of three internal clock sources (/2, /4, /8) obtained by prescaling the system clock. Figure 10.17 shows the timing. External clock source: The external clock input pin (TCLKA-TCLKD) source is selected by bits TPSC2-TPSC0 in TCR and its valid edges are selected with the CKEG1 and CKEG0 bits in TCR. The rising edge, falling edge, or both edges can be selected. The pulse width of the external clock signal must be at least 1.5 system clocks when a single edge is selected and at least 2.5 system clocks when both edges are selected. Shorter pulses will not be counted correctly. Figure 10.18 shows the timing when both edges are detected. Rev. 7.00 Jan 31, 2006 page 259 of 658 REJ09B0272-0700 Section 10 16-Bit Integrated Timer Pulse Unit (ITU) CK Internal clock TCNT input clock N-1 TCNT value N N+1 Figure 10.17 Count Timing for Internal Clock Sources CK External clock input pin TCNT input clock TCNT N-1 N N+1 Figure 10.18 Count Timing for External Clock Sources (Both-Edge Detection) Compare-Match Waveform Output Function: For ITU channels 0, 1, 3, and 4, the output from the corresponding TIOCA and TIOCB pins upon compare matches A and B can be in three modes: 0-level output, 1-level output, or toggle. Toggle output cannot be selected for channel 2. * Procedure for selecting the waveform output mode (figure 10.19): 1. Set TIOR to select 0 output, 1 output, or toggle output for compare match output. The compare match output pin will output 0 until the first compare match occurs. 2. Set a value in GRA or GRB to select the compare match timing. 3. Set the STR bit in TSTR to 1 to start counting. Rev. 7.00 Jan 31, 2006 page 260 of 658 REJ09B0272-0700 Section 10 16-Bit Integrated Timer Pulse Unit (ITU) Output selection Select waveform output mode (1) Select output timing (2) Start counting (3) Waveform output Figure 10.19 Procedure for Selecting Compare Match Waveform Output Mode * Waveform output operation Figure 10.20 illustrates 0 output/1 output. In the example, TCNT is a free-running counter, 0 is output upon compare match A, and 1 is output upon compare match B. When the pin level matches the set level, the pin level does not change. Figure 10.21 shows an example of toggle output. In the figure, TCNT operates as a periodic counter cleared by GRB compare match with toggle output at both compare match A and compare match B. TCNT value H'FFFF GRB GRA Time TIOCB Does not change Does not change 1 output TIOCA Does not change Does not change 0 output Figure 10.20 Example of 0 Output/1 Output Rev. 7.00 Jan 31, 2006 page 261 of 658 REJ09B0272-0700 Section 10 16-Bit Integrated Timer Pulse Unit (ITU) Counter cleared at GRB compare match TCNT value GRB GRA Time TIOCB Toggle output TIOCA Toggle output Figure 10.21 Example of Toggle Output * Compare match output timing The compare match signal is generated in the last state in which TCNT and the general register match (when TCNT changes from the matching value to the next value). When a compare match signal is generated, the output value set in TIOR is output to the output compare pin (TIOCA, TIOCB). Accordingly, when TCNT matches a general register, the compare match signal is not generated until the next counter clock pulse. Figure 10.22 shows the output timing of the compare match signal. CK TCNT input clock TCNT N GR N N-1 Compare match signal TIOCA TIOCB Figure 10.22 Compare Match Signal Output Timing Rev. 7.00 Jan 31, 2006 page 262 of 658 REJ09B0272-0700 Section 10 16-Bit Integrated Timer Pulse Unit (ITU) Input Capture Mode: In input capture mode, the counter value is captured into a general register when the input edge is detected at an input capture/output compare pin (TIOCA, TIOCB). Detection can take place on the rising edge, falling edge, or both edges. The pulse width and cycle can be measured by using the input capture function. * Procedure for selecting input capture mode (figure 10.23) 1. Set TIOR to select the input capture function of GR and select the rising edge, falling edge, or both edges as the input edge of the input capture signal. Put the corresponding port into input-capture mode using the pin function controller before setting TIOR. 2. Set the STR bit in TSTR to 1 to start the TCNT count. Input selection Select input-capture input (1) Start counting (2) Capture Figure 10.23 Procedure for Selecting Input Capture Mode Rev. 7.00 Jan 31, 2006 page 263 of 658 REJ09B0272-0700 Section 10 16-Bit Integrated Timer Pulse Unit (ITU) * Input capture operation Figure 10.24 illustrates input capture. The falling edge of TIOCB and both edges of TIOCA are selected as input capture edges. In the example, TCNT is set to clear at GRB input capture. TCNT value Counter cleared by TIOCB input (falling edge) H'0180 H'0160 H'0005 H'0000 Time TIOCB TIOCA GRA H'0005 H'0160 GRB H'0180 Figure 10.24 Input Capture Operation Rev. 7.00 Jan 31, 2006 page 264 of 658 REJ09B0272-0700 Section 10 16-Bit Integrated Timer Pulse Unit (ITU) * Input capture timing Input capture on the rising edge, falling edge, or both edges can be selected by settings in TIOR. Figure 10.25 shows the timing when the rising edge is selected. The pulse width of the input capture signal must be at least 1.5 system clocks for single-edge capture, and 2.5 system clocks for capture of both edges. CK Input capture input Input capture signal TCNT N GRA/GRB N Figure 10.25 Input Capture Signal Timing Rev. 7.00 Jan 31, 2006 page 265 of 658 REJ09B0272-0700 Section 10 16-Bit Integrated Timer Pulse Unit (ITU) 10.4.3 Synchronizing Mode In synchronizing mode, two or more timer counters can be rewritten simultaneously (synchronized preset). Multiple timer counters can also be cleared simultaneously using TCR settings (synchronized clear). Synchronizing mode enables the general registers to be incremented with a single time base. All five channels can be set for synchronous operation. Procedure for Selecting Synchronizing Mode (figure 10.26): 1. Set 1 in the SYNC bit of the timer synchro register (TSNC) to use the channels in the synchronizing mode. 2. When a value is written in TCNT in any of the synchronized channels, the same value is simultaneously written in TCNT in the other channels. 3. Set the counter to clear with compare match/input capture using bits CCLR1 and CCLR0 in TCR. 4. Set the counter clear source to synchronized clear using the CCLR1 and CCLR0 bits. 5. Set the STR bits in TSTR to 1 to start the TCNT count. Select synchronizing mode Set synchronizing mode (1) Synchronized preset Set TCNT Synchronized clear (2) Channel that generated clear source? Yes No Select counter clear source (3) Select counter clear source (4) Start counting (5) Start counting (5) Synchronizing preset Counter clear Synchronized clear Figure 10.26 Procedure for Selecting Synchronizing Mode Rev. 7.00 Jan 31, 2006 page 266 of 658 REJ09B0272-0700 Section 10 16-Bit Integrated Timer Pulse Unit (ITU) Synchronized Operation: Figure 10.27 shows an example of synchronized operation. Channels 0, 1, and 2 are set to synchronized operation and PWM output. Channel 0 is set for a counter clear upon compare match with GRB0. Channels 1 and 2 are set for counter clears by synchronizing clears. Accordingly, their timers are sync preset, then sync cleared by a GRB0 compare match, and then a three-phase PWM waveform is output from the TIOCA0, TIOCA1, and TIOCA2 pins. See section 10.4.4, PWM Mode, for details on PWM mode. TCNT0-TCNT2 values Synchronized clear on GRB0 compare match GRB0 GRB1 GRA0 GRB2 GRA1 GRA2 Time TIOCA0 TIOCA1 TIOCA2 Figure 10.27 Example of Synchronized Operation Rev. 7.00 Jan 31, 2006 page 267 of 658 REJ09B0272-0700 Section 10 16-Bit Integrated Timer Pulse Unit (ITU) 10.4.4 PWM Mode PWM mode is controlled using both GRA and GRB in pairs. The PWM waveform is output from the TIOCA output pin. The PWM waveform's 1 output timing is set in GRA and the 0 output timing is set in GRB. A PWM waveform with a duty cycle between 0% and 100% can be output from the TIOCA pin by selecting either compare match GRA or GRB as the counter clear source for the timer counter. All five channels can be set to PWM mode. Table 10.11 lists the combinations of PWM output pins and registers. Note that when GRA and GRB are set to the same value, the output will not change even if a compare match occurs. Table 10.11 Combinations of PWM Output Pins and Registers Channel Output Pin 1 Output 0 Output 0 TIOCA0 GRA0 GRB0 1 TIOCA1 GRA1 GRB1 2 TIOCA2 GRA2 GRB2 3 TIOCA3 GRA3 GRB3 4 TIOCA4 GRA4 GRB4 Procedure for Selecting PWM Mode (Figure 10.28): 1. Set bits TPSC2-TPSC0 in TCR to select the counter clock source. If an external clock source is selected, set bits CKEG1 and CKEG0 in TCR to select the desired edge of the external clock signal. 2. Set CCLR1 and CCLR0 in TCR to select the counter clear source. 3. Set the time at which the PWM waveform should go to 1 in GRA. 4. Set the time at which the PWM waveform should go to 0 in GRB. 5. Set the PWM bit in TMDR to select PWM mode. When PWM mode is selected, regardless of the contents of TIOR, GRA and GRB become output compare registers specifying the times at which the PWM waveform goes high and low. TIOCA becomes a PWM output pin. TIOCB functions according to the setting of bits IOB1 and IOB0 in TIOR. 6. Set the STR bit in TSTR to start the TCNT count. Rev. 7.00 Jan 31, 2006 page 268 of 658 REJ09B0272-0700 Section 10 16-Bit Integrated Timer Pulse Unit (ITU) PWM mode Select counter clock (1) Select counter clear source (2) Set GRA (3) Set GRB (4) Select PWM mode (5) Start counting (6) PWM mode Figure 10.28 Procedure for Selecting PWM Mode PWM Mode Operation: Figure 10.29 illustrates PWM mode operation. When PWM mode is set, the TIOCA pin becomes the output pin. Output is 1 when TCNT matches GRA, and 0 when TCNT matches GRB. TCNT can be cleared by compare match with either GRA or GRB. This can be used in both free-running and synchronized operation. Figure 10.30 shows examples of PWM waveforms output with 0% and 100% duty cycles. A 0% duty waveform can be obtained by setting the counter clear source to GRB and then setting GRA to a larger value than GRB. A 100% duty waveform can be obtained by setting the counter clear source to GRA and then setting GRB to a larger value than GRA. Rev. 7.00 Jan 31, 2006 page 269 of 658 REJ09B0272-0700 Section 10 16-Bit Integrated Timer Pulse Unit (ITU) TCNT value Counter cleared by GRA compare match GRA GRB Time TIOCA a. Counter cleared by GRA TCNT value Counter cleared by GRB compare match GRB GRA Time TIOCA b. Counter cleared by GRB Figure 10.29 PWM Mode Operation Example 1 Rev. 7.00 Jan 31, 2006 page 270 of 658 REJ09B0272-0700 Section 10 16-Bit Integrated Timer Pulse Unit (ITU) TCNT value Counter cleared on compare match B GRB GRA Time H'0000 TIOCA GRA write GRA write a. 0% duty TCNT value Counter cleared on compare match A GRA GRB Time H'0000 TIOCA GRB write GRB write b. 100% duty Figure 10.30 PWM Mode Operation Example 2 Rev. 7.00 Jan 31, 2006 page 271 of 658 REJ09B0272-0700 Section 10 16-Bit Integrated Timer Pulse Unit (ITU) 10.4.5 Reset-Synchronized PWM Mode In reset-synchronized PWM mode, three pairs of complementary positive and negative PWM waveforms that share a common wave turning point can be obtained using channels 3 and 4. When set for reset-synchronized PWM mode, the TIOCA3, TIOCB3, TIOCA4, TOCXA4, TIOCB4, and TOCXB4 pins become PWM output pins and TCNT3 becomes an up-counter. Table 10.12 shows the PWM output pins used and table 10.13 shows the settings of the registers used. Table 10.12 Output Pins for Reset-Synchronized PWM Mode Channel Output Pin Description 3 TIOCA3 PWM output 1 TIOCB3 PWM output 1' (negative-phase waveform of PWM output 1) TIOCA4 PWM output 2 4 TOCXA4 PWM output 2' (negative-phase waveform of PWM output 2) TIOCB4 PWM output 3 TOCXB4 PWM output 3' (negative-phase waveform of PWM output 3) Table 10.13 Register Settings for Reset-Synchronized PWM Mode Register Setting TCNT3 Initial setting of H'0000 TCNT4 Not used (functions independently) GRA3 Sets count cycle for TCNT3 GRB3 Sets the turning point for PWM waveform output by the TIOCA3 and TIOCB3 pins GRA4 Sets the turning point for PWM waveform output by the TIOCA4 and TOCXA4 pins GRB4 Sets the turning point for PWM waveform output by the TIOCB4 and TOCXB4 pins Procedure for Selecting Reset-Synchronized PWM Mode (figure 10.31): 1. Clear the STR3 bit in TSTR to halt TCNT3. Reset-synchronized PWM mode must be set while TCNT3 is halted. 2. Set bits TPSC2-TPSC0 in TCR to select the counter clock source for channel 3. If an external clock source is selected, select the external clock edge with bits CKEG1 and CKEG0 in TCR. 3. Set bits CCLR1 and CCLR0 in TCR3 to select GRA3 as a counter clear source. 4. Set bits CMD1 and CMD0 in TFCR to select reset-synchronized PWM mode. TIOCA3, TIOCB3, TIOCA4, TIOCB4, TOCXA4, and TOCXB4 become PWM output pins. 5. Reset TCNT3 (to H'0000). TCNT4 need not be set. Rev. 7.00 Jan 31, 2006 page 272 of 658 REJ09B0272-0700 Section 10 16-Bit Integrated Timer Pulse Unit (ITU) 6. GRA3 is the waveform period register. Set the waveform period value in GRA3. Set the transition times of the PWM output waveforms in GRB3, GRA4, and GRB4. Set times within the compare match range of TCNT3. X GRA3 (X: set value) 7. Set the PFC for the external pin to be used. 8. Set the STR3 bit in TSTR to 1 to start the TCNT3 count. Reset synchronized PWM mode Stop counting (1) Select counter clock (2) Select counter clear source (3) Select reset-synchronized PWM mode (4) Set TCNT (5) Set general registers (6) Start Setcounting PFC (7) Start counting (8) Reset-synchronized PWM mode Figure 10.31 Procedure for Selecting Reset-Synchronized PWM Mode Rev. 7.00 Jan 31, 2006 page 273 of 658 REJ09B0272-0700 Section 10 16-Bit Integrated Timer Pulse Unit (ITU) Reset-Synchronized PWM Mode Operation: Figure 10.32 shows an example of operation in reset-synchronized PWM mode. TCNT3 operates as an up-counter that is cleared to H'0000 at compare match with GRA3. TCNT4 runs independently and is isolated from GRA4 and GRB4. The PWM waveform outputs toggle at each compare match (GRB3, GRA3, and GRB4 with TCNT3) and when the counter is cleared. See section 10.4.8, Buffer Mode, for details on simultaneously setting reset-synchronized PWM mode and buffer operation. TCNT value Counter cleared at GRA3 compare match GRA3 GRB3 GRA4 GRB4 Time TIOCA3 TIOCB3 TIOCA4 TOCXA4 TIOCB4 TOCXB4 Figure 10.32 Reset-Synchronized PWM Mode Operation Example 1 Rev. 7.00 Jan 31, 2006 page 274 of 658 REJ09B0272-0700 Section 10 16-Bit Integrated Timer Pulse Unit (ITU) 10.4.6 Complementary PWM Mode In complementary PWM mode, three pairs of complementary, non-overlapping, positive and negative PWM waveforms can be obtained using channels 3 and 4. In complementary PWM mode, the TIOCA3, TIOCB3, TIOCA4, TOCXA4, TIOCB4, and TOCXB4 pins become PWM output pins and TCNT3 and TCNT4 become up-counters. Table 10.14 shows the PWM output pins used and table 10.15 shows the settings of the registers used. Table 10.14 Output Pins for Complementary PWM Mode Channel Output Pin Description 3 TIOCA3 PWM output 1 TIOCB3 PWM output 1' (non-overlapping negative-phase waveform of PWM output 1) TIOCA4 PWM output 2 TOCXA4 PWM output 2' (non-overlapping negative-phase waveform of PWM output 2) TIOCB4 PWM output 3 TOCXB4 PWM output 3' (non-overlapping negative-phase waveform of PWM output 3) 4 Table 10.15 Register Settings for Complementary PWM Mode Register Setting TCNT3 Initial setting of non-overlap cycle (difference with TCNT4) TCNT4 Initial setting of H'0000 GRA3 Sets upper limit of TCNT3-1 GRB3 Sets the turning point for PWM waveform output by the TIOCA3 and TIOCB3 pins GRA4 Sets the turning point for PWM waveform output by the TIOCA4 and TOCXA4 pins GRB4 Sets the turning point for PWM waveform output by the TIOCB4 and TOCXB4 pins Procedure for Selecting Complementary PWM Mode (Figure 10.33): 1. Clear the STR3 and STR4 bits in TSTR to halt the timer counters. Complementary PWM mode must be set while TCNT3 and TCNT4 are halted. 2. Set bits TPSC2-TPSC0 in TCR to select the same counter clock source for channels 3 and 4. If an external clock source is selected, select the external clock edge with bits CKEG1 and CKEG0 in TCR. Do not select any counter clear source with bits CCLR1 and CCLR0 in TCR. Rev. 7.00 Jan 31, 2006 page 275 of 658 REJ09B0272-0700 Section 10 16-Bit Integrated Timer Pulse Unit (ITU) 3. Set bits CMD1 and CMD0 in TMDB to select complementary PWM mode. TIOCA3, TIOCB3, TIOCA4, TIOCB4, TOCXA4, and TOCXB4 become PWM pins. 4. Reset TCNT4 (to H'0000). Set the non-overlap offset in TCNT3. Do not set TCNT3 and TCNT4 to the same value. 5. GRA3 is the waveform period register. Set the upper limit of TCNT3-1*. Set the transition times of the PWM output waveforms in GRB3, GRA4, and GRB4. Set times within the compare match range of TCNT3 and TCNT4. TX (X: initial setting of GRB3, GRA4, and GRB4; T: initial setting of TCNT3) Note: * GRA3 = [cycle count/2] + [count of non-overlaps] - 2cyc=[upper limit of TCNT3]-1 6. Set the PFC for the external pin to be used. 7. Set the STR3 and STR4 bits in TSTR to 1 to start the TCNT3 and TCNT4 counts. Complementary PWM mode Stop counting (1) Select counter clock (2) Select complementary PWM mode (3) Set TCNT (4) Set general registers (5) Set PFC (6) Start counting (7) Complementary PWM mode Note: To re-establish complementary PWM mode after it has been aborted, start settings from step 1. Figure 10.33 Procedure for Selecting Complementary PWM Mode Rev. 7.00 Jan 31, 2006 page 276 of 658 REJ09B0272-0700 Section 10 16-Bit Integrated Timer Pulse Unit (ITU) Complementary PWM Mode Operation: Figure 10.34 shows an example of operation in complementary PWM mode. TCNT3 and TCNT4 operate as up/down-counters, counting down from compare match of TCNT3 and GRA3 and counting up when TCNT4 underflows. PWM waveforms are output by repeated compare matches with GRB3, GRA4, and GRB4 in the sequence TCNT3, TCNT4, TCNT4, TCNT3 (in this mode, TCNT3 starts out at a higher value than TCNT4). Figure 10.35 shows examples of PWM waveforms with 0% and 100% duty cycles (in one phase) in complementary PWM mode. In this example, the pin output changes upon GRB3 compare match, so duty cycles of 0% and 100% can be obtained by setting GRB3 to a value larger than GRA3. Combining buffer operation with the above operation makes it easy to change the duty while operating. See section 10.4.8, Buffer Mode, for details. TCNT3, TCNT4 value GRA3 Down-counting starts at compare match between TCNT3 and GRA3 TCNT3 GRB3 GRA4 GRB4 TCNT4 Time Up-counting starts at TCNT4 underflow TIOCA3 TIOCB3 TIOCA4 TOCXA4 TIOCB4 TOCXB4 Figure 10.34 Complementary PWM Mode Operation Example 1 Rev. 7.00 Jan 31, 2006 page 277 of 658 REJ09B0272-0700 Section 10 16-Bit Integrated Timer Pulse Unit (ITU) TCNT3, TCNT4 value GRA3 GRB3 Time TIOCA3 TIOCB3 0% duty (a) With 0% duty TCNT3, TCNT4 value GRA3 GRB3 Time TIOCA3 TIOCB3 100% duty (b) With 100% duty Figure 10.35 Complementary PWM Mode Operation Example 2 At the point where the up-count/down-count changes in complementary PWM mode, TCNT3 and TCNT4 will overshoot and undershoot, respectively. When this occurs, the setting conditions for the IMFA bit of channel 3 and the overflow flag (OVF) of channel 4 are different from usual. Transfer conditions for the buffer also differ. The timing is as shown in figures 10.36 and 10.37. Rev. 7.00 Jan 31, 2006 page 278 of 658 REJ09B0272-0700 Section 10 16-Bit Integrated Timer Pulse Unit (ITU) TCNT3 N-1 N GRA3 N+1 N N-1 N Flag not set IMFA Set to 1 Buffer transfer signal (BR to GR) GR Buffer transfer performed Buffer transfer not performed Figure 10.36 Overshoot Timing Underflow Overflow TCNT4 H' 0001 H' 0000 H' FFFF H' 0000 Flag not set OVF Set to 1 Buffer transfer signal (BR to GR) GR Buffer transfer performed Buffer transfer not performed Figure 10.37 Undershoot Timing The IMFA bit of channel 3 is set to 1 for increment pulses and the OVF bit of channel 4 is set to 1 for underflows only. The buffer register (BR) set for the buffer operation is transferred to GR upon compare match A3 (when incrementing) or TCNT4 underflow. Rev. 7.00 Jan 31, 2006 page 279 of 658 REJ09B0272-0700 Section 10 16-Bit Integrated Timer Pulse Unit (ITU) GR Setting in Complementary PWM Mode: Note the following when setting the general registers in complementary PWM mode and when making changes during operation. * Initial values: Settings from H'0000 to T-1 (T: TCNT3 initial setting) are prohibited. After counting starts, this setting is allowed from the point when the first A3 compare match occurs. * Methods of changing settings: Use buffer operation. Writing directly to general registers may result in incorrect waveform output. * When changing settings: See figure 10.38. GRA3 GR H' 0000 Prohibited BR GR Figure 10.38 Example of Changing GR Settings with Buffer Operation (1) Buffer Transfers when Changing from Increment to Decrement: When the contents of GR are in the range GRA3 - T + 1 to GRA3, do not transfer a value outside this range. When the contents of GR are outside this range, do not a transfer a value within it. Figure 10.39 illustrates a point for caution regarding changing of GR settings with buffer operation. GRA3 + 1 GRA3 GRA3 - T + 1 GRA3 - T Changes prohibited TCNT3 TCNT4 Figure 10.39 Caution on Changing GR Settings with Buffer Operation (1) Buffer Transfers when Changing from Decrement to Increment: When the contents of GR are in the range H'0000 to T-1, do not transfer a value outside this range. When the contents of GR are outside this range, do not transfer a value within it. Figure 10.40 illustrates this point for caution regarding changing of GR settings with buffer operation Rev. 7.00 Jan 31, 2006 page 280 of 658 REJ09B0272-0700 Section 10 16-Bit Integrated Timer Pulse Unit (ITU) TCNT3 TCNT4 T T-1 Changes prohibited H' 0000 H' FFFF Figure 10.40 Caution on Changing GR Settings with Buffer Operation (2) When GR Settings are Outside the Count Range (H'0000-GRA3): Waveforms with a duty cycle of 0% and 100% can be output by setting GR outside the count area. Be sure to make the direction of the count (increment/decrement) when writing a setting from outside the count area into the buffer register (BR) the same as the count direction when writing the setting that returns to within the count area in BR. GRA3 GR H' 0000 0% duty 100% duty Output pin Output pin BR GR Write on decrement Write on increment Figure 10.41 Example of Changing GR Settings with Buffer Operation (2) The above settings are made by detecting the occurrence of a GRA3 compare match or underflow of TCNT4 and then writing to BR. They can also be accomplished by starting the DMAC with a GRA3 compare match. Rev. 7.00 Jan 31, 2006 page 281 of 658 REJ09B0272-0700 Section 10 16-Bit Integrated Timer Pulse Unit (ITU) 10.4.7 Phase Counting Mode Phase counting mode detects the phase differential of two external clock inputs (TCLKA and TCLKB) and increments or decrements TCNT2. When phase counting mode is set, the TCLKA and TCLKB pins become external clock input pins, regardless of the settings of the TPSC2- TPSC0 bits in TCR2 or the CKEG1 and CKEG0 bits. TCNT2 also becomes an up/down-counter. Since the TCR2 CCLR1/CCLR0 bits, TIOR2, TIER2, TSR2, GRA2, and GRB2 are all enabled, input capture and compare match functions and interrupt sources can be used. Phase counting is available only for channel 2. Procedure for Selecting Phase Counting Mode: Figure 10.42 shows the procedure for selecting phase counting mode. 1. Set the MDF bit in the timer mode register (TMDR) to 1 to select phase counting mode. 2. Select the flag set conditions using the FDIR bit in TMDR. 3. Set the STR2 bit in the timer start register (TSTR) to 1 to start the count. Phase counting mode Select phase counting mode (1) Select flag setting condition (2) Start counting (3) Phase counting mode Figure 10.42 Procedure for Selecting Phase Counting Mode Phase Counting Operation: Figure 10.43 shows an example of phase counting mode operation. Table 10.16 lists the up-counting and down-counting conditions for TCNT2. The ITU counts on both rising and falling edges of TCLKA and TCLKB. The phase differential and overlap of TCLKA and TCLKB must be 1.5 cycles or more and the pulse width must be 2.5 cycles or more. Rev. 7.00 Jan 31, 2006 page 282 of 658 REJ09B0272-0700 Section 10 16-Bit Integrated Timer Pulse Unit (ITU) TCNT2 value Increment Decrement TCNT2 Time TCLKB TCLKA Figure 10.43 Phase Counting Mode Operation Table 10.16 Up/Down-Counting Conditions Counting Direction Increment TCLKB Rising High Falling Low Rising High Falling Low TCLKA Low Rising High Falling High Falling Low Rising Phase differential Decrement Phase differential Pulse width Pulse width TCLKA TCLKB Overlap Overlap Phase differential, overlap: 1.5 cycles minimum Pulse width: 2.5 cycles minimum Figure 10.44 Phase Differentials, Overlap, and Pulse Width in Phase Counting Mode Rev. 7.00 Jan 31, 2006 page 283 of 658 REJ09B0272-0700 Section 10 16-Bit Integrated Timer Pulse Unit (ITU) 10.4.8 Buffer Mode In buffer mode, the buffer operation functions differ depending on whether the general registers are set to output compare or input capture, reset-synchronized PWM mode, or complementary PWM mode. Buffer mode is a function of channels 3 and 4 only. Buffer operations set this way function as follows. GR is an Output Compare Register: The value of the buffer register of a channel is transferred to GR when a compare match occurs in the channel. This is illustrated in figure 10.45. Compare match signal BR GR Comparator TCNT Figure 10.45 Compare Match Buffer Operation GR is an Input Capture Register: TCNT values are transferred to GR when input capture occurs and the value previously stored in GR is transferred to BR. This operation is illustrated in figure 10.46. Input capture signal BR GR TCNT Figure 10.46 Input Capture Buffer Operation Complementary PWM Mode: When the count direction of TCNT3 and TCNT4 changes, the BR value is transferred to GR. The following timing is employed for this transfer: * When there is a TCNT3/GRA3 compare-match * When there is a TCNT4 underflows Rev. 7.00 Jan 31, 2006 page 284 of 658 REJ09B0272-0700 Section 10 16-Bit Integrated Timer Pulse Unit (ITU) Reset-Synchronized PWM Mode: The BR value is transferred to GR upon a GRA3 compare match. Procedure for Selecting Buffer Mode (Figure 10.47): 1. Set TIOR to select the output compare or input capture function of GR. 2. Set bits BFA3, BFB3 and BFB4 in TFCR to select buffer mode for GR. 3. Set the STR bit in TSTR to 1 to start the TCNT count. Buffer mode Select general register function (1) Select buffer mode (2) Start counting (3) Buffer mode Figure 10.47 Procedure for Selecting Buffer Mode Buffer Mode Operation: Figure 10.48 shows an example of an operation in buffer mode with GRA set as an output compare register and GRA and buffer register A (BRA) set for buffer operation. TCNT operates as a periodic counter that is cleared by a GRB compare match. TIOCA and TIOCB are set to toggle at compare matches A and B. Since buffer mode is selected, when TIOCA toggles at compare match A, the BRA value is simultaneously transferred to GRA. This operation is repeated at every compare match A. The transfer timing is shown in figure 10.49. Rev. 7.00 Jan 31, 2006 page 285 of 658 REJ09B0272-0700 Section 10 16-Bit Integrated Timer Pulse Unit (ITU) Counter cleared by compare match B TCNT value GRB H' 0250 H' 0200 H' 0100 H' 0000 Time BRA H' 0200 GRA H' 0250 H' 0100 H' 0200 H' 0200 H' 0200 H' 0100 Toggle output TIOCB TIOCA Toggle output Compare match A Figure 10.48 Buffer Mode Operation Example 1 (Output Compare Register) CK TCNT n n+1 Compare match signal Buffer transfer signal BR GR N n N Figure 10.49 Compare Match Timing Example for Buffer Operation Figure 10.50 shows an example of input capture operation in buffer mode between GRA and BRA with GRA as an input capture register. TCNT is cleared by input capture B. The falling edge is selected as the input capture edge at TIOCB. Both edges are selected as input capture edges at TIOCA. When the TCNT value is stored in GRA by input capture A, the previous GRA value is transferred to BRA. The timing is shown in figure 10.51. Rev. 7.00 Jan 31, 2006 page 286 of 658 REJ09B0272-0700 Section 10 16-Bit Integrated Timer Pulse Unit (ITU) TCNT value Counter cleared at input capture B H' 0180 H' 0160 H' 0005 Time TIOCB TIOCA GRA H' 0160 H' 0005 H' 0005 BRA H' 0160 H' 0180 GRB Input capture A Figure 10.50 Buffer Mode Operation Example 2 (Input Capture Register) CK TIOC pin Input capture signal n TCNT GR BR n+1 M n m M N N+1 n N M n Figure 10.51 Input Capture Timing Example for Buffer Operation Rev. 7.00 Jan 31, 2006 page 287 of 658 REJ09B0272-0700 Section 10 16-Bit Integrated Timer Pulse Unit (ITU) An example of buffer operation in complementary PWM mode between GRB3 and BRB3 is shown in figure 10.52. By making GRB3 larger than GRA3 using buffer operation, a PWM waveform with a duty cycle of 0% is generated. The transfer from BRB to GRB occurs upon TCNT3 and GRA compare match and TCNT4 underflow. TCNT3 and TCNT4 values TCNT3 GRB3 H' 1FFF GRA3 H' 0999 TCNT4 H' 0000 Time BRB3 H' 0999 GRB3 H' 0999 H' 1FFF H' 0999 H' 1FFF H' 0999 H' 1FFF H' 0999 TIOCA3 TIOCB3 Figure 10.52 Buffer Mode Operation Example 3 (Complementary PWM Mode) Rev. 7.00 Jan 31, 2006 page 288 of 658 REJ09B0272-0700 Section 10 16-Bit Integrated Timer Pulse Unit (ITU) 10.4.9 ITU Output Timing ITU outputs in channels 3 and 4 can be inverted with TOCR. Output Inversion Timing with TOCR: Output levels can be inverted by inverting the output level select bits (OLS4 and OLS3) in TOCR in complementary PWM mode and resetsynchronized PWM mode. Figure 10.53 illustrates the timing. T1 T2 T3 CK Address TOCR address TOCR ITU output pin Inversion Figure 10.53 Example of Inverting ITU Output Levels by Writing to TOCR Rev. 7.00 Jan 31, 2006 page 289 of 658 REJ09B0272-0700 Section 10 16-Bit Integrated Timer Pulse Unit (ITU) 10.5 Interrupts The ITU has two interrupt sources: input capture/compare match and overflow. 10.5.1 Timing of Setting Status Flags Timing for Setting IMFA and IMFB in a Compare Match: The IMF bits in TSR are set to 1 by a compare match signal generated when TCNT matches a general register. The compare match signal is generated in the last state in which the values match (when TCNT is updated from the matching count to the next count). Therefore, when TCNT matches GRA or GRB, the compare match signal is not generated until the next timer clock input. Figure 10.54 shows the timing of setting the IMF bits. CK TCNT input clock TCNT N GR N+1 N Compare match signal IMF IMI Figure 10.54 Timing of Setting Compare Match Flags (IMFA, IMFB) Rev. 7.00 Jan 31, 2006 page 290 of 658 REJ09B0272-0700 Section 10 16-Bit Integrated Timer Pulse Unit (ITU) Timing of Setting IMFA, IMFB for Input Capture: IMFA and IMFB are set to 1 by an input capture signal. At this time, the TCNT contents are transferred to GR. Figure 10.55 shows the timing. CK Input capture signal IMF N TCNT N GR IMI Figure 10.55 Timing of Setting IMFA and IMFB for Input Capture Timing of Setting Overflow Flag (OVF): OVF is set to 1 when TCNT overflows from H'FFFF to H'0000 or underflows from H'0000 to H'FFFF. Figure 10.56 shows the timing. CK TCNT H' FFFF H' 0000 Overflow signal OVF OVI Figure 10.56 Timing of Setting OVF Rev. 7.00 Jan 31, 2006 page 291 of 658 REJ09B0272-0700 Section 10 16-Bit Integrated Timer Pulse Unit (ITU) 10.5.2 Status Flag Clear Timing The status flags are cleared by being read by the CPU when set to 1, then being written with 0. This timing is shown in figure 10.57. TSR write cycle T1 T2 T3 CK TSR address Address IMF, OVF Figure 10.57 Timing of Status Flag Clearing Rev. 7.00 Jan 31, 2006 page 292 of 658 REJ09B0272-0700 Section 10 16-Bit Integrated Timer Pulse Unit (ITU) 10.5.3 Interrupt Sources and DMAC Activation The ITU has compare match/input capture A interrupts, compare match/input capture B interrupts and overflow interrupts for each channel. Each of the fifteen of these three types of interrupts are allocated their own independently vectored addresses. When the interrupt's interrupt request flag is set to 1 and the interrupt enable bit is set to 1, the interrupt is requested. The channel priority order can be changed with the interrupt controller. For more information, see section 5, Interrupt Controller (INTC). The compare match/input capture A interrupts of channels 0-3 can start the DMAC to transfer data. Table 10.17 lists the interrupt sources. Table 10.17 ITU Interrupt Sources Channel Interrupt Source Description DMAC Activation Priority Order* 0 IMIA0 Compare match or input capture A0 Yes High IMIB0 Compare match or input capture B0 No 1 2 3 4 OVI0 Overflow 0 No IMIA1 Compare match or input capture A1 Yes IMIB1 Compare match or input capture B1 No OVI1 Overflow 1 No IMIA2 Compare match or input capture A2 Yes IMIB2 Compare match or input capture B2 No OVI2 Overflow 2 No IMIA3 Compare match or input capture A3 Yes IMIB3 Compare match or input capture B3 No OVI3 Overflow 3 No IMIA4 Compare match or input capture A4 No IMIB4 Compare match or input capture B4 No OVI4 Overflow 4 No Low Note: * Indicates the initial status following a reset. The ranking of channels can be altered using the interrupt controller. Rev. 7.00 Jan 31, 2006 page 293 of 658 REJ09B0272-0700 Section 10 16-Bit Integrated Timer Pulse Unit (ITU) 10.6 Notes and Precautions This section describes contention and other matters requiring special attention during ITU operation. 10.6.1 Contention between TCNT Write and Clear If a counter clear signal occurs in the T3 state of a TCNT write cycle, clearing the counter takes priority and the write is not performed. The timing is shown in figure 10.58. TCNT write cycle by CPU T1 T2 T3 CK Address TCNT address Internal write signal Counter clear signal TCNT N H' 0000 Figure 10.58 Contention between TCNT Write and Clear Rev. 7.00 Jan 31, 2006 page 294 of 658 REJ09B0272-0700 Section 10 16-Bit Integrated Timer Pulse Unit (ITU) 10.6.2 Contention between TCNT Word Write and Increment If an increment pulse occurs in the T3 state of a TCNT word write cycle, writing takes priority and TCNT is not incremented. The timing is shown in figure 10.59. TCNT word write cycle by CPU T1 T2 T3 CK Address TCNT address Internal write signal TCNT input clock TCNT N M TCNT write data Figure 10.59 Contention between TCNT Word Write and Increment Rev. 7.00 Jan 31, 2006 page 295 of 658 REJ09B0272-0700 Section 10 16-Bit Integrated Timer Pulse Unit (ITU) 10.6.3 Contention between TCNT Byte Write and Increment If an increment pulse occurs in the T2 state or T3 state of a TCNT byte write cycle, counter writing takes priority and the byte data on the side that was previously written is not incremented. The TCNT byte data that was not written is also not incremented and retains its previous value. The timing is shown in figure 10.60 (which shows an increment during state T2 of a byte write cycle to TCNTH). TCNTH byte write cycle by CPU T1 T2 T3 CK Address TCNTH address Internal write signal TCNT input clock N TCNTH M TCNT write data TCNTL X X+1 X Figure 10.60 Contention between TCNT Byte Write and Increment Rev. 7.00 Jan 31, 2006 page 296 of 658 REJ09B0272-0700 Section 10 16-Bit Integrated Timer Pulse Unit (ITU) 10.6.4 Contention between GR Write and Compare Match If a compare match occurs in the T3 state of a general register (GR) write cycle, writing takes priority and the compare match signal is inhibited. The timing is shown in figure 10.61. GR write cycle T1 T2 T3 CK Address GR address Internal write signal TCNT N N+1 GR N M GR write data Compare match signal Inhibited Figure 10.61 Contention between General Register Write and Compare Match Rev. 7.00 Jan 31, 2006 page 297 of 658 REJ09B0272-0700 Section 10 16-Bit Integrated Timer Pulse Unit (ITU) 10.6.5 Contention between TCNT Write and Overflow/Underflow If an overflow occurs in the T3 state of a TCNT write cycle, writing takes priority over counter incrementing. OVF is set to 1. The same applies to underflows. The timing is shown in figure 10.62. TCNT write cycle T1 T2 T3 CK Address TCNT address Internal write signal TCNT input clock Overflow signal TCNT H'FFFF M TCNT write data OVF Figure 10.62 Contention between TCNT Write and Overflow Rev. 7.00 Jan 31, 2006 page 298 of 658 REJ09B0272-0700 Section 10 16-Bit Integrated Timer Pulse Unit (ITU) 10.6.6 Contention between General Register Read and Input Capture If an input capture signal is generated during the T3 state of a general register read cycle, the value before input capture is read. The timing is shown in figure 10.63. GR read cycle T1 T2 T3 CK Address GR address Internal read signal Input capture signal GR Internal data bus X M X Figure 10.63 Contention between General Register Read and Input Capture Rev. 7.00 Jan 31, 2006 page 299 of 658 REJ09B0272-0700 Section 10 16-Bit Integrated Timer Pulse Unit (ITU) 10.6.7 Contention Between Counter Clearing by Input Capture and Counter Increment If an input capture signal and counter increment signal occur simultaneously, the counter is cleared by the input capture signal. The counter is not incremented by the increment signal. The TCNT value before the counter is cleared is transferred to the general register. The timing is shown in figure 10.64. CK Input capture signal Counter clear signal TCNT input clock TCNT GR N H'0000 N Figure 10.64 Contention between Counter Clearing by Input Capture and Counter Increment Rev. 7.00 Jan 31, 2006 page 300 of 658 REJ09B0272-0700 Section 10 16-Bit Integrated Timer Pulse Unit (ITU) 10.6.8 Contention between General Register Write and Input Capture If an input capture signal is generated during the T3 state of a general register write cycle, the input capture transfer takes priority and the write to GR is not performed. The timing is shown in figure 10.65. GR write cycle T1 T2 T3 CK Address GR address Internal write signal Input capture signal TCNT GR M M Figure 10.65 Contention between General Register Write and Input Capture 10.6.9 Note on Waveform Cycle Setting When a counter is cleared by compare match, the counter is cleared in the last state in which the TCNT value matches the GR value (when TCNT is updated from the matching count to the next count). The actual counter frequency is therefore given by the following formula: f = /(N + 1) (f: counter frequency; : operating frequency; N: value set in GR) Rev. 7.00 Jan 31, 2006 page 301 of 658 REJ09B0272-0700 Section 10 16-Bit Integrated Timer Pulse Unit (ITU) 10.6.10 Contention between BR Write and Input Capture When a buffer register (BR) is being used as an input capture register and an input capture signal is generated in the T3 state of the write cycle, the buffer operation takes priority over the BR write. The timing is shown in figure 10.66. BR write cycle T1 T2 T3 CK Address BR address Internal write signal Input capture signal GR N X TCNT value BR M N Figure 10.66 Contention between BR Write and Input Capture Rev. 7.00 Jan 31, 2006 page 302 of 658 REJ09B0272-0700 Section 10 16-Bit Integrated Timer Pulse Unit (ITU) 10.6.11 Note on Writing in Synchronizing Mode After synchronizing mode is selected, if TCNT is written by byte access, all 16 bits of all synchronized counters assume the same value as the counter that was addressed. Example: Figures 10.67 and 10.68 show byte write and word write when channels 2 and 3 are synchronized TCNT2 TCNT3 W X Y Z Upper byte Lower byte Write A to upper byte of channel 2 TCNT2 TCNT3 A X A X Upper byte Lower byte TCNT2 Y A TCNT3 Y A Upper byte Lower byte Write A to lower byte of channel 3 Figure 10.67 Byte Write to Channel 2 or Byte Write to Channel 3 TCNT2 W X TCNT3 Y Z Upper byte Lower byte Word write of AB for channel 2 or 3 TCNT2 A B TCNT3 A B Upper byte Lower byte Figure 10.68 Word Write to Channel 2 or Word Write to Channel 3 10.6.12 Note on Setting Reset-Synchronized PWM Mode/Complementary PWM Mode When the CMD1 and CMD0 bits in TFCR are set, note the following. 1. Writes to CMD1 and CMD0 should be carried out while TCNT3 and TCNT4 are halted. 2. Changes of setting from reset-synchronized PWM mode to complementary PWM mode and vice versa are prohibited. Set reset-synchronized PWM mode or complementary PWM mode after first setting normal operation (clear CMD1 bit to 0). Rev. 7.00 Jan 31, 2006 page 303 of 658 REJ09B0272-0700 Section 10 16-Bit Integrated Timer Pulse Unit (ITU) 10.6.13 Clearing Complementary PWM Mode Figure 10.69 shows the procedure for clearing complementary PWM mode. First, reset combination mode bits CMD1 and CMD0 in the timer function control register (TFCR) from 10 to either 00 or 01. The mode will switch from complementary PWM mode to normal operating mode. Next, wait for at least 1 cycle of the counter input clock being used for channels 3 and 4 and then clear counter start bits STR3 and STR4 in the timer start register (TSTR). The channel 3 and 4 counters, TCNT3 and TCNT4, will stop counting. Clearing complementary PWM mode by any other procedure may result in changes other than those set for the output waveform when complementary PWM mode is set again. Complementary PWM mode Clear complementary PWM mode Halt count Normal operation 1. Clear the CMD1 bit in TFCR to 0 to set channels 3 and 4 for normal operation 2. Wait at least 1 clock cycle after setting channels 3 and 4 for normal operation and then clear the STR3 and STR4 bits in TSTR to 0 to halt the TCNT3 and TCNT4 counters Figure 10.69 Clearing Complementary PWM Mode 10.6.14 Note on Counter Clearing by Input Capture If TCNT is cleared (to H'0000) by input capture when its value is H'FFFF, overflow will not occur. Rev. 7.00 Jan 31, 2006 page 304 of 658 REJ09B0272-0700 Section 10 16-Bit Integrated Timer Pulse Unit (ITU) 10.6.15 ITU Operating Modes Table 10.18 ITU Operating Modes (Channel 0) Register Setting TSNC Operating Mode Sync TMDR TFCR TOCR TIOR0 TCR0 MDF FDIR PWM Reset Comp Sync PWM PWM Buffer Output Level Select IOA IOB Clear Clock Select Select Synchronized preset SYNC0 -- =1 -- -- -- -- -- PWM -- -- PWM0 -- =1 -- -- -- -- * Output compare A function -- -- PWM0 -- =0 -- -- -- IOA2 = 0, others: don't care Output compare B function -- -- -- -- -- -- IOB2 = 0, others: don't care Input capture A function -- -- PWM0 -- =0 -- -- -- IOA2 = 1, others: don't care Input capture B function -- -- PWM0 -- =0 -- -- -- IOB2 = 1, others: don't care Counter Clear Function Clear at compare match/ input capture A -- -- -- -- -- -- CCLR1 =0 CCLR0 =1 Clear at compare match/ input capture B -- -- -- -- -- -- CCLR1 =1 CCLR0 =0 Synchronized clear SYNC0 -- =1 -- -- -- -- -- CCLR1 =1 CCLR0 =1 : Settable, --: Setting does not affect current mode Note: * In PWM mode, the input capture function cannot be used. When compare match A and compare match B occur simultaneously, the compare match signal is inhibited. Rev. 7.00 Jan 31, 2006 page 305 of 658 REJ09B0272-0700 Section 10 16-Bit Integrated Timer Pulse Unit (ITU) Table 10.19 ITU Operating Modes (Channel 1) Register Setting TSNC Operating Mode Sync TMDR TFCR MDF FDIR PWM Reset Comp Sync PWM PWM Buffer Output Level Select IOA TOCR TIOR1 TCR1 IOB Clear Clock Select Select Synchronized preset SYNC1 -- =1 -- -- -- -- -- PWM -- -- PWM1 -- =1 -- -- -- -- * Output compare A function -- -- PWM1 -- =0 -- -- -- IOA2 = 0, others: don't care Output compare B function -- -- -- -- -- -- IOB2 = 0, others: don't care Input capture A function -- -- PWM1 -- =0 -- -- -- IOA2 = 1, others: don't care Input capture B function -- -- PWM1 -- =0 -- -- -- IOB2 = 1, others: don't care Counter Clear Function Clear at compare match/ input capture A -- -- -- -- -- -- CCLR1 =0 CCLR0 =1 Clear at compare match/ input capture B -- -- -- -- -- -- CCLR1 =1 CCLR0 =0 Synchronized clear SYNC1 -- =1 -- -- -- -- -- CCLR1 =1 CCLR0 =1 : Settable, --: Setting does not affect current mode Note: * In PWM mode, the input capture function cannot be used. When compare match A and compare match B occur simultaneously, the compare match signal is inhibited. Rev. 7.00 Jan 31, 2006 page 306 of 658 REJ09B0272-0700 Section 10 16-Bit Integrated Timer Pulse Unit (ITU) Table 10.20 ITU Operating Modes (Channel 2) Register Setting TSNC Operating Mode Sync TMDR TFCR MDF FDIR PWM Reset Comp Sync PWM PWM Buffer Output Level Select IOA TOCR TIOR2 TCR2 IOB Clear Clock Select Select Synchronized preset SYNC2 -- =1 -- -- -- -- -- PWM -- -- PWM2 -- =1 -- -- -- -- * Output compare A function -- -- PWM2 -- =0 -- -- -- IOA2 = 0, others: don't care Output compare B function -- -- -- -- -- -- IOB2 = 0, others: don't care Input capture A function -- -- PWM2 -- =0 -- -- -- IOA2 = 1, others: don't care Input capture B function -- -- PWM2 -- =0 -- -- -- IOB2 = 1, others: don't care Counter Clear Function Clear at compare match/ input capture A -- -- -- -- -- -- CCLR1 =0 CCLR0 =1 Clear at compare match/ input capture B -- -- -- -- -- -- CCLR1 =1 CCLR0 =0 Synchronized clear SYNC2 -- =1 -- -- -- -- -- CCLR1 =1 CCLR0 =1 Phase counting -- -- -- -- MDF =1 -- : Settable, --: Setting does not affect current mode Note: * In PWM mode, the input capture function cannot be used. When compare match A and compare match B occur simultaneously, the compare match signal is inhibited. Rev. 7.00 Jan 31, 2006 page 307 of 658 REJ09B0272-0700 Section 10 16-Bit Integrated Timer Pulse Unit (ITU) Table 10.21 ITU Operating Modes (Channel 3) Register Setting TSNC Operating Mode Sync TMDR TFCR MDF FDIR PWM Reset Comp Sync PWM PWM Buffer Output Level Select IOA IOB Clear Clock Select Select *2 TOCR TIOR3 TCR3 Synchronized preset SYNC3 -- =1 -- -- PWM mode -- -- PWM3 CMD1 CMD1 =1 =0 =0 -- -- *1 Output compare A function -- -- PWM3 CMD1 CMD1 =0 =0 =0 -- IOA2 = 0, others: don't care Output compare B function -- -- CMD1 CMD1 =0 =0 -- IOB2 = 0, others: don't care Input capture A function -- -- PWM3 CMD1 CMD1 =0 =0 =0 -- IOA2 = 1, others: don't care Input capture B function -- -- PWM3 CMD1 CMD1 =0 =0 =0 -- IOB2 = 1, others: don't care Counter Clear Function Clear at compare match/ input capture A -- -- CMD1 *3 = 1, CMD0 =0 inhibited -- CCLR1 =0 CCLR0 =1 Clear at compare match/ input capture B -- -- CMD1 CMD1 =0 =0 -- CCLR1 =1 CCLR0 =0 Synchronized clear SYNC3 -- =1 -- CMD1 = 1, CMD0 =0 inhibited -- CCLR1 =1 CCLR0 =1 Rev. 7.00 Jan 31, 2006 page 308 of 658 REJ09B0272-0700 Section 10 16-Bit Integrated Timer Pulse Unit (ITU) Register Setting TSNC Operating Mode Sync TMDR TFCR MDF FDIR PWM Reset Comp Sync PWM PWM Buffer Output Level Select IOA TOCR TIOR3 IOB TCR3 Clear Clock Select Select Comple*2 mentary PWM mode -- -- -- CMD1 =1 CMD0 =0 CMD1 =1 CMD0 =0 -- -- CCLR1 *4 =0 CCLR0 =0 Reset synchronized PWM mode -- -- -- CMD1 =1 CMD0 =1 CMD1 =1 CMD0 =1 -- -- CCLR1 =0 CCLR0 =1 Buffer (BRA) -- -- BFA3 = -- 1, others: don't care Buffer (BRB) -- -- BFB3 = -- 1, others: don't care : Settable, --: Setting does not affect current mode Notes: 1. In PWM mode, the input capture function cannot be used. When compare match A and compare match B occur simultaneously, the compare match signal is inhibited. 2. When set for complementary PWM mode, do not simultaneously set channel 3 and channel 4 to function synchronously. 3. Counter clearing by input capture A cannot be used when reset-synchronized PWM mode is set. 4. Clock selection when complementary PWM mode is set should be the same for channels 3 and 4. Rev. 7.00 Jan 31, 2006 page 309 of 658 REJ09B0272-0700 Section 10 16-Bit Integrated Timer Pulse Unit (ITU) Table 10.22 ITU Operating Modes (Channel 4) Register Setting TSNC Operating Mode Sync TMDR TFCR MDF FDIR PWM Reset Comp Sync PWM PWM Buffer Output Level Select IOA IOB Clear Clock Select Select *2 TOCR TIOR4 TCR4 Synchronized preset SYNC4 =1 -- -- -- PWM -- -- PWM4 CMD1 CMD1 =1 =0 =0 -- -- *1 Output compare A function -- -- PWM4 CMD1 CMD1 =0 =0 =0 -- IOA2 = 0, others: don't care Output compare B function -- -- CMD1 CMD1 =0 =0 -- IOB2 = 0, others: don't care Input capture A function -- -- PWM4 CMD1 CMD1 =0 =0 =0 -- IOA2 = 1, others: don't care Input capture B function -- -- PWM4 CMD1 CMD1 =0 =0 =0 -- IOB2 = 1, others: don't care Counter Clear Function Clear at compare match/ input capture A -- -- CMD1 *3 = 1, CMD0 =0 inhibited -- CCLR1 =0 CCLR0 =1 Clear at compare match/ input capture B -- -- CMD1 *3 = 1, CMD0 =0 inhibited -- CCLR1 =1 CCLR0 =0 Synchronized clear SYNC4 =1 -- -- CMD1 *3 = 1, CMD1 =0 inhibited -- CCLR1 =1 CCLR0 =1 Rev. 7.00 Jan 31, 2006 page 310 of 658 REJ09B0272-0700 Section 10 16-Bit Integrated Timer Pulse Unit (ITU) Register Setting TSNC Operating Mode Sync TFCR MDF FDIR PWM Reset Comp Sync PWM PWM Buffer Output Level Select IOA TOCR TIOR4 IOB TCR4 Clear Clock Select Select -- -- -- CMD1 =1 CMD0 =0 CMD1 =1 CMD0 =0 -- -- CCLR1 *4 =0 CCLR0 =0 Reset synchronized PWM -- -- -- CMD1 =1 CMD0 =1 CMD1 =1 CMD0 =1 -- -- *5 *5 Buffer (BRA) -- -- BFA4 -- = 1, others: don't care Buffer (BRB) -- -- BFB4 -- = 1, others: don't care Complementary PWM *2 TMDR : Settable, --: Setting does not affect current mode Notes: 1. In PWM mode, the input capture function cannot be used. When compare match A and compare match B occur simultaneously, the compare match signal is inhibited. 2. When set for complementary PWM mode, do not simultaneously set channel 3 and channel 4 to function synchronously. 3. Counter clearing works with reset-synchronized PWM mode, but TCNT4 runs independently. The output waveform is not affected. 4. Clock selection when complementary PWM mode is set should be the same for channels 3 and 4. 5. In reset-synchronized PWM mode, TCNT4 runs independently. The output waveform is not affected. Rev. 7.00 Jan 31, 2006 page 311 of 658 REJ09B0272-0700 Section 10 16-Bit Integrated Timer Pulse Unit (ITU) Rev. 7.00 Jan 31, 2006 page 312 of 658 REJ09B0272-0700 Section 11 Programmable Timing Pattern Controller (TPC) Section 11 Programmable Timing Pattern Controller (TPC) 11.1 Overview The SuperH microcomputer has an on-chip programmable timing pattern controller (TPC). The TPC can provide pulse outputs by using the 16-bit integrated timer pulse unit (ITU) as a time base. The TPC pulse outputs are divided into 4-bit groups 3-0. These can operate simultaneously or independently. 11.1.1 Features Features of the programmable timing pattern controller are listed below: * 16-bit output data: Maximum 16-bit data can be output. TPC output can be enabled on a bitby-bit basis. * Four output groups: Output trigger signals can be selected in 4-bit groups to provide up to four different 4-bit outputs. * Selectable output trigger signals: Output trigger signals can be selected by group from the 4-channel compare-match signals of the 16-bit integrated timer pulse unit (ITU). * Non-overlap mode: A non-overlap interval can be set to come between multiple pulse outputs. * Can connect to DMA controller: The compare-match signals selected as output trigger signals can activate the DMA controller for sequential output of data without CPU intervention. Rev. 7.00 Jan 31, 2006 page 313 of 658 REJ09B0272-0700 Section 11 Programmable Timing Pattern Controller (TPC) 11.1.2 Block Diagram Figure 11.1 shows a block diagram of the TPC. ITU compare match signal Control logic TP15 TP14 TP13 TP12 TP11 TP10 TP9 TP8 TP7 TP6 TP5 TP4 TP3 TP2 TP1 TP0 PBCR1 PBCR2 NDERA NDERB TPMR TPCR Pulse output pin group 3 NDRB Pulse output pin group 2 PBDR Pulse output pin group 1 NDRA Pulse output pin group 0 TPC TPMR: TPC output mode register TPCR: TPC output control register NDERB: Next data enable register NDERA: Next data enable register PBCR1: Port B control register 1 PBCR2: Port B control register 2 B NDRB: Next data register B A NDRA: Next data register A PBDR: Port B data register Figure 11.1 Block Diagram of TPC Rev. 7.00 Jan 31, 2006 page 314 of 658 REJ09B0272-0700 Internal data bus Section 11 Programmable Timing Pattern Controller (TPC) 11.1.3 Input/Output Pins Table 11.1 summarizes the TPC input/output pins. Table 11.1 TPC Pins Name Symbol Input/Output Function TPC output 0 TP0 Output Group 0 pulse output TPC output 1 TP1 Output TPC output 2 TP2 Output TPC output 3 TP3 Output TPC output 4 TP4 Output TPC output 5 TP5 Output TPC output 6 TP6 Output TPC output 7 TP7 Output TPC output 8 TP8 Output TPC output 9 TP9 Output TPC output 10 TP10 Output TPC output 11 TP11 Output TPC output 12 TP12 Output TPC output 13 TP13 Output TPC output 14 TP14 Output TPC output 15 TP15 Output Group 1 pulse output Group 2 pulse output Group 3 pulse output Rev. 7.00 Jan 31, 2006 page 315 of 658 REJ09B0272-0700 Section 11 Programmable Timing Pattern Controller (TPC) 11.1.4 Registers Table 11.2 summarizes the TPC registers. Table 11.2 TPC Registers Access Size Name Abbreviation R/W Initial Value Address* Port B control register 1 PBCR1 R/W H'0000 H'5FFFFCC 8, 16 Port B control register 2 PBCR2 R/W H'0000 H'5FFFFCE 8, 16 Port B data register PBDR 2 R/(W)* H'0000 H'5FFFFC2 8, 16 TPC output mode register TPMR R/W H'F0 H'5FFFFF0 8, 16 TPC output control register TPCR R/W H'FF H'5FFFFF1 8, 16 Next data enable register B NDERB R/W H'00 H'5FFFFF2 8, 16 Next data enable register A NDERA R/W H'00 H'5FFFFF3 8, 16 Next data register A NDRA R/W H'00 H'5FFFFF5/ 3 H'5FFFFF7* 8, 16 Next data register B NDRB R/W H'00 H'5FFFFF4/ 3 H'5FFFFF6* 8, 16 1 Notes: 1. Only the values of bits A27-A24 and A8-A0 are valid; bits A23-A9 are ignored. For details on the register addresses, see section 8.3.5, Area Descriptions. 2. Bits used for TPC output cannot be written to. 3. These addresses change depending on the TPCR settings. When TPC output groups 0 and 1 have the same output trigger, the NDRA address is H'5FFFFF5; when their output triggers are different, the NDRA address for group 0 is H'5FFFFF7 and the address for group 1 is H'5FFFFF5. Likewise, when TPC output groups 2 and 3 have the same output trigger, the NDRB address is H'5FFFFF4; when their output triggers are different, the NDRB address for group 0 is H'5FFFFF6 and the address for group 1 is H'5FFFFF4. Rev. 7.00 Jan 31, 2006 page 316 of 658 REJ09B0272-0700 Section 11 Programmable Timing Pattern Controller (TPC) 11.2 Register Descriptions 11.2.1 Port B Control Registers 1 and 2 (PBCR1, PCBR2) Port B control registers 1 and 2 (PBCR1 and PBCR2) are 16-bit read/write registers that set the functions of port B pins. Port B consists of the dual-use pins TP15-TP0. Bits corresponding to the pins to be used for TPC output must be set to 11. For details, see the port B description in section 15, Pin Function Controller (PFC). PCBR1 Bit 15 14 13 12 11 10 9 8 PB15 MD1 PB15 MD0 PB14 MD1 PB14 MD0 PB13 MD1 PB13 MD0 PB12 MD1 PB12 MD0 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 PB11 MD1 PB11 MD0 PB10 MD1 PB10 MD0 PB9 MD1 PB9 MD0 PB8 MD1 PB8 MD0 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W 15 14 13 12 11 10 9 8 Bit PCBR2 Bit PB7MD1 PB7MD0 PB6MD1 PB6MD0 PB5MD1 PB5MD0 PB4MD1 PB4MD0 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 Bit PB3MD1 PB3MD0 PB2MD1 PB2MD0 PB1MD1 PB1MD0 PB0MD1 PB0MD0 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Rev. 7.00 Jan 31, 2006 page 317 of 658 REJ09B0272-0700 Section 11 Programmable Timing Pattern Controller (TPC) 11.2.2 Port B Data Register (PBDR) The port B data register (PBDR) is a 16-bit read/write register that stores output data for groups 0- 3 when TPC output is used. For details of PBDR, see section 16, I/O Ports. Bit 15 14 13 12 11 10 9 PB15DR PB14DR PB13DR PB12DR PB11DR PB10DR PB9DR Initial value 8 PB8DR 0 0 0 0 0 0 0 0 R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* 7 6 5 4 3 2 1 0 PB7DR PB6DR PB5DR PB4DR PB3DR PB2DR PB1DR PB0DR Initial value 0 0 0 0 0 0 0 0 Read/Write R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* Read/Write Note: * Bits set to TPC output by NDERA or NDERB are read-only. Bit Note: * Bits set to TPC output by NDERA or NDERB are read-only. 11.2.3 Next Data Register A (NDRA) NDRA is an eight-bit read/write register that stores the next output data for TPC output groups 1 and 0 (TP7-TP0). When used for TPC output, the contents of NDRA are transferred to the corresponding PBDR bits when the ITU compare match specified in the TPC output control register, TPCR, occurs. The address of NDRA differs depending on whether TPCR settings select the same trigger or different triggers for TPC output groups 1 and 0. NDRA is initialized to H'00 by a reset. It is not initialized in standby mode. Same Trigger for TPC Output Groups 1 and 0: If TPC output groups 1 and 0 are triggered by the same compare match, the address of NDRA is H'FFFFF5. The upper 4 bits become group 1 and the lower 4 bits become group 0. Address H'5FFFFF7 in such cases consists entirely of reserved bits. These bits cannot be modified and are always read as 1. Address H'5FFFFF5 Bits 7-4--Next Data 7-4 (NDR7-NDR4): NDR7-NDR4 store the next output data for TPC output group 1. Rev. 7.00 Jan 31, 2006 page 318 of 658 REJ09B0272-0700 Section 11 Programmable Timing Pattern Controller (TPC) Bits 3-0--Next Data 3-0 (NDR3-NDR0): NDR3-NDR0 store the next output data for TPC output group 0. Bit 7 6 5 4 3 2 1 0 NDR7 NDR6 NDR5 NDR4 NDR3 NDR2 NDR1 NDR0 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Address H'5FFFFF7 Bits 7-0--Reserved: These bits are always read as 1. The write value should always be 1. Bit 7 6 5 4 3 2 1 0 -- -- -- -- -- -- -- -- Initial value 1 1 1 1 1 1 1 1 Read/Write -- -- -- -- -- -- -- -- Different Triggers for TPC Output Groups 1 and 0: If TPC output groups 1 and 0 are triggered by different compare matches, the address of the upper 4 bits of NDRA (group 1) is H'5FFFFF5 and the address of the lower 4 bits of NDRA (group 0) is H'5FFFFF7. Bits 3-0 of address H'5FFFFF5 and bits 7-4 of address H'5FFFFF7 are reserved bits. The write value should always be 1. These bits are always read as 1. Address H'5FFFFF5 Bits 7-4--Next Data 7-4 (NDR7-NDR4): NDR7-NDR4 store the next output data for TPC output group 1. Bits 3-0--Reserved: These bits are always read as 1. The write value should always be 1. Bit 7 6 5 4 3 2 1 0 NDR7 NDR6 NDR5 NDR4 -- -- -- -- Initial value 0 0 0 0 1 1 1 1 Read/Write R/W R/W R/W R/W -- -- -- -- Address H'5FFFFF7 Bits 7-4--Reserved: These bits are always read as 1. The write value should always be 1. Rev. 7.00 Jan 31, 2006 page 319 of 658 REJ09B0272-0700 Section 11 Programmable Timing Pattern Controller (TPC) Bits 3-0--Next Data 3-0 (NDR3-NDR0): NDR3-NDR0 store the next output data for TPC output group 0. Bit 7 6 5 4 3 2 1 0 -- -- -- -- NDR3 NDR2 NDR1 NDR0 Initial value 1 1 1 1 0 0 0 0 Read/Write -- -- -- -- R/W R/W R/W R/W 11.2.4 Next Data Register B (NDRB) NDRB is an eight-bit read/write register that stores the next output data for TPC output groups 3 and 2 (TP15-TP8). When used for TPC output, the contents of NDRB are transferred to the corresponding PBDR bits when the ITU compare match specified in the TPC output control register, TPCR, occurs. The address of NDRB differs depending on whether TPCR settings select the same trigger or different triggers for TPC output groups 3 and 2. NDRB is initialized to H'00 by a reset. It is not initialized in standby mode. Same Trigger for TPC Output Groups 3 and 2: If TPC output groups 3 and 2 are triggered by the same compare match, the address of NDRB is H'FFFFF4. The upper 4 bits become group 3 and the lower 4 bits become group 2. Address H'5FFFFF6 consists entirely of reserved bits. These bits are always read as 1, and the write value should always be 1. Address H'5FFFFF4 Bits 7-4--Next Data 15-12 (NDR15-NDR12): NDR15-NDR12 store the next output data for TPC output group 3. Bits 3-0--Next Data 11-8 (NDR11-NDR8): NDR11-NDR8 store the next output data for TPC output group 2. Bit 7 6 5 4 3 2 1 0 NDR15 NDR14 NDR13 NDR12 NDR11 NDR10 NDR9 NDR8 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Rev. 7.00 Jan 31, 2006 page 320 of 658 REJ09B0272-0700 Section 11 Programmable Timing Pattern Controller (TPC) Address H'5FFFFF6 Bits 7-0--Reserved: These bits are always read as 1. The write value should always be 1. Bit 7 6 5 4 3 2 1 0 -- -- -- -- -- -- -- -- Initial value 1 1 1 1 1 1 1 1 Read/Write -- -- -- -- -- -- -- -- Different Triggers for TPC Output Groups 3 and 2: If TPC output groups 3 and 2 are triggered by different compare matches, the address of the upper 4 bits of NDRB (group 3) is H'5FFFFF4 and the address of the lower 4 bits of NDRB (group 2) is H'5FFFFF6. Bits 3-0 of address H'5FFFFF4 and bits 7-4 of address H'5FFFFF6 are reserved bits. These bits are always read as 1. The write value should always be 1. Address H'5FFFFF4 Bits 7-4--Next Data 15-12 (NDR15-NDR12): NDR15-NDR12 store the next output data for TPC output group 3. Bits 3-0--Reserved: These bits are always read as 1. The write value should always be 1. Bit 7 6 5 4 3 2 1 0 NDR15 NDR14 NDR13 NDR12 -- -- -- -- Initial value 0 0 0 0 1 1 1 1 Read/Write R/W R/W R/W R/W -- -- -- -- Address H'5FFFFF6 Bits 7-4--Reserved: These bits are always read as 1. The write value should always be 1. Bits 3-0--Next Data 11-8 (NDR11-NDR8): NDR11-NDR8 store the next output data for TPC output group 2. Bit 7 6 5 4 3 2 1 0 -- -- -- -- NDR11 NDR10 NDR9 NDR8 Initial value 1 1 1 1 0 0 0 0 Read/Write -- -- -- -- R/W R/W R/W R/W Rev. 7.00 Jan 31, 2006 page 321 of 658 REJ09B0272-0700 Section 11 Programmable Timing Pattern Controller (TPC) 11.2.5 Next Data Enable Register A (NDERA) NDERA is an eight-bit read/write register that enables TPC output groups 1 and 0 (TP7-TP0) on a bit-by-bit basis. When the bits enabled for TPC output by NDERA generate the ITU compare match selected in the TPC output control register, the value of the next data register A (NDRA) is automatically transferred to the corresponding PBDR bits and the output value is updated. For disabled bits, there is no transfer and the output value does not change. NDERA is initialized to H'00 by a reset. It is not initialized in standby mode. Bit 7 6 5 4 3 2 1 0 NDER7 NDER6 NDER5 NDER4 NDER3 NDER2 NDER1 NDER0 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Bits 7-0--Next Data Enable 7-0 (NDER7-NDER0): NDER7-NDER0 select enabling/disabling for TPC output groups 1 and 0 (TP7-TP0) in bit units. Bit 7-0: NDER7-NDER0 Description 0 Disables TPC outputs TP7-TP0 (transfer from NDR7-NDR0 to PB7-PB0 is disabled) (Initial value) 1 Enables TPC outputs TP7-TP0 (transfer from NDR7-NDR0 to PB7-PB0 is enabled) 11.2.6 Next Data Enable Register B (NDERB) NDERB is an eight-bit read/write register that enables TPC output groups 3 and 2 (TP15-TP8) on a bit-by-bit basis. When the bits enabled for TPC output by NDERB generate the ITU compare match selected in the TPC output control register, the value of the next data register B (NDRB) is automatically transferred to the corresponding PBDR bits and the output value is updated. For disabled bits, there is no transfer and the output value does not change. NDERB is initialized to H'00 by a reset. It is not initialized in standby mode. Rev. 7.00 Jan 31, 2006 page 322 of 658 REJ09B0272-0700 Section 11 Programmable Timing Pattern Controller (TPC) Bit 7 6 5 4 3 2 1 NDER15 NDER14 NDER13 NDER12 NDER11 NDER10 NDER9 0 NDER8 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Bits 7-0--Next Data Enable 15-8 (NDER15-NDER8): NDER15-NDER8 select enabling/disabling for TPC output groups 3 and 2 (TP15-TP8) in bit units. Bit 7-0: NDER15-NDER8 Description 0 Disables TPC outputs TP15-TP8 (transfer from NDR15-NDR8 to PB15-PB8 is disabled) (Initial value) 1 Enables TPC outputs TP15-TP8 (transfer from NDR15-NDR8 to PB15-PB8 is enabled) 11.2.7 TPC Output Control Register (TPCR) TPCR is an eight-bit read/write register that selects output trigger signals for TPC outputs. TPCR is initialized to H'FF by a reset. It is not initialized in standby mode. Bit 7 6 5 4 3 2 1 0 G3CMS1 G3CMS0 G2CMS1 G2CMS0 G1CMS1 G1CMS0 G0CMS1 G0CMS0 Initial value 1 1 1 1 1 1 1 1 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Bits 7 and 6--Group 3 Compare Match Select 1 and 0 (G3CMS1 and G3CMS0): G3CMS1 and G3CMS0 select the compare match that triggers TPC output group 3 (TP15-TP12). Bit 7: G3CMS1 Bit 6: G3CMS0 0 0 TPC output group 3 (TP15-TP12) output is triggered by compare match in ITU channel 0 1 TPC output group 3 (TP15-TP12) output is triggered by compare match in ITU channel 1 0 TPC output group 3 (TP15-TP12) output is triggered by compare match in ITU channel 2 1 TPC output group 3 (TP15-TP12) output is triggered by compare match in ITU channel 3 (Initial value) 1 Description Rev. 7.00 Jan 31, 2006 page 323 of 658 REJ09B0272-0700 Section 11 Programmable Timing Pattern Controller (TPC) Bits 5 and 4--Group 2 Compare Match Select 1 and 0 (G2CMS1 and G2CMS0): G2CMS1 and G2CMS0 select the ITU channel that triggers TPC output group 2 (TP11-TP8). Bit 5: G2CMS1 Bit 4: G2CMS0 0 0 TPC output group 2 (TP11-TP18) output is triggered by compare match in ITU channel 0 1 TPC output group 2 (TP11-TP18) output is triggered by compare match in ITU channel 1 0 TPC output group 2 (TP11-TP18) output is triggered by compare match in ITU channel 2 1 TPC output group 2 (TP11-TP18) output is triggered by compare match in ITU channel 3 (Initial value) 1 Description Bits 3 and 2--Group 1 Compare Match Select 1 and 0 (G1CMS1 and G1CMS0): G1CMS1 and G1CMS0 select the ITU channel that triggers TPC output group 1 (TP7-TP4). Bit 3: G1CMS1 Bit 2: G1CMS0 0 0 TPC output group 1 (TP7-TP4) output is triggered by compare match in ITU channel 0 1 TPC output group 1 (TP7-TP4) output is triggered by compare match in ITU channel 1 0 TPC output group 1 (TP7-TP4) output is triggered by compare match in ITU channel 2 1 TPC output group 1 (TP7-TP4) output is triggered by compare match in ITU channel 3 (Initial value) 1 Description Rev. 7.00 Jan 31, 2006 page 324 of 658 REJ09B0272-0700 Section 11 Programmable Timing Pattern Controller (TPC) Bits 1 and 0--Group 0 Compare Match Select 1 and 0 (G0CMS1 and G0CMS0): G0CMS1 and G0CMS0 select the ITU channel that triggers TPC output group 0 (TP3-TP0). Bit 1: G0CMS1 Bit 0: G0CMS0 0 0 TPC output group 0 (TP3-TP0) output is triggered by compare match in ITU channel 0 1 TPC output group 0 (TP3-TP0) output is triggered by compare match in ITU channel 1 0 TPC output group 0 (TP3-TP0) output is triggered by compare match in ITU channel 2 1 TPC output group 0 (TP3-TP0) output is triggered by compare match in ITU channel 3 (Initial value) 1 11.2.8 Description TPC Output Mode Register (TPMR) TPMR is an eight-bit read/write register that selects between the TPC's ordinary output and nonoverlap output modes in group units. During non-overlap operation, the output waveform cycle is set in ITU general register B (GRB) for use as the output trigger and a non-overlap period is set in general register A (GRA). The output value then changes on compare matches A and B. For details, see section 11.3.4, TPC Output Non-Overlap Operation. TPMR is initialized to H'F0 by a reset. It is not initialized in standby mode. Bit 7 6 5 4 -- -- -- -- 3 2 1 0 Initial value 1 1 1 1 0 0 0 0 Read/Write -- -- -- -- R/W R/W R/W R/W G3NOV G2NOV G1NOV G0NOV Bits 7-4--Reserved: These bits are always read as 1. The write value should always be 1. Bit 3--Group 3 Non-Overlap Mode (G3NOV): G3NOV selects ordinary or non-overlap mode for TPC output group 3 (TP15-TP12). Bit 3: G3NOV Description 0 TPC output group 3 operates normally (output value updated according to compare match A of the ITU channel selected by TPCR) (Initial value) 1 TPC output group 3 operates in non-overlap mode (1 output and 0 output can be performed independently according to compare match A and B of the ITU channel selected by TPCR) Rev. 7.00 Jan 31, 2006 page 325 of 658 REJ09B0272-0700 Section 11 Programmable Timing Pattern Controller (TPC) Bit 2--Group 2 Non-Overlap Mode (G2NOV): G2NOV selects ordinary or non-overlap mode for TPC output group 2 (TP11-TP8). Bit 2: G2NOV Description 0 TPC output group 2 operates normally (output value updated according to compare match A of the ITU channel selected by TPCR) (Initial value) 1 TPC output group 2 operates in non-overlap mode (1 output and 0 output can be performed independently according to compare match A and B of the ITU channel selected by TPCR) Bit 1--Group 1 Non-Overlap Mode (G1NOV): G1NOV selects ordinary or non-overlap mode for TPC output group 1 (TP7-TP4). Bit 1: G1NOV Description 0 TPC output group 1 operates normally (output value updated according to compare match A of the ITU channel selected by TPCR) (Initial value) 1 TPC output group 1 operates in non-overlap mode (1 output and 0 output can be performed independently according to compare match A and B of the ITU channel selected by TPCR) Bit 0--Group 0 Non-Overlap Mode (G0NOV): G0NOV selects ordinary or non-overlap mode for TPC output group 0 (TP3-TP0). Bit 0: G0NOV Description 0 TPC output group 0 operates normally (output value updated according to compare match A of the ITU channel selected by TPCR) (Initial value) 1 TPC output group 0 operates in non-overlap mode (1 output and 0 output can be performed independently according to compare match A and B of the ITU channel selected by TPCR) 11.3 Operation 11.3.1 Overview When corresponding bits in the PBCR1, PBCR2, NDERA, and NDERB registers are set to 1, TPC output is enabled and the PBDR data register values are output. After that, when the compare match event selected by TPCR occurs, the next data register contents (NDRA and NDRB) are transferred to PBDR and output values are updated. Figure 11.2 illustrates the TPC output operation. Rev. 7.00 Jan 31, 2006 page 326 of 658 REJ09B0272-0700 Section 11 Programmable Timing Pattern Controller (TPC) CR NDER Q Q Output trigger signal C Port function select Q DR D Q NDR D Internal data bus TPC output pin Figure 11.2 TPC Output Operation If new data is written in next data registers A and B before the next compare match occurs, a maximum 16 bits of data can be output at each successive compare match. See section 11.3.4, TPC Output Non-Overlap Operation, for details on non-overlap operation. 11.3.2 Output Timing If TPC output is enabled, next data register (NDRA/NDRB) contents are transferred to the data register (PBDR) and output when the selected compare match occurs. Figure 11.3 shows the timing of these operations. The example is for ordinary output upon compare match A with groups 2 and 3. Rev. 7.00 Jan 31, 2006 page 327 of 658 REJ09B0272-0700 Section 11 Programmable Timing Pattern Controller (TPC) CK N TCNT GRA N+1 N Compare match A signal n NDRB PBDR m n TP15-TP8 m n Figure 11.3 Transfer and Output Timing for NDRB Data (Example) 11.3.3 Examples of Use of Ordinary TPC Output Settings for Ordinary TPC Output (Figure 11.4): 1. Select GRA as the output compare register (output disable) with the timer I/O control register (TIOR). 2. Set the TPC output trigger cycle. 3. Select the counter clock with the TPSC2-TPSC0 bits in the timer control register (TCR). Select the counter clear sources with the CCLR1 and CCLR0 bits. 4. Set the timer interrupt enable register (TIER) to enable IMIA interrupts. Transfers to NDR can also be set using the DMAC. 5. Set the initial output value in the I/O port data register to be used by the TPC. 6. Set the I/O port control register to be used by the TPC as the TP pin function (11). 7. Set to 1 the bit that performs TPC output to the next data enable register (NDER). 8. Select the ITU compare match that will be the TPC output trigger using the TPC output control register (TPCR). 9. Set the next TPC output value in NDR. 10. Set 1 in the STR bit of the timer start register (TSTR) and start the timer counter. 11. Set the next output value in NDR whenever an IMIA interrupt is generated. Rev. 7.00 Jan 31, 2006 page 328 of 658 REJ09B0272-0700 Section 11 Programmable Timing Pattern Controller (TPC) Ordinary TPC output operation Select GR function (1) Set GRA (2) Set count operation (3) Select interrupt request (4) Set initial output value (5) Set port output (6) Set TPC output enable (7) ITU setting Port and TPC setting Select TPC output trigger ITU setting (8) Set next TPC output value (9) Start count (10) Compare match? No Yes Set next TPC output value (11) Figure 11.4 Example of Setting Procedure for Ordinary TPC Output Rev. 7.00 Jan 31, 2006 page 329 of 658 REJ09B0272-0700 Section 11 Programmable Timing Pattern Controller (TPC) Five-Phase Pulse Output (Figure 11.5): Figure 11.5 shows an example of 5-phase pulse output generated at regular intervals using TPC output. 1. Set the GRA register of the ITU that serves as output trigger as the output compare register. Set the cycle time in GRA of the ITU and select counter clearing upon compare match A. Set the IMIEA bit in TIER to 1 to enable the compare match A interrupt. 2. Write H'FFC0 in PBCR1, write H'F8 in NDERB, and set G3CMS0, G3CMS1, G2CMS1, and G2CMS0 in TPCR to set the ITU compare match selected in step 1 as the output trigger. Write output data H'80 in NDRB. 3. When the selected ITU channel starts operating and a compare match occurs, the values in NDRB are transferred to PBDR and output. The compare match/input capture A (IMIA) interrupt handling routine writes the next output data (H'C0) in NDRB. 4. Five-phase pulse output can be obtained by writing H'40, H'60, H'20, H'30, H'10, H'18, H'08, H'88... at successive compare match interrupts. If the DMA controller is set for activation by compare match, pulse output can be obtained without imposing a load on the CPU. TCNT value TCNT GRA Compare matches H'0000 NDRB PBDR Time 80 C0 40 60 20 30 10 18 08 88 80 C0 8000 C000 4000 6000 2000 3000 1000 1800 0800 8800 8000 C000 TP15 TP14 TP13 TP12 TP11 Figure 11.5 TPC Output Example (5-Phase Pulse Output) Rev. 7.00 Jan 31, 2006 page 330 of 658 REJ09B0272-0700 Section 11 Programmable Timing Pattern Controller (TPC) 11.3.4 TPC Output Non-Overlap Operation Setting Procedures for TPC Output Non-Overlap Operation (Figure 11.6): 1. Select GRA and GRB as output compare registers (output disable) with the timer I/O control register (TIOR). 2. Set the TPC output trigger cycle in GRB and the non-overlap cycle in GRA. 3. Select the counter clock with the TPSC2-TPSC0 bits in the timer control register (TCR). Select the counter clear sources with the CCLR1 and CCLR0 bits. 4. Set the timer interrupt enable register (TIER) to enable IMIA interrupts. Transfers to NDR can also be set using the DMAC. 5. Set the initial output value in the I/O port data register to be used by the TPC. 6. Set the I/O port control register to be used by the TPC as the TP pin function (11). 7. Set to 1 the bit that performs TPC output to the next data enable register (NDER). 8. Select the ITU compare match that will be the TPC output trigger using the TPC output control register (TPCR). 9. Select the group that performs non-overlap operation in the TPC output mode register (TPMR). 10. Set the next TPC output value in NDR. 11. Set 1 in the STR bit of the timer start register (TSTR) and start the timer counter. 12. Set the next output value in NDR whenever an IMIA interrupt is generated. Rev. 7.00 Jan 31, 2006 page 331 of 658 REJ09B0272-0700 Section 11 Programmable Timing Pattern Controller (TPC) TPC output nonoverlap operation Select GR function (1) Set GRA (2) Set count operation (3) Select interrupt request (4) Set initial output value (5) Set TPC output (6) Set TPC transfer enable (7) Select TPC output trigger (8) Select non-overlap group (9) Set next TPC output value (10) Start count (11) ITU setting Port and TPC setting ITU setting Compare match A? No Yes Set next TPC output value (12) Figure 11.6 Example of Setting Procedure for TPC Output Non-Overlap Operation Rev. 7.00 Jan 31, 2006 page 332 of 658 REJ09B0272-0700 Section 11 Programmable Timing Pattern Controller (TPC) TPC Output Non-Overlap Operation (Four-Phase Complementary Non-Overlap Output) (Figure 11.7): 1. Set the GRA and GRB registers of the ITU that serves as output triggers as output compare registers. Set the cycle in GRB and the non-overlap cycle time in GRA and select counter clearing upon compare match B. Set the IMIEA bit in TIER to 1 to enable the IMIA interrupt. 2. Write H'FFFF in PBCR1, write H'FF in NDERB, and set G3CMS1, G3CMS0, G2CMS1, and G2CMS0 in TPCR to set the ITU compare match selected in step 1 as the output trigger. Set the G3NOV and G2NOV bits in TPMR to 1 to set non-overlap operation. Write output data H'95 in NDRB. 3. When the selected ITU channel starts operating and a GRB compare match occurs, 1 output changes to 0 output; when a GRA compare match occurs, 0 output changes to 1 output. (The change from 0 output to 1 output is delayed by the value set in GRA.) The IMIA interrupt handling routine writes the next output data (H'65) in NDRB. 4. Four-phase complementary non-overlap output can be obtained by writing H'59, H'56, H'95... at successive IMIA interrupts. If the DMA controller is set for activation by compare match, pulse output can be obtained without imposing a load on the CPU. Rev. 7.00 Jan 31, 2006 page 333 of 658 REJ09B0272-0700 Section 11 Programmable Timing Pattern Controller (TPC) TCNT value GRB TCNT GRA Time H'0000 NDRB 95 PBDR 00 65 95 05 59 65 41 56 59 50 95 56 14 65 95 05 65 Non-overlap cycle TP15 TP14 TP13 TP12 TP11 TP10 TP9 TP8 Figure 11.7 Non-Overlap Output Example (Four-Phase Complementary Output) Rev. 7.00 Jan 31, 2006 page 334 of 658 REJ09B0272-0700 Section 11 Programmable Timing Pattern Controller (TPC) 11.3.5 TPC Output by Input Capture TPC can also be output by using input capture rather than ITU compare matches. The general register A (GRA) of the ITU selected by TPCR functions as an input capture register and TPC output occurs in response to an input capture signal. Figure 11.8 shows the timing. CK TIOC pin Input capture signal NDR DR N M N Figure 11.8 TPC Output by Input Capture Rev. 7.00 Jan 31, 2006 page 335 of 658 REJ09B0272-0700 Section 11 Programmable Timing Pattern Controller (TPC) 11.4 Usage Notes 11.4.1 Non-Overlap Operation During non-overlap operation, transfers from NDR to data registers (DR) occur as follows. 1. NDR contents are always transferred to DR on compare match A. 2. The contents of bits transferred from NDR are only transferred on compare match B when they are 0. No transfer occurs for a 1. Figure 11.9 illustrates TPC output during non-overlap operation. CR NDER Q Q Compare match A Compare match B C Port function select Q DR D Q TPC output pin Figure 11.9 TPC Output Non-Overlap Operation Rev. 7.00 Jan 31, 2006 page 336 of 658 REJ09B0272-0700 NDR D Section 11 Programmable Timing Pattern Controller (TPC) When a compare match B occurs before the compare match A, the 0 data transfer can be performed before the 1 data transfer, so a non-overlapping waveform can be output. In such cases, be sure not to change the NDR contents until the compare match A after the compare match B occurs (non-overlap period). This can be ensured by writing the next data to NDR in the IMIA interrupt handling routine. The DMAC can also be started using an IMIA interrupt. However, these write operations should be performed prior to the next compare match B. The timing is shown in figure 11.10. Compare match A Compare match B NDR write NDR write NDR DR 0 output 0/1 output 0 output 0/1 output NDR write period NDR write disable period NDR write period NDR write disable period Figure 11.10 Non-Overlap Operation and NDR Write Timing Rev. 7.00 Jan 31, 2006 page 337 of 658 REJ09B0272-0700 Section 11 Programmable Timing Pattern Controller (TPC) Rev. 7.00 Jan 31, 2006 page 338 of 658 REJ09B0272-0700 Section 12 Watchdog Timer (WDT) Section 12 Watchdog Timer (WDT) 12.1 Overview The SuperH microcomputer has a one-channel watchdog timer (WDT) for monitoring system operations. If the system becomes uncontrolled and the timer counter overflows without being rewritten correctly by the CPU, an overflow signal (WDTOVF) is output externally. The WDT can simultaneously generate an internal reset signal for the entire chip. When this watchdog function is not needed, the WDT can be used as an interval timer. In the interval timer operation, an interval timer interrupt is generated at each counter overflow. The WDT is also used in recovering from standby mode. 12.1.1 Features WDT features are listed below: * Watchdog timer mode interval timer mode can be selected. * Outputs WDTOVF in or watchdog timer mode. When the counter overflows in watchdog timer mode, overflow signal WDTOVF is output externally. It is possible to select whether or not to reset the chip internally when this happens. Either the power-on reset or manual reset signal can be selected as the internal reset signal. * Generates interrupts in interval timer mode. When the counter overflows, it generates an interval timer interrupt. * Used to clear standby mode. * Selection of eight counter clock sources Rev. 7.00 Jan 31, 2006 page 339 of 658 REJ09B0272-0700 Section 12 Watchdog Timer (WDT) 12.1.2 Block Diagram Figure 12.1 shows a block diagram of the WDT. Overflow Interrupt control Clock WDTOVF Internal reset signal* Clock select Reset control RSTCSR TCNT /2 /64 /128 /256 /512 /1024 /4096 /8192 Internal clock sources TCSR Bus interface Module bus Internal data bus ITI (interrupt signal) WDT TCSR: Timer control/status register TCNT: Timer counter RSTCSR: Reset control/status register Note: * The internal reset signal can be generated by a register setting. The type of reset can be selected (power-on or manual reset). Figure 12.1 Block Diagram of WDT 12.1.3 Pin Configuration Table 12.1 shows the pin configuration. Table 12.1 Pin Configuration Pin Abbreviation I/O Function Watchdog timer overflow WDTOVF O Outputs the counter overflow signal in watchdog mode Rev. 7.00 Jan 31, 2006 page 340 of 658 REJ09B0272-0700 Section 12 Watchdog Timer (WDT) 12.1.4 Register Configuration Table 12.2 summarizes the three WDT registers. They are used to select the clock, switch the WDT mode, and control the reset signal. Table 12.2 WDT Registers Read* H'5FFFFB8 H'5FFFFB8 Abbreviation R/W Timer control/status register TCSR 3 R/(W)* H'18 Timer counter TCNT R/W H'00 Reset control/status register R/(W)* RSTCSR 4 1 Write* Name 3 Address* Initial Value 2 H'5FFFFB9 H'1F H'5FFFFBA H'5FFFFBB Notes: 1. Write by word transfer. A byte or longword write cannot be used. 2. Read by byte transfer. The correct value cannot be obtained by a word or longword read. 3. Only 0 can be written in bit 7, to clear the flag. 4. Only the values of bits A27-A24 and A8-A0 are valid; bits A23-A9 are ignored. For details on the register addresses, see section 8.3.5, Area Descriptions 12.2 Register Descriptions 12.2.1 Timer Counter (TCNT) TCNT is an eight-bit readable and writable up-counter. TCNT differs from other registers in that it is more difficult to write. See section 12.2.4, Notes on Register Access, for details. When the timer enable bit (TME) in the timer control/status register (TCSR) is set to 1, the timer counter starts counting pulses of an internal clock source selected by clock select bits 2-0 (CKS2-CKS0) in TCSR. When the value of TCNT overflows (changes from H'FF to H'00), a watchdog timer overflow signal (WDTOVF) or interval timer interrupt (ITI) is generated, depending on the mode selected with the WT/IT bit in TCSR. TCNT is initialized to H'00 by a reset and when the TME bit is cleared to 0. It is not initialized in standby mode. Bit 7 6 5 4 3 2 1 0 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Rev. 7.00 Jan 31, 2006 page 341 of 658 REJ09B0272-0700 Section 12 Watchdog Timer (WDT) 12.2.2 Timer Control/Status Register (TCSR) The timer control/status register (TCSR) is an eight-bit read/write register. TCSR differs from other registers in being more difficult to write. See section 12.2.4, Register Access, for details. Its functions include selecting the timer mode and clock source. Bits 7-5 are initialized to 000 by a reset and in standby mode. Bits 2-0 are initialized to 000 by a reset, but retain their values in standby mode. Bit 7 6 5 4 3 2 1 0 OVF WT/IT TME -- -- CKS2 CKS1 CKS0 Initial value 0 0 0 1 1 0 0 0 Read/Write R/(W)* R/W R/W -- -- R/W R/W R/W Note: * Only 0 can be written, to clear the flag. Bit 7--Overflow Flag (OVF): OVF indicates that TCNT has overflowed from H'FF to H'00 in interval timer mode. It is not set in watchdog timer mode. Bit 7: OVF Description 0 No overflow of TCNT in interval timer mode 1 TCNT overflow in interval timer mode (Initial value) Cleared by reading OVF, then writing 0 in OVF Bit 6--Timer Mode Select (WT/IT IT): IT WT/IT selects whether to use the WDT as a watchdog timer or interval timer. When TCNT overflows, the WDT either generates an interval timer interrupt (ITI) or generates a WDTOVF signal, depending on the mode selected. Bit 6: WT/IT IT Description 0 Interval timer mode: interval timer interrupt to the CPU when TCNT overflows (Initial value) 1 Watchdog timer mode: WDTOVF signal output externally when TCNT overflows. Section 12.2.3, Reset Control/Status Register (RSTCSR), describes in detail what happens when TCNT overflows in watchdog timer mode. Rev. 7.00 Jan 31, 2006 page 342 of 658 REJ09B0272-0700 Section 12 Watchdog Timer (WDT) Bit 5--Timer Enable (TME): TME enables or disables the timer. Bit 5: TME Description 0 Timer disabled: TCNT is initialized to H'00 and count-up stops (Initial value) 1 Timer enabled: TCNT starts counting. A WDTOVF signal or interrupt is generated when TCNT overflows. Bits 4 and 3--Reserved): These bits are always read as 1. The write value should always be 1. Bits 2-0--Clock Select 2-0 (CKS2-CKS0): CKS2-CKS0 select one of eight internal clock sources for input to TCNT. The clock signals are obtained by dividing the frequency of the system clock (). Description Bit 2: CKS2 Bit 1: CKS1 Bit 0: CKS0 Clock Source Overflow Interval* ( = 20 MHz) 0 0 0 /2 (Initial value) 25.6 s 0 0 1 /64 819.2 s 0 1 0 /128 1.6 ms 0 1 1 /256 3.3 ms 1 0 0 /512 6.6 ms 1 0 1 /1024 13.1 ms 1 1 0 /4096 52.4 ms 1 1 1 /8192 104.9 ms Note: * The overflow interval listed is the time from when the TCNT begins counting at H'00 until an overflow occurs. 12.2.3 Reset Control/Status Register (RSTCSR) RSTCSR is an eight-bit read/write register that controls output of the reset signal generated by timer counter (TCNT) overflow and selects the internal reset signal type. RSTCSR differs from other registers in that it is more difficult to write. See section 12.2.4, Notes on Register Access, for details. RSTCR is initialized to H'1F by input of a reset signal from the RES pin, but is not initialized by the internal reset signal generated by overflow of the WDT. It is initialized to H'1F in standby mode. Rev. 7.00 Jan 31, 2006 page 343 of 658 REJ09B0272-0700 Section 12 Watchdog Timer (WDT) Bit 7 6 5 4 3 2 1 0 WOVF RSTE RSTS -- -- -- -- -- Initial value 0 0 0 1 1 1 1 1 Read/Write R/(W)* R/W R/W -- -- -- -- -- Note: * Only 0 can be written in bit 7, to clear the flag. Bit 7--Watchdog Timer Overflow (WOVF): WOVF indicates that TCNT has overflowed (from H'FF to H'00) in watchdog timer mode. It is not set in interval timer mode. Bit 7: WOVF Description 0 No TCNT overflow in watchdog timer mode (Initial value) Cleared when software reads WOVF, then writes 0 in WOVF 1 Set by TCNT overflow in watchdog timer mode Bit 6--Reset Enable (RSTE): RSTE selects whether to reset the chip internally if the TCNT overflows in watchdog timer mode. Bit 6: RSTE Description 0 Not reset when TCNT overflows (Initial value) LSI not reset internally, but TCNT and TCSR reset within WDT. 1 Reset when TCNT overflows Bit 5--Reset Select (RSTS): RSTS selects the type of internal reset generated if TCNT overflows in watchdog timer mode. Bit 5: RSTS Description 0 Power-on reset 1 Manual reset (Initial value) Bits 4-0--Reserved: These bits are always read as 1. The write value should always be 1. 12.2.4 Notes on Register Access The watchdog timer's TCNT, TCSR, and RSTCSR registers differ from other registers in that they are more difficult to write. The procedures for writing and reading these registers are given below. Writing to TCNT and TCSR: These registers must be written by a word transfer instruction. They cannot be written by byte transfer instructions. TCNT and TCSR both have the same write Rev. 7.00 Jan 31, 2006 page 344 of 658 REJ09B0272-0700 Section 12 Watchdog Timer (WDT) address. The write data must be contained in the lower byte of the written word. The upper byte must be H'5A (for TCNT) or H'A5 (for TCSR) (figure 12.2). This transfers the write data from the lower byte to TCNT or TCSR. Writing to TCNT 15 Address: H'5FFFFB8 8 7 H'5A 0 Write data Writing to TCSR 15 Address: H'5FFFFB8 8 7 H'A5 0 Write data Figure 12.2 Writing to TCNT and TCSR Writing to RSTCSR: RSTCSR must be written by a word access to address H'5FFFFFBA. It cannot be written by byte transfer instructions. Procedures for writing 0 in WOVF (bit 7) and for writing to RSTE (bit 6) and RSTS (bit 5) are different, as shown in figure 12.3. To write 0 in the WOVF bit, the write data must be H'A5 in the upper byte and H'00 in the lower byte. This clears the WOVF bit to 0. The RSTE and RSTS bits are not affected. To write to the RSTE and RSTS bits, the upper byte must be H'5A and the lower byte must be the write data. The values of bits 6 and 5 of the lower byte are transferred to the RSTE and RSTS bits, respectively. The WOVF bit is not affected. Writing 0 to the WOVF bit 15 Address: H'5FFFFBA 8 7 H'A5 0 H'00 Writing to the RSTE and RSTS bits 15 Address: H'5FFFFBA 8 H'5A 7 0 Write data Figure 12.3 Writing to RSTCSR Reading from TCNT, TCSR, and RSTCSR: TCNT, TCSR, and RSTCSR are read like other registers. Use byte transfer instructions. The read addresses are H'5FFFFB8 for TCSR, H'5FFFFB9 for TCNT, and H'5FFFFBB for RSTCSR. Rev. 7.00 Jan 31, 2006 page 345 of 658 REJ09B0272-0700 Section 12 Watchdog Timer (WDT) 12.3 Operation 12.3.1 Operation in Watchdog Timer Mode To use the WDT as a watchdog timer, set the WT/IT and TME bits in TCSR to 1. Software must prevent TCNT overflow by rewriting the TCNT value (normally by writing H'00) before overflow occurs. If TCNT fails to be rewritten and overflows due to a system crash or the like, a WDTOVF signal is output (figure 12.4). The WDTOVF signal can be used to reset external system devices. The WDTOVF signal is output for 128 clock cycles. If the RSTE bit in RSTCSR is set to 1, a signal to reset the chip will be generated internally simultaneous to the WDTOVF signal when TCNT overflows. Either a power-on reset or a manual reset can be selected by the RSTS bit in RSTCSR. The internal reset signal is output for 512 clock cycles. When a watchdog reset is generated simultaneously with input at the RES pin, the software distinguishes the RES reset from the watchdog reset by checking the WOVF bit in RSTCSR. The RES reset takes priority. The WOVF bit is cleared to 0. Rev. 7.00 Jan 31, 2006 page 346 of 658 REJ09B0272-0700 Section 12 Watchdog Timer (WDT) TCNT value Overflow H'FF H'00 Time WT/IT = 1 TME = 1 H'00 written in TCNT WOVF = 1 WT/IT = 1 H'00 written TME = 1 in TCNT WDTOVF and internal reset generated WDTOVF signal 128 clocks Internal reset signal* 512 clocks WT/IT: Timer mode select bit TME: Timer enable bit Note: * The internal reset signal is only generated when the RSTE bit is 1. Figure 12.4 Operation in Watchdog Timer Mode Rev. 7.00 Jan 31, 2006 page 347 of 658 REJ09B0272-0700 Section 12 Watchdog Timer (WDT) 12.3.2 Operation in Interval Timer Mode To use the WDT as an interval timer, clear WT/IT to 0 and set TME to 1. An interval timer interrupt (ITI) is generated each time the timer counter overflows. This function can be used to generate interval timer interrupts at regular intervals (figure 12.5). TCNT value Overflow H'FF Overflow Overflow Overflow H'00 Time WT/IT = 0 TME = 1 ITI ITI ITI ITI ITI: Interval timer interrupt request Figure 12.5 Operation in Interval Timer Mode 12.3.3 Operation in Standby Mode The watchdog timer has a special function to clear standby mode with an NMI interrupt. When using standby mode, set the WDT as described below. Transition to Standby Mode: The TME bit in TCSR must be cleared to 0 to stop the watchdog timer counter before it enters standby mode. The chip cannot enter standby mode while the TME bit is set to 1. Set bits CKS2-CKS0 so that the counter overflow interval is equal to or longer than the oscillation settling time. See sections 20.1.3 and 20.2.3, AC Characteristics, for the oscillation settling time. Recovery from Standby Mode: When an NMI request signal is received in standby mode, the clock oscillator starts running and the watchdog timer starts counting at the rate selected by bits CKS2-CKS0 before standby mode was entered. When TCNT overflows (changes from H'FF to H'00), the system clock () is presumed to be stable and usable; clock signals are supplied to the entire chip and standby mode ends. For details on standby mode, see section 19, Power Down State. Rev. 7.00 Jan 31, 2006 page 348 of 658 REJ09B0272-0700 Section 12 Watchdog Timer (WDT) 12.3.4 Timing of Overflow Flag (OVF) Setting In interval timer mode, when TCNT overflows the OVF flag in TCSR is set to 1 and an interval timer interrupt is requested (figure 12.6). CK H'FF TCNT H'00 Overflow signal (internal signal) OVF Figure 12.6 Timing of OVF Setting 12.3.5 Timing of Watchdog Timer Overflow Flag (WOVF) Setting When TCNT overflows the WOVF bit in RSTCSR is set to 1 and a WDTOVF signal is output. When the RSTE bit is set to 1, TCNT overflow enables an internal reset signal to be generated for the entire chip (figure 12.7). CK TCNT H'FF H'00 Overflow signal (internal signal) WOVF Figure 12.7 Timing of WOVF Bit Setting and Internal Reset Rev. 7.00 Jan 31, 2006 page 349 of 658 REJ09B0272-0700 Section 12 Watchdog Timer (WDT) 12.4 Usage Notes 12.4.1 TCNT Write and Increment Contention If a timer counter clock pulse is generated during the T3 state of a write cycle to TCNT, the write takes priority and the timer counter is not incremented (figure 12.8). TCNT write cycle T1 T2 T3 CK Address TCNT address Internal write signal TCNT input clock TCNT N M Counter write data Figure 12.8 Contention between TCNT Write and Increment 12.4.2 Changing CKS2-CKS0 Bit Values If the values of bits CKS2-CKS0 are altered while the WDT is running, the count may increment incorrectly. Always stop the watchdog timer (by clearing the TME bit to 0) before changing the values of bits CKS2-CKS0. 12.4.3 Changing Watchdog Timer/Interval Timer Modes To prevent incorrect operation, always stop the watchdog timer (by clearing the TME bit to 0) before switching between interval timer mode and watchdog timer mode. Rev. 7.00 Jan 31, 2006 page 350 of 658 REJ09B0272-0700 Section 12 Watchdog Timer (WDT) 12.4.4 System Reset With WDTOVF If a WDTOVF signal is input to the RES pin, the chip cannot initialize correctly. Avoid logical input of the WDTOVF output signal to the RES input pin. To reset the entire system with the WDTOVF signal, use the circuit shown in figure 12.9. SuperH microcomputer Reset input Reset signal to entire system RES WDTOVF Figure 12.9 Example of System Reset Circuit Using WDTOVF Signal 12.4.5 Internal Reset With Watchdog Timer If the RSTE bit is cleared to 0 in watchdog timer mode, the chip will not reset internally when a TCNT overflow occurs, but TCNT and TCSR in the WDT will reset. Rev. 7.00 Jan 31, 2006 page 351 of 658 REJ09B0272-0700 Section 12 Watchdog Timer (WDT) Rev. 7.00 Jan 31, 2006 page 352 of 658 REJ09B0272-0700 Section 13 Serial Communication Interface (SCI) Section 13 Serial Communication Interface (SCI) 13.1 Overview The SuperH microcomputer has a serial communication interface (SCI) with two independent channels. Both channels are functionally identical. The SCI supports both asynchronous and synchronous serial communication. It also has a multiprocessor communication function for serial communication between two or more processors. 13.1.1 Features SCI features are listed below: * Asynchronous mode Serial data communication is synchronized using a start-stop method in character units. The SCI can communicate with a universal asynchronous receiver/transmitter (UART), an asynchronous communication interface adapter (ACIA), or any other chip that employs standard asynchronous serial communication. It can also communicate with two or more other processors using the multiprocessor communication function. There are twelve selectable serial data communication formats. Data length: seven or eight bits Stop bit length: one or two bits Parity: even, odd, or none Multiprocessor bit: one or none Receive error detection: parity, overrun, and framing errors Break detection: by reading the RxD level directly when a framing error occurs * Synchronous mode Serial data communication is synchronized with a clock signal. The SCI can communicate with other chips having a synchronous communication function. There is one serial data communication format. Data length: eight bits Receive error detection: overrun errors * Full duplex communication: The transmitting and receiving sections are independent, so the SCI can transmit and receive simultaneously. Both sections use double buffering, so continuous data transfer is possible in both the transmit and receive directions. * On-chip baud rate generator with selectable bit rates Rev. 7.00 Jan 31, 2006 page 353 of 658 REJ09B0272-0700 Section 13 Serial Communication Interface (SCI) * Internal or external transmit/receive clock source: baud rate generator (internal) or SCK pin (external) * Four types of interrupts: Transmit-data-empty, transmit-end, receive-data-full, and receiveerror interrupts are requested independently. The transmit-data-empty and receive-data-full interrupts can start the direct memory access controller (DMAC) to transfer data. 13.1.2 Block Diagram Bus interface Figure 13.1 shows a block diagram of the SCI. Module data bus RDR TDR BRR SSR SCR RxD RSR TSR SMR Transmit/ receive control TxD Parity generation Parity check SCK Baud rate generator External clock SMR: Serial mode register SCR: Serial control register SSR: Serial status register BRR: Bit rate register Figure 13.1 Block Diagram of SCI Rev. 7.00 Jan 31, 2006 page 354 of 658 REJ09B0272-0700 /4 /16 /64 Clock SCI RSR: Receive shift register RDR: Receive data register TSR: Transmit shift register TDR: Transmit data register Internal data bus TEI TXI RXI ERI Section 13 Serial Communication Interface (SCI) 13.1.3 Input/Output Pins Table 13.1 summarizes the SCI pins by channel. Table 13.1 SCI Pins Channel Pin Name Abbreviation Input/Output Function 0 Serial clock pin SCK0 Input/output SCI0 clock input/output 1 13.1.4 Receive data pin RxD0 Input SCI0 receive data input Transmit data pin TxD0 Output SCI0 transmit data output Serial clock pin SCK1 Input/output SCI1 clock input/output Receive data pin RxD1 Input SCI1 receive data input Transmit data pin TxD1 Output SCI1 transmit data output Register Configuration Table 13.2 summarizes the SCI internal registers. These registers select the communication mode (asynchronous or synchronous), specify the data format and bit rate, and control the transmitter and receiver sections. Rev. 7.00 Jan 31, 2006 page 355 of 658 REJ09B0272-0700 Section 13 Serial Communication Interface (SCI) Table 13.2 Registers Name Abbreviation R/W Initial Value Access size H'05FFFEC0 Serial mode register SMR0 R/W H'00 8, 16 H'05FFFEC1 Bit rate register BRR0 R/W H'FF 8, 16 H'05FFFEC2 Serial control register SCR0 R/W H'00 8, 16 H'05FFFEC3 Transmit data register TDR0 R/W H'FF 8, 16 H'05FFFEC4 Serial status register SSR0 R/(W)* H'84 8, 16 H'05FFFEC5 Receive data register RDR0 R H'00 8, 16 H'05FFFEC8 Serial mode register SMR1 R/W H'00 8, 16 H'05FFFEC9 Bit rate register BRR1 R/W H'FF 8, 16 H'05FFFECA Serial control register SCR1 R/W H'00 8, 16 H'05FFFECB Transmit data register TDR1 R/W H'FF 8, 16 H'05FFFECC Serial status register SSR1 R/(W)* H'84 8, 16 H'05FFFECD Receive data register RDR1 R H'00 8, 16 Channel Address* 0 1 1 2 2 Notes: 1. Only the values of bits A27-A24 and A8-A0 are valid; bits A23-A9 are ignored. For details on the register addresses, see section 8.3.5, Area Descriptions. 2. Only 0 can be written, to clear flags. 13.2 Register Descriptions 13.2.1 Receive Shift Register The receive shift register (RSR) receives serial data. Data input at the RxD pin is loaded into RSR in the order received, LSB (bit 0) first. In this way the SCI converts received data to parallel form. When one byte has been received, it is automatically transferred to the receive data register (RDR). The CPU cannot read or write to RSR directly. Bit 7 6 5 4 3 2 1 0 Read/Write -- -- -- -- -- -- -- -- 13.2.2 Receive Data Register The receive data register (RDR) stores serial receive data. The SCI completes the reception of one byte of serial data by moving the received data from the receive shift register (RSR) into RDR for Rev. 7.00 Jan 31, 2006 page 356 of 658 REJ09B0272-0700 Section 13 Serial Communication Interface (SCI) storage. RSR is then ready to receive the next data. This double buffering allows the SCI to receive data continuously. The CPU can read but not write to RDR. RDR is initialized to H'00 by a reset and in standby mode. Bit 7 6 5 4 3 2 1 0 Initial value 0 0 0 0 0 0 0 0 Read/Write R R R R R R R R 13.2.3 Transmit Shift Register The transmit shift register (TSR) transmits serial data. The SCI loads transmit data from the transmit data register (TDR) into TSR, then transmits the data serially from the TxD pin, LSB (bit 0) first. After transmitting one data byte, the SCI automatically loads the next transmit data from TDR into TSR and starts transmitting again. If the TDRE bit in SSR is 1, however, the SCI does not load the TDR contents into TSR. The CPU cannot read or write to TSR directly. Bit 7 6 5 4 3 2 1 0 Read/Write -- -- -- -- -- -- -- -- 13.2.4 Transmit Data Register The transmit data register (TDR) is an eight-bit register that stores data for serial transmission. When the SCI detects that the transmit shift register (TSR) is empty, it moves transmit data written in TDR into TSR and starts serial transmission. Continuous serial transmission is possible by writing the next transmit data in TDR during serial transmission from TSR. The CPU can always read and write to TDR. TDR is initialized to H'FF by a reset and in standby mode. Bit 7 6 5 4 3 2 1 0 Initial value 1 1 1 1 1 1 1 1 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Rev. 7.00 Jan 31, 2006 page 357 of 658 REJ09B0272-0700 Section 13 Serial Communication Interface (SCI) 13.2.5 Serial Mode Register The serial mode register (SMR) is an eight-bit register that specifies the SCI serial communication format and selects the clock source for the baud rate generator. The CPU can always read and write to SMR. SMR is initialized to H'00 by a reset and in standby mode. Bit 7 6 5 4 3 2 1 0 C/A CHR PE O/E STOP MP CKS1 CKS0 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Bit 7--Communication Mode (C/A A): C/A selects whether the SCI operates in asynchronous or synchronous mode. Bit 7: C/A A Description 0 Asynchronous mode 1 Synchronous mode (Initial value) Bit 6--Character Length (CHR): CHR selects seven-bit or eight-bit data in asynchronous mode. In synchronous mode, the data length is always eight bits, regardless of the CHR setting. Bit 6: CHR Description 0 Eight-bit data 1 Seven-bit data. When seven-bit data is selected, the MSB (bit 7) of the transmit data register is not transmitted. (Initial value) Bit 5--Parity Enable (PE): PE selects whether to add a parity bit to transmit data and check the parity of receive data, in asynchronous mode. In synchronous mode, a parity bit is neither added nor checked, regardless of the PE setting. Bit 5: PE Description 0 Parity bit not added or checked 1 Parity bit added and checked. When PE is set to 1, an even or odd parity bit is added to transmit data, depending on the parity mode (O/E) setting. Receive data parity is checked according to the even/odd (O/E) mode setting. Rev. 7.00 Jan 31, 2006 page 358 of 658 REJ09B0272-0700 (Initial value) Section 13 Serial Communication Interface (SCI) Bit 4--Parity Mode (O/E E): O/E selects even or odd parity when parity bits are added and checked. The O/E setting is used only in asynchronous mode and only when the parity enable bit (PE) is set to 1 to enable parity addition and checking. The O/E setting is ignored in synchronous mode, or in asynchronous mode when parity addition and checking is disabled. Bit 4: O/E E Description 0 Even parity (Initial value) If even parity is selected, the parity bit added to transmit data makes an even number of 1s in the transmitted character and parity bit combined. Receive data must have an even number of 1s in the received character and parity bit combined. 1 Odd parity If odd parity is selected, the parity bit added to transmit data makes an odd number of 1s in the transmitted character and parity bit combined. Receive data must have an odd number of 1s in the received character and parity bit combined. Bit 3--Stop Bit Length (STOP): STOP selects one or two bits as the stop bit length in asynchronous mode. This setting is used only in asynchronous mode. It is ignored in synchronous mode because no stop bits are added. In receiving, only the first stop bit is checked, regardless of the STOP bit setting. If the second stop bit is 1, it is treated as a stop bit. If the second stop bit is 0, it is treated as the start bit of the next incoming character. Bit 3: STOP Description 0 One stop bit (Initial value) In transmitting, a single 1-bit is added at the end of each transmitted character. 1 Two stop bits. In transmitting, two 1-bits are added at the end of each transmitted character. Bit 2--Multiprocessor Mode (MP): MP selects multiprocessor format. When multiprocessor format is selected, settings of the parity enable (PE) and parity mode (O/E) bits are ignored. The MP bit setting is used only in asynchronous mode; it is ignored in synchronous mode. For the multiprocessor communication function, see section 13.3.3, Multiprocessor Communication. Bit 2: MP Description 0 Multiprocessor function disabled 1 Multiprocessor format selected (Initial value) Rev. 7.00 Jan 31, 2006 page 359 of 658 REJ09B0272-0700 Section 13 Serial Communication Interface (SCI) Bits 1 and 0--Clock Select 1 and 0 (CKS1 and CKS0): CKS1 and CKS0 select the internal clock source of the on-chip baud rate generator. Four clock sources are available: , /4, /16, and /64. For further information on the clock source, bit rate register settings, and baud rate, see section 13.2.8, Bit Rate Register (BRR). Bit 1: CKS1 Bit 0: CKS0 Description 0 0 System clock () 1 /4 0 /16 1 /64 1 13.2.6 (Initial value) Serial Control Register The serial control register (SCR) enables the SCI transmitter/receiver, selects serial clock output in asynchronous mode, enables and disables interrupts, and selects the transmit/receive clock source. The CPU can always read and write to SCR. SCR is initialized to H'00 by a reset and in standby mode. Bit 7 6 5 4 3 2 1 0 TIE RIE TE RE MPIE TEIE CKE1 CKE0 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Bit 7--Transmit Interrupt Enable (TIE): TIE enables or disables the transmit-data-empty interrupt (TXI) requested when the transmit data register empty bit (TDRE) in the serial status register (SSR) is set to 1 due to transfer of serial transmit data from TDR to TSR. Bit 7: TIE Description 0 Transmit-data-empty interrupt request (TXI) is disabled (Initial value) The TXI interrupt request can be cleared by reading TDRE after it has been set to 1, then clearing TDRE to 0, or by clearing TIE to 0. 1 Transmit-data-empty interrupt request (TXI) is enabled Rev. 7.00 Jan 31, 2006 page 360 of 658 REJ09B0272-0700 Section 13 Serial Communication Interface (SCI) Bit 6--Receive Interrupt Enable (RIE): RIE enables or disables the receive-data-full interrupt (RXI) requested when the receive data register full bit (RDRF) in the serial status register (SSR) is set to 1 due to transfer of serial receive data from RSR to RDR. Also enables or disables receiveerror interrupt (ERI) requests. Bit 6: RIE Description 0 Receive-data-full interrupt (RXI) and receive-error interrupt (ERI) requests are disabled (Initial value) RXI and ERI interrupt requests can be cleared by reading the RDRF flag or error flag (FER, PER, or ORER) after it has been set to 1, then clearing the flag to 0, or by clearing RIE to 0. 1 Receive-data-full interrupt (RXI) and receive-error interrupt (ERI) requests are enabled Bit 5--Transmit Enable (TE): TE enables or disables the SCI transmitter. Bit 5: TE Description 0 Transmitter disabled (Initial value) The transmit data register empty bit (TDRE) in the serial status register (SSR) is fixed at 1. 1 Transmitter enabled. Serial transmission starts when the transmit data register empty (TDRE) bit in the serial status register (SSR) is cleared to 0 after writing transmit data into TDR. Select the transmit format in SMR before setting TE to 1. Bit 4--Receive Enable (RE): RE enables or disables the SCI receiver. Bit 4: RE Description 0 Receiver disabled (Initial value) Clearing RE to 0 does not affect the receive flags (RDRF, FER, PER, ORER). These flags retain their previous values. 1 Receiver enabled. Serial reception starts when a start bit is detected in asynchronous mode, or serial clock input is detected in synchronous mode. Select the receive format in SMR before setting RE to 1. Rev. 7.00 Jan 31, 2006 page 361 of 658 REJ09B0272-0700 Section 13 Serial Communication Interface (SCI) Bit 3--Multiprocessor Interrupt Enable (MPIE): MPIE enables or disables multiprocessor interrupts. The MPIE setting is used only in asynchronous mode, and only if the multiprocessor mode bit (MP) in the serial mode register (SMR) is set to 1 during reception. The MPIE setting is ignored in synchronous mode or when the MP bit is cleared to 0. Bit 3: MPIE Description 0 Multiprocessor interrupts are disabled (normal receive operation) (Initial value) MPE is cleared to 0 when: 1. MPIE is cleared to 0, or 2. Multiprocessor bit (MPB) is set to 1 in receive data. 1 Multiprocessor interrupts are enabled: Receive-data-full interrupt requests (RXI), receive-error interrupt requests (ERI), and setting of the RDRF, FER, and ORER status flags in the serial status register (SSR) are disabled until the multiprocessor bit is set to 1. The SCI does not transfer receive data from RSR to RDR, does not detect receive errors, and does not set the RDRF, FER, and ORER flags in the serial status register (SSR). When it receives data that includes MPB = 1, MPB is set to 1, and the SCI automatically clears MPIE to 0, generates RXI and ERI interrupts (if the TIE and RIE bits in SCR are set to 1), and allows FER and ORER to be set. Bit 2--Transmit-End Interrupt Enable (TEIE): TEIE enables or disables the transmit-end interrupt (TEI) requested if TDR does not contain new transmit data when the MSB is transmitted. Bit 2: TEIE Description 0 Transmit-end interrupt (TEI) requests are disabled (Initial value) The TEI request can be cleared by reading the TDRE bit in the serial status register (SSR) after it has been set to 1, then clearing TDRE to 0; by clearing the transmit end (TEND) bit to 0; or by clearing the TEIE bit to 0. 1 Transmit-end interrupt (TEI) requests are enabled. Bits 1 and 0--Clock Enable 1 and 0 (CKE1 and CKE0): CKE1 and CKE0 select the SCI clock source and enable or disable clock output from the SCK pin. Depending on the combination of CKE1 and CKE0, the SCK pin can be used for general-purpose input/output, serial clock output, or serial clock input. The SCK pin function should be selected in advance with the pin function controller (PFC). The CKE0 setting is valid only in asynchronous mode, and only when the SCI is internally clocked (CKE1 = 0). The CKE0 setting is ignored in synchronous mode, or when an external clock source is selected (CKE1 = 1). Select the SCI operating mode in the serial mode register Rev. 7.00 Jan 31, 2006 page 362 of 658 REJ09B0272-0700 Section 13 Serial Communication Interface (SCI) (SMR) before setting CKE1 and CKE0. For further details on selection of the SCI clock source, see table 13.9 in section 13.3, Operation. Bit 1: CKE1 Bit 0: CKE0 1 Description* 0 0 Asynchronous mode Internal clock, SCK pin used for input pin (input signal 2 is ignored) or output pin (output level is undefined)* (Initial value) Synchronous mode Internal clock, SCK pin used for serial clock output* (Initial value) Asynchronous mode Internal clock, SCK pin used for clock output* Synchronous mode Internal clock, SCK pin used for serial clock output Asynchronous mode External clock, SCK pin used for clock input* Synchronous mode External clock, SCK pin used for serial clock input Asynchronous mode External clock, SCK pin used for clock input* Synchronous mode External clock, SCK pin used for serial clock input 0 1 1 1 0 1 2 3 4 4 Notes: 1. The SCK pin is multiplexed with other functions. Set the pin function controller (PFC) to select the SCK function and SCK input/output for the SCK pin. 2. Initial value 3. The output clock frequency is the same as the bit rate. 4. The input clock frequency is 16 times the bit rate. 13.2.7 Serial Status Register The serial status register (SSR) is an 8-bit register containing multiprocessor bit values, and status flags that indicate the SCI operating status. The CPU can always read and write to SSR, but cannot write 1 in the status flags (TDRE, RDRF, ORER, PER, and FER). These flags can be cleared to 0 only if they have first been read (after being set to 1). Bits 2 (TEND) and 1 (MPB) are read-only bits that cannot be written. SSR is initialized to H'84 by a reset and in standby mode. Bit 7 6 5 4 3 2 1 0 TDRE RDRF ORER FER PER TEND MPB MPBT Initial value 1 0 0 0 0 1 0 0 Read/Write R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R R R/W Note: * Only 0 can be written, to clear the flag. Rev. 7.00 Jan 31, 2006 page 363 of 658 REJ09B0272-0700 Section 13 Serial Communication Interface (SCI) Bit 7--Transmit Data Register Empty (TDRE): TDRE indicates that the SCI has loaded transmit data from TDR into TSR and new serial transmit data can be written in TDR. Bit 7: TDRE Description 0 TDR contains valid transmit data TDRE is cleared to 0 when: 1 * Software reads TDRE after it has been set to 1, then writes 0 in TDRE * The DMAC writes data in TDR TDR does not contain valid transmit data (Initial value) TDRE is set to 1 when: * The chip is reset or enters standby mode * The TE bit in the serial control register (SCR) is cleared to 0 * TDR contents are loaded into TSR, so new data can be written in TDR Bit 6--Receive Data Register Full (RDRF): RDRF indicates that RDR contains received data. Bit 6: RDRF Description 0 RDR does not contain valid received data (Initial value) RDRF is cleared to 0 when: 1 * The chip is reset or enters standby mode * Software reads RDRF after it has been set to 1, then writes 0 in RDRF * The DMAC reads data from RDR RDR contains valid received data. RDRF is set to 1 when serial data is received normally and transferred from RSR to RDR. Note: RDR and RDRF are not affected by detection of receive errors or by clearing of the RE bit to 0 in the serial control register. They retain their previous contents. If RDRF is still set to 1 when reception of the next data ends, an overrun error (ORER) occurs and the received data is lost. Rev. 7.00 Jan 31, 2006 page 364 of 658 REJ09B0272-0700 Section 13 Serial Communication Interface (SCI) Bit 5--Overrun Error (ORER): Indicates that data reception ended abnormally due to an overrun error. Bit 5: ORER Description 0 Receiving is in progress or has ended normally* 1 (Initial value) ORER is cleared to 0 when: 1 * The chip is reset or enters standby mode * Software reads ORER after it has been set to 1, then writes 0 in ORER 2 A receive overrun error occurred* ORER is set to 1 if reception of the next serial data ends when RDRF is set to 1 Notes: 1. Clearing the RE bit to 0 in the serial control register does not affect the ORER bit, which retains its previous value. 2. RDR continues to hold the data received before the overrun error, so subsequent receive data is lost. Serial receiving cannot continue while ORER is set to 1. In synchronous mode, serial transmitting is disabled. Bit 4--Framing Error (FER): FER indicates that data reception ended abnormally due to a framing error in the asynchronous mode. Bit 4: FER Description 0 Receiving is in progress or has ended normally (Initial value) Clearing the RE bit to 0 in the serial control register does not affect the FER bit, which retains its previous value. FER is cleared to 0 when: 1 * The chip is reset or enters standby mode * Software reads FER after it has been set to 1, then writes 0 in FER A receive framing error occurred. When the stop bit length is two bits, only the first bit is checked. The second stop bit is not checked. When a framing error occurs, the SCI transfers the receive data into RDR but does not set RDRF. Serial receiving cannot continue while FER is set to 1. In synchronous mode, serial transmitting is also disabled. FER is set to 1 if the stop bit at the end of receive data is checked and found to be 0. Rev. 7.00 Jan 31, 2006 page 365 of 658 REJ09B0272-0700 Section 13 Serial Communication Interface (SCI) Bit 3--Parity Error (PER): PER indicates that data reception (with parity) ended abnormally due to a parity error in asynchronous mode. Bit 3: PER Description 0 Receiving is in progress or has ended normally (Initial value) Clearing the RE bit to 0 in the serial control register does not affect the PER bit, which retains its previous value. PER is cleared to 0 when: 1 * The chip is reset or enters standby mode * Software reads PER after it has been set to 1, then writes 0 in PER A receive parity error occurred. When a parity error occurs, the SCI transfers the receive data into RDR but does not set RDRF. Serial receiving cannot continue while PER is set to 1. In synchronous mode, serial transmitting is also disabled. PER is set to 1 if the number of 1s in receive data, including the parity bit, does not match the even or odd parity setting of the parity mode bit (O/E) in the serial mode register (SMR). Bit 2--Transmit End (TEND): TEND indicates that when the last bit of a serial character was transmitted, TDR did not contain new transmit data, so transmission has ended. TEND is a readonly bit and cannot be written. Bit 2: TEND Description 0 Transmission is in progress TEND is cleared to 0 when: 1 * Software reads TDRE after it has been set to 1, then writes 0 in TDRE * The DMAC writes data in TDR End of transmission (Initial value) TEND is set to 1 when: * The chip is reset or enters standby mode * TE is cleared to 0 in the serial control register (SCR) * TDRE is 1 when the last bit of a one-byte serial character is transmitted Rev. 7.00 Jan 31, 2006 page 366 of 658 REJ09B0272-0700 Section 13 Serial Communication Interface (SCI) Bit 1--Multiprocessor Bit (MPB): MPB stores the value of the multiprocessor bit in receive data when a multiprocessor format is selected for receiving in asynchronous mode. The MPB is a readonly bit and cannot be written. Bit 1: MPB Description 0 Multiprocessor bit value in receive data is 0 (Initial value) If RE is cleared to 0 when a multiprocessor format is selected, MPB retains its previous value. 1 Multiprocessor bit value in receive data is 1 Bit 0--Multiprocessor Bit Transfer (MPBT): MPBT stores the value of the multiprocessor bit added to transmit data when a multiprocessor format is selected for transmitting in asynchronous mode. The MPBT setting is ignored in synchronous mode, when a multiprocessor format is not selected, or when the SCI is not transmitting. Bit 0: MPBT Description 0 Multiprocessor bit value in transmit data is 0 1 Multiprocessor bit value in transmit data is 1 13.2.8 (Initial value) Bit Rate Register (BRR) The bit rate register (BRR) is an eight-bit register that, together with the baud rate generator clock source selected by the CKS1 and CKS0 bits in the serial mode register (SMR), determines the serial transmit/receive bit rate. The CPU can always read and write to BRR. BRR is initialized to H'FF by a reset and in standby mode. SCI0 and SCI1 have independent baud rate generator control, so different values can be set in the two channels. Bit 7 6 5 4 3 2 1 0 Initial value 1 1 1 1 1 1 1 1 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Table 13.3 shows examples of BRR settings in asynchronous mode; table 13.4 shows examples of BBR settings in synchronous mode. Rev. 7.00 Jan 31, 2006 page 367 of 658 REJ09B0272-0700 Section 13 Serial Communication Interface (SCI) Table 13.3 Bit Rates and BRR Settings in Asynchronous Mode (MHz) 2 2.097152 Bit Rate (bits/s) n N Error (%) n N Error (%) 110 1 141 0.03 1 148 -0.04 150 1 103 0.16 1 108 0.21 300 0 207 0.16 0 217 0.21 600 0 103 0.16 0 108 0.21 1200 0 51 0.16 0 54 -0.70 2400 0 25 0.16 0 26 1.14 4800 0 12 0.16 0 13 -2.48 9600 -- -- -- 0 6 -2.48 19200 -- -- -- -- -- -- 31250 0 1 0.00 -- -- -- 38400 -- -- -- -- -- -- (MHz) 2.4576 3 3.6864 Bit Rate (bits/s) n N Error (%) n N Error (%) n N Error (%) 110 1 174 -0.26 1 212 0.03 2 64 0.70 150 1 127 0.00 1 155 0.16 1 191 0.00 300 0 255 0.00 1 77 0.16 1 95 0.00 600 0 127 0.00 0 155 0.16 0 191 0.00 1200 0 63 0.00 0 77 0.16 0 95 0.00 2400 0 31 0.00 0 38 0.16 0 47 0.00 4800 0 15 0.00 0 19 -2.34 0 23 0.00 9600 0 7 0.00 0 9 -2.34 0 11 0.00 19200 0 3 0.00 0 4 -2.34 0 5 0.00 31250 -- -- -- 0 2 0.00 -- -- -- 38400 0 1 0.00 -- -- -- 0 2 0.00 Rev. 7.00 Jan 31, 2006 page 368 of 658 REJ09B0272-0700 Section 13 Serial Communication Interface (SCI) (MHz) 4 4.9152 5 Bit Rate (bits/s) n N Error (%) n N Error (%) n N Error (%) 110 2 70 0.03 2 86 0.31 2 88 -0.25 150 1 207 0.16 1 255 0.00 2 64 0.16 300 1 103 0.16 1 127 0.00 1 129 0.16 600 0 207 0.16 0 255 0.00 1 64 0.16 1200 0 103 0.16 0 127 0.00 0 129 0.16 2400 0 51 0.16 0 63 0.00 0 64 0.16 4800 0 25 0.16 0 31 0.00 0 32 -1.36 9600 0 12 0.16 0 15 0.00 0 15 1.73 19200 -- -- -- 0 7 0.00 0 7 1.73 31250 0 3 0.00 0 4 -1.70 0 4 0.00 38400 -- -- -- 0 3 0.00 0 3 1.73 (MHz) 6 6.144 7.3728 Bit Rate (bits/s) n N Error (%) n N Error (%) n N Error (%) 110 2 106 -0.44 2 108 0.08 2 130 -0.07 150 2 77 0.16 2 79 0.00 2 95 0.00 300 1 155 0.16 1 159 0.00 1 191 0.00 600 1 77 0.16 1 79 0.00 1 95 0.00 1200 0 155 0.16 0 159 0.00 0 191 0.00 2400 0 77 0.16 0 79 0.00 0 95 0.00 4800 0 38 0.16 0 39 0.00 0 47 0.00 9600 0 19 -2.34 0 19 0.00 0 23 0.00 19200 0 9 -2.34 0 9 0.00 0 11 0.00 31250 0 5 0.00 0 5 2.40 -- -- -- 38400 0 4 -2.34 0 4 0.00 0 5 0.00 Rev. 7.00 Jan 31, 2006 page 369 of 658 REJ09B0272-0700 Section 13 Serial Communication Interface (SCI) (MHz) 8 9.8304 10 12 Bit Rate (bits/s) n N Error (%) n N Error (%) n N Error (%) n N Error (%) 110 2 141 0.03 2 174 -0.26 2 177 -0.25 2 212 0.03 150 2 103 0.16 2 127 0.00 2 129 0.16 2 155 0.16 300 1 207 0.16 1 255 0.00 2 64 0.16 2 77 0.16 600 1 103 0.16 1 127 0.00 1 129 0.16 1 155 0.16 1200 0 207 0.16 0 255 0.00 1 64 0.16 1 77 0.16 2400 0 103 0.16 0 127 0.00 0 129 0.16 0 155 0.16 4800 0 51 0.16 0 63 0.00 0 64 0.16 0 77 0.16 9600 0 25 0.16 0 31 0.00 0 32 -1.36 0 38 0.16 19200 0 12 0.16 0 15 0.00 0 15 1.73 0 19 -2.34 31250 0 7 0.00 0 9 -1.70 0 9 0.00 0 11 0.00 38400 -- -- -- 0 7 0.00 0 7 1.73 0 9 -2.34 (MHz) 12.288 14 14.7456 16 Bit Rate (bits/s) n N Error (%) n N Error (%) n N Error (%) n N Error (%) 110 2 217 0.08 2 248 -0.17 3 64 0.70 3 70 0.03 150 2 159 0.00 2 181 0.16 2 191 0.00 2 207 0.16 300 2 79 0.00 2 90 0.16 2 95 0.00 2 103 0.16 600 1 159 0.00 1 181 0.16 1 191 0.00 1 207 0.16 1200 1 79 0.00 1 90 0.16 1 95 0.00 1 103 0.16 2400 0 159 0.00 0 181 0.16 0 191 0.00 0 207 0.16 4800 0 79 0.00 0 90 0.16 0 95 0.00 0 103 0.16 9600 0 39 0.00 0 45 -0.93 0 47 0.00 0 51 0.16 19200 0 19 0.00 0 22 -0.93 0 23 0.00 0 25 0.16 31250 0 11 2.40 0 13 0.00 0 14 -1.70 0 15 0.00 38400 0 9 0.00 -- -- -- 0 11 0.00 0 12 0.16 Rev. 7.00 Jan 31, 2006 page 370 of 658 REJ09B0272-0700 Section 13 Serial Communication Interface (SCI) (MHz) 17.2032 Bit Rate (bits/s) n N 18 Error (%) n N 19.6608 Error (%) n N Error (%) 20 n N Error (%) 110 3 75 0.48 3 79 -0.12 3 86 0.31 3 88 -0.25 150 2 223 0.00 2 233 0.16 2 255 0.00 3 64 0.16 300 2 111 0.00 2 116 0.16 2 127 0.00 2 129 0.16 600 1 223 0.00 1 233 0.16 1 255 0.00 2 64 0.16 1200 1 111 0.00 1 116 0.16 1 127 0.00 1 129 0.16 2400 0 223 0.00 0 233 0.16 0 255 0.00 1 64 0.16 4800 0 111 0.00 0 116 0.16 0 127 0.00 0 129 0.16 9600 0 55 0.00 0 58 -0.69 0 63 0.00 0 64 0.16 19200 0 27 0.00 0 28 1.02 0 31 0.00 0 32 -1.36 31250 0 16 1.20 0 17 0.00 0 19 -1.70 0 19 0.00 38400 0 13 0.00 0 14 -2.34 0 15 0.00 0 15 1.73 Note: Settings with an error of 1% or less are recommended. Rev. 7.00 Jan 31, 2006 page 371 of 658 REJ09B0272-0700 Section 13 Serial Communication Interface (SCI) Table 13.4 Bit Rates and BRR Settings in Synchronous Mode (MHz) 2 4 8 10 16 20 Bit Rate (bits/s) n N n N n N n N n N n N 110 3 70 -- -- -- -- -- -- -- -- -- -- 250 2 124 2 249 3 124 -- -- 3 249 -- -- 500 1 249 2 124 2 249 -- -- 3 124 -- -- 1k 1 124 1 249 2 124 -- -- 2 249 -- -- 2.5k 0 199 1 99 1 199 1 249 2 99 2 124 5k 0 99 0 199 1 99 1 124 1 199 1 249 10k 0 49 0 99 0 199 0 249 1 99 1 124 25k 0 19 0 39 0 79 0 99 0 159 0 199 50k 0 9 0 19 0 39 0 49 0 79 0 99 100k 0 4 0 9 0 19 0 24 0 39 0 49 250k 0 1 0 3 0 7 0 9 0 15 0 19 500k 0 0* 0 1 0 3 0 4 0 7 0 9 0 0* 0 1 -- -- 0 3 0 4 0 0* 1M 2.5M -- -- 5M Blank: No setting available --: Setting possible, but error occurs *: Continuous transmission/reception not possible The BRR setting is calculated as follows: Asynchronous mode N = [/(64 x 22n - 1 x B)] x 106 - 1 Synchronous mode N = [/(8 x 22n - 1 x B)] x 106 - 1 B: Bit rate (bits/s) N: BRR setting for baud rate generator (0 N 255) : frequency (MHz) n: Baud rate generator clock source (n = 0, 1, 2, 3) For the clock sources and values of n, see following table. Rev. 7.00 Jan 31, 2006 page 372 of 658 REJ09B0272-0700 -- -- 0 1 -- -- 0 0* Section 13 Serial Communication Interface (SCI) SMR Settings n Clock Source CKS1 CKS0 0 0 0 1 /4 0 1 2 /16 1 0 3 /64 1 1 The bit rate error for asynchronous mode is given by the following formula: Error (%) = {( x 106)/[(N + 1) x B x 64 x 22n - 1] - 1 } x 100 Rev. 7.00 Jan 31, 2006 page 373 of 658 REJ09B0272-0700 Section 13 Serial Communication Interface (SCI) Table 13.5 indicates the maximum bit rates in asynchronous mode when the baud rate generator is used. Tables 13.6 and 13.7 show the maximum rates for external clock input. Table 13.5 Maximum Bit Rates for Various Frequencies with Baud Rate Generator (Asynchronous Mode) Settings (MHz) Maximum Bit Rate (bits/s) n N 2 62500 0 0 2.097152 65536 0 0 2.4576 76800 0 0 3 93750 0 0 3.6864 115200 0 0 4 125000 0 0 4.9152 153600 0 0 5 156250 0 0 6 187500 0 0 6.144 192000 0 0 7.3728 230400 0 0 8 250000 0 0 9.8304 307200 0 0 10 312500 0 0 12 375000 0 0 12.288 384000 0 0 14 437500 0 0 14.7456 460800 0 0 16 500000 0 0 17.2032 537600 0 0 18 562500 0 0 19.6608 614400 0 0 20 625000 0 0 Rev. 7.00 Jan 31, 2006 page 374 of 658 REJ09B0272-0700 Section 13 Serial Communication Interface (SCI) Table 13.6 Maximum Bit Rates with External Clock Input (Asynchronous Mode) (MHz) External Input Clock (MHz) Maximum Bit Rate (bits/s) 2 0.5000 31250 2.097152 0.5243 32768 2.4576 0.6144 38400 3 0.7500 46875 3.6864 0.9216 57600 4 1.0000 62500 4.9152 1.2288 76800 5 1.2500 78125 6 1.5000 93750 6.144 1.5360 96000 7.3728 1.8432 115200 8 2.0000 125000 9.8304 2.4576 153600 10 2.5000 156250 12 3.0000 187500 12.288 3.0720 192000 14 3.5000 218750 14.7456 3.6834 230400 16 4.0000 250000 17.2032 4.3008 268800 18 4.5000 281250 19.6608 4.9152 307200 20 5.0000 312500 Rev. 7.00 Jan 31, 2006 page 375 of 658 REJ09B0272-0700 Section 13 Serial Communication Interface (SCI) Table 13.7 Maximum Bit Rates with External Clock Input (Synchronous Mode) (MHz) External Input Clock (MHz) Maximum Bit Rate (bits/s) 2 0.3333 333333.3 4 0.6667 666666.7 6 1.0000 1000000.0 8 1.3333 1333333.3 10 1.6667 1666666.7 12 2.0000 2000000.0 14 2.3333 2333333.3 16 2.6667 2666666.7 18 3.0000 3000000.0 20 3.3333 3333333.3 13.3 Operation 13.3.1 Overview The SCI has an asynchronous mode in which characters are synchronized individually, and a synchronous mode in which communication is synchronized with clock pulses. Serial communication is possible in either mode. Asynchronous/synchronous mode and the communication format are selected in the serial mode register (SMR), as shown in table 13.8. The SCI clock source is selected by the C/A bit in the serial mode register (SMR) and the CKE1 and CKE0 bits in the serial control register (SCR), as shown in table 13.9. Asynchronous Mode: * Data length is selectable: seven or eight bits. * Parity and multiprocessor bits are selectable, and so is the stop bit length (one or two bits). The preceding selections constitute the communication format and character length. * In receiving, it is possible to detect framing errors (FER), parity errors (PER), overrun errors (ORER), and the break state. * An internal or external clock can be selected as the SCI clock source. When an internal clock is selected, the SCI operates using the on-chip baud rate generator, and can output a serial clock signal with a frequency matching the bit rate. When an external clock is selected, the external clock input must have a frequency 16 times the bit rate. (The on-chip baud rate generator is not used.) Rev. 7.00 Jan 31, 2006 page 376 of 658 REJ09B0272-0700 Section 13 Serial Communication Interface (SCI) Synchronous Mode: * The communication format has a fixed eight-bit data length. * In receiving, it is possible to detect overrun errors (ORER). * An internal or external clock can be selected as the SCI clock source. When an internal clock is selected, the SCI operates using the on-chip baud rate generator, and outputs a serial clock signal to external devices. When an external clock is selected, the SCI operates on the input serial clock. The on-chip baud rate generator is not used. Table 13.8 Serial Mode Register Settings and SCI Communication Formats SMR Settings SCI Communication Format Mode Bit 7: Bit 6: Bit 5: Bit 2: Bit 3: C/A CHR PE MP STOP Data Length Parity Bit Multipro- Stop Bit cessor Bit Length Asynchronous 0 8-bit Absent Absent 0 0 0 0 1 1 2 bits 0 Present 1 bit 1 1 0 0 2 bits 7-bit Absent 1 bit 1 1 2 bits 0 Present 1 bit 1 Asynchronous (multiprocesso r format) 0 1 * 1 * 1 * 0 1 * * 2 bits 8-bit Absent Present * * 1 bit 2 bits 7-bit 1 bit 1 * Synchronous 0 1 bit 2 bits 8-bit Absent None Note: Asterisks (*) in the table indicate don't-care bits. Rev. 7.00 Jan 31, 2006 page 377 of 658 REJ09B0272-0700 Section 13 Serial Communication Interface (SCI) Table 13.9 SMR and SCR Settings and SCI Clock Source Selection SMR Mode Asynchronous mode SCR Settings SCI Transmit/Receive Clock Bit 7: C/A A Bit 1: CKE1 Bit 0: CKE0 Clock Source SCK Pin Function* 0 0 0 Internal SCI does not use the SCK pin 1 1 0 Outputs a clock with frequency matching the bit rate External Inputs a clock with frequency 16 times the bit rate Internal Outputs the serial clock External Inputs the serial clock 1 Synchronous mode 1 0 0 1 1 0 1 Note: * Select the function in combination with the pin function controller (PFC). 13.3.2 Operation in Asynchronous Mode In asynchronous mode, each transmitted or received character begins with a start bit and ends with a stop bit. Serial communication is synchronized one character at a time. The transmitting and receiving sections of the SCI are independent, so full duplex communication is possible. The transmitter and receiver are both double buffered, so data can be written and read while transmitting and receiving are in progress, enabling continuous transmitting and receiving. Figure 13.2 shows the general format of asynchronous serial communication. In asynchronous serial communication, the communication line is normally held in the mark (high) state. The SCI monitors the line and starts serial communication when the line goes to the space (low) state, indicating a start bit. One serial character consists of a start bit (low), data (LSB first), parity bit (high or low), and stop bit (high), in that order. When receiving in asynchronous mode, the SCI synchronizes on the falling edge of the start bit. The SCI samples each data bit on the eighth pulse of a clock with a frequency 16 times the bit rate. Receive data is latched at the center of each bit. Rev. 7.00 Jan 31, 2006 page 378 of 658 REJ09B0272-0700 Section 13 Serial Communication Interface (SCI) 1 Serial data (LSB) 0 D0 (MSB) D1 D2 D3 D4 D5 Start bit D6 D7 Idle (mark) state 1 0/1 1 1 Parity bit Stop bit 1 or no bit 1 or 2 bits Transmit/receive data 1 bit 7 or 8 bits One unit of communication (character or frame) Figure 13.2 Data Format in Asynchronous Communication (Example: 8-Bit Data with Parity and Two Stop Bits) Rev. 7.00 Jan 31, 2006 page 379 of 658 REJ09B0272-0700 Section 13 Serial Communication Interface (SCI) Transmit/Receive Formats: Table 13.10 shows the 12 communication formats that can be selected in asynchronous mode. The format is selected by settings in the serial mode register (SMR). Table 13.10 Serial Communication Formats (Asynchronous Mode) SMR Bits CHR PE MP STOP 1 2 3 4 5 6 7 8 9 10 11 12 0 0 0 0 START 8-bit data STOP 0 0 0 1 START 8-bit data STOP STOP 0 1 0 0 START 8-bit data P STOP 0 1 0 1 START 8-bit data P STOP STOP 1 0 0 0 START 7-bit data STOP 1 0 0 1 START 7-bit data STOP STOP 1 1 0 0 START 7-bit data P STOP 1 1 0 1 START 7-bit data P STOP STOP 0 -- 1 0 START 8-bit data MPB STOP 0 -- 1 1 START 8-bit data MPB STOP STOP 1 -- 1 0 START 7-bit data MPB STOP 1 -- 1 1 START 7-bit data MPB STOP STOP --: Don't care bits. Notes: START: Start bit STOP: Stop bit P: Parity bit MPB: Multiprocessor bit Clock: An internal clock generated by the on-chip baud rate generator or an external clock input from the SCK pin can be selected as the SCI transmit/receive clock. The clock source is selected by the C/A bit in the serial mode register (SMR) and bits CKE1 and CKE0 in the serial control register (SCR) (table 13.9). When an external clock is input at the SCK pin, it must have a frequency equal to 16 times the desired bit rate. Rev. 7.00 Jan 31, 2006 page 380 of 658 REJ09B0272-0700 Section 13 Serial Communication Interface (SCI) When the SCI operates on an internal clock, it can output a clock signal at the SCK pin. The frequency of this output clock is equal to the bit rate. The phase is aligned as in figure 13.3 so that the rising edge of the clock occurs at the center of each transmit data bit. 0 D0 D1 D2 D3 D4 D5 D6 D7 0/1 1 1 1 frame Figure 13.3 Phase Relationship Between Output Clock and Serial Data (Asynchronous Mode) Transmitting and Receiving Data (SCI initialization (Asynchronous Mode)): Before transmitting or receiving, software must clear the TE and RE bits to 0 in the serial control register (SCR), then initialize the SCI as follows. When changing the communication mode or format, always clear the TE and RE bits to 0 before following the procedure given below. Clearing TE to 0 sets TDRE to 1 and initializes the transmit shift register (TSR). Clearing RE to 0, however, does not initialize the RDRF, PER, FER, and ORER flags and receive data register (RDR), which retain their previous contents. When an external clock is used, the clock should not be stopped during initialization or subsequent operation. SCI operation becomes unreliable if the clock is stopped. Figure 13.4 shows a sample flowchart for initializing the SCI. The procedure for initializing the SCI is as follows: 1. Select the communication format in the serial mode register (SMR). 2. Write the value corresponding to the bit rate in the bit rate register (BRR) unless an external clock is used. 3. Select the clock source in the serial control register (SCR). Leave RIE, TIE, TEIE, MPIE, TE, and RE cleared to 0. If clock output is selected in asynchronous mode, clock output starts immediately after the setting is made in SCR. 4. Wait for at least the interval required to transmit or receive one bit, then set TE or RE in the serial control register (SCR) to 1. Also set RIE, TIE, TEIE, and MPIE as necessary. Setting TE or RE enables the SCI to use the TxD or RxD pin. The initial states are the mark transmit state, and the idle receive state (waiting for a start bit). Rev. 7.00 Jan 31, 2006 page 381 of 658 REJ09B0272-0700 Section 13 Serial Communication Interface (SCI) Start of initialization Clear TE and RE bits to 0 in SCR Select communication format in SMR (1) Set value in BRR (2) Set CKE1 and CKE0 bits in SCR (leaving TE and RE cleared to 0) (3) Wait 1-bit interval elapsed? No Yes Set TE or RE to 1 in SCR; Set RIE, TIE, TEIE, and MPIE as necessary (4) End Figure 13.4 Sample Flowchart for SCI Initialization Transmitting Serial Data (Asynchronous Mode): Figure 13.5 shows a sample flowchart for transmitting serial data. The procedure for transmitting serial data is as follows: 1. SCI initialization: select the TxD pin function with the PFC. 2. SCI status check and transmit data write: read the serial status register (SSR), check that the TDRE bit is 1, then write transmit data in the transmit data register (TDR) and clear TDRE to 0. 3. To continue transmitting serial data: read the TDRE bit to check whether it is safe to write (1); if so, write data in TDR, then clear TDRE to 0. When the DMAC is started by a transmit-dataempty interrupt request (TXI) to write data in TDR, the TDRE bit is checked and cleared automatically. 4. To output a break signal at the end of serial transmission: set the DR bit to 0, then clear TE to 0 in SCR and set the TxD pin function as output port with the PFC. Rev. 7.00 Jan 31, 2006 page 382 of 658 REJ09B0272-0700 Section 13 Serial Communication Interface (SCI) Initialize (1) Start transmitting Read TDRE bit in SSR (2) No TDRE = 1? Yes Write transmit data in TDR and clear TDRE bit to 0 in SSR (3) All data transmitted? No Yes Read TEND bit in SSR No TEND = 1? Yes No Output break signal? (4) Yes Set DR = 0 Clear TE bit of SCR to 0; Select theTxD pin function as an output port with the PFC Transmission ends Figure 13.5 Sample Flowchart for Transmitting Serial Data Rev. 7.00 Jan 31, 2006 page 383 of 658 REJ09B0272-0700 Section 13 Serial Communication Interface (SCI) In transmitting serial data, the SCI operates as follows: 1. The SCI monitors the TDRE bit in SSR. When TDRE is cleared to 0, the SCI recognizes that the transmit data register (TDR) contains new data, and loads this data from TDR into the transmit shift register (TSR). 2. After loading the data from TDR into TSR, the SCI sets the TDRE bit to 1 and starts transmitting. If the transmit-data-empty interrupt enable bit (TIE) is set to 1 in SCR, the SCI requests a transmit-data-empty interrupt (TXI) at this time. Serial transmit data is transmitted in the following order from the TxD pin: a. Start bit: one 0 bit is output. b. Transmit data: seven or eight bits of data are output, LSB first. c. Parity bit or multiprocessor bit: one parity bit (even or odd parity) or one multiprocessor bit is output. Formats in which neither a parity bit nor a multiprocessor bit is output can also be selected. d. Stop bit: one or two 1-bits (stop bits) are output. e. Mark state: output of 1-bits continues until the start bit of the next transmit data. 3. The SCI checks the TDRE bit when it outputs the stop bit. If TDRE is 0, the SCI loads new data from TDR into TSR, outputs the stop bit, then begins serial transmission of the next frame. If TDRE is 1, the SCI sets the TEND bit to 1 in SSR, outputs the stop bit, then continues output of 1-bits in the mark state. If the transmit-end interrupt enable bit (TEIE) in SCR is set to 1, a transmit-end interrupt (TEI) is requested. Figure 13.6 shows an example of SCI transmit operation in asynchronous mode. Rev. 7.00 Jan 31, 2006 page 384 of 658 REJ09B0272-0700 Section 13 Serial Communication Interface (SCI) 1 Serial data Start bit 0 Parity Stop Start bit bit bit Data D0 D1 D7 0/1 1 0 Parity Stop bit bit Data D0 D1 D7 0/1 1 1 Idle (mark) state TDRE TEND TXI TXI interrupt request handler writes data in TDR and clears TDRE to 0 TXI request TEI request 1 frame Figure 13.6 Example of SCI Transmit Operation in Asynchronous Mode (8-Bit Data with Parity and One Stop Bit) Receiving Serial Data (Asynchronous Mode): Figure 13.7 shows a sample flowchart for receiving serial data. The procedure for receiving serial data is listed below. 1. SCI initialization: select the RxD pin function with the PFC. 2. Receive error handling and break detection: if a receive error occurs, read the ORER, PER and FER bits in SSR to identify the error. After executing the necessary error handling, clear ORER, PER, and FER all to 0. Receiving cannot resume if ORER, PER, or FER remains set to 1. When a framing error occurs, the RxD pin can be read to detect the break state. 3. SCI status check and receive data read: read the serial status register (SR), check that RDRF is set to 1, then read receive data from the receive data register (RDR) and clear RDRF to 0. The RXI interrupt can also be used to determine if the RDRF bit has changed from 0 to 1. 4. To continue receiving serial data: read RDRF and RDR, and clear RDRF to 0 before the stop bit of the current frame is received. If the DMAC is started by a receive-data-full interrupt (RXI) to read RDR, the RDRF bit is cleared automatically, so this step is unnecessary. Rev. 7.00 Jan 31, 2006 page 385 of 658 REJ09B0272-0700 Section 13 Serial Communication Interface (SCI) Initialization (1) Start receiving Read the ORER, PER, and FER bits in SSR PER, FER, ORER = 1? Yes (2) No Read the RDRF bit in SSR No Error handling (3) RDRF = 1? Yes Read the RDR's receive data and (4) clear the RDRF bit in SSR to 0 No Total count received? Yes Clear the RE bit in SCR to 0 Reception ends Figure 13.7 Sample Flowchart for Receiving Serial Data Rev. 7.00 Jan 31, 2006 page 386 of 658 REJ09B0272-0700 Section 13 Serial Communication Interface (SCI) Start of error handling No ORER = 1? Yes Overrun error handling No FER = 1? Yes Break? Yes No Framing error handling No Clear RE bit to 0 in SCR PER = 1? Yes Parity error handling Clear ORER, PER, and FER to 0 in SSR End Figure 13.7 Sample Flowchart for Receiving Serial Data (cont) Rev. 7.00 Jan 31, 2006 page 387 of 658 REJ09B0272-0700 Section 13 Serial Communication Interface (SCI) In receiving, the SCI operates as follows: 1. The SCI monitors the receive data line. When it detects a start bit (0), the SCI synchronizes internally and starts receiving. 2. Receive data is shifted into RSR in order from the LSB to the MSB. 3. The parity bit and stop bit are received. After receiving these bits, the SCI makes the following checks: a. Parity check: The number of 1s in the receive data must match the even or odd parity setting of the O/E bit in SMR. b. Stop bit check: The stop bit value must be 1. If there are two stop bits, only the first stop bit is checked. c. Status check: RDRF must be 0 so that receive data can be loaded from RSR into RDR. If these checks all pass, the SCI sets RDRF to 1 and stores the received data in RDR. If one of the checks fails (receive error), the SCI operates as indicated in table 13.11. Note: 2. When a receive error flag is set, further receiving is disabled. The RDRF bit is not set to 1. Be sure to clear the error flags. After setting RDRF to 1, if the receive-data-full interrupt enable bit (RIE) is set to 1 in SCR, the SCI requests a receive-data-full interrupt (RXI). If one of the error flags (ORER, PER, or FER) is set to 1 and the receive-data-full interrupt enable bit (RIE) in SCR is also set to 1, the SCI requests a receive-error interrupt (ERI). Figure 13.8 shows an example of SCI receive operation in asynchronous mode. Table 13.11 Receive Error Conditions and SCI Operation Receive Error Abbreviation Condition Data Transfer Overrun error ORER Receiving of next data ends while RDRF is still set to 1 in SSR Receive data not loaded from RSR into RDR Framing error FER Stop bit is 0 Receive data loaded from RSR into RDR Parity error PER Parity of receive data differs from even/odd parity setting in SMR Receive data loaded from RSR into RDR Rev. 7.00 Jan 31, 2006 page 388 of 658 REJ09B0272-0700 Section 13 Serial Communication Interface (SCI) 1 Serial data Start bit 0 Parity Stop Start bit bit bit Data D0 D1 D7 1 0/1 0 Parity Stop bit bit Data D0 D1 D7 0/1 0 1 Idle (mark) state TDRE RXI request FER 1 frame RXI interrupt handler reads data in RDR and clears RDRF to 0 Framing error, ERI request Figure 13.8 Example of SCI Receive Operation (8-Bit Data with Parity and One Stop Bit) 13.3.3 Multiprocessor Communication The multiprocessor communication function enables several processors to share a single serial communication line. The processors communicate in asynchronous mode using a format with an additional multiprocessor bit (multiprocessor format). In multiprocessor communication, each receiving processor is addressed by a unique ID. A serial communication cycle consists of an ID-sending cycle that identifies the receiving processor, and a data-sending cycle. The multiprocessor bit distinguishes ID-sending cycles from data-sending cycles. The transmitting processor starts by sending the ID of the receiving processor with which it wants to communicate as data with the multiprocessor bit set to 1. Next the transmitting processor sends transmit data with the multiprocessor bit cleared to 0. Receiving processors skip incoming data until they receive data with the multiprocessor bit set to 1. When they receive data with the multiprocessor bit set to 1, receiving processors compare the data with their IDs. The receiving processor with a matching ID continues to receive further incoming data. Processors with IDs not matching the received data skip further incoming data until they again receive data with the multiprocessor bit set to 1. Multiple processors can send and receive data in this way. Figure 13.9 shows an example of communication between processors using the multiprocessor format. Rev. 7.00 Jan 31, 2006 page 389 of 658 REJ09B0272-0700 Section 13 Serial Communication Interface (SCI) Transmitting processor Serial communication line Receiving processor A Receiving processor B Receiving processor C Receiving processor D (ID = 01) (ID = 02) (ID = 03) (ID = 04) Serial data H'01 H'AA (MPB = 1) ID-sending cycle: receiving processor address (MPB = 0) Data-sending cycle: data sent to receiving processor specified by ID MPB: multiprocessor bit Figure 13.9 Example of Communication between Processors Using Multiprocessor Format (Sending Data H'AA to Receiving Processor A) Communication Formats: Four formats are available. Parity-bit settings are ignored when a multiprocessor format is selected. For details see table 13.8. Clock: See the description in the asynchronous mode section. Transmitting Multiprocessor Serial Data: Figure 13.10 shows a sample flowchart for transmitting multiprocessor serial data. The procedure for transmitting multiprocessor serial data is listed below. 1. SCI initialization: select the TxD pin function with the PFC. 2. SCI status check and transmit data write: read the serial status register (SSR), check that the TDRE bit is 1, then write transmit data in the transmit data register (TDR). Also set MPBT (multiprocessor bit transfer) to 0 or 1 in SSR. Finally, clear TDRE to 0. 3. To continue transmitting serial data: read the TDRE bit to check whether it is safe to write (1); if so, write data in TDR, then clear TDRE to 0. When the DMAC is started by a transmit-dataempty interrupt request (TXI) to write data in TDR, the TDRE bit is checked and cleared automatically. 4. To output a break signal at the end of serial transmission: set the DR bit to 0 (I/O data port register), then clear TE to 0 in SCR and set the TxD pin function as output port with the PFC. Rev. 7.00 Jan 31, 2006 page 390 of 658 REJ09B0272-0700 Section 13 Serial Communication Interface (SCI) Initialize (1) Start transmitting Read TDRE bit in SSR (2) No TDRE = 1? Yes Write transmit data in TDR and set MPBT in SSR Clear TDRE bit to 0 No All data transmitted? (3) Yes Read TEND bit in SSR No TEND = 1? Yes No Output break signal? (4) Yes Set DR = 0 Clear TE bit to 0 in SCR; select theTxD pin function as an output port with the PFC End Figure 13.10 Sample Flowchart for Transmitting Multiprocessor Serial Data Rev. 7.00 Jan 31, 2006 page 391 of 658 REJ09B0272-0700 Section 13 Serial Communication Interface (SCI) In transmitting serial data, the SCI operates as follows: 1. The SCI monitors the TDRE bit in SSR. When TDRE is cleared to 0 the SCI recognizes that the transmit data register (TDR) contains new data, and loads this data from TDR into the transmit shift register (TSR). 2. After loading the data from TDR into TSR, the SCI sets the TDRE bit to 1 and starts transmitting. If the transmit-data-empty interrupt enable bit (TIE) in SCR is set to 1, the SCI requests a transmit-data-empty interrupt (TXI) at this time. Serial transmit data is transmitted in the following order from the TxD pin (figure 13.11): a. Start bit: one 0 bit is output. b. Transmit data: seven or eight bits are output, LSB first. c. Multiprocessor bit: one multiprocessor bit (MPBT value) is output. d. Stop bit: one or two 1-bits (stop bits) are output. e. Mark state: output of 1-bits continues until the start bit of the next transmit data. 3. The SCI checks the TDRE bit when it outputs the stop bit. If TDRE is 0, the SCI loads data from TDR into TSR, outputs the stop bit, then begins serial transmission of the next frame. If TDRE is 1, the SCI sets the TEND bit in SSR to 1, outputs the stop bit, then continues output of 1-bits in the mark state. If the transmit-end interrupt enable bit (TEIE) in SCR is set to 1, a transmit-end interrupt (TEI) is requested at this time. 1 Serial data Start bit 0 Multiprocessor Stop Start bit bit bit Data D0 D1 D7 0/1 1 0 D0 Multiprocessor Stop 1 Data bit bit D1 D7 0/1 1 Idle (mark) state TDRE TEND TXI TXI interrupt request handler writes data in TDR and clears TDRE to 0 TXI request TEI request 1 frame Figure 13.11 Example of SCI Multiprocessor Transmit Operation (8-Bit Data with Multiprocessor Bit and One Stop Bit) Rev. 7.00 Jan 31, 2006 page 392 of 658 REJ09B0272-0700 Section 13 Serial Communication Interface (SCI) Receiving Multiprocessor Serial Data: Figure 13.12 shows a sample flowchart for receiving multiprocessor serial data. The procedure for receiving multiprocessor serial data is listed below. 1. SCI initialization: select the RxD pin function with the PFC. 2. ID receive cycle: set the MPIE bit in the serial control register (SCR) to 1. 3. SCI status check and compare to ID reception: read the serial status register (SSR), check that RDRF is set to 1, then read data from the receive data register (RDR) and compare with the processor's own ID. If the ID does not match the receive data, set MPIE to 1 again and clear RDRF to 0. If the ID matches the receive data, clear RDRF to 0. 4. Receive error handling and break detection: if a receive error occurs, read the ORER and FER bits in SSR to identify the error. After executing the necessary error handling, clear both ORER and FER to 0. Receiving cannot resume if ORER or FER remain set to 1. When a framing error occurs, the RxD pin can be read to detect the break state. 5. SCI status check and data receiving: read SSR, check that RDRF is set to 1, then read data from the receive data register (RDR). Rev. 7.00 Jan 31, 2006 page 393 of 658 REJ09B0272-0700 Section 13 Serial Communication Interface (SCI) Initialization (1) Start receiving Set the MPIE bit in SCR to 1 (2) Read the ORER and FER bits in SSR FER = 1 or ORER = 1? No Read the RDRF bit in SSR No Yes (3) RDRF = 1? Yes Read the receive data in RDR No Own ID? Yes Read the ORER and FER bits in SSR FER = 1 or ORER = 1? Yes No Read the RDRF bit in SSR RDRF = 1? (5) No Yes Read the receive data in RDR No Total count received? Yes Clear the RE bit in SCR to 0 (4) Error handling Reception ends Figure 13.12 Sample Flowchart for Receiving Multiprocessor Serial Data Rev. 7.00 Jan 31, 2006 page 394 of 658 REJ09B0272-0700 Section 13 Serial Communication Interface (SCI) Start of error handling No ORER = 1? Yes Overrun error handling No FER = 1? Yes Break? Yes No Framing error handling Clear RE bit to 0 in SCR Clear ORER and FER to 0 in SSR End Figure 13.12 Sample Flowchart for Receiving Multiprocessor Serial Data (cont) Rev. 7.00 Jan 31, 2006 page 395 of 658 REJ09B0272-0700 Section 13 Serial Communication Interface (SCI) Figure 13.13 shows an example of SCI receive operation using a multiprocessor format. 1 Serial data Stop Start Data ID1 MPB bit bit Start bit 0 D0 D1 D7 1 1 0 Data 1 D0 D1 D7 Stop 1 MPB bit 1 Idle (mark) 0 state MPB MPIE RDRF RDR value RXI request, (multiprocessor interrupt) MPIE = 0 ID1 RXI interrupt handler reads data in RDR and clears RDRF to 0 Not own ID, so MPIE is set to 1 again No RXI interrupt, RDR maintains state Figure 13.13 Example of SCI Receive Operation (Own ID Does Not Match Data) (8-Bit Data with Multiprocessor Bit and One Stop Bit) Rev. 7.00 Jan 31, 2006 page 396 of 658 REJ09B0272-0700 Section 13 Serial Communication Interface (SCI) 1 Serial data Start bit 0 Stop Start bit MPB bit Data ID2 D0 D1 D7 1 1 0 Data 2 D0 D1 D7 Stop 1 MPB bit 1 Idle (mark) 0 state MPB MPIE RDRF RDR value ID1 RXI request, (multiprocessor interrupt) MPIE = 0 ID2 RXI interrupt handler reads data in RDR and clears RDRF to 0 Own ID, so receving continues, with data received at each RXI Data2 MPIE bit is again set to 1 Figure 13.13 Example of SCI Receive Operation (Own ID Matches Data) (8-Bit Data with Multiprocessor Bit and One Stop Bit) (cont) 13.3.4 Synchronous Operation In synchronous mode, the SCI transmits and receives data in synchronization with clock pulses. This mode is suitable for high-speed serial communication. The SCI transmitter and receiver share the same clock but are otherwise independent, so full duplex communication is possible. The transmitter and receiver are also double buffered, so continuous transmitting or receiving is possible by reading or writing data while transmitting or receiving is in progress. Figure 13.14 shows the general format in synchronous serial communication. Rev. 7.00 Jan 31, 2006 page 397 of 658 REJ09B0272-0700 Section 13 Serial Communication Interface (SCI) Transfer direction One unit (character or frame) of serial data * * Serial clock LSB Serial data Bit 0 MSB Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Note: * High except in continuous transmitting or receiving. Figure 13.14 Data Format in Synchronous Communication In synchronous serial communication, each data bit is output on the communication line from one falling edge of the serial clock to the next. Data is guaranteed valid at the rising edge of the serial clock. In each character, the serial data bits are transmitted in order from the LSB (first) to the MSB (last). After output of the MSB, the communication line remains in the state of the MSB. In synchronous mode, the SCI transmits or receives data by synchronizing with the falling edge of the serial clock. Communication Format: The data length is fixed at eight bits. No parity bit or multiprocessor bit can be added. Clock: An internal clock generated by the on-chip baud rate generator or an external clock input from the SCK pin can be selected as the SCI transmit/receive clock. The clock source is selected by the C/A bit in the serial mode register (SMR) and bits CKE1 and CKE0 in the serial control register (SCR). See table 13.6. When the SCI operates on an internal clock, it outputs the clock signal at the SCK pin. Eight clock pulses are output per transmitted or received character. When the SCI is not transmitting or receiving, the clock signal remains in the high state. Figure 13.15 shows an example of SCI transmit operation. In transmitting serial data, the SCI operates as follows. 1. The SCI monitors the TDRE bit in SSR. When TDRE is cleared to 0 the SCI recognizes that the transmit data register (TDR) contains new data, and loads this data from TDR into the transmit shift register (TSR). 2. After loading the data from TDR into TSR, the SCI sets the TDRE bit to 1 and starts transmitting. If the transmit-data-empty interrupt enable bit (TIE) in SCR is set to 1, the SCI requests a transmit-data-empty interrupt (TXI) at this time. Rev. 7.00 Jan 31, 2006 page 398 of 658 REJ09B0272-0700 Section 13 Serial Communication Interface (SCI) If clock output is selected, the SCI outputs eight serial clock pulses. If an external clock source is selected, the SCI outputs data in synchronization with the input clock. Data is output from the TxD pin in order from the LSB (bit 0) to the MSB (bit 7). 3. The SCI checks the TDRE bit when it outputs the MSB (bit 7). If TDRE is 0, the SCI loads data from TDR into TSR, transmits the MSB, then begins serial transmission of the next frame. If TDRE is 1, the SCI sets the TEND bit in SSR to 1, transmits the MSB, then holds the transmit data pin (TxD) in the MSB state. If the transmit-end interrupt enable bit (TEIE) in SCR is set to 1, a transmit-end interrupt (TEI) is requested at this time. 4. After the end of serial transmission, the SCK pin is held in the high state. Transmit direction Serial clock LSB Serial data Bit 0 MSB Bit 1 Bit 7 Bit 0 Bit 1 Bit 6 Bit 7 TDRE TEND TXI request TXI interrupt handler writes data in TDR and clears TDRE to 0 TEI request TXI request 1 frame Figure 13.15 Example of SCI Transmit Operation Transmitting and Receiving Data: SCI Initialization (Synchronous Mode): Before transmitting or receiving, software must clear the TE and RE bits to 0 in the serial control register (SCR), then initialize the SCI as follows. When changing the communication mode or format, always clear the TE and RE bits to 0 before following the procedure given below. Clearing TE to 0 sets TDRE to 1 and initializes the transmit shift register (TSR). Clearing RE to 0, however, does not initialize the RDRF, PER, FER, and ORER flags and receive data register (RDR), which retain their previous contents. Figure 13.16 shows a sample flowchart for initializing the SCI. Rev. 7.00 Jan 31, 2006 page 399 of 658 REJ09B0272-0700 Section 13 Serial Communication Interface (SCI) 1. Select the communication format in the serial mode register (SMR). 2. Write the value corresponding to the bit rate in the bit rate register (BRR) unless an external clock is used. 3. Select the clock source in the serial control register (SCR). Leave RIE, TIE, TEIE, MPIE, TE, and RE cleared to 0. 4. Wait for at least the interval required to transmit or receive one bit, then set TE or RE in the serial control register (SCR) to 1. Also set RIE, TIE, TEIE, and MPIE. Setting the corresponding bit of the pin function controller, TE, and RE enables the SCI to use the TxD or RxD pin. Start of initialization Clear TE and RE bits to 0 in SCR Select communication format in SMR (1) Set value in BRR (2) Set RIE, TIE, TEIE, MPIE, CKE1, and CKE0 bits in SCR (leaving TE and RE cleared to 0) (3) Wait 1-bit interval elapsed? No Yes Set TE or RE to 1 in SCR; Set RIE, TIE, TEIE, and MPIE (4) End Figure 13.16 Sample Flowchart for SCI Initialization Rev. 7.00 Jan 31, 2006 page 400 of 658 REJ09B0272-0700 Section 13 Serial Communication Interface (SCI) Transmitting Serial Data (Synchronous Mode): Figure 13.17 shows a sample flowchart for transmitting serial data. The procedure for transmitting serial data is listed below. 1. SCI initialization: select the TxD pin function with the PFC. 2. SCI status check and transmit data write: read the serial status register (SSR), check that the TDRE bit is 1, then write transmit data in the transmit data register (TDR) and clear TDRE to 0. 3. To continue transmitting serial data: read the TDRE bit to check whether it is safe to write (1); if so, write data in TDR, then clear TDRE to 0. When the DMAC is started by a transmit-dataempty interrupt request (TXI) to write data in TDR, the TDRE bit is checked and cleared automatically. Initialize (1) Start transmitting Read TDRE bit in SSR (2) No TDRE = 1? Yes Write transmit data in TDR and clear TDRE bit to 0 in SSR All data transmitted? No (3) Yes Read TEND bit in SSR TEND = 1? No Yes Clear TE bit SCR to 0 Transmission ends Figure 13.17 Sample Flowchart for Serial Transmitting Rev. 7.00 Jan 31, 2006 page 401 of 658 REJ09B0272-0700 Section 13 Serial Communication Interface (SCI) Receiving Serial Data (Synchronous Mode): Figure 13.18 shows a sample flowchart for receiving serial data. When switching from asynchronous mode to synchronous mode, make sure that ORER, PER, and FER are cleared to 0. If PER or FER is set to 1, the RDRF bit will not be set and both transmitting and receiving will be disabled. Figure 13.19 shows an example of SCI receive operation. The procedure for receiving serial data is listed below. 1. SCI initialization: select the RxD pin function with the PFC. 2. Receive error handling and break detection: if a receive error occurs, read the ORER bit in SSR to identify the error. After executing the necessary error handling, clear ORER to 0. Transmitting/receiving cannot resume if ORER remains set to 1. 3. SCI status check and receive data read: read the serial status register (SSR), check that RDRF is set to 1, then read receive data from the receive data register (RDR) and clear RDRF to 0. The RXI interrupt can also be used to determine if the RDRF bit has changed from 0 to 1. 4. To continue receiving serial data: read RDR, and clear RDRF to 0 before the frame MSB (bit 7) of the current frame is received. If the DMAC is started by a receive-data-full interrupt (RXI) to read RDR, the RDRF bit is cleared automatically, so this step is unnecessary. Rev. 7.00 Jan 31, 2006 page 402 of 658 REJ09B0272-0700 Section 13 Serial Communication Interface (SCI) Initialization (1) Start receiving Read ORER bit in SSR Yes ORER = 1? No (2) Error handling Read RDRF bit in SSR No (3) RDRF = 1? Yes Read receive data in RDR and clear RDRF bit in SSR to 0 No (4) Total count received? Yes Clear RE bit in SCR to 0 Reception ends Figure 13.18 Sample Flowchart for Serial Receiving Rev. 7.00 Jan 31, 2006 page 403 of 658 REJ09B0272-0700 Section 13 Serial Communication Interface (SCI) Error handling No ORER = 1? Yes Overrun error handling Clear ORER bit in SSR to 0 End Figure 13.18 Sample Flowchart for Serial Receiving (cont) Receive direction Serial clock Serial data Bit 7 Bit 0 Bit 7 Bit 0 Bit 1 Bit 6 Bit 7 RDRF ORER RXI request RXI interrupt handler reads data in RDR and clears RDRF to 0 RXI request Overrun error, ERI request 1 frame Figure 13.19 Example of SCI Receive Operation In receiving, the SCI operates as follows: 1. The SCI synchronizes with serial clock input or output and initializes internally. 2. Receive data is shifted into RSR in order from the LSB to the MSB. After receiving the data, the SCI checks that RDRF is 0 so that receive data can be loaded from RSR into RDR. If this check passes, the SCI sets RDRF to 1 and stores the received data in RDR. If the check does Rev. 7.00 Jan 31, 2006 page 404 of 658 REJ09B0272-0700 Section 13 Serial Communication Interface (SCI) not pass (receive error), the SCI operates as indicated in table 13.8. When the error flag is set to 1 and the RDRF bit is cleared to 0, the RDRF bit will not be set to 1 during reception. When restarting reception, be sure to clear the error flag to 0. 3. After setting RDRF to 1, if the receive-data-full interrupt enable bit (RIE) is set to 1 in SCR, the SCI requests a receive-data-full interrupt (RXI). If the ORER bit is set to 1 and the receive-data-full interrupt enable bit (RIE) in SCR is also set to 1, the SCI requests a receiveerror interrupt (ERI). Transmitting and Receiving Serial Data Simultaneously (Synchronous Mode): Figure 13.20 shows a sample flowchart for transmitting and receiving serial data simultaneously. The procedure for transmitting and receiving serial data simultaneously is listed below. 1. SCI initialization: select the TxD and RxD pin function with the PFC. 2. SCI status check and transmit data write: read the serial status register (SSR), check that the TDRE bit is 1, then write transmit data in the transmit data register (TDR) and clear TDRE to 0. The TXI interrupt can also be used to determine if the TDRE bit has changed from 0 to 1. 3. Receive error handling: if a receive error occurs, read the ORER bit in SSR to identify the error. After executing the necessary error handling, clear ORER to 0. Transmitting/receiving cannot resume if ORER remains set to 1. 4. SCI status check and receive data read: read the serial status register (SSR), check that RDRF is set to 1, then read receive data from the receive data register (RDR) and clear RDRF to 0. The RXI interrupt can also be used to determine if the RDRF bit has changed from 0 to 1. 5. To continue transmitting and receiving serial data: read the RDRF bit and RDR, and clear RDRF to 0 before the MSB (bit 7) of the current frame is received. Also read the TDRE bit to check whether it is safe to write (1); if so, write data in TDR, then clear TDRE to 0 before the MSB (bit 7) of the current frame is transmitted. When the DMAC is started by a transmit-dataempty interrupt request (TXI) to write data in TDR, the TDRE bit is checked and cleared automatically. When the DMAC is started by a receive-data-full interrupt (RXI) to read RDR, the RDRF bit is cleared automatically. Rev. 7.00 Jan 31, 2006 page 405 of 658 REJ09B0272-0700 Section 13 Serial Communication Interface (SCI) Initialization (1) Start transmitting and receiving Read TDRE bit in SSR No (2) TDRE = 1? Yes Write transmit data to TDR and clear TDRE bit in SSR to 0 Read ORER bit in SSR ORER = 1? No Read RDRF bit in SSR No Yes (3) Error handling (4) RDRF = 1? Yes Read receive data in RDR and clear RDRF bit in SSR to 0 No (5) Total count transmitted and received? Yes Clear TE and RE bits in SCR to 0 Transmitting/receiving ends Note: When switching from transmitting or receiving to simultaneous transmitting and receiving, clear both the TE bit and the RE bit to 0, then set both this to 1 simultaneously. Figure 13.20 Sample Flowchart for Serial Transmitting and Receiving Rev. 7.00 Jan 31, 2006 page 406 of 658 REJ09B0272-0700 Section 13 Serial Communication Interface (SCI) 13.4 SCI Interrupt Sources and the DMAC The SCI has four interrupt sources in each channel: transmit-end (TEI), receive-error (ERI), receive-data-full (RXI), and transmit-data-empty (TXI). Table 13.12 lists the interrupt sources and indicates their priority. These interrupts can be enabled and disabled by the TIE, RIE, and TEIE bits in the serial control register (SCR). Each interrupt request is sent separately to the interrupt controller. TXI is requested when the TDRE bit in SSR is set to 1. TXI can start the direct memory access controller (DMAC) to transfer data. TDRE is automatically cleared to 0 when the DMAC executes a data transfer to the transmit data register (TDR). RXI is requested when the RDRF bit in SSR is set to 1. RXI can start the DMAC to transfer data. RDRF is automatically cleared to 0 when the DMAC executes a data transfer to the receive data register (RDR). ERI is requested when the ORER, PER, or FER bit in SSR is set to 1. ERI cannot start the DMAC. TEI is requested when the TEND bit in SSR is set to 1. TEI cannot start the DMAC. A TXI interrupt indicates that transmit data writing is enabled. A TEI interrupt indicates that the transmit operation is complete. Table 13.12 SCI Interrupt Sources Interrupt Source Description DMAC Activation Priority ERI Receive error (ORER, PER, or FER) No High RXI Receive data full (RDRF) Yes TXI Transmit data empty (TDRE) Yes TEI Transmit end (TEND) No Low 13.5 Usage Notes Note the following points when using the SCI. TDR Write and TDRE Flags: The TDRE bit in the serial status register (SSR) is a status flag indicating loading of transmit data from TDR into TSR. The SCI sets TDRE to 1 when it transfers data from TDR to TSR. Data can be written in TDR regardless of the status of the TDRE bit. If new data is written in TDR when TDRE is 0, the old data stored in TDR will be lost because this data has not yet been transferred to TSR. Before writing transmit data to TDR, be sure to check that TDRE is set to 1. Rev. 7.00 Jan 31, 2006 page 407 of 658 REJ09B0272-0700 Section 13 Serial Communication Interface (SCI) Simultaneous Multiple Receive Errors: Table 13.13 indicates the state of the SSR status flags when multiple receive errors occur simultaneously. When an overrun error occurs, the RSR contents cannot be transferred to RDR, so receive data is lost. Table 13.13 SSR Status Flags and Transfer of Receive Data Receive Error Status RDRF ORER FER PER Receive Data Transfer RSR RDR Overrun error 1 1 0 0 X Framing error 0 0 1 0 O Parity error 0 0 0 1 O SSR Status Flags Overrun error + framing error 1 1 1 0 X Overrun error + parity error 1 1 0 1 X Framing error + parity error 0 0 1 1 O Overrun error + framing error + parity error 1 1 1 1 X O: X: Receive data is transferred from RSR to RDR. Receive data is not transferred from RSR to RDR. Break Detection and Processing: Break signals can be detected by reading the RxD pin directly when a framing error (FER) is detected. In the break state, the input from the RxD pin consists of all 0s, so FER is set and the parity error flag (PER) may also be set. In the break state, the SCI receiver continues to operate, so if the FER bit is cleared to 0, it will be set to 1 again. Sending a Break Signal: When TE is cleared to 0 the TxD pin becomes an I/O port, the level and direction (input or output) of which are determined by the data register (DR) of the I/O port and the control register (CR) of the PFC. This feature can be used to send a break signal. The DR value substitutes for the mark state until the PFC setting is performed. The DR bits should therefore be set as an output port that outputs 1 beforehand. To send a break signal during serial transmission, clear the DR bit to 0, and select output port as the TxD pin function by the PFC. When TE is cleared to 0, the transmitter is initialized, regardless of its current state. Receive Error Flags and Transmitter Operation (Synchronous Mode Only): When a receive error flag (ORER, PER, or FER) is set to 1, the SCI will not start transmitting even if TDRE is set to 1. Be sure to clear the receive error flags to 0 before starting to transmit. Note that clearing RE to 0 does not clear the receive error flags. Receive Data Sampling Timing and Receive Margin in Asynchronous Mode: In asynchronous mode, the SCI operates on a base clock of 16 times the bit rate frequency. In receiving, the SCI Rev. 7.00 Jan 31, 2006 page 408 of 658 REJ09B0272-0700 Section 13 Serial Communication Interface (SCI) synchronizes internally with the falling edge of the start bit, which it samples on the base clock. Receive data is latched on the rising edge of the eighth base clock pulse. See figure 13.21. 16 clocks 8 clocks Internal base clock 0 1 2 3 4 5 6 7 8 9 10111213 1415 0 1 2 3 4 5 6 7 8 9 10111213 1415 0 1 2 3 4 5 -7.5 clocks Receive data (RxD) +7.5 clocks Start bit D0 D1 Synchronization sampling timing Data sampling timing Figure 13.21 Receive Data Sampling Timing in Asynchronous Mode The receive margin in asynchronous mode can therefore be expressed as shown in equation 1. Equation 1: M = 0.5 - M: N: D: L: F: 1 2N - (L - 0.5)F - D - 0.5 (1 + F ) x 100% N Receive margin (%) Ratio of clock frequency to bit rate (N = 16) Clock duty cycle (D = 0 to 1.0) Frame length (L = 9 to 12) Absolute deviation of clock frequency From equation (1), if F = 0 and D = 0.5 the receive margin is 46.875%, as given by equation 2. Equation 2: D M = 0.5, F = 0 = (0.5 - 1/(2 x 16)) x 100% = 46.875% (2) This is a theoretical value. A reasonable margin to allow in system designs is 20-30%. Rev. 7.00 Jan 31, 2006 page 409 of 658 REJ09B0272-0700 Section 13 Serial Communication Interface (SCI) Constraints on DMAC Use: * When using an external clock source for the serial clock, update TDR with the DMAC, and then input the transmit clock after the elapse of five system clocks or more. If a transmit clock is input in the first four system clocks after TDR is written, an error may occur (figure 13.22). * Before reading the receive data register (RDR) with the DMAC, select the receive-data-full interrupt of the SCI as an activation source using the resource select bit (RS) in the channel control register (CHCR). SCK t TDRE D0 D1 D2 D3 D4 D5 D6 D7 Note: During external clock operation, an error may occur if t is 4 or less. Figure 13.22 Example of Synchronous Transmitting with DMAC Cautions on Use of Synchronous External Clock Mode: * Set TE = RE = 1 only when the external clock SCI is 1. * Do not set TE = RE = 1 until at least 4 clocks after the external clock SCK has changed from 0 to 1. * When receiving, RDRF is set to 1 when RE is cleared to 0 2.5-3.5 clocks after the rising edge of the RxD D7 bit SCK input, but copying to RDR is not possible. Caution on Synchronous Internal Clock Mode: When receiving, RDRF is set to 1 when RE is cleared to 0 1.5 clocks after the rising edge of the RxD D7 bit SCK output, but copying to RDR is not possible. Rev. 7.00 Jan 31, 2006 page 410 of 658 REJ09B0272-0700 Section 14 A/D Converter Section 14 A/D Converter 14.1 Overview The SuperH microcomputer includes an analog-to-digital converter module which can be programmed for input of analog signals up to eight channels. A/D conversion is performed by the successive approximations method with 10-bit resolution. 14.1.1 Features * 10-bit resolution * Eight analog input channels * User definable analog conversion voltage range * The analog conversion voltage range can be set with the analog reference power pin (AVref) as the analog reference voltage * Rapid conversion time: 6.7 s per channel (at 20 MHz) * Single mode or scan mode (selectable) Single mode: One-channel A/D conversion Scan mode: A/D conversion repeated on one to four channels * Four 16-bit data registers: A/D conversion results are transferred to and stored in the data registers corresponding to channels * Sample-and-hold circuit * External trigger input can start A/D conversion * ADI: A/D interrupt request Can be generated at end of each conversion cycle Can start direct memory access controller (DMAC) Rev. 7.00 Jan 31, 2006 page 411 of 658 REJ09B0272-0700 Section 14 A/D Converter 14.1.2 Block Diagram Bus interface Figure 14.1 shows a block diagram of the A/D converter. Internal data bus ADCR ADCSR AVSS ADDRD 10-bit D/A ADDRC AVref ADDRB AVCC ADDRA Successive approximations register Module data bus AN0 AN1 + AN2 AN3 AN4 AN5 AN6 AN7 /8 Analog multiplexer - Control circuit /16 Comparator Sample-andhold circuit ADI interrupt signal ADTRG A/D converter ADCR: A/D control register ADCSR: A/D control/status register ADDRA: A/D data register A ADDRB: A/D data register B ADDRC: A/D data register C ADDRD: A/D data register D Figure 14.1 Block Diagram of A/D Converter Rev. 7.00 Jan 31, 2006 page 412 of 658 REJ09B0272-0700 Section 14 A/D Converter 14.1.3 Configuration of Input Pins Table 14.1 lists input pins for the A/D converter. The eight analog input pins are grouped into two sets. Group 0 comprises analog input pins 0-3 (AN0-AN3) and group 1 comprises pins 4-7 (AN4- AN7). Pins AVCC and AVSS are the power supply pins for the analog circuits of the A/D converter. AVref is the analog reference voltage for A/D conversion. Table 14.1 Input Pins Pin Name Abbreviation I/O Function Analog supply voltage AVCC I Power supply for the analog circuits Analog ground AVSS I Ground and reference voltage for the analog circuits Analog reference power supply AVref I Reference voltage for the analog circuits Analog input 0 AN0 I Analog input pins, group 0 Analog input 1 AN1 I Analog input 2 AN2 I Analog input 3 AN3 I Analog input 4 AN4 I Analog input 5 AN5 I Analog input 6 AN6 I Analog input 7 AN7 I A/D conversion trigger input ADTRG I Analog input pins, group 1 A/D conversion start external trigger input Rev. 7.00 Jan 31, 2006 page 413 of 658 REJ09B0272-0700 Section 14 A/D Converter 14.1.4 Configuration of A/D Registers The A/D converter includes the registers listed in table 14.2. Table 14.2 A/D Registers Register Name Abbreviation R/W Initial Value 1 Address* Access Size A/D data register A (high) ADDRAH R H'00 H'05FFFEE0 8, 16 A/D data register A (low) ADDRAL R H'00 H'05FFFEE1 16 A/D data register B (high) ADDRBH R H'00 H'05FFFEE2 8, 16 A/D data register B (low) ADDRBL R H'00 H'05FFFEE3 16 A/D data register C (high) ADDRCH R H'00 H'05FFFEE4 8, 16 A/D data register C (low) ADDRCL R H'00 H'05FFFEE5 16 A/D data register D (high) ADDRDH R H'00 H'05FFFEE6 8, 16 A/D data register D (low) ADDRDL R H'00 H'05FFFEE7 16 A/D control/status register ADCSR 2 R/(W)* H'00 H'05FFFEE8 8, 16 A/D control register ADCR R/W H'05FFFEE9 8, 16 H'7F Notes: 1. Only the values of bits A27-A24 and A8-A0 are valid; bits A23-A9 are ignored. For details on the register addresses, see section 8.3.5, Area Descriptions. 2. Only 0 can be written in bit 7, to clear the flag. 14.2 Register Descriptions 14.2.1 A/D Data Registers A-D (ADDRA-ADDRD) The four A/D data registers (ADDRA-ADDRD) are 16-bit read-only registers that store the results of the A/D conversion. Each result consists of 10 bits. The first 8 bits are stored in the upper byte of the data register corresponding to the selected channel. The last two bits are stored in the lower byte of the data register. Bits 5-0 of the lower byte are reserved and are always read as 0. Each data register is assigned to two analog input channels (table 14.3). The A/D data registers are always readable by the CPU. The upper byte can be read directly and the lower byte is read via a temporary register (TEMP). See section 14.3, CPU Interface, for details. The A/D data registers are initialized to H'0000 by a reset and in standby mode. Rev. 7.00 Jan 31, 2006 page 414 of 658 REJ09B0272-0700 Section 14 A/D Converter Bit 15 14 13 12 11 10 9 8 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 Initial value 0 0 0 0 0 0 0 0 Read/Write R R R R R R R R Bit 7 6 5 4 3 2 1 0 AD1 AD0 -- -- -- -- -- -- Initial value 0 0 0 0 0 0 0 0 Read/Write R R R R R R R R n = A-D Table 14.3 Assignment of Data Registers to Analog Input Channels Analog Input Channel Group 0 Group 1 A/D Data Register AN0 AN4 ADDRA AN1 AN5 ADDRB AN2 AN6 ADDRC AN3 AN7 ADDRD 14.2.2 A/D Control/Status Register (ADCSR) The A/D control/status register (ADCSR) is an 8-bit read/write register that controls the operation of the A/D converter (mode selection, etc.). ADCSR is initialized to H'00 by a reset and in standby mode. Bit 7 6 5 4 3 2 1 0 ADF ADIE ADST SCAN CKS CH2 CH1 CH0 Initial value 0 0 0 0 0 0 0 0 Read/Write R/(W)* R/W R/W R/W R/W R/W R/W R/W Note: * Only 0 can be written, to clear the flag. Rev. 7.00 Jan 31, 2006 page 415 of 658 REJ09B0272-0700 Section 14 A/D Converter Bit 7--A/D End Flag (ADF): ADF indicates that A/D conversion is completed. Bit 7 (ADF) Description 0 Cleared to 0 under the following conditions: 1 (Initial value) * The CPU reads the ADF bit while the bit is set to 1, then writes 0 in the bit * The ADI starts the DMAC and the A/D conversion register is accessed Set to 1 at the following times: * Single mode: When A/D conversion is complete * Scan mode: When A/D conversion of all selected channels is complete Bit 6--A/D Interrupt Enable (ADIE): ADIE selects whether or not an A/D interrupt (ADI) is requested when A/D conversion is completed. Bit 6 (ADIE) Description 0 The A/D interrupt (ADI) request is disabled 1 The A/D interrupt (ADI) request is enabled (Initial value) Bit 5--A/D Start (ADST): ADST selects the start or halting of A/D conversion. Whenever the A/D converter is operating, this bit is set to 1. It can also be set to 1 by the A/D conversion trigger input pin (ADTRG). Bit 5 (ADST) Description 0 A/D conversion is halted 1 * Single mode: A/D conversion is performed. This bit is automatically cleared to 0 at the end of the conversion. * Scan mode: A/D conversion starts and continues cyclically on the selected channels until this bit is cleared to 0 by software, a reset, or standby mode. (Initial value) Bit 4--Scan Mode (SCAN): SCAN selects either scan mode or single mode for operation. See section 14.4, Operation, for descriptions of these modes. The mode should be changed only when the ADST bit is cleared to 0. Bit 4 (SCAN) Description 0 Single mode 1 Scan mode Rev. 7.00 Jan 31, 2006 page 416 of 658 REJ09B0272-0700 (Initial value) Section 14 A/D Converter Bit 3--Clock Select (CKS): CKS selects the A/D conversion time. The conversion time should be changed only when the ADST bit is cleared to 0. Bit 3 (CKS) Description 0 Conversion time = 266 states (maximum) 1 Conversion time = 134 states (maximum) (Initial value) Bits 2-0--Channel Select 2-0 (CH2-CH0): CH2-CH0 select analog input channels together with the SCAN bit. The channel selection should be changed only when the ADST bit is cleared to 0. Group Select Channel Select CH2 0 1 14.2.3 CH1 Selected Channels CH0 Single Mode Scan Mode 0 0 AN0 AN0 (Initial value) 0 1 AN1 AN0 and AN1 1 0 AN2 AN0-AN2 1 1 AN3 AN0-AN3 0 0 AN4 AN4 0 1 AN5 AN4 and AN5 1 0 AN6 AN4-AN6 1 1 AN7 AN4-AN7 A/D Control Register (ADCR) The A/D control register (ADCR) is an 8-bit read/write register that selects whether or not to start the A/D conversion when an external trigger is input. ADCR is initialized to H'7F by a reset and in standby mode. Bit 7 6 5 4 3 2 1 0 TRGE -- -- -- -- -- -- -- Initial value 0 1 1 1 1 1 1 1 Read/Write R/W -- -- -- -- -- -- -- Rev. 7.00 Jan 31, 2006 page 417 of 658 REJ09B0272-0700 Section 14 A/D Converter Bit 7--Trigger Enable (TRGE): TRGE selects whether or not to start A/D conversion when an external trigger is input. Bit 7 (TRGE) Description 0 When an external trigger is input, A/D conversion does not start 1 A/D conversion starts at the falling edge of an input signal from the external trigger pin (ADTRG). (Initial value) Bits 6-0--Reserved): These bits are always read as 1. The write value should always be 1. 14.3 CPU Interface The A/D data registers (ADDRA-ADDRD) are 16-bit registers, but they are connected to the CPU by an 8-bit data bus. Therefore, the upper byte of each register can be read directly, but the lower byte is accessed through an 8-bit temporary register (TEMP). When the CPU reads the upper byte of an A/D data register, the upper byte is transferred to the CPU and the lower byte to TEMP. When the lower byte is accessed, the value in TEMP is transferred to the CPU. A program should first read the upper byte, then the lower byte of the A/D data register. This can be performed by reading ADDR from the upper byte end using a word transfer instruction (MOV.W, etc.). Reading only the upper byte would assure the CPU of obtaining consistent data. If the program reads only the lower byte, however, consistent data will not be guaranteed. Figure 14.2 shows the data flow during access to A/D data registers. Rev. 7.00 Jan 31, 2006 page 418 of 658 REJ09B0272-0700 Section 14 A/D Converter Upper byte read CPU receives data H'AA Module internal data bus Bus interface TEMP [H'40] ADDRn H [H'AA] ADDRn L [H'40] n = A to D Lower byte read CPU receives data H'40 Module internal data bus Bus interface TEMP [H'40] ADDRn H [H'AA] ADDRn L [H'40] n = A to D Figure 14.2 Read Access to A/D Data Register (Reading H'AA40) Rev. 7.00 Jan 31, 2006 page 419 of 658 REJ09B0272-0700 Section 14 A/D Converter 14.4 Operation The A/D converter operates by successive approximations with a 10-bit resolution. Its two modes, single mode and scan mode, are described below. 14.4.1 Single Mode (SCAN = 0) In single mode, A/D conversion is performed on a single channel. A/D conversion starts when the ADST bit in the A/D control/status register (ADCSR) is set to 1 by software or an external trigger input. During the conversion process the ADST bit remains set at 1. When the conversion is completed, the ADST bit is automatically cleared to 0. When the conversion is completed, the ADF bit is set to 1. If the interrupt enable bit (ADIE) in ADCSR is also set to 1, an A/D conversion interrupt (ADI) is requested. When ADCSR is read and 1 is written in the ADF bit, the ADF bit is cleared to 0. Before changing a mode or analog input channel, clear the ADST bit in ADCSR to 0 to stop A/D conversion in order to prevent malfunctions. Setting the ADST bit to 1 after changing the mode or channel starts A/D conversion again (changing the mode or channel and setting the ADST bit can be performed simultaneously). The following is an example of the A/D conversion process in single mode when channel 1 (AN1) is selected. See figure 14.3 for the timing. 1. The program selects single mode (SCAN = 0) and input channel AN1 (CH2 = CH1 = 0, CH0 = 1), enables the A/D interrupt request (ADIE = 1), and sets the ADST bit to 1 to start A/D conversion. 2. At the end of the conversion process the A/D converter transfers the result to register ADDRB, sets the ADF bit to 1, clears the ADST bit to 0, and halts. 3. Since ADF = 1 and ADIE = 1, an A/D interrupt is requested. 4. The A/D interrupt handling routine is started. 5. The interrupt handling routine reads the ADF value; since it is 1, it writes a 0 into the ADF bit. 6. The interrupt handling routine reads and processes the A/D conversion result (ADDRB). 7. The routine ends. Steps 2-7 can now be repeated by setting the ADST bit to 1 again. Rev. 7.00 Jan 31, 2006 page 420 of 658 REJ09B0272-0700 Waiting Waiting Channel 3 (AN3) operating Clear* Set* Read result A/D conversion result 1 Waiting A/D conversion result 2 Note: * Downward arrows () indicate instruction execution. ADDRD ADDRC ADDRB ADDRA Set* Set* Waiting A/D conversion 1 Waiting Channel 2 (AN2) operating Channel 1 (AN1) operating Channel 0 (AN0) operating ADF ADST A/D conversion starts ADIE Read result A/D conversion result 2 Waiting Clear* Section 14 A/D Converter Figure 14.3 A/D Operation in Single Mode (Channel 1 Selected) Rev. 7.00 Jan 31, 2006 page 421 of 658 REJ09B0272-0700 Section 14 A/D Converter 14.4.2 Scan Mode (SCAN = 1) Scan mode can be used to monitor analog inputs on one or more channels. When the ADST bit in ADCSR is set to 1 by software or an external trigger input, A/D conversion starts with the first channel (AN0 when CH2 = 0, AN4 when CH2 = 1) in the group. If the scan group includes more than one channel, conversion of the second channel (AN1 or AN5) begins as soon as conversion of the first channel ends. Conversion of the selected channels continues cyclically until the ADST bit is cleared to 0. The conversion results are stored in the data registers corresponding to the selected channels. Before changing a mode or analog input channels, clear the ADST bit in ADCSR to 0 to stop A/D conversion in order to prevent malfunctions. Setting the ADST bit to 1 after changing the mode or channel selects the first channel and starts A/D conversion again (changing the mode or channel and setting the ADST bit can be performed simultaneously). The following is an example of the A/D conversion process in scan mode when three channels in group 0 are selected (AN0, AN1, and AN2). See figure 14.4 for the timing. 1. The program selects scan mode (SCAN = 1), scan group 0 (CH2 = 0), and analog input channels AN0-AN2 (CH1 = 1, CH2 = CH0 = 0), then sets the ADST bit to 1 to start A/D conversion. 2. The A/D converter samples the input at the first channel (AN0), converts the voltage level to a digital value, and transfers the result to register ADDRA. Next, the second channel (AN1) is automatically selected and conversion begins. 3. Then it does the same for the third channel (AN2). 4. After all selected channels (AN0-AN2) have been converted, the A/D converter sets the ADF bit to 1 and begins conversion on channel AN0 again. If the ADIE bit is set to 1, an A/D interrupt (ADI) is requested after the A/D conversion. 5. Steps 2-4 are repeated cyclically as long as the ADST bit remains set at 1. To stop A/D conversion, clear the ADST bit to 0. The moment the ADST bit is set to 1 again, A/D conversion begins with the first channel (AN0). Rev. 7.00 Jan 31, 2006 page 422 of 658 REJ09B0272-0700 Waiting Waiting Channel 2 (AN2) operating Channel 3 (AN3) operating *2 Waiting A/D conversion result 4 A/D conversion result 3 A/D conversion result 2 Transfer A/D conversion result 1 Clear*1 Clear*1 Waiting Waiting Waiting A/D conversion 5 A/D conversion 4 A/D conversion 3 A/D conversion 2 Waiting A/D conversion time Continuous A/D conversion Notes: 1. Downward arrow indicates instruction executed by software. 2. Data being converted is ignored. ADDRD ADDRC ADDRB ADDRA Waiting Waiting A/D conversion 1 Channel 1 (AN1) operating Channel 0 (AN0) operating ADF ADST Set*1 Section 14 A/D Converter Figure 14.4 A/D Operation in Scan Mode (Channels 0-2 Selected) Rev. 7.00 Jan 31, 2006 page 423 of 658 REJ09B0272-0700 Section 14 A/D Converter 14.4.3 Input Sampling Time and A/D Conversion Time With a built-in sample-and-hold circuit, the A/D converter performs input sampling at time tD after control/status register (ADSCR) access is started. See figure 14.5 for A/D conversion timing and table 14.4 for A/D conversion times. The total conversion time includes tD and the input sampling time, as shown in figure 14.5. The purpose of tD is to synchronize the ADCSR write time with the A/D conversion process; therefore the duration of tD is variable. As a result, the total conversion time varies within the ranges shown in table 14.4. In scan mode, the ranges given in table 14.4 apply to the first conversion. The duration of the second and subsequent conversion processes is fixed at 256 states (CKS = 0) or 128 states (CKS = 1). *1 CK Address *2 Write signal Input sampling timing ADF tD tSPL tCONV tD A/D start delay tSPL Input sampling time tCONV A/D conversion time Notes: 1. ADSCR write cycle 2. ADSCR address Figure 14.5 A/D Conversion Timing Rev. 7.00 Jan 31, 2006 page 424 of 658 REJ09B0272-0700 Section 14 A/D Converter Table 14.4 A/D Conversion Time (Single Mode) CKS = 0 CKS = 1 Item Symbol Min Typ Max Min Typ Max A/D start delay tD 10 -- 17 6 -- 9 Input sampling time tSPL -- 64 -- -- 32 -- Total A/D conversion time tCONV 259 -- 266 131 -- 134 Note: Values are the number of states (tcyc). 14.4.4 A/D Conversion Start by External Trigger Input The A/D converter can be started when an external trigger is input. The external trigger is input from the ADTRG input pin when the trigger enable (TRGE) bit in the A/D control register (ADCR) is set to 1. When the ADTRG input pin is asserted low, the A/D start (ADST) bit in the A/D control/status register (ADCSR) is set to 1 and A/D conversion begins. All other operations are the same as when the ADST bit is set to 1, regardless of whether the mode is single or scan. For the timing, see figure 14.6. CK ADTRG External trigger signal ADST A/D conversion Figure 14.6 External Trigger Input Timing 14.5 Interrupts and DMA Transfer Requests The A/D converter can generate an A/D interrupt (ADI) request at the end of conversion. The ADI request is enabled by setting the ADIE bit in ADCSR to 1, or is disabled by clearing the bit to 0. When ADI is generated, the DMAC can be started. DMA transfers can be performed by requesting an ADI interrupt by setting the resource select bits (RS3-RS0) in the DMA channel control register (CHCR) of the direct memory access controller (DMAC). The ADF bit in the A/D control/status register (ADCSR) is automatically cleared to 0 when the DMAC accesses an A/D converter register. Rev. 7.00 Jan 31, 2006 page 425 of 658 REJ09B0272-0700 Section 14 A/D Converter 14.6 Definitions of A/D Conversion Accuracy The A/D converter compares an analog value input from an analog input channel to its analog reference value and converts it into 10-bit digital data. The absolute accuracy of this A/D conversion is the deviation between the input analog value and the output digital value. It includes the following errors: * Offset error * Full-scale error * Quantization error * Nonlinearity error These four error quantities are explained below using figure 14.7. In the figure, the 10 bits of the A/D converter have been simplified to 3 bits. Offset error is the deviation between actual and ideal A/D conversion characteristics when the digital output value changes from the minimum (zero voltage) 0000000000 (000 in the figure) to 000000001 (001 in the figure)(figure 14.7, item (1)). Full-scale error is the deviation between actual and ideal A/D conversion characteristics when the digital output value changes from 1111111110 (110 in the figure) to the maximum 1111111111 (111 in the figure)(figure 14.7, item (2)). Quantization error is the intrinsic error of the A/D converter and is expressed as 1/2 LSB (figure 14.7, item (3)). Nonlinearity error is the deviation between actual and ideal A/D conversion characteristics between zero voltage and full-scale voltage (figure 14.7, item (4)). Note that it does not include offset, full-scale, or quantization error. Digital output 111 (2) Full-scale error Digital output Ideal A/D conversion characteristic Ideal A/D conversion characteristic 110 101 100 (4) Nonlinearity error 011 010 001 000 (3) Quantization error 0 1/8 2/8 3/8 4/8 5/8 6/8 7/8 FS Analog input voltage FS: Full-scale voltage Actual A/D convertion characteristic (1) Offset error FS Analog input voltage Figure 14.7 Definitions of A/D Conversion Accuracy Rev. 7.00 Jan 31, 2006 page 426 of 658 REJ09B0272-0700 Section 14 A/D Converter 14.7 A/D Converter Usage Notes When using the A/D converter, note the points listed in section 14.7.1 below. 14.7.1 Setting Analog Input Voltage * Analog Input Voltage Range: During A/D conversion, the voltages input to the analog input pins ANn should be in the range AVSS ANn AVref. * Relationships of AVCC and AVSS to VCC and VSS: AVCC, AVSS, VCC and VSS should be related as follows: AVCC = VCC 10% and AVSS = VSS. If the A/D converter is not used, set AVCC = VCC and AVSS = VSS. * AVref Input Range: The analog reference voltage input at the AVref pin should be in the range AVref AVCC. If the converter is not used, set AVref = VCC. * When the converter is neither in use nor in standby mode, connect AVCC and AVref to the power voltage (VCC). 14.7.2 Handling of Analog Input Pins To prevent damage from voltage surges at the analog input pins (AN0-AN7), connect an input protection circuit like the one shown in figure 14.8. The circuit shown also includes an RC filter to prevent errors due to noise. This circuit is shown as an example: The circuit constants should be selected according to actual application conditions. Table 14.5 list the analog input pin specifications and figure 14.9 shows an equivalent circuit diagram of the analog input ports. AVCC AVref 100 * * 0.1 F SuperH microcomputer AN0-AN7 AVSS Note: * 10 F 0.01 F Figure 14.8 Example of Analog Input Protection Circuit Rev. 7.00 Jan 31, 2006 page 427 of 658 REJ09B0272-0700 Section 14 A/D Converter 1.0 k AN0-AN7 20 pF Analog multiplexer A/D converter 1 M Note: All figures are reference values. Figure 14.9 Analog Input Pin Equivalent Circuit Table 14.5 Analog Input Pin Ratings Item Min Max Unit Analog input capacitance -- 20 pF Allowable signal-source impedance -- 3 k 14.7.3 Switchover between Analog Input and General Port Functions 1. Switchover to/from general port function When the A/D converter is started by setting the A/D start bit (ADST) to 1 in the A/D control/status register (ADCSR), or by asserting the ADTRG pin, port C pins begin functioning as analog input pins (ANn). When A/D conversion ends, the pins are switched back to the general port (digital input) function. 2. Port C pins not used for A/D conversion Pins not selected as AN pins by the channel select setting can be used in the following combinations as general port pins in both single mode and scan mode. a. When any or all of pins AN0 to AN3 are used for A/D conversion, AN4 to AN7 can be used as general port pins. b. When any or all of pins AN4 to AN7 are used for A/D conversion, AN0 to AN3 can be used as general port pins. Rev. 7.00 Jan 31, 2006 page 428 of 658 REJ09B0272-0700 Section 15 Pin Function Controller (PFC) Section 15 Pin Function Controller (PFC) 15.1 Overview The pin function controller (PFC) is composed of registers for selecting the function of multiplexed pins and the direction of input/output. The pin function and input/output direction can be selected for each pin individually without regard to the operating mode of the chip. Table 15.1 lists the multiplexed pins. Table 15.1 List of Multiplexed Pins Function 3 (Related Module) Function 4 (Related Module) Pin No. (PRQP0112 JA-A) Pin No. (PTQP0120 LA-A) Port Function 1 Function 2 (Related Module) (Related Module) A PA15 I/O (port) IRQ3 input (INTC) DREQ1 input (DMAC) -- 69 74 A*3 PA14 I/O (port) IRQ2 input (INTC) DACK1 output (DMAC) -- 68 73 A PA13 I/O (port) IRQ1 input (INTC) TCLKB input (ITU) DREQ0 input (DMAC) 67 72 A*3 PA12 I/O (port) IRQ0 input (INTC) TCLKA input (ITU) DACK0 output (DMAC) 66 71 A PA11 I/O (port) DPH I/O (D bus) TIOCB1 I/O (ITU) -- 65 70 A PA10 I/O (port) DPL I/O (D bus) TIOCA1 I/O (ITU) -- 64 69 A PA9 I/O (port) AH output (BSC) ADTRG input (A/D) IRQOUT output (INTC) 63 68 A PA8 I/O (port) BREQ input (system) -- -- 62 67 A PA7 I/O (port) BACK output (system) -- -- 60 65 A PA6 I/O (port) RD output (BSC) -- -- 59 64 A PA5 I/O (port) WRH output (BSC) -- (LBS output (BSC))*1 -- 58 63 A PA4 I/O (port) WRL output (BSC) (WR output (BSC))*1 -- -- 57 62 A PA3 I/O (port) CS7 output (BSC) WAIT input (BSC) -- 56 59 A PA2 I/O (port) CS6 output (BSC) TIOCB0 I/O (ITU) -- 55 58 A PA1 I/O (port) CS5 output (BSC) RAS output (BSC) -- 54 57 A PA0 I/O (port) CS4 output (BSC) TIOCA0 I/O (ITU) -- 53 56 B PB15 I/O (port) IRQ7 input (INTC) -- TP15 output (TPC) 2 3 B PB14 I/O (port) IRQ6 input (INTC) -- TP14 output (TPC) 1 2 B PB13 I/O (port) IRQ5 input (INTC) SCK1 I/O (SCI) TP13 output (TPC) 112 119 B PB12 I/O (port) IRQ4 input (INTC) SCK0 I/O (SCI) TP12 output (TPC) 111 118 B PB11 I/O (port) TxD1 output (SCI) TP11 output (TPC) -- 110 117 B PB10 I/O (port) RxD1 input (SCI) TP10 output (TPC) -- 109 116 Rev. 7.00 Jan 31, 2006 page 429 of 658 REJ09B0272-0700 Section 15 Pin Function Controller (PFC) Port Function 1 Function 2 (Related Module) (Related Module) Function 3 (Related Module) Function 4 (Related Module) Pin No. (PRQP0112 JA-A) Pin No. (PTQP0120 LA-A) B PB9 I/O (port) TxD0 output (SCI) TP9 output (TPC) -- 108 115 B PB8 I/O (port) RxD0 input (SCI) TP8 output (TPC) -- 107 114 B PB7 I/O (port) TCLKD input (ITU) TOCXB4 output (ITU) TP7 output (TPC) 105 112 B PB6 I/O (port) TCLKC input (ITU) TOCXA4 output (ITU) TP6 output (TPC) 104 111 B PB5 I/O (port) TIOCB4 I/O (ITU) TP5 output (TPC) -- 103 110 B PB4 I/O (port) TIOCA4 I/O (ITU) TP4 output (TPC) -- 102 109 B PB3 I/O (port) TIOCB3 I/O (ITU) TP3 output (TPC) -- 101 108 B PB2 I/O (port) TIOCA3 I/O (ITU) TP2 output (TPC) -- 100 107 B PB1 I/O (port) TIOCB2 I/O (ITU) TP1 output (TPC) -- 98 105 B PB0 I/O (port) TIOCA2 I/O (ITU) TP0 output (TPC) -- 97 103 C*2 PC7 input (port) AN7 input (A/D) -- -- 95 101 2 PC6 input (port) AN6 input (A/D) -- -- 94 100 C* 2 PC5 input (port) AN5 input (A/D) -- -- 93 99 C*2 PC4 input (port) AN4 input (A/D) -- -- 92 98 C*2 PC3 input (port) AN3 input (A/D) -- -- 90 96 C*2 PC2 input (port) AN2 input (A/D) -- -- 89 95 C*2 PC1 input (port) AN1 input (A/D) -- -- 88 94 C*2 PC0 input (port) AN0 input (A/D) -- -- 87 93 -- CS1 output (BSC) CASH output (BSC) -- -- 49 52 -- CS3 output (BSC) CASL output (BSC) -- -- 51 54 C* INTC: Interrupt controller DMAC: Direct memory access controller ITU: 16-bit integrated timer pulse unit D bus: Data bus control BSC: Bus state controller System: System control A/D: A/D converter SCI: Serial communication interface TPC: Programmable timing pattern controller Port: I/O port Notes: 1. The bus control register of the bus state controller handles switching between the two functions. 2. The function of port C pins automatically changes to analog input (AN0-AN7) when the A/D converter begins to operate. 3. The initial setting is DACK (output). Rev. 7.00 Jan 31, 2006 page 430 of 658 REJ09B0272-0700 Section 15 Pin Function Controller (PFC) 15.2 Register Configuration Table 15.2 summarizes the registers of the pin function controller. Table 15.2 Pin Function Controller Registers Name Abbreviation R/W Initial Value Address* Access Size Port A I/O register PAIOR R/W H'0000 H'5FFFFC4 8, 16, 32 Port A control register 1 PACR1 R/W H'3302 H'5FFFFC8 8, 16, 32 Port A control register 2 PACR2 R/W H'FF95 H'5FFFFCA 8, 16, 32 Port B I/O register PBIOR R/W H'0000 H'5FFFFC6 8, 16, 32 Port B control register 1 PBCR1 R/W H'0000 H'5FFFFCC 8, 16, 32 Port B control register 2 PBCR2 R/W H'0000 H'5FFFFCE 8, 16, 32 Column address strobe pin control register CASCR R/W H'5FFF H'5FFFFEE 8, 16, 32 Note: * Only the values of bits A27-A24 and A8-A0 are valid; bits A23-A9 are ignored. For details on the register addresses, see section 8.3.5, Area Descriptions. 15.3 Register Descriptions 15.3.1 Port A I/O Register (PAIOR) The port A I/O register (PAIOR) is a 16-bit read/write register that selects input or output for the 16 pins of port A. Bits PA15IOR-PA0IOR correspond to pins PA15/IRQ3/DREQ1- PA0/CS4/TIOCA0. PAIOR is enabled when the port A pins function as input/outputs (PA15- PA0) and for ITU input capture and output compare (TIOCA1, TIOCA0, TIOCB1, and TIOCB0). For other functions, they are disabled. For port A pin functions PA15-PA0 and TIOCA1, TIOCA0, TIOCB1, and TIOCB0, a given pin in port A is an output pin if its corresponding PAIOR bit is set to 1, and an input pin if the bit is cleared to 0. PAIOR is initialized to H'0000 by a power-on reset; however, it is not initialized by a manual reset, or in standby mode or sleep mode. Bit Initial value Read/Write 15 PA15 IOR 0 R/W 14 PA14 IOR 0 R/W 13 PA13 IOR 0 R/W 12 PA12 IOR 0 R/W 11 PA11 IOR 0 R/W 10 PA10 IOR 0 R/W 9 PA9 IOR 0 R/W 8 PA8 IOR 0 R/W Rev. 7.00 Jan 31, 2006 page 431 of 658 REJ09B0272-0700 Section 15 Pin Function Controller (PFC) Bit 7 PA7 IOR 0 R/W Initial value Read/Write 15.3.2 6 PA6 IOR 0 R/W 5 PA5 IOR 0 R/W 4 PA4 IOR 0 R/W 3 PA3 IOR 0 R/W 2 PA2 IOR 0 R/W 1 PA1 IOR 0 R/W 0 PA0 IOR 0 R/W Port A Control Registers (PACR1 and PACR2) PACR1 and PACR2 are 16-bit read/write registers that select the functions of the sixteen multiplexed pins of port A. PACR1 selects the function of the upper eight bits of port A; PACR2 selects the function of the lower eight bits of port A. PACR1 and PACR2 are initialized to H'3302 and H'FF95 respectively by a power-on reset but are not initialized by a manual reset, or in standby mode or sleep mode. PACR1: Bit 15 14 13 12 11 10 9 8 PA15 MD1 PA15 MD0 PA14 MD1 PA14 MD0 PA13 MD1 PA13 MD0 PA12 MD1 PA12 MD0 Initial value 0 0 1 1 0 0 1 1 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 PA11 MD1 PA11 MD0 PA10 MD1 PA10 MD0 PA9 MD1 PA9 MD0 -- PA8 MD Initial value 0 0 0 0 0 0 1 0 Read/Write R/W R/W R/W R/W R/W R/W -- R/W Bit Bits 15 and 14--PA15 Mode (PA15MD1 and PA15MD0): PA15MD1 and PA15MD0 select the function of the PA15/IRQ3/DREQ1 pin. Bit 15: PA15MD1 Bit 14: PA15MD0 Function 0 0 Input/output (PA15) 1 Interrupt request input (IRQ3) 0 Reserved 1 DMA transfer request input (DREQ1) 1 Rev. 7.00 Jan 31, 2006 page 432 of 658 REJ09B0272-0700 (Initial value) Section 15 Pin Function Controller (PFC) Bits 13 and 12--PA14 Mode (PA14MD1 and PA14MD0): PA14MD1 and PA14MD0 select the function of the PA14/IRQ2/DACK1 pin. Bit 13: PA14MD1 Bit 12: PA14MD0 Function 0 0 Input/output (PA14) 1 Interrupt request input (IRQ2) 1 0 Reserved 1 DMA transfer acknowledge output (DACK1) (Initial value) Bits 11 and 10--PA13 Mode (PA13MD1 and PA13MD0): PA13MD1 and PA13MD0 select the function of the PA13/IRQ1/DREQ0/TCLKB pin. Bit 11: PA13MD1 Bit 10: PA13MD0 Function 0 0 Input/output (PA13) 1 Interrupt request input (IRQ1) 0 ITU timer clock input (TCLKB) 1 DMA transfer request input (DREQ0) 1 (Initial value) Bits 9 and 8--PA12 Mode (PA12MD1 and PA12MD0): PA12MD1 and PA12MD0 select the function of the PA12/IRQ0/DACK0/TCLKA pin. Bit 9: PA12MD1 Bit 8: PA12MD0 Function 0 0 Input/output (PA12) 1 Interrupt request input (IRQ0) 0 ITU timer clock input (TCLKA) 1 DMA transfer acknowledge output (DACK0) 1 (Initial value) Rev. 7.00 Jan 31, 2006 page 433 of 658 REJ09B0272-0700 Section 15 Pin Function Controller (PFC) Bits 7 and 6--PA11 Mode (PA11MD1 and PA11MD0): PA11MD1 and PA11MD0 select the function of the PA11/DPH/TIOCB1 pin. Bit 7: PA11MD1 Bit 6: PA11MD0 Function 0 0 Input/output (PA11) 1 Upper data bus parity input/output (DPH) 1 0 ITU input capture/output compare (TIOCB1) 1 Reserved (Initial value) Bits 5 and 4--PA10 Mode (PA10MD1 and PA10MD0): PA10MD1 and MA10MD0 select the function of the PA10/DPL/TIOCA1 pin. Bit 5: PA10MD1 Bit 4: PA10MD0 Function 0 0 Input/output (PA10) 1 Lower data bus parity input/output (DPL) 0 ITU input capture/output compare (TIOCA1) 1 Reserved 1 (Initial value) Bits 3 and 2--PA9 Mode (PA9MD1 and PA9MD0): PA9MD1 and PA9MD0 select the function of the PA9/AH/IRQOUT/ADTRG pin. Bit 3: PA9MD1 Bit 2: PA9MD0 Function 0 0 Input/output (PA9) 1 Address hold output (AH) 0 A/D conversion trigger input (ADTRG) 1 Interrupt request output (IRQOUT) 1 (Initial value) Bit 1--Reserved: This bit is always read as 1. The write value should always be 1. Bit 0--PA8 Mode (PA8MD): PA8MD selects the function of the PA8/BREQ pin. Bit 0: PA8MD Function 0 Input/output (PA8) 1 Bus request input (BREQ) Rev. 7.00 Jan 31, 2006 page 434 of 658 REJ09B0272-0700 (Initial value) Section 15 Pin Function Controller (PFC) PACR2: Bit 15 14 13 12 11 10 9 8 -- PA7MD -- PA6MD -- PA5MD -- PA4MD Initial value 1 1 1 1 1 1 1 1 Read/Write -- R/W -- R/W -- R/W -- R/W 7 6 5 4 3 2 1 0 Bit PA3MD1 PA3MD0 PA2MD1 PA2MD0 PA1MD1 PA1MD0 PA0MD1 PA0MD0 Initial value 1 0 0 1 0 1 0 1 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Bit 15--Reserved: This bit is always read as 1. The write value should always be 1. Bit 14--PA7 Mode (PA7MD): PA7MD selects the function of the PA7/BACK pin. Bit 14: PA7MD Function 0 Input/output (PA7) 1 Bus request acknowledge output (BACK) (Initial value) Bit 13--Reserved: This bit is always read as 1. The write value should always be 1. Bit 12--PA6 Mode (PA6MD): PA6MD selects the function of the PA6/RD pin. Bit 12: PA6MD Function 0 Input/output (PA6) 1 Read output (RD) (Initial value) Bit 11--Reserved: This bit is always read as 1. The write value should always be 1. Bit 10--PA5 Mode (PA5MD): PA5MD selects the function of the PA5/WRH (LBS) pin. Bit 10: PA5MD Function 0 Input/output (PA5) 1 Upper write output (WRH) or lower byte strobe output (LBS) (Initial value) Bit 9--Reserved: This bit is alway read as 1. The write value should always be 1. Rev. 7.00 Jan 31, 2006 page 435 of 658 REJ09B0272-0700 Section 15 Pin Function Controller (PFC) Bit 8--PA4 Mode (PA4MD): PA4MD selects the function of the PA4/WRL (WR) pin. Bit 8: PA4MD Function 0 Input/output (PA4) 1 Lower write output (WRL) or write output (WR) (Initial value) Bits 7 and 6--PA3 Mode (PA3MD1 and PA3MD0): PA3MD1 and PA3MD0 select the function of the PA3/CS7/WAIT pin. This pin has a pull-up MOS that is used when it functions as a WAIT pin to allow selection of pull-up or no pull-up (for the WAIT pin) using the wait state control register of the bus state controller (BSC). There is no pull-up when it functions as PA3 or CS7. Bit 7: PA3MD1 Bit 6: PA3MD0 Function 0 0 Input/output (PA3) 1 Chip select output (CS7) 0 Wait state input (WAIT) 1 Reserved 1 (Initial value) Bits 5 and 4--PA2 Mode (PA2MD1 and PA2MD0): PA2MD1 and PA2MD0 select the function of the PA2/CS6/TIOCB0 pin. Bit 5: PA2MD1 Bit 4: PA2MD0 Function 0 0 Input/output (PA2) 1 Chip select output (CS6) 0 ITU input capture/output compare (TIOCB0) 1 Reserved 1 (Initial value) Bits 3 and 2--PA1 Mode (PA1MD1 and PA1MD0): PA1MD1 and PA1MD0 select the function of the PA1/CS5/RAS pin. Bit 3: PA1MD1 Bit 2: PA1MD0 Function 0 0 Input/output (PA1) 1 Chip select output (CS5) 0 Row address strobe output (RAS) 1 Reserved 1 Rev. 7.00 Jan 31, 2006 page 436 of 658 REJ09B0272-0700 (Initial value) Section 15 Pin Function Controller (PFC) Bits 1 and 0--PA0 Mode (PA0MD1 and PA0MD0): PA0MD1 and PA0MD0 select the function of the PA0/CS4/TIOCA0 pin. Bit 1: PA0MD1 Bit 0: PA0MD0 Function 0 0 Input/output (PA0) 1 Chip select output (CS4) 1 0 ITU input capture/output compare (TIOCA0) 1 Reserved 15.3.3 (Initial value) Port B I/O Register (PBIOR) The port A I/O register (PAIOR) is a 16-bit read/write register that selects input or output for the 16 pins of port A. Bits PB15IOR-PB0IOR correspond to pins of port B. PBIOR is enabled when the port B pins function as input/outputs (PB15-PB0), for ITU input capture and output compare (TIOCA4, TIOCA3, TIOCA2, TIOCB4, TIOCB3, and TIOCB2), and as serial clocks (SCK1, SCK0). For other functions, they are disabled. For port B pin functions PB15-PB0, and TIOCA4, TIOCA3, TIOCA2, TIOCB4, TIOCB3, and TIOCB2, and SCK1/SCK0, a given pin in port B is an output pin if its corresponding PBIOR bit is set to 1, and an input pin if the bit is cleared to 0. PBIOR is initialized to H'0000 by a power-on reset; however, it is not initialized by a manual reset, or in standby mode or sleep mode. Bit 15 14 13 12 11 10 9 8 PB15 IOR PB14 IOR PB13 IOR PB12 IOR PB11 IOR PB10 IOR PB9 IOR PB8 IOR Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 PB7 IOR PB6 IOR PB5 IOR PB4 IOR PB3 IOR PB2 IOR PB1 IOR PB0 IOR Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Bit Rev. 7.00 Jan 31, 2006 page 437 of 658 REJ09B0272-0700 Section 15 Pin Function Controller (PFC) 15.3.4 Port B Control Registers (PBCR1 and PBCR2) PBCR1 and PBCR2 are 16-bit read/write registers that select the functions of the sixteen multiplexed pins of port B. PBCR1 selects the function of the upper eight bits of port B; PBCR2 selects the function of the lower eight bits of port B. PBCR1 and PBCR2 are initialized to H'0000 by a power-on reset, but are not initialized by a manual reset, or in standby mode or sleep mode. PBCR1: Bit 15 14 13 12 11 10 9 8 PB15 MD1 PB15 MD0 PB14 MD1 PB14 MD0 PB13 MD1 PB13 MD0 PB12 MD1 PB12 MD0 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 PB11 MD1 PB11 MD0 PB10 MD1 PB10 MD0 PB9 MD1 PB9 MD0 PB8 MD1 PB8 MD0 Bit Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Bits 15 and 14--PB15 Mode (PB15MD1 and PB15MD0): PB15MD1 and PB15MD0 select the function of the PB15/TP15/IRQ7 pin. Bit 15: PB15MD1 Bit 14: PB15MD0 Function 0 0 Input/output (PB15) 1 Interrupt request input (IRQ7) 0 Reserved 1 Timing pattern output (TP15) 1 Rev. 7.00 Jan 31, 2006 page 438 of 658 REJ09B0272-0700 (Initial value) Section 15 Pin Function Controller (PFC) Bits 13 and 12--PB14 Mode (PB14MD1 and PB14MD0): PB14MD1 and PB14MD0 select the function of the PB14/TP14/IRQ6 pin. Bit 13: PB14MD1 Bit 12: PB14MD0 Function 0 0 Input/output (PB14) 1 Interrupt request input (IRQ6) 1 0 Reserved 1 Timing pattern output (TP14) (Initial value) Bits 11 and 10--PB13 Mode (PB13MD1 and PB13MD0): PB13MD1 and PB13MD0 select the function of the PB13/TP13/IRQ5/SCK1 pin. Bit 11: PB13MD1 Bit 10: PB13MD0 Function 0 0 Input/output (PB13) 1 Interrupt request input (IRQ5) 0 Serial clock input/output (SCK1) 1 Timing pattern output (TP13) 1 (Initial value) Bits 9 and 8--PB12 Mode (PB12MD1 and PB12MD0): PB12MD1 and PB12MD0 select the function of the PB12/TP12/IRQ4/SCK0 pin. Bit 9: PB12MD1 Bit 8: PB12MD0 Function 0 0 Input/output (PB12) 1 Interrupt request input (IRQ4) 0 Serial clock input/output (SCK0) 1 Timing pattern output (TP12) 1 (Initial value) Rev. 7.00 Jan 31, 2006 page 439 of 658 REJ09B0272-0700 Section 15 Pin Function Controller (PFC) Bits 7 and 6: PB11 Mode--PB11MD1 and PB11MD0): PB11MD1 and PB11MD0 select the function of the PB11/TP11/TxD1 pin. Bit 7: PB11MD1 Bit 6: PB11MD0 Function 0 0 1 Reserved 1 0 Transmit data output (TxD1) 1 Timing pattern output (TP11) Input/output (PB11) (Initial value) Bits 5 and 4--PB10 Mode (PB10MD1 and PB10MD0): PB10MD1 and PB10MD0 select the function of the PB10/TP10/RxD1 pin. Bit 5: PB10MD1 Bit 4: PB10MD0 Function 0 0 Input/output (PB10) 1 Reserved 0 Receive data input (RxD1) 1 Timing pattern output (TP10) 1 (Initial value) Bits 3 and 2--PB9 Mode (PB9MD1 and PB9MD0): PB9MD1 and PB9MD0 select the function of the PB9/TP9/TxD0 pin. Bit 3: PB9MD1 Bit 2: PB9MD0 Function 0 0 Input/output (PB9) 1 Reserved 0 Transmit data output (TxD0) 1 Timing pattern output (TP9) 1 Rev. 7.00 Jan 31, 2006 page 440 of 658 REJ09B0272-0700 (Initial value) Section 15 Pin Function Controller (PFC) Bits 1 and 0--PB8 Mode (PB8MD1 and PB8MD0): PB8MD1 and PB8MD0 select the function of the PB8/TP8/RxD0 pin. Bit 1: PB8MD1 Bit 0: PB8MD0 Function 0 0 Input/output (PB8) 1 Reserved 1 0 Receive data input (RxD0) 1 Timing pattern output (TP8) (Initial value) PBCR2: Bit 15 14 13 12 11 10 9 8 PB7MD1 PB7MD0 PB6MD1 PB6MD0 PB5MD1 PB5MD0 PB4MD1 PB4MD0 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 Bit PB3MD1 PB3MD0 PB2MD1 PB2MD0 PB1MD1 PB1MD0 PB0MD1 PB0MD0 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Bits 15 and 14--PB7 Mode (PB7MD1 and PB7MD0): PB7MD1 and PB7MD0 select the function of the PB7/TP7/TOCXB4/TCLKD pin. Bit 15: PB7MD1 Bit 14: PB7MD0 Function 0 0 Input/output (PB7) 1 ITU timer clock input (TCLKD) 0 ITU output compare (TOCXB4) 1 Timing pattern output (TP7) 1 (Initial value) Rev. 7.00 Jan 31, 2006 page 441 of 658 REJ09B0272-0700 Section 15 Pin Function Controller (PFC) Bits 13 and 12--PB6 Mode (PB6MD1 and PB6MD0): PB6MD1 and PB6MD0 select the function of the PB6/TP6/TOCXA4/TCLKC pin. Bit 13: PB6MD1 Bit 12: PB6MD0 Function 0 0 Input/output (PB6) 1 ITU timer clock input (TCLKC) 1 0 ITU output compare (TOCXA4) 1 Timing pattern output (TP6) (Initial value) Bits 11 and 10--PB5 Mode (PB5MD1 and PB5MD0): PB5MD1 and PB5MD0 select the function of the PB5/TP5/TIOCB4 pin. Bit 11: PB5MD1 Bit 10: PB5MD0 Function 0 0 Input/output (PB5) 1 Reserved 0 ITU input capture/output compare (TIOCB4) 1 Timing pattern output (TP5) 1 (Initial value) Bits 9 and 8--PB4 Mode (PB4MD1 and PB4MD0): PB4MD1 and PB4MD0 select the function of the PB4/TP4/TIOCA4 pin. Bit 9: PB4MD1 Bit 8: PB4MD0 Function 0 0 Input/output (PB4) 1 Reserved 0 ITU input capture/output compare (TIOCA4) 1 Timing pattern output (TP4) 1 Rev. 7.00 Jan 31, 2006 page 442 of 658 REJ09B0272-0700 (Initial value) Section 15 Pin Function Controller (PFC) Bits 7 and 6--PB3 Mode (PB3MD1 and PB3MD0): PB3MD1 and PB3MD0 select the function of the PB3/TP3/TIOCB3 pin. Bit 7: PB3MD1 Bit 6: PB3MD0 Function 0 0 Input/output (PB3) 1 Reserved 1 0 ITU input capture/output compare (TIOCB3) 1 Timing pattern output (TP3) (Initial value) Bits 5 and 4--PB2 Mode (PB2MD1 and PB2MD0): PB2MD1 and PB2MD0 select the function of the PB2/TP2/TIOCA3 pin. Bit 5: PB2MD1 Bit 4: PB2MD0 Function 0 0 Input/output (PB2) 1 Reserved 0 ITU input capture/output compare (TIOCA3) 1 Timing pattern output (TP2) 1 (Initial value) Bits 3 and 2--PB1 Mode (PB1MD1 and PB1MD0): PB1MD1 and PB1MD0 select the function of the PB1/TP1/TIOCB2 pin. Bit 3: PB1MD1 Bit 2: PB1MD0 Function 0 0 Input/output (PB1) 1 Reserved 0 ITU input capture/output compare (TIOCB2) 1 Timing pattern output (TP1) 1 (Initial value) Rev. 7.00 Jan 31, 2006 page 443 of 658 REJ09B0272-0700 Section 15 Pin Function Controller (PFC) Bits 1 and 0--PB0 Mode (PB0MD1 and PB0MD0): PB0MD1 and PB0MD0 select the function of the PB0/TP0/TIOCA2 pin. Bit 1: PB0MD1 Bit 0: PB0MD0 Function 0 0 Input/output (PB0) 1 Reserved 1 0 ITU input capture/output compare (TIOCA2) 1 Timing pattern output (TP0) 15.3.5 (Initial value) Column Address Strobe Pin Control Register (CASCR) CASCR is a 16-bit read/write register that allows selection between column address strobe and chip select pin functions. CASCR is initialized to H'5FFF by a power-on reset, but is not initialized by a manual reset, or in standby mode or sleep mode. Bit 15 14 13 12 11 10 9 8 CASH MD1 CASH MD0 CASL MD1 CASL MD0 -- -- -- -- Initial value 0 1 0 1 1 1 1 1 Read/Write R/W R/W R/W R/W -- -- -- -- 7 6 5 4 3 2 1 0 -- -- -- -- -- -- -- -- Initial value 1 1 1 1 1 1 1 1 Read/Write -- -- -- -- -- -- -- -- Bit Bits 15 and 14--CASH Mode (CASHMD1 and CASHMD0): CASHMD1 and CASHMD0 select the function of the CS1/CASH pin. Bit 15: Bit 14: CASHMD1 CASHMD0 Function 0 0 Reserved 1 Chip select output (CS1) 0 Column address strobe output (CASH) 1 Reserved 1 Rev. 7.00 Jan 31, 2006 page 444 of 658 REJ09B0272-0700 (Initial value) Section 15 Pin Function Controller (PFC) Bits 13 and 12--CASL Mode (CASLMD1 and CASLMD0): CASLMD1 and CASLMD0 select the function of the CS3/CASL pin. Bit 13: CASLMD1 Bit 12: CASLMD0 Function 0 0 Reserved 1 Chip select output (CS3) 1 0 Column address strobe output (CASL) 1 Reserved (Initial value) Bits 11-0--Reserved: These bits are always read as 1. The write value should always be 1. Rev. 7.00 Jan 31, 2006 page 445 of 658 REJ09B0272-0700 Section 15 Pin Function Controller (PFC) Rev. 7.00 Jan 31, 2006 page 446 of 658 REJ09B0272-0700 Section 16 I/O Ports (I/O) Section 16 I/O Ports (I/O) 16.1 Overview There are three ports, A, B, and C. Ports A and B are 16-bit I/O ports, while port C is an 8-bit input port. The pins of the ports are all multiplexed for use as general-purpose I/Os (or inputs in the case of port C) or for other functions. (Use the pin function controller (PFC) to select the function of multiplexed pins.) Ports A, B, and C each have one data register for storing pin data. 16.2 Port A Port A is a 16-pin input/output port, as shown in figure 16.1. The PA3/CS7/WAIT pin of port A has a pull-up MOS so that when it is functioning as a WAIT pin, the wait state control register of the bus state controller can be used to select whether to pull up the WAIT pin or not. It is not pulled up when the pin is functioning as either PA3 or CS7. Port A PA15 (Input/output)/IRQ3 (Input)/DREQ1 (Input) PA14 (Input/output)/IRQ2 (Input)/DACK1 (Output) PA13 (Input/output)/IRQ1 (Input)/DREQ0 (Input)/TCLKB (Input) PA12 (Input/output)/IRQ0 (Input)/DACK0 (Output)/TCLKA (Input) PA11 (Input/output)/DPH (Input/output)/TIOCB1 (Input/output) PA10 (Input/output)/DPL (Input/output)/TIOCA1 (Input/output) PA9 (Input/output)/AH (Output)/IRQOUT (Output)/ADTRG (Input) PA8 (Input/output)/BREQ (Input) PA7 (Input/output)/BACK (Output) PA6 (Input/output)/RD (Output) PA5 (Input/output)/WRH (Output) (LBS (Output)) PA4 (Input/output)/WRL (Output) (WR (Output)) PA3 (Input/output)/CS7 (Output)/WAIT (Input) PA2 (Input/output)/CS6 (Output)/TIOCB0 (Input/output) PA1 (Input/output)/CS5 (Output)/RAS (Output) PA0 (Input/output)/CS4 (Output)/TIOCA0 (Input/output) Figure 16.1 Port A Configuration 16.2.1 Register Configuration Table 16.1 summarizes the port A register. Rev. 7.00 Jan 31, 2006 page 447 of 658 REJ09B0272-0700 Section 16 I/O Ports (I/O) Table 16.1 Port A Register Name Abbreviation R/W Initial Value Address* Access Size Port A data register PADR R/W H'0000 H'5FFFFC0 8, 16, 32 Note: * Only the values of bits A27-A24 and A8-A0 are valid; bits A23-A9 are ignored. For details on the register addresses, see section 8.3.5, Area Descriptions. 16.2.2 Port A Data Register (PADR) PADR is a 16-bit read/write register that stores data for port A. Bits PA15DR-PA0DR correspond to the PA15/IRQ3/DREQ1-PA0/CS4/TIOCA0 pins. When the pins are used as ordinary outputs, they will output whatever value is written in PADR; when PADR is read, the register value will be output regardless of the pin status. When the pins are used as ordinary inputs, the pin status rather than the register value is read directly when PADR is read. When a value is written to PADR, that value can be written into PADR, but it will not affect the pin status. Table 16.2 shows port A data register read/write operations. PADR is initialized by a power-on reset. However, PADR is not initialized by a manual reset, or in standby mode or sleep mode. Bit 15 14 13 12 11 10 9 PA15DR PA14DR PA13DR PA12DR PA11DR PA10DR PA9DR 8 PA8DR Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 PA7DR PA6DR PA5DR PA4DR PA3DR PA2DR PA1DR PA0DR Bit Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Table 16.2 Port A Data Register (PADR) Read/Write Operations PAIOR Pin Status Read Write 0 Input Pin status Can write to PADR, but it has no effect on pin status. Other function Pin status Can write to PADR, but it has no effect on pin status. Output PADR value Value written is output by pin Other function PADR value Can write to PADR, but it has no effect on pin status. 1 Rev. 7.00 Jan 31, 2006 page 448 of 658 REJ09B0272-0700 Section 16 I/O Ports (I/O) 16.3 Port B Port B is a 16-bit input/output port as shown in figure 16.2. Port B PB15 (Input/output)/TP15 (Output)/IRQ7 (Input) PB14 (Input/output)/TP14 (Output)/IRQ6 (Input) PB13 (Input/output)/TP13 (Output)/IRQ5 (Input)/SCK1 (Input/output) PB12 (Input/output)/TP12 (Output)/IRQ4 (Input)/SCK0 (Input/output) PB11 (Input/output)/TP11 (Output)/TxD1 (Output) PB10 (Input/output)/TP10 (Output)/RxD1 (Input) PB9 (Input/output)/TP9 (Output)/TxD0 (Output) PB8 (Input/output)/TP8 (Output)/RxD0 (Input) PB7 (Input/output)/TP7 (Output)/TOCXB4 (Output)/TCLKD (Input) PB6 (Input/output)/TP6 (Output)/TOCXA4 (Output)/TCLKC (Input) PB5 (Input/output)/TP5 (Output)/TIOCB4 (Input/output) PB4 (Input/output)/TP4 (Output)/TIOCA4 (Input/output) PB3 (Input/output)/TP3 (Output)/TIOCB3 (Input/output) PB2 (Input/output)/TP2 (Output)/TIOCA3 (Input/output) PB1 (Input/output)/TP1 (Output)/TIOCB2 (Input/output) PB0 (Input/output)/TP0 (Output)/TIOCA2 (Input/output) Figure 16.2 Port B Configuration 16.3.1 Register Configuration Table 16.3 summarizes the port B register. Table 16.3 Port B Register Name Abbreviation R/W Initial Value Address* Access Size Port B data register PBDR R/W H'0000 H'5FFFFC2 8, 16, 32 Note: * Only the values of bits A27-A24 and A8-A0 are valid; bits A23-A9 are ignored. For details on the register addresses, see section 8.3.5, Area Descriptions. Rev. 7.00 Jan 31, 2006 page 449 of 658 REJ09B0272-0700 Section 16 I/O Ports (I/O) 16.3.2 Port B Data Register (PBDR) PBDR is a 16-bit read/write register that stores data for port B. Bits PB15DR-PB0DR correspond to the PB15/TP15/IRQ7-PB0/TP0/TIOCA2 pins. When the pins are used as ordinary outputs, they will output whatever value is written in PBDR; when PBDR is read, the register value will be output regardless of the pin status. When the pins are used as ordinary inputs, the pin status rather than the register value is read directly when PBDR is read. When a value is written to PBDR, that value can be written into PBDR, but it will not affect the pin status. When the pin function is set to timing pattern output and the TPC output is enabled by the TPC next data enable register (NDER), no value can be written to PBDR. Table 16.4 shows port B data register read/write operations. PBDR is initialized by a power-on reset. However, PBDR is not initialized by a manual reset, or in standby mode or sleep mode. Bit 15 14 13 12 11 10 9 PB15DR PB14DR PB13DR PB12DR PB11DR PB10DR PB9DR 8 PB8DR Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Bit 7 6 5 4 3 2 1 0 PB7DR PB6DR PB5DR PB4DR PB3DR PB2DR PB1DR PB0DR Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Table 16.4 Port B Data Register (PBDR) Read/Write Operations PBIOR Pin Status Read Write 0 Input Pin status Can write to PBDR, but it has no effect on pin status TPn Pin status Disabled Other function Pin status Can write to PBDR, but it has no effect on pin status Output PBDR value Value written is output by pin TPn PBDR value Disabled Other function PBDR value Can write to PBDR, but it has no effect on pin status 1 TPn: Timing pattern output Rev. 7.00 Jan 31, 2006 page 450 of 658 REJ09B0272-0700 Section 16 I/O Ports (I/O) 16.4 Port C Port C is an eight-bit input port as shown in figure 16.3. PC7 (Input)/AN7 (Input) PC6 (Input)/AN6 (Input) PC5 (Input)/AN5 (Input) PC4 (Input)/AN4 (Input) Port C PC3 (Input)/AN3 (Input) PC2 (Input)/AN2 (Input) PC1 (Input)/AN1 (Input) PC0 (Input)/AN0 (Input) Figure 16.3 Port C Configuration 16.4.1 Register Configuration Table 16.5 summarizes the port C register. Table 16.5 Port C Register Name Abbreviation R/W Initial Value Address* Access Size Port C data register PCDR R/W -- H'5FFFFD0 8, 16, 32 Note: * Only the values of bits A27-A24 and A8-A0 are valid; bits A23-A9 are ignored. For details on the register addresses, see section 8.3.5, Area Descriptions. Rev. 7.00 Jan 31, 2006 page 451 of 658 REJ09B0272-0700 Section 16 I/O Ports (I/O) 16.4.2 Port C Data Register (PCDR) PCDR is an 16-bit read-only register that stores data for port C (writes to bits 15-8 are ignored, and the read value is always undefined). Bits PC7DR-PC0DR correspond to the PC7/AN7- PC0/AN0 pins respectively. Any values written to these bits will be ignored and will not affect the pin status. When the bits are read, the pin status rather than the bit value is read directly. When analog input of the A/D converter is being sampled, however, every bit is read as 1. Table 16.6 shows port C data register read/write operations (bits 7-0). PCDR is not initialized by a power-on reset or manual reset, or in standby mode or sleep mode (bits 15-8 are always undefined; bits 7-0 always reflect the pin status). Bit 15 14 13 12 11 10 9 8 -- -- -- -- -- -- -- -- Initial value -- -- -- -- -- -- -- -- Read/Write R R R R R R R R Bit 7 6 5 4 3 2 1 0 PC7DR PC6DR PC5DR PC4DR PC3DR PC2DR PC1DR PC0DR Initial value -- -- -- -- -- -- -- -- Read/Write R R R R R R R R Table 16.6 Port C Data Register (PCDR) Read/Write Operations Pin I/O Pin Function Read Write Input General purpose Pin status read Ignored (no effect on pin status) ANn Read as 1 Ignored (no effect on pin status) ANn: Analog input Rev. 7.00 Jan 31, 2006 page 452 of 658 REJ09B0272-0700 Section 17 ROM Section 17 ROM 17.1 Overview The SH7034 microcomputer has 64 kbytes of on-chip ROM (mask ROM or PROM). The on-chip ROM is connected to the CPU and the direct memory access controller (DMAC) through a 32-bit data bus (figure 17.1). The CPU can access the on-chip ROM in 8-, 16- and 32-bit widths and the DMAC can access the ROM in 8- and 16-bit widths. Data in the on-chip ROM can always be accessed in one cycle. Internal data bus (32 bits) H'0000000 H'0000001 H'0000002 H'0000003 H'0000004 H'0000005 H'0000006 H'0000007 On-chip ROM H'000FFFC Note: H'000FFFD H'000FFFE H'000FFFF The addresses shown in the figure are the uppermost shadow addresses in the on-chip ROM space. Figure 17.1 Block Diagram of ROM The operating mode determines whether the on-chip ROM is valid or not. The operating mode is selected using mode-setting pins MD0-MD2 as shown in table 17.1. When using the on-chip ROM, select mode 2; otherwise, select mode 0 or 1. The on-chip ROM is allocated to addresses H'0000000-H'000FFFF of memory area 0. Memory area 0 (H'0000000-H'0FFFFFF and H'8000000-H'8FFFFFF) is divided into 64-kbyte shadows. No matter which shadow is accessed, the on-chip ROM is accessed. See section 8, Bus State Controller (BSC), for more information on shadows. Rev. 7.00 Jan 31, 2006 page 453 of 658 REJ09B0272-0700 Section 17 ROM Table 17.1 Operating Modes and ROM Mode Setting Pins Operating Mode MD2 MD1 MD0 Area 0 Mode 0 (MCU mode 0) 0 0 0 On-chip ROM disabled, external 8-bit space Mode 1 (MCU mode 1) 0 0 1 On-chip ROM disabled, external 16-bit space Mode 2 (MCU mode 2) 0 1 0 On-chip ROM enabled Mode 7 (PROM mode) 1 1 1 -- 0: Low 1: High When the SH7034 is set to PROM mode, programs can be written in the PROM version in the same way as with ordinary EPROM, using a general-purpose EPROM programmer. 17.2 PROM Mode 17.2.1 Setting PROM Mode To program the on-chip PROM, set the pins as shown in figure 17.2 and use the chip in PROM mode. 17.2.2 Socket Adapter Pin Correspondence and Memory Map Mount the socket adapter on the SH7034 as shown in figure 17.2. This allows the on-chip PROM to be programmed in exactly the same way as ordinary 32-pin EPROMs (HN27C101). Figure 17.2 shows the correspondence between SH7034 pins and HN27C101 pins. Figure 17.3 shows the memory map of the on-chip ROM. The address range of the HN27C101 (128 kbytes) is H'00000-H'1FFFF. The on-chip PROM (64 kbytes) is not found in the latter half (H'10000-H'1FFFF). When programming with a PROM programmer, the program address range must be set to H'0000- H'FFFF. The data for the H'10000-H'1FFFF address area should all be H'FF. Set byte mode, not page mode. Rev. 7.00 Jan 31, 2006 page 454 of 658 REJ09B0272-0700 Section 17 ROM SH7034 Pin Number Pin Name VPP 77 76 NMI 4 AD0 5 AD1 6 AD2 7 AD3 8 AD4 9 AD5 10 AD6 11 AD7 23 A0/HBS 24 A1 25 A2 26 A3 27 A4 28 A5 29 A6 30 A7 32 A8 33 A9 34 A10 35 A11 36 A12 37 A13 38 A14 39 A15 41 A16 55 PA2/CS6/TIOCB0 56 PA3/CS7/WAIT 42 A17 44 A18 VCC 15, 43, 70, 75, 83, 84, 99 80 MD0 81 MD1 82 MD2 AVCC, AVref 85, 86 79 RES 3, 12, 22, 31, 40, VSS 52, 61, 72, 96, 106 87-90, 92-95 PC0/AN0-PC3/AN3 PC4/AN4-PC7/AN7 AVSS 91 Pins other than the above NC (leave open) EPROM Socket HN27C101 Adapter Pin Name Pin Number VPP 1 A9 26 I/O0 13 I/O1 14 I/O2 15 I/O3 17 I/O4 18 I/O5 19 I/O6 20 I/O7 21 A0 12 A1 11 A2 10 A3 9 A4 8 A5 7 A6 6 A7 5 A8 27 OE 24 A10 23 A11 25 A12 4 A13 28 A14 29 A15 3 A16 2 PGM 31 CE 22 VCC 32 VSS 16 * VPP: PROM program power adapter (12.5 V) * A16-A0: Address input * I/O7-I/O0: Data input/ output * OE: Output enable * PGM: Program enable * CE: Chip enable Figure 17.2 Correspondence Between SH7034 Pins and HN27C101 Pins Rev. 7.00 Jan 31, 2006 page 455 of 658 REJ09B0272-0700 Section 17 ROM Addresses in MCU modes 0, 1, and 2* Addresses in PROM mode H'0000000 H'0000 On-chip ROM space (area 0) H'000FFFF H'FFFF Note: * Addresses in the figure are the uppermost shadow addresses of the on-chip ROM space. Figure 17.3 Memory Map of On-chip ROM 17.3 PROM Programming The write/verify specifications in PROM mode are the same as for the standard EPROM HN27C101. Page programming is not supported, so do not set the PROM programmer to page programming mode. Naturally, PROM programmers that only support page programming mode cannot be used. When selecting a PROM programmer, check that the byte-by-byte high-speed, high-reliability programming method is supported. 17.3.1 Selecting the Programming Mode There are two on-chip PROM programming modes: write and verify (which reads and confirms the data written). Use the pins to select the modes (table 17.2). Rev. 7.00 Jan 31, 2006 page 456 of 658 REJ09B0272-0700 Section 17 ROM Table 17.2 Selecting PROM Programming Mode Pin Mode CE OE PGM VPP VCC I/O7-I/O0 A16-A0 Write 0 1 0 VPP VCC Data input Address input Verify 0 0 1 Data output Program inhibit 0 0 0 High impedance 0 1 1 1 0 0 1 1 1 Legend: 0: Low 1: High VPP: VPP level VCC: VCC level 17.3.2 Write/Verify and Electrical Characteristics Write/Verify: Write/verify can be accomplished by an efficient high-speed, high-reliability programming method. This method can write data quickly and accurately without placing voltage stress on the device. The basic flowchart for this high-speed, high-reliability programming method is shown in figure 17.4. Rev. 7.00 Jan 31, 2006 page 457 of 658 REJ09B0272-0700 Section 17 ROM Start Set EPROM programmer to write/verify mode (VCC = 6.0 V 0.25 V, VPP = 12.5 V 0.3 V) Address = 0 n=0 n+1n No Yes Data write (tPW = 0.2 ms 5%) n = 25? No Address + 1 Address Verify result OK? Yes Data write (tOPW = 0.2 n ms) Final address? No Yes Set EPROM programmer to read mode (VCC = 5.0 V 0.25 V, VPP = VCC) No good VCC: VPP: tPW: tOPW: Power supply PROM program power supply Initial programming pulse width Overprogramming pulse width No Results of reading all address OK? Yes End Figure 17.4 Basic Flowchart of High-Speed, High-Reliability Programming Rev. 7.00 Jan 31, 2006 page 458 of 658 REJ09B0272-0700 Section 17 ROM Electrical Characteristics: Tables 17.3 and 17.4 show the electrical characteristics of programming. Figure 17.5 shows the timing. Table 17.3 DC Characteristics (VCC = 6.0 V 0.25 V, VPP = 12.5 0.3 V, VSS = 0 V, Ta = 25 5uC) Item Pins Symbol Min Typ Max Unit Input high voltage I/O7-I/O0, A16-A0, OE, CE, PGM VIH 2.4 -- VCC + 0.3 V Test Conditions Input low voltage I/O7-I/O0, A16-A0, OE, CE, PGM VIL -0.3 -- 0.8 V Output high voltage I/O7-I/O0 VOH 2.4 -- -- V IOH = -200 A Output low voltage I/O7-I/O0 VOL -- -- 0.45 V IOL = 1.6 mA Input leakage current I/O7-I/O0, A16-A0, OE, CE, PGM |ILI| -- -- 2 A VIN = 5.25 V/0.5 V VCC current ICC -- -- 40 mA VPP current IPP -- -- 40 mA Rev. 7.00 Jan 31, 2006 page 459 of 658 REJ09B0272-0700 Section 17 ROM Table 17.4 AC Characteristics (VCC = 6.0 V 0.25 V, VPP = 12.5 0.3 V, VSS = 0 V, Ta = 25 5uC) Item Symbol Min Typ Max Unit Test Conditions Address setup time tAS 2 -- -- s Figure 17.5* OE setup time tOES 2 -- -- s Data setup time tDS 2 -- -- s Address hold time tAH 0 -- -- s Data hold time tDH 2 -- -- s 2 Data output disable time tDF* -- -- 130 ns VPP setup time tVPS 2 -- -- s PGM pulse width in initial programming tPW 0.19 0.20 0.21 ms 3 tOPW * 0.19 -- 5.25 ms VCC setup time tVCS 2 -- -- s CE setup time tCES 2 -- -- s Data output delay time tOE 0 -- 150 ns PGM pulse width in overprogramming Notes: 1. Input pulse level: 0.45-2.4 V Input rise, fall time 20 ns Input timing reference levels: 0.8 V, 2.0 V Output timing reference levels: 0.8 V, 2.0 V 2. tDF is defined at the point where the output is in the open state and the output level cannot be referenced. 3. tOPW is defined by the value given in the flowchart. Rev. 7.00 Jan 31, 2006 page 460 of 658 REJ09B0272-0700 1 Section 17 ROM Write Verify Address tAS tAH Write data Data VPP VCC Read data tDF tDH tDS VPP VCC tVPS VCC + 1 VCC tVCS CE tCES PGM tPW OE tOES tOE (tOPW)* Note: * tOPW is defined by the value given in the flowchart. Figure 17.5 Write/Verify Timing 17.3.3 Notes on Writing 1. Always write using the prescribed voltage and timing. The write voltage (programming voltage) VPP is 12.5 V (when the EPROM programmer is set to the Renesas specifications for HN27C101, VPP is 12.5 V.) Applying a voltage in excess of the rated voltage may damage the device. Pay particular attention to overshoot in the EPROM programmer. 2. Before programming, always check that the index marks on the EPROM programmer socket, socket adapter, and device are aligned with each other. If they are not correctly aligned, an overcurrent may be generated, damaging the device. 3. Do not touch the socket adapter or device during writing. Contact can cause malfunctions that will prevent data from being written accurately. Rev. 7.00 Jan 31, 2006 page 461 of 658 REJ09B0272-0700 Section 17 ROM 4. Page programming mode cannot be used. Always set the equipment to byte programming mode. 5. The capacity of the on-chip ROM is 64 kbytes, so the data of PROM programmer addresses H'10000-H'1FFFF should be H'FF. Always set the range for PROM addresses to H'0000- H'FFFF. 6. When write errors occur on consecutive addresses, stop writing. Check to see if there are any abnormalities in the EPROM programmer and socket adapter. 17.3.4 Reliability after Writing After programming, it is recommended that the device be left to stand at a high temperature to increase the reliability of data retention. Letting it stand at a high temperature is a type of screening method that can eliminate of initial data retention defects of the on-chip PROM's memory cells within a short period of time. Figure 17.6 shows the flow from programming of the on-chip PROM, including screening, to mounting on the device board. Writing and verification of program Flowchart from figure 17.4 Let stand in nonconductive, high temperature environment (125-150C, 24-48 hours) Data read and verification (VCC = 5.0 V) Mount on board Figure 17.6 Screening Flow If abnormalities are found when the program is written and verified or the program is read and checked after writing/verification or letting the chip stand at high temperature, contact Renesas' engineering department. Rev. 7.00 Jan 31, 2006 page 462 of 658 REJ09B0272-0700 Section 18 RAM Section 18 RAM 18.1 Overview The SH7032 microcomputer has 8-kbytes of on-chip RAM; the SH7034 has 4 kbytes. The on-chip RAM is linked to the CPU and direct memory access controller (DMAC) with a 32-bit data bus (figure 18.1). The CPU can access data in the on-chip RAM in byte, word, or longword units. The DMAC can access byte or word data. On-chip RAM data can always be accessed in one state, making the RAM ideal for use as a program area, stack area, or data area, which require highspeed access. The contents of the on-chip RAM are held in both the sleep and standby modes. Memory area 7 addresses H'FFFE000 to H'FFFFFFF are allocated to the on-chip RAM in the SH7032. In the SH7034, addresses H'FFFF000 to H'FFFFFFF are allocated. Rev. 7.00 Jan 31, 2006 page 463 of 658 REJ09B0272-0700 Section 18 RAM SH7032 Internal data bus (32 bits) H'FFFE000 H'FFFE001 H'FFFE002 H'FFFE003 H'FFFE004 H'FFFE005 H'FFFE006 H'FFFE007 On-chip RAM H'FFFFFFC H'FFFFFFD H'FFFFFFE H'FFFFFF Note: Addresses in the figure are the lowest shadow addresses in on-chip RAM space. SH7034 Internal data bus (32 bits) H'FFFF000 H'FFFF001 H'FFFF002 H'FFFF003 H'FFFF004 H'FFFF005 H'FFFF006 H'FFFF007 On-chip RAM H'FFFFFFC H'FFFFFFD H'FFFFFFE H'FFFFFFF Note: Addresses in the figure are the lowest shadow addresses in on-chip RAM space. Figure 18.1 Block Diagram of RAM 18.2 Operation Accesses to addresses H'FFFE000-H'FFFFFFF (SH7032) or addresses H'FFFF000-H'FFFFFFF (SH7034) are directed to the on-chip RAM. Memory area 7 (H'F000000-H'FFFFFFF) is divided into shadows in 8 kbyte units for the SH7032 and 4-kbyte units for the SH7034. All shadow accesses are on-chip RAM accesses. For more information on shadows, see section 8, Bus State Controller (BSC). Rev. 7.00 Jan 31, 2006 page 464 of 658 REJ09B0272-0700 Section 19 Power-Down State Section 19 Power-Down State 19.1 Overview In the power-down state, all CPU functions are halted. This lowers power consumption of the SH microprocessor dramatically. 19.1.1 Power-Down Modes The power-down state includes the following two modes: 1. Sleep mode 2. Standby mode Sleep mode and standby mode are entered from the program execution state according to the transition conditions given in table 19.1. Table 19.1 also describes procedures for exiting each mode and the states of the CPU and supporting functions. Table 19.1 Power-Down State State Mode Sleep mode Entering Procedure Clock Execute SLEEP Runs instruction with SBY bit set to 0 in SBYCR Standby Execute SLEEP Halted mode instruction with SBY bit set to 1 in SBYCR Supporting CPU Functions Registers RAM I/O Ports Exiting Procedure CPU Halted Run Held * Interrupt * DMA address error * Power-on reset * Manual reset Held or * high-Z*2 * NMI interrupt * Manual reset Halted Held 1 Halted* Held Held Held Power-on reset SBYCR: Standby control register SBY: Standby bit Notes: 1. Some of the registers of the on-chip supporting modules are not initialized in standby mode. For details, see table 19.3, Register States in Standby Mode, in section 19.4.1, Transition to Standby Mode, or the descriptions of registers given where the on-chip supporting modules are covered. 2. The status of I/O ports in standby mode are set by the port high-impedance bit (HIZ) in SBYCR. See section 19.2, Standby Control Register (SBYCR), for details. The status of pins other than the I/O ports are described in appendix B, Pin States. Rev. 7.00 Jan 31, 2006 page 465 of 658 REJ09B0272-0700 Section 19 Power-Down State 19.1.2 Register Table 19.2 summarizes the register related to the power-down state. Table 19.2 Standby Control Register (SBYCR) Name Abbreviation R/W Initial Value Address* Access size Standby control register SBYCR R/W H'1F 8, 16, 32 H'5FFFFBC Note: * Only the values of bits A27-A24 and A8-A0 are valid; bits A23-A9 are ignored. For details on the register addresses, see section 8.3.5, Area Descriptions. 19.2 Standby Control Register (SBYCR) The standby control register (SBYCR) is an 8-bit read/write register. It is used to enter standby mode and also sets the port states in standby mode. SBYCR is initialized to H'1F by a reset. Bit 7 6 5 4 3 2 1 0 SBY HIZ -- -- -- -- -- -- Initial value 0 0 0 1 1 1 1 1 Read/Write R/W R/W -- -- -- -- -- -- Bit 7 Standby (SBY): SBY enables transition to standby mode. The SBY bit cannot be set to 1 while the timer enable bit (bit TME) in timer control/status register TCSR of the watchdog timer (WDT) is set to 1. To enter standby mode, clear the TME bit to 0 to halt the WDT and then set the SBY bit. SBY Description 0 Executing SLEEP instruction puts the chip into sleep mode 1 Executing SLEEP instruction puts the chip into standby mode (Initial value) Bit 6 Port High-Impedance (HIZ): HIZ selects whether I/O ports remain in their previous states during standby, or are placed in the high-impedance state when standby mode is entered. The HIZ bit cannot be set to 1 while the TME bit is set to 1. To place the pins of the I/O ports in high impedance, clear the TME bit to 0 before setting the HIZ bit. HIZ Description 0 Port states are maintained during standby 1 Ports are placed in the high-impedance state in standby Rev. 7.00 Jan 31, 2006 page 466 of 658 REJ09B0272-0700 (Initial value) Section 19 Power-Down State Bits 5-0 Reserved: Bit 5 is a read-only bit that is always read as 0. Only write 0 in bit 5. Writing to bits 4-0 is disabled. These bits are always read as 1. 19.3 Sleep Mode 19.3.1 Transition to Sleep Mode Execution of the SLEEP instruction when the standby bit (SBY) in the standby control register (SBYCR) is cleared to 0 causes a transition from the program execution state to sleep mode. Although the CPU halts immediately after executing the SLEEP instruction, the contents of its internal registers remain unchanged. The on-chip supporting modules do not halt in sleep mode. 19.3.2 Exiting Sleep Mode Sleep mode is exited by an interrupt, DMA address error, power-on reset, or manual reset. Exit by Interrupt: When an interrupt occurs, sleep mode is exited and interrupt exception handling is executed. Sleep mode is not exited if the interrupt cannot be accepted because its priority level is equal to or less than the mask level set in the CPU's status register (SR). Likewise, sleep mode is not exited if the interrupt is disabled by the on-chip supporting module. Exit by DMA Address Error: If the DMAC operates during sleep mode and a DMA address error occurs, sleep mode is exited and DMA address error exception handling is executed. Exit by Power-On Reset: If the RES signal goes low while the NMI signal is high, sleep mode is exited and the power-on reset state is entered. If the NMI signal is brought from low to high in order to set the chip for a power-on reset, an NMI interrupt will occur whenever the rising edge of NMI is selected as the valid edge (with NMI edge select bit NMIE in the interrupt control register (ICR) of the interrupt controller). When this occurs, the NMI interrupt clears sleep mode. Exit by Manual Reset: If the RES signal goes low while the NMI signal is low, sleep mode is exited and the manual reset state is entered. If the NMI signal is brought from high to low in order to set the chip for a manual reset, sleep mode will be exited by an NMI interrupt whenever the falling edge of NMI is selected as the valid edge (with the NMIE bit). Rev. 7.00 Jan 31, 2006 page 467 of 658 REJ09B0272-0700 Section 19 Power-Down State 19.4 Standby Mode 19.4.1 Transition to Standby Mode To enter standby mode, set the standby bit (SBY) to 1 in the standby control register (SBYCR), then execute the SLEEP instruction. The chip switches from the program execution state to standby mode. Standby mode greatly reduces power consumption by halting not only the CPU, but the clock and on-chip supporting modules as well. Some registers of the on-chip supporting modules are initialized, others are not (See table 19.3). As long as the specified voltage is supplied, however, CPU register contents and on-chip RAM data are held. The I/O port state (hold or high impedance) depends on the port high-impedance bit (HIZ) in SBYCR. For details on the states of these pins, see appendix B, Pin States. Table 19.3 Register States in Standby Mode Module Registers Initialized Registers That Hold Data Interrupt controller (INTC) -- All registers User break controller (UBC) -- All registers Bus state controller (BSC) -- All registers Pin function controller (PFC) -- All registers I/O ports -- All registers Direct memory access controller (DMAC) All registers -- Watchdog timer (WDT) * * * Bits 7-5 (OVF, WT/IT, TME) in timer control status register (TCSR) Reset control/status register (RSTCSR) * Bits 2-0 (CKS2-CKS0) in timer control status register (TCSR) Timer counter (TCNT) 16-bit integrated timer pulse unit (ITU) All registers -- Programmable timing pattern controller (TPC) -- All registers Serial communication interface (SCI) * * * * * * Receive data register (RDR) Transmit data register (TDR) Serial mode register (SMR) Serial control register (SCR) Serial status register (SSR) Bit rate register (BBR) -- A/D converter (A/D) All registers -- Power-down state register -- Standby control register (SBYCR) Rev. 7.00 Jan 31, 2006 page 468 of 658 REJ09B0272-0700 Section 19 Power-Down State 19.4.2 Exiting Standby Mode Standby mode is exited by an NMI interrupt, a power-on reset, or a manual reset. Exit by NMI: When a rising edge or falling edge (as selected by the NMIE bit in the interrupt control register (ICR) of the interrupt controller (INTC)) is detected at the NMI pin, the clock oscillator begins operating. At first, clock pulses are supplied only to the watchdog timer. After the time that was selected before entering standby mode using clock select bits 2-0 (CKS2-CKS0) in the timer control/status register (TCSR) of the watchdog timer (WDT), the watchdog timer overflows. After the overflow, the clock is considered stable and supplied to the entire chip. Standby mode is exited and the NMI exception handling sequence begins. When standby mode is cleared by an NMI interrupt, bits CKS2-CKS0 must be set so that the WDT overflow interval is equal to or greater than the clock settling time. When standby mode is cleared when the falling edge has been selected with the NMI bit, be sure that the NMI pin is high when standby mode is entered (when the clock is halted) and low when the chip returns from standby mode (clock starts up after the oscillator is stabilized). Likewise, when standby mode is cleared when the rising edge has been selected with the NMI bit, be sure that the NMI pin is low when standby mode is entered (clock halted) and high when the chip returns from standby mode (clock starts up after the oscillator is stabilized). Exit by Power-On Reset: If the RES signal goes low while the NMI signal is high, standby mode is exited and the power-on reset state is entered. If the NMI signal is brought from low to high in order to set the chip for a power-on reset, standby mode will not be exited by an NMI interrupt, because the NMI signal is initialized for the falling edge in standby mode (by the NMIE bit). Exit by Manual Reset: If the RES signal goes low while the NMI signal is low, standby mode is exited and the manual reset state is entered. If the NMI signal is brought from high to low in order to set the chip for a manual reset, standby mode will first be exited by an NMI interrupt, because the NMI signal is initialized for the falling edge in standby mode (by the NMIE bit). 19.4.3 Standby Mode Application In this example, standby mode is entered on the falling edge of the NMI signal and exited on the rising edge of the NMI signal. Figure 19.1 shows the timing. After an NMI interrupt is accepted on a high-to-low transition at the NMI pin while NMI edge select bit NMIE in the interrupt control register (ICR) is cleared to 0 to select falling edge detection, the NMI exception handling routine sets NMIE to 1 (selecting rising edge detection) and sets the SBY bit to 1. Finally, it executes a SLEEP instruction to enter standby mode. Standby mode is exited on the rising edge of the NMI signal. Rev. 7.00 Jan 31, 2006 page 469 of 658 REJ09B0272-0700 Section 19 Power-Down State Oscillator CK NMI NMIE SSBY Clock setting time NMI exception handling Exception handling routine SBY = 1 SLEEP instruction Standby Oscillation mode start time Time set in WDT Figure 19.1 NMI Timing for Standby Mode (Example) Rev. 7.00 Jan 31, 2006 page 470 of 658 REJ09B0272-0700 NMI exception handling Section 20 Electrical Characteristics Section 20 Electrical Characteristics 20.1 SH7032 and SH7034 Electrical Characteristics 20.1.1 Absolute Maximum Ratings Table 20.1 shows the absolute maximum ratings. Table 20.1 Absolute Maximum Ratings Item Symbol Rating Unit Power supply voltage VCC -0.3 to +7.0 V Program voltage VPP -0.3 to +13.5 V Input voltage (except port C) Vin -0.3 to VCC + 0.3 V Input voltage (port C) Vin -0.3 to AVCC + 0.3 V Analog power supply voltage AVCC -0.3 to +7.0 V Analog reference voltage AVref -0.3 to AVCC + 0.3 V Analog input voltage VAN -0.3 to AVCC + 0.3 V Operating temperature Topr -20 to +75* uC Storage temperature Tstg -55 to +125 uC Caution: Operating the chip in excess of the absolute maximum rating may result in permanent damage. Note: * Regular-specification products; for wide-temperature-range products, Topr = -40 to +85C 20.1.2 DC Characteristics Table 20.2 lists DC characteristics. Table 20.3 lists the permissible output current values. Rev. 7.00 Jan 31, 2006 page 471 of 658 REJ09B0272-0700 Section 20 Electrical Characteristics Table 20.2 DC Characteristics (1) Conditions: VCC = 5.0 V 10%, AVCC = 5.0 V 10%, AVCC = VCC 10%, AVref = 4.5 V to AVCC, VSS = AVSS = 0 V, = 20 MHz, Ta = -20 to +75C*) Note: * Regular-specification products; for wide-temperature-range products, Ta = -40 to +85C Item Symbol Min Input high-level RES, NMI, voltage MD2-MD0 VIH Max Unit VCC - 0.7 -- VCC + 0.3 V EXTAL VCC x 0.7 -- VCC + 0.3 V Port C 2.2 -- AVCC + 0.3 V Other input pins 2.2 -- VCC + 0.3 V -0.3 -- 0.5 V -0.3 -- 0.8 V -- -- V Input low-level RES, NMI, voltage MD2-MD0 VIL Other input pins Schmidt trigger PA13-PA10, VT+ 4.0 PA2, PA0, input voltage - VT -- PB7-PB0 VT+-VT- 0.4 Typ Test Conditions -- 1.0 V -- -- V -- -- 1.0 A Vin = 0.5 to VCC - 0.5 V NMI, MD2-MD0 -- -- 1.0 A Vin = 0.5 to VCC - 0.5 V Port C -- -- 1.0 A Vin = 0.5 to AVCC - 0.5 V 3-state leakage Ports A and |ITSI| current B, CS3-CS0, (off state) A21-A0, AD15-AD0 -- -- 1.0 A Vin = 0.5 to VCC - 0.5 V Input pull-up MOS current PA3 -Ip 20 -- 300 A Vin = 0V Output highlevel voltage All output pins VOH VCC - 0.5 -- -- V IOH = -200 A 3.5 -- -- V IOH = -1 mA Output low level voltage All output pins VOL -- -- 0.4 V IOL = 1.6 mA -- -- 1.2 V IOL = 8 mA Input leakage current RES |Iin| Rev. 7.00 Jan 31, 2006 page 472 of 658 REJ09B0272-0700 Section 20 Electrical Characteristics Item Input capacitance Current consumption Symbol Min Typ Max Unit Test Conditions Cin -- -- 30 pF NMI -- -- 30 pF All other input pins -- -- 20 pF Vin = 0 V Input signal f = 1 MHz Ta = 25C -- 60 90 mA f = 12.5 MHz -- 100 130 mA f = 20 MHz -- 40 70 mA f = 12.5 MHz -- 60 90 mA f = 20 MHz -- 0.01 5* A Ta 50C 50C < Ta RES Ordinary operation ICC Sleep Standby Analog power During A/D supply current conversion AICC While A/D converter is waiting Reference power supply current RAM standby voltage During A/D conversion AIref While A/D converter is waiting VRAM 1 2 -- -- 20.0* A -- 1.0 2 mA -- 0.01 5 A -- 0.5 1 mA -- 0.01 5 A 2.0 -- -- V AVref = 5.0 V Notes: 1. 50 A for the SH7032. 2. 300 A for the SH7032. Usage Notes: 1. If the A/D converter is not used, do not leave the AVCC, Vref, and AVSS pins open. Connect AVCC and AVref to VCC, and connect AVSS to VSS. 2. Current dissipation values are for VIH min = VCC - 0.5 V and VIL max = 0.5 V with all output pins unloaded and the on-chip pull-up transistors in the off state. 3. When the A/D converter is not used, and in standby mode, AVCC and AVref must still be connected to the power supply (VCC). 4. The ZTAT and mask versions have the same functions, and the electrical characteristics of both are within specification, but characteristic-related performance values, operating margins, noise margins, noise emission, etc., are different. Caution is therefore required in carrying out system design, and when switching between ZTAT and mask versions. Rev. 7.00 Jan 31, 2006 page 473 of 658 REJ09B0272-0700 Section 20 Electrical Characteristics Table 20.2 DC Characteristics (2) Conditions: VCC = 3.0 V to 5.5 V, AVCC = 3.0 to 5.5 V, AVCC = VCC 10%, AVref = 3.0 V to AVCC, VSS = AVSS = 0 V, = 12.5 MHz, Ta = -20 to +75C*) Note: * Regular-specification products; for wide-temperature-range products, Ta = -40 to +85C Item Symbol Min Input high-level RES, NMI, voltage MD2-MD0 VIH VCC x 0.9 -- Max Unit VCC + 0.3 V V EXTAL VCC x 0.7 -- VCC + 0.3 Port C VCC x 0.7 -- AVCC + 0.3 V Other input pins VCC x 0.7 -- VCC + 0.3 V -0.3 -- VCC x 0.1 V -0.3 -- VCC x 0.2 V -- V Input low-level RES, NMI, voltage MD2-MD0 VIL Other input pins Schmidt trigger PA13-10, PA2, PA0, input voltage PB7-PB0 Input leakage current Typ RES VT + - VCC x 0.9 -- VCC x 0.2 V VT+-VT- VCC x 0.07 -- -- V |Iin| VT -- -- Test Conditions -- -- 1.0 A Vin = 0.5 to VCC - 0.5 V NMI, MD2-MD0 -- -- 1.0 A Vin = 0.5 to VCC - 0.5 V Port C -- -- 1.0 A Vin = 0.5 to AVCC - 0.5 V 3-state leakage Ports A and |ITSI| current B, CS3-CS0, (off state) A21-A0, AD15-AD0 -- -- 1.0 A Vin = 0.5 to VCC - 0.5 V Input pull-up MOS current PA3 -Ip 20 -- 300 A Vin = 0V Output highlevel voltage All output pins VOH VCC - 0.5 -- -- V IOH = -200 A VCC - 1.0 -- -- V IOH = -1 mA Output low level voltage All output pins VOL -- -- 0.4 V IOL = 1.6 mA -- -- 1.2 V IOL = 8 mA Rev. 7.00 Jan 31, 2006 page 474 of 658 REJ09B0272-0700 Section 20 Electrical Characteristics Item Input capacitance Current consumption Symbol Min Typ Max Unit Test Conditions Cin -- -- 30 pF NMI -- -- 30 pF All other input pins -- -- 20 pF Vin = 0 V Input signal f = 1 MHz Ta = 25C -- 60 90 mA f = 12.5 MHz -- 40 70 mA f = 12.5 MHz -- 0.01 1 5.0* A Ta 50C -- -- 20.0* A 50C < Ta -- 0.5 1.5 mA AVCC = 3.0 V -- 1.0 2.0 mA AVCC = 5.0 V -- 0.01 5.0 A -- 0.4 0.8 mA AVref = 3.0 V -- 0.5 1 mA AVref = 5.0 V -- 0.01 5.0 A 2.0 -- -- V RES Ordinary operation ICC Sleep Standby Analog power During A/D supply current conversion AICC While A/D converter is waiting During A/D conversion AIref While A/D converter is waiting RAM standby voltage VRAM 2 Notes: 1. 50 A for the SH7032. 2. 300 A for the SH7032. Rev. 7.00 Jan 31, 2006 page 475 of 658 REJ09B0272-0700 Section 20 Electrical Characteristics Usage Notes: 1. If the A/D converter is not used, do not leave the AVCC, Vref, and AVSS pins open. Connect AVCC and AVref to VCC, and connect AVSS to VSS. 2. Current dissipation values are for VIH min = VCC - 0.5 V and VIL max = 0.5 V with all output pins unloaded and the on-chip pull-up transistors in the off state. 3. ICC depends on VCC and f as follows: ICC max = 1.0 (mA) + 1.29 (mA/MHz * V) x VCC x f [ordinary operation] ICC max = 1.0 (mA) + 1.00 (mA/MHz * V) x VCC x f [sleep] 4. When the A/D converter is not used, and in standby mode, AVCC and AVref must still be connected to the power supply (VCC). 5. The ZTAT and mask versions have the same functions, and the electrical characteristics of both are within specification, but characteristic-related performance values, operating margins, noise margins, noise emission, etc., are different. Caution is therefore required in carrying out system design, and when switching between ZTAT and mask versions. Table 20.3 Permitted Output Current Values Case A: VCC = 3.0 to 5.5 V, AVCC = 3.0 to 5.5 V, AVCC = VCC 10%, AVref = 3.0 V to AVCC, VSS = AVSS = 0 V, Ta = -20 to +75C*) Case B: VCC = 5.0 V 10%, AVCC= 5.0 V 10%, AVCC = VCC 10%, AVref = 4.5 V to AVCC, VSS = AVSS = 0 V, Ta = -20 to +75C*) Note: * Regular-specification products; for wide-temperature-range products, Ta = -40 to +85C Item Symbol Case A Case B 12.5 MHz 20 MHz Min Typ Max Min Typ Max Unit Output low-level permissible IOL current (per pin) -- -- 10 -- -- 10 mA Output low-level permissible IOL current (total) -- -- 80 -- -- 80 mA Output high-level -IOH permissible current (per pin) -- -- 2.0 -- -- 2.0 mA Output high-level permissible current (total) -- -- 25 -- -- 25 mA - IOH Caution: To ensure reliability of the chip, do not exceed the output current values given in table 20.3. Rev. 7.00 Jan 31, 2006 page 476 of 658 REJ09B0272-0700 Section 20 Electrical Characteristics 20.1.3 AC Characteristics The following AC timing chart represents the AC characteristics, not signal functions. For signal functions, see the explanation in the text. (1) Clock Timing Table 20.4 Clock Timing Case A: VCC = 3.0 to 5.5 V, AVCC = 3.0 to 5.5 V, AVCC = VCC 10%, AVref = 3.0 V to AVCC, VSS = AVSS = 0 V, Ta = -20 to +75C*) Case B: VCC = 5.0 V 10%, AVCC = 5.0 V 10%, AVCC = VCC 10%, AVref = 4.5 V to AVCC, VSS = AVSS = 0 V, Ta = -20 to +75C*) Note: * Regular-specification products; for wide-temperature-range products, Ta = -40 to +85C Case A Case B 12.5 MHz 20 MHz Symbol Min Max Min Max Unit Figures EXTAL input high level pulse width tEXH 20 -- 10 -- ns 20.1 EXTAL input low level pulse width tEXL 20 -- 10 -- ns EXTAL input rise time tEXr -- 10 -- 5 ns EXTAL input fall time tEXf -- 10 -- 5 ns Clock cycle time tcyc 80 500 50 500 ns 20.1, 20.2 Clock high pulse width tCH 30 -- 20 -- ns 20.2 Clock low pulse width tCL 30 -- 20 -- ns Clock rise time tCr -- 10 -- 5 ns Clock fall time tCf -- 10 -- 5 ns Reset oscillation settling time tOSC1 10 -- 10 -- ms Software standby oscillation settling time tOSC2 10 -- 10 -- ms Item 20.3 Rev. 7.00 Jan 31, 2006 page 477 of 658 REJ09B0272-0700 Section 20 Electrical Characteristics tcyc tEXH 1/2 VCC EXTAL tEXL VIH VIL tEXr tEXf Figure 20.1 EXTAL Input Timing tCYC tCH tCL CK tCf tCr Figure 20.2 System Clock Timing CK VCC tOSC2 tOSC1 RES Figure 20.3 Oscillation Settling Time Rev. 7.00 Jan 31, 2006 page 478 of 658 REJ09B0272-0700 Section 20 Electrical Characteristics (2) Control Signal Timing Table 20.5 Control Signal Timing Case A: VCC = 3.0 to 5.5 V, AVCC = 3.0 to 5.5 V, AVCC = VCC 10%, AVref = 3.0 V to AVCC, VSS = AVSS = 0 V, Ta = -20 to +75C*) Case B: VCC = 5.0 V 10%, AVCC = 5.0 V 10%, AVCC = VCC 10%, AVref = 4.5 V to AVCC, VSS = AVSS = 0 V, Ta = -20 to +75C*) Note: * Regular-specification products; for wide-temperature-range products, Ta = -40 to +85C Case A Case B 12.5 MHz 20 MHz Item Symbol Min Max Min Max Unit Figure RES setup time tRESS 320 -- 200 -- ns RES pulse width tRESW 20 -- 20 -- tcyc NMI reset setup time tNMIRS 320 -- 200 -- ns NMI reset hold time tNMIRH 320 -- 200 -- ns NMI setup time tNMIS 160 -- 100 -- ns NMI hold time tNMIH 80 -- 50 -- ns IRQ0-IRQ7 setup time (edge detection) tIRQES 160 -- 100 -- ns IRQ0-IRQ7 setup time (level detection) tIRQLS 160 -- 100 -- ns IRQ0-IRQ7 hold time tIRQEH 80 -- 50 -- ns IRQOUT output delay time tIRQOD -- 80 -- 50 ns 20.6 Bus request setup time tBRQS 80 -- 50 -- ns 20.7 Bus acknowledge delay time 1 tBACD1 -- 80 -- 50 ns Bus acknowledge delay time 2 tBACD2 -- 80 -- 50 ns Bus 3-state delay time tBZD -- 80 -- 50 ns 20.4 20.5 Rev. 7.00 Jan 31, 2006 page 479 of 658 REJ09B0272-0700 Section 20 Electrical Characteristics CK tRESS tRESS RES tNMIRS tRESW tNMIRH NMI Figure 20.4 Reset Input Timing CK tNMIS tNMIH tIRQES tIRQEH NMI IRQ edge tIRQLS IRQ level Figure 20.5 Interrupt Signal Input Timing CK tIRQOD tIRQOD IRQOUT Figure 20.6 Interrupt Signal Output Timing Rev. 7.00 Jan 31, 2006 page 480 of 658 REJ09B0272-0700 Section 20 Electrical Characteristics CK tBRQS BREQ (Input) tBRQS tBACD1 BACK (Output) tBACD2 tBZD RD, WR, RAS, CAS, CSn tBZD A21-A0 Figure 20.7 Bus Release Timing Rev. 7.00 Jan 31, 2006 page 481 of 658 REJ09B0272-0700 Section 20 Electrical Characteristics (3) Bus Timing Tables 20.6 to 20.8 show the bus timing. Table 20.6 Bus Timing (1) Conditions: VCC = 5.0 V 10%, AVCC = 5.0 V 10%, AVCC = VCC 10%, AVref = 4.5 V to AVCC, VSS = AVSS = 0 V, = 20 MHz, Ta = -20 to +75C* Note: * Regular-specification products; for wide-temperature-range products, Ta = -40 to +85C Item Symbol Min Max Unit 1 Figures Address delay time tAD -- 20* ns 20.8, 20.9, 20.11-20.14, 20.19, 20.20 CS delay time 1 tCSD1 -- 25 ns 20.8, 20.9, 20.20 CS delay time 2 tCSD2 -- 25 ns CS delay time 3 tCSD3 -- 20 ns tCSD4 -- 20 ns tcyc x 0.65 - 20 -- ns CS delay time 4 6 2 6 2 Access time 1* 35% duty* tRDAC1 from read strobe 50% duty Access time 2* 35% duty* tRDAC2 from read strobe 50% duty 6 2 tcyc x 0.5 - 20 -- ns tcyc x (n+1.65) - 20* -- ns 3 3 tcyc x (n+1.5)- 20* -- ns tcyc x (n+0.65) - 20* -- ns 3 20.19 20.8, 20.9, 20.10 Access time 3* 35% duty* tRDAC3 from read strobe 50% duty tcyc x (n+0.5)- 20* -- ns Read strobe delay time tRSD -- 20 ns 20.8, 20.9, 20.11-20.15, 20.19 Read data setup time tRDS 15 -- ns Read data hold time tRDH 0 -- ns 20.8, 20.9, 20.11-20.14, 20.19 Write strobe delay time 1 tWSD1 -- 20 ns 20.9, 20.13, 20.14, 20.19, 20.20 Write strobe delay time 2 tWSD2 -- 20 ns 20.9, 20.13, 20.14, 20.19 Write strobe delay time 3 tWSD3 -- 20 ns 20.11, 20.12 Write strobe delay time 4 tWSD4 -- 20 ns 20.11, 20.12, 20.20 Write data delay time 1 tWDD1 -- 35 ns 20.9, 20.13, 20.14, 19 Write data delay time 2 tWDD2 -- 20 ns 20.11, 20.12 3 Rev. 7.00 Jan 31, 2006 page 482 of 658 REJ09B0272-0700 20.19 Section 20 Electrical Characteristics Item Symbol Min Max Unit Figures Write data hold time tWDH 0 -- ns 20.9, 20.11-20.14 Parity output delay time 1 tWPDD1 -- 40 ns 20.9, 20.13, 20.14 Parity output delay time 2 tWPDD2 -- 20 ns 20.11, 20.12 Parity output hold time tWPDH 0 -- ns 20.9, 20.11-20.14 Wait setup time tWTS 14 -- ns 20.10, 20.15, 20.19 tWTH 10 -- ns Wait hold time 6 Read data access time 1* 4 tACC1 tcyc - 30* -- ns 20.8, 20.11, 20.12 6 Read data access time 2* tACC2 3 tcyc x (n+2) - 30* -- ns 20.9, 20.10, 20.13-20.15 RAS delay time 1 tRASD1 -- 20 ns RAS delay time 2 tRASD2 -- 30 ns 20.11-20.14, 20.16-20.18 CAS delay time 1 tCASD1 -- 20 ns 20.11 7 CAS delay time 2* tCASD2 -- 20 ns CAS delay time 3* 7 tCASD3 -- 20 ns 20.13, 20.14, 20.16-20.18 Column address setup time tASC 0 -- ns 20.11, 20.12 Read data access 35% 6 2 time from CAS 1* duty* tCAC1 tcyc x 0.65 -19 -- ns tcyc x 0.5 - 19 -- ns Read data access time from 6 CAS 2* 50% duty tCAC2 tcyc x (n+1) - 25* -- ns 20.13-20.15 Read data access time from 6 RAS 1* tRAC1 tcyc x 1.5 - 20 -- ns 20.11, 20.12 Read data access time from 6 RAS 2* tRAC2 tcyc x (n+2.5) 3 - 20* -- ns 20.13-20.15 tcyc x 0.25 -- ns 20.12 High-speed page mode CAS tCP precharge time 3 Rev. 7.00 Jan 31, 2006 page 483 of 658 REJ09B0272-0700 Section 20 Electrical Characteristics Item Symbol Min Max Unit Figures AH delay time 1 tAHD1 -- 20 ns AH delay time 2 tAHD2 -- 20 ns Multiplexed address delay time tMAD -- 30 ns Multiplexed address hold time tMAH 0 -- ns DACK0, DACK1 delay time 1 tDACD1 -- 23 ns DACK0, DACK1 delay time 2 20.19 20.8, 20.9, 20.11- 20.14, 20.19, 20.20 tDACD2 -- 23 ns 7 DACK0, DACK1 delay time 3* tDACD3 -- 20 ns 20.9, 20.13, 20.14, 20.19 DACK0, DACK1 delay time 4 tDACD4 -- 20 ns 20.11, 20.12 tDACD5 -- 20 ns 35% duty* tRDD -- tcyc x 0.35 + 12 ns 50% duty -- DACK0, DACK1 delay time 5 Read delay time 2 tcyc x 0.5 + 15 ns 20.8, 20.9, 20.11- 20.15, 20.19 Data setup time for CAS tDS 0* -- ns 20.11, 20.13 CAS setup time for RAS tCSR 10 -- ns 20.16-20.18 Row address hold time tRAH 10 -- ns 20.11, 20.13 Write command hold time tWCH 15 -- ns Write command setup time Access time from 6 CAS precharge* 5 2 35% duty* tWCS 0 -- ns 50% duty tWCS 0 -- ns tACP tcyc -20 -- ns Notes: 1. 2. 3. 4. 5. 6. 20.11 20.12 HBS and LBS signals are 25 ns. When frequency is 10 MHz or more. n is the number of wait cycles. Access time from addresses A0 to A21 is tcyc-25 ns. -5ns for parity output of DRAM long-pitch access. It is not necessary to meet the tRDS specification as long as the access time specification is met. 7. In the relationship of tCASD2 and tCASD3 with respect to tDACD3, a Min-Max combination does not occur because of the logic structure. Rev. 7.00 Jan 31, 2006 page 484 of 658 REJ09B0272-0700 Section 20 Electrical Characteristics T1 CK tAD A21-A0 HBS, LBS tCSD2 tCSD1 CSn tRDD tRDAC1*1 tRSD RD (Read) tACC1*2 tRDS AD15-AD0 DPH, DPL (Read) tDACD1 tRDH*3 tDACD2 DACK0 DACK1 Notes: 1. For tRDAC1, use tcyc x 0.65 - 20 (for 35% duty) or tcyc x 0.5 - 20 (for 50% duty) instead of tcyc - tRDD - tRDS. 2. For tACC1, use tcyc - 30 instead of tcyc - tAD (or tCSD1) - tRDS. 3. tRDH is measured from A21-A0, CSn, or RD, whichever is negated first. Figure 20.8 Basic Bus Cycle: One-State Access Rev. 7.00 Jan 31, 2006 page 485 of 658 REJ09B0272-0700 Section 20 Electrical Characteristics T1 CK T2 tAD A21-A0 HBS, LBS tCSD2 tCSD1 CSn tRDD tRDAC2*1 tRSD RD (Read) tACC2*2 AD15-AD0 DPH, DPL (Read) DACK0 DACK1 (Read) tDACD1 tWSD1 tRDH*3 tRDS tDACD2 tWSD2 WRH, WRL, WR (Write) tWDH tWDD1 AD15-AD0 (Write) tWPDH tWPDD1 PL (Write) tDACD3 tDACD3 DACK0 DACK1 (Write) Notes: 1. For tRDAC2, use tcyc x (n + 1.65) - 20 (for 35% duty) or tcyc x (n + 1.5) - 20 (for 50% duty) instead of tcyc x (n + 2) - tRDD - tRDS. 2. For tACC2, use tcyc x (n + 2) - 30 instead of tcyc x (n + 2) - tAD (or tCSD1) - tRDS. 3. tRDH is measured from A21-A0, CSn, or RD, whichever is negated first. Figure 20.9 Basic Bus Cycle: Two-State Access Rev. 7.00 Jan 31, 2006 page 486 of 658 REJ09B0272-0700 Section 20 Electrical Characteristics T1 TW T2 CK A21-A0 HBS, LBS CSn tRDAC2*1 RD (Read) tACC2*2 AD15-AD0 DPH, DPL (Read) DACK0 DACK1 (Read) WRH, WRL, WR (Write) AD15-AD0 DPH, DPL (Write) DACK0 DACK1 (Write) tWTS tWTH tWTS tWTH WAIT Notes: 1. For tRDAC2, use tcyc x (n+1.65) - 20 (for 35% duty) or tcyc x (n+1.5) - 20 (for 50% duty) instead of tcyc x (n+2) - tRDD - tRDS. 2. For tACC2, use tcyc x (n+2) - 30 instead of tcyc x (n+2) - tAD (or tCSD1) - tRDS. Figure 20.10 Basic Bus Cycle: Two States + Wait State Rev. 7.00 Jan 31, 2006 page 487 of 658 REJ09B0272-0700 Section 20 Electrical Characteristics Tp Tr Tc CK tAD tAD Row A21-A0 Column tRASD1 tRASD2 tRAH RAS tDS tASC CAS tRDD tRSD tWCH RD(Read) WRH, WRL, WR(Read) tDACD1 DACK0 DACK1 (Read) tCASD1 tDACD2 tCAC1*1 tACC1*2 tRAC1*3 AD15-AD0 DPH, DPL (Read) RD(Write) tRDS tWSD3 WRH, WRL, WR(Write) tWCS tWDD2 AD15-AD0 (Write) tWSD4 tWDH tWPDH tWPDD2 DPH, DPL (Write) tRDH*4 tDACD4 tDACD5 DACK0 DACK1 (Write) Notes: 1. For tCAC1, use tcyc x 0.65 - 19 (for 35% duty) or tcyc x 0.5 - 19 (for 50% duty) instead of tcyc - tAD - tASC - tRDS. 2. For tACC1, use tcyc - 30 instead of tcyc - tAD - tRDS. 3. For tRAC1, use tcyc x 1.5 - 20 instead of tcyc x 1.5 - tRASD1 - tRDS. 4. tRDH is measured from A21-A0, RAS, or CAS, whichever is negated first. Figure 20.11 DRAM Bus Cycle (Short-Pitch, Normal Mode) Rev. 7.00 Jan 31, 2006 page 488 of 658 REJ09B0272-0700 Section 20 Electrical Characteristics Tp Tr Tc Tc Tc Tc CK tAD A21-A0 tAD Row address Column address Column address Column address Column address tRASD2 tRASD1 RAS tASC tCP CAS tRDD tRSD RD(Read) WRH, WRL, WR(Read) tCAC1*1 AD15-AD0 DPH, DPL (Read) DACK0 DACK1 (Read) tRAC1*3 tACC1*2 tACP tRDS tRDH*4 tRDH*5 tDACD1 tDACD2 Notes: 1. For tCAC1, use tcyc x 0.65 - 19 (for 35% duty) or tcyc x 0.5 - 19 (for 50% duty) instead of tcyc - tAD - tASC - tRDS. It is not necessary to meet the tRDS specification as long as the tCAC1 specification is met. 2. For tACC1, use tcyc - 30 instead of tcyc - tAD - tRDS. It is not necessary to meet the tRDS specification as long as the tACC1 specification is met. 3. For tRAC1, use tcyc x 1.5 - 20 instead of tcyc x 1.5 - tRASD1 - tRDS. It is not necessary to meet the tRDS specification as long as the tRAC1 specification is met. 4. tRDH is measured from A21-A0 or CAS, whichever is negated first. 5. tRDH is measured from A21-A0, RAS, or CAS, whichever is negated first. Figure 20.12 (a) DRAM Bus Cycle (Short-Pitch, High-Speed Page Mode: Read) Rev. 7.00 Jan 31, 2006 page 489 of 658 REJ09B0272-0700 Section 20 Electrical Characteristics Tp Tr Silent cycle Tc Tc CK tAD A21-A0 tAD Row address Column address Column address tRASD2 tRASD1 RAS tASC CAS RD (Write) tWSD3 tWSD4 WRH, WRL, WR (Write) tWDD2 tWDH tWPDD2 tWPDH AD15-AD0 DPH, DPL (Write) DPH, DPL (Write) tDACD4 tDACD5 tDACD5 DACK0 DACK1 (Write) Figure 20.12 (b) DRAM Bus Cycle (Short-Pitch, High-Speed Page Mode: Write) Note: For details of the silent cycle, see section 8.5.5, DRAM Burst Mode. Rev. 7.00 Jan 31, 2006 page 490 of 658 REJ09B0272-0700 Section 20 Electrical Characteristics Tp Tr Tc1 Tc2 CK tAD A21-A0 tRASD1 tAD Row tRAH Column tRASD2 RAS tDS tCASD2 CAS tCASD3 tRDD tRSD RD(Read) WRH, WRL, WR(Read) AD15-AD0 DPH, DPL (Read) DACK0 DACK1 (Read) tWCH tRAC2*3 tACC2*2 tCAC2*1 tRDS tRDH*4 tDACD2 tDACD1 RD(Write) WRH, WRL, WR(Write) AD15-AD0 (Write) DPH, DPL (Write) tWSD1 tWSD2 tWDH tWDD1 tWPDH tWPDD1 tDACD3 tDACD3 DACK0 DACK1 (Write) Notes: 1. 2. 3. 4. For tCAC2, use tcyc x (n + 1) - 25 instead of tcyc x (n + 1) - tCASD2 - tRDS. For tACC2, use tcyc x (n + 2) - 30 instead of tcyc x (n + 2) - tAD - tRDS. For tRAC2, use tcyc x (n + 2.5) - 20 instead of tcyc x (n + 2.5) - tRASD1 - tRDS. tRDH is measured from A21-A0, CAS, or RAS, whichever is negated first. Figure 20.13 DRAM Bus Cycle: (Long-Pitch, Normal Mode) Rev. 7.00 Jan 31, 2006 page 491 of 658 REJ09B0272-0700 Section 20 Electrical Characteristics Tp Tr Tc1 Tc2 Tc1 Tc2 CK tAD A21-A0 tAD Row tRASD1 Column Column tRASD2 RAS tCASD2 CAS tCASD3 tRDD tRSD RD(Read) WRH, WRL, WR (Read) AD15-AD0 DPH, DPL (Read) tCASD3 tRAC2*3 DACK0 DACK1 (Read) RD(Write) WRH, WRL, WR(Write) tACC2*2 tCAC2*1 tRDS tRDH*4 tDACD1 tDACD2 tWSD1 tWDD1 tWSD2 tRDH*5 tDACD1 tWSD1 tDACD2 tWSD2 tWDH tWDD1 tWDH tWPDH tWPDD1 tWPDH AD15-AD0 (Write) tWPDD1 DPH, DPL (Write) DACK0 DACK1 (Write) Notes: 1. 2. 3. 4. 5. tDACD3 tDACD3 tDACD3 tDACD3 For tCAC2, use tcyc x (n + 1) - 25 instead of tcyc x (n + 1) - tCASD2 - tRDS. For tACC2, use tcyc x (n + 2) - 30 instead of tcyc x (n + 2) - tAD - tRDS. For tRAC2, use tcyc x (n + 2.5) - 20 instead of tcyc x (n + 2.5) - tRASD2 - tRDS. tRDH is measured from A21-A0 or CAS, whichever is negated first. tRDH is measured from A21-A0, RAS, or CAS whichever is negated first. Figure 20.14 DRAM Bus Cycle: (Long-Pitch, High-Speed Page Mode) Rev. 7.00 Jan 31, 2006 page 492 of 658 REJ09B0272-0700 Section 20 Electrical Characteristics Tp Tr Tc1 Tw Tc2 CK A21-A0 Row Column tRSD RAS CAS tRDD RD(Read) WRH, WRL, WR(Read) tCAC2*1 tACC2*2 tRAC2*3 AD15-AD0 DPH, DPL (Read) DACK0 DACK1 (Read) RD(Write) WRH, WRL, WR(Write) AD15-AD0 (Write) DPH, DPL (Write) DACK0 DACK1 (Write) tWTS tWTH tWTS tWTH WAIT Notes: 1. For tCAC2, use tcyc x (n + 1) - 25 instead of tcyc x (n + 1) - tCASD2 - tRDS. 2. For tACC2, use tcyc x (n + 2) - 30 instead of tcyc x (n + 2) - tAD - tRDS. 3. For tRAC2, use tcyc x (n + 2.5) - 20 instead of tcyc x (n + 2.5) - tRASD1 - tRDS. Figure 20.15 DRAM Bus Cycle: (Long-Pitch, High-Speed Page Mode + Wait State) Rev. 7.00 Jan 31, 2006 page 493 of 658 REJ09B0272-0700 Section 20 Electrical Characteristics TRp TRr TRc CK tRASD1 RAS tRASD2 tCSR tCASD3 tCASD2 CAS WRH, WRL, WR Figure 20.16 CAS-before-RAS Refresh (Short-Pitch) TRp TRr TRc TRc CK tRASD1 RAS tRASD2 tCSR tCASD3 tCASD2 CAS WRH, WRL, WR Figure 20.17 CAS-before-RAS Refresh (Long-Pitch) Rev. 7.00 Jan 31, 2006 page 494 of 658 REJ09B0272-0700 Section 20 Electrical Characteristics TRp TRr TRc TRcc CK tRASD2 tRASD1 RAS tCSR tCASD3 tCASD2 CAS Figure 20.18 Self-Refresh Rev. 7.00 Jan 31, 2006 page 495 of 658 REJ09B0272-0700 Section 20 Electrical Characteristics T2 T1 T3 T4 CK tAD A21-A0 HBS, LBS tCSD3 tCSD4 CS6 tAHD1 tAHD2 AH tRDD RD (Read) tMAD AD15-AD0 (Read) tMAH tRSD tRDAC3 Address tRDH Data (input) tDACD1 tDACD2 DACK0 DACK1 (Read) tWSD1 tWSD2 WRH, WRL, WR (Write) tMAD AD15-AD0 (Write) tMAH tWDD1 Data (output) Address tDACD3 DACK0 DACK1 (Write) tWDH tDACD3 tWTH tWTS WAIT Figure 20.19 Address/Data Multiplex I/O Bus Cycle Rev. 7.00 Jan 31, 2006 page 496 of 658 REJ09B0272-0700 Section 20 Electrical Characteristics T1 CK tAD A21-A0 HBS, LBS tCSD2 tCSD1 CSn tWSD1 tWSD4 tDACD1 tDACD2 WRH, WRL, WR (Write) DACK0 DACK1 (Write) Figure 20.20 DMA Single Transfer/One-State Access Write Rev. 7.00 Jan 31, 2006 page 497 of 658 REJ09B0272-0700 Section 20 Electrical Characteristics Table 20.7 Bus Timing (2) Conditions: VCC = 3.0 to 5.5 V, AVCC = 3.0 to 5.5 V, AVCC = VCC 10%, AVref = 3.0 V to AVCC, VSS = AVSS = 0 V, = 12.5 MHz, Ta = -20 to +75C* Note: * Regular-specification products; for wide-temperature-range products, Ta = -40 to +85C Item Symbol Min Max Unit Figures Address delay time tAD -- 40 ns 20.21, 20.22, 20.24- 20.27, 20.32, 20.33 CS delay time 1 CS delay time 2 tCSD1 -- 40 ns 20.21, 20.22, 20.33 tCSD2 -- 40 ns CS delay time 3 tCSD3 -- 40 ns tCSD4 -- 40 ns Access time 1* 35% duty* tRDAC1 tcyc x 0.65 - 35 from read strobe 50% duty tcyc x 0.5 - 35 4 1 2 Access time 2* 35% duty* tRDAC2 tcyc x (n+1.65) - 35* 2 from read strobe 50% duty tcyc x (n+1.5) - 35* 4 1 2 Access time 3* 35% duty* tRDAC3 tcyc x (n+0.65) - 35* 2 from read strobe 50% duty tcyc x (n+0.5) - 35* Read strobe delay time tRSD -- -- ns -- ns -- ns -- ns -- ns -- ns 40 ns 20.21, 20.22, 20.24-20.28, 20.32 Read data setup time tRDS 25 -- ns 20.21, 20.22, Read data hold time tRDH 0 -- ns 20.24-20.27, 20.32 Write strobe delay time 1 tWSD1 -- 40 ns 20.22, 20.26, 20.27, 20.32, 20.33 Write strobe delay time 2 tWSD2 -- 30 ns 20.22, 20.26, 20.27, 20.32 Write strobe delay time 3 tWSD3 -- 40 ns 20.24, 20.25 Write strobe delay time 4 tWSD4 -- 40 ns 20.24, 20.25, 20.33 Write data delay time 1 tWDD1 -- 70 ns 20.22, 20.26, 20.27, 20.32 Write data delay time 2 tWDD2 -- 40 ns 20.24, 20.26 Write data hold time tWDH -10 -- ns 20.22, 20.24-20.27, 20.32 Parity output delay time 1 tWPDD1 -- 80 ns 20.22, 20.24, 20.27 Parity output delay time 2 tWPDD2 -- 40 ns 20.24, 20.25 Parity output hold time tWPDH -10 -- ns 20.22, 20.23-20.27 CS delay time 4 4 1 Rev. 7.00 Jan 31, 2006 page 498 of 658 REJ09B0272-0700 20.32 20.21, 20.22, 20.23 20.32 Section 20 Electrical Characteristics Item Symbol Min Max Unit Figures Wait setup time tWTS 40 -- ns Wait hold time -- ns 20.23, 20.28, 20.32 tWTH 10 4 Read data access time 1* tACC1 tcyc - 44 -- ns 20.21, 20.24, 20.25 Read data access time 2* 4 tACC2 tcyc x (n+2) - 44* -- ns 20.22, 20.23, 20.26-20.28 RAS delay time 1 tRASD1 -- 40 ns RAS delay time 2 tRASD2 -- 40 ns 20.24-20.27, 20.29- 20.31 CAS delay time 1 2 tCASD1 -- 40 ns 20.24 5 tCASD2 -- 40 ns 5 tCASD3 -- 40 ns 20.26, 20.27, 20.29- 20.31 tASC 0 -- ns 20.24, 20.25 tcyc x 0.65 - 35 -- ns -- ns tcyc x (n+1) - 35* -- ns 20.26-20.28 Read data access time from tRAC1 4 RAS 1* tcyc x 1.5 - 35 -- ns 20.24, 20.25 Read data access time from tRAC2 4 RAS 2* tcyc x (n+2.5) - 35* -- ns 20.26-20.28 High-speed page mode CAS tCP precharge time tcyc x 0.25 -- ns 20.25 AH delay time 1 tAHD1 -- 40 ns 20.32 AH delay time 2 tAHD2 -- 40 ns Multiplexed address delay time tMAD -- 40 ns Multiplexed address hold time tMAH -10 -- ns CAS delay time 2* CAS delay time 3* Column address setup time 1 Read data 35% duty* tCAC1 access time from 50% duty 4 CAS 1* Read data access time from tCAC2 4 CAS 2* tcyc x 0.5 - 35 2 2 Rev. 7.00 Jan 31, 2006 page 499 of 658 REJ09B0272-0700 Section 20 Electrical Characteristics Item Symbol Min Max Unit Figures DACK0, DACK1 delay time 1 tDACD1 -- 40 ns 20.21, 20.22, 20.24- 20.27, 20.32, 20.33 DACK0, DACK1 delay time 2 tDACD2 -- 40 ns 5 DACK0, DACK1 delay time 3* tDACD3 -- 40 ns 20.22, 20.26, 20.27, 20.32 DACK0, DACK1 delay time 4 tDACD4 -- 40 ns 20.24, 20.25 DACK0, DACK1 delay time 5 tDACD5 -- 40 ns tRDD -- tcyc x 0.35 + 35 ns 1 Read delay time 35% duty* tcyc x 0.5 + 35 ns 20.21, 20.22, 20.2420.28, 20.32 Data setup time for CAS tDS 0* -- ns 20.24, 20.26 CAS setup time for RAS tCSR 10 -- ns 20.29-20.31 Row address hold time tRAH 10 -- ns 20.24, 20.26 Write command hold time tWCH 15 -- ns 1 Write command 35% duty* setup time 50% duty tWCS 0 -- ns tWCS 0 -- ns tACP tcyc -- -20 ns 50% duty Access time from CAS 4 precharge* -- Notes: 1. 2. 3. 4. 3 20.24 20.25 When frequency is 10 MHz or more. n is the number of wait cycles. -5 ns for parity output of DRAM long-pitch access It is not necessary to meet the tRDS specification as long as the access time specification is met. 5. In the relationship of tCASD2 and tCASD3 with respect to tDACD3, a Min-Max combination does not occur because of the logic structure. Rev. 7.00 Jan 31, 2006 page 500 of 658 REJ09B0272-0700 Section 20 Electrical Characteristics T1 CK tAD A21-A0 HBS, LBS tCSD2 tCSD1 CSn tRDD tRDAC1*1 tRSD RD (Read) tACC1*2 tRDS AD15-AD0 DPH, DPL (Read) tDACD1 tRDH*3 tDACD2 DACK0 DACK1 Notes: 1. For tRDAC1, use tcyc x 0.65 - 35 (for 35% duty) or tcyc x 0.5 - 35 (for 50% duty) instead of tcyc - tRDD - tRDS. 2. For tACC1, use tcyc - 44 instead of tcyc - tAD (or tCSD1) - tRDS. 3. tRDH is measured from A21-A0, CSn, or RD, whichever is negated first. Figure 20.21 Basic Bus Cycle: One-State Access Rev. 7.00 Jan 31, 2006 page 501 of 658 REJ09B0272-0700 Section 20 Electrical Characteristics T1 T2 CK tAD A21-A0 HBS, LBS tCSD2 tCSD1 CSn tRDAC2*1 tRDD tRSD RD (Read) tACC2*2 AD15-AD0 DPH, DPL (Read) DACK0 DACK1 (Read) tDACD1 tWSD1 tRDH*3 tRDS tDACD2 tWSD2 WRH, WRL, WR (Write) tWDH tWDD1 AD15-AD0 (Write) tWPDH tWPDD1 DPH, DPL (Write) tDACD3 tDACD3 DACK0 DACK1 (Write) Notes: 1. For tRDAC2, use tcyc x (n + 1.65) - 35 (for 35% duty) or tcyc x (n + 1.5) - 35 (for 50% duty) instead of tcyc x (n + 2) - tRDD - tRDS. 2. For tACC2, use tcyc x (n + 2) - 44 instead of tcyc x (n + 2) - tAD (or tCSD1) - tRDS. 3. tRDH is measured from A21-A0, CSn, or RD, whichever is negated first. Figure 20.22 Basic Bus Cycle: Two-State Access Rev. 7.00 Jan 31, 2006 page 502 of 658 REJ09B0272-0700 Section 20 Electrical Characteristics T1 TW T2 CK A21-A0 HBS, LBS CSn tRDAC2*1 RD (Read) tACC2*2 AD15-AD0 DPH, DPL (Read) DACK0 DACK1 (Read) WRH, WRL, WR (Write) AD15-AD0 DPH, DPL (Write) DACK0 DACK1 (Write) tWTS tWTH tWTS tWTH WAIT Notes: 1. For tRDAC2, use tcyc x (n + 1.65) - 35 (for 35% duty) or tcyc x (n + 1.5) - 35 (for 50% duty) instead of tcyc x (n + 2) - tRDD - tRDS. 2. For tACC2, use tcyc x (n + 2) - 44 instead of tcyc x (n + 2) - tAD (or tCSD1) - tRDS. Figure 20.23 Basic Bus Cycle: Two States + Wait State Rev. 7.00 Jan 31, 2006 page 503 of 658 REJ09B0272-0700 Section 20 Electrical Characteristics Tp Tr Tc CK tAD tAD Row A21-A0 tRASD1 Column tRASD2 tRAH RAS tDS tASC CAS tCASD1 tRSD tRDD RD(Read) tWCH WRH, WRL, WR(Read) tDACD1 tDACD2 DACK0 DACK1 (Read) *1 t tACC1*2 CAC1 tRAC1*3 tRDS AD15-AD0 DPH, DPL (Read) RD(Write) tWSD3 WRH, WRL, WR(Write) tWCS tWDD2 AD15-AD0 (Write) tWSD4 tWDH tWPDH tWPDD2 DPH, DPL (Write) tRDH*4 tDACD4 tDACD5 DACK0 DACK1 (Write) Notes: 1. For tCAC1, use tcyc x 0.65 - 35 (for 35% duty) or tcyc x 0.5 - 35 (for 50% duty) instead of tcyc - tAD - tASC - tRDS. 2. For tACC1, use tcyc - 44 instead of tcyc - tAD - tRDS. 3. For tRAC1, use tcyc x 1.5 - 35 instead of tcyc x 1.5 - tRASD1 - tRDS. 4. tRDH is measured from A21-A0, RAS, or CAS, whichever is negated first. Figure 20.24 DRAM Bus Cycle (Short-Pitch, Normal Mode) Rev. 7.00 Jan 31, 2006 page 504 of 658 REJ09B0272-0700 Section 20 Electrical Characteristics Tp Tr Tc Tc Tc Tc CK tAD A21-A0 tAD Row address Column address Column address Column address Column address tRASD2 tRASD1 RAS tASC tCP CAS tRDD tRSD RD(Read) WRH, WRL, WR(Read) tCAC1*1 AD15-AD0 DPH, DPL (Read) DACK0 DACK1 (Read) tRAC1*3 tACC1*2 tACP tRDS tRDH*4 tRDH*5 tDACD1 tDACD2 Notes: 1. For tCAC1, use tcyc x 0.65 - 35 (for 35% duty) or tcyc x 0.5 - 35 (for 50% duty) instead of tcyc - tAD - tASC - tRDS. It is not necessary to meet the tRDS specification as long as the tCAC1 specification is met. 2. For tACC1, use tcyc - 44 instead of tcyc - tAD - tRDS. It is not necessary to meet the tRDS specification as long as the tACC1 specification is met. 3. For tRAC1, use tcyc x 1.5 - 35 instead of tcyc x 1.5 - tRASD1 - tRDS. It is not necessary to meet the tRDS specification as long as the tRAC1 specification is met. 4. tRDH is measured from A21-A0 or CAS, whichever is negated first. 5. tRDH is measured from A21-A0, RAS, or CAS, whichever is negated first. Figure 20.25 (a) DRAM Bus Cycle (Short-Pitch, High-Speed Page Mode: Read) Rev. 7.00 Jan 31, 2006 page 505 of 658 REJ09B0272-0700 Section 20 Electrical Characteristics Tp Tr Silent cycle Tc Tc CK tAD A21-A0 tAD Row address Column address Column address tRASD2 tRASD1 RAS tASC CAS RD (Write) tWSD3 tWSD4 WRH, WRL, WR (Write) tWDD2 tWDH tWPDD2 tWPDH AD15-AD0 DPH, DPL (Write) DPH, DPL (Write) tDACD4 tDACD5 tDACD5 DACK0 DACK1 (Write) Figure 20.25 (b) DRAM Bus Cycle (Short-Pitch, High-Speed Page Mode: Write) Note: For details of the silent cycle, see section 8.5.5, DRAM Burst Mode. Rev. 7.00 Jan 31, 2006 page 506 of 658 REJ09B0272-0700 Section 20 Electrical Characteristics Tp Tr Tc1 Tc2 CK tAD A21-A0 tRASD1 tAD Row tRAH Column tRASD2 RAS tDS tCASD2 CAS tCASD3 tRDD tRSD RD(Read) tWCH WRH, WRL, WR(Read) tCAC2*1 tACC2*2 tRAC2*3 AD15-AD0 DPH, DPL (Read) DACK0 DACK1 (Read) tRDS tRDH*4 tDACD2 tDACD1 RD(Write) WRH, WRL, WR(Write) AD15-AD0 (Write) DPH, DPL (Write) tWSD1 tWSD2 tWDH tWDD1 tWPDH tWPDD1 tDACD3 tDACD3 DACK0 DACK1 (Write) Notes: 1. 2. 3. 4. For tCAC2, use tcyc x (n + 1) - 35 instead of tcyc x (n + 1) - tCASD2 - tRDS. For tACC2, use tcyc x (n + 2) - 44 instead of tcyc x (n + 2) - tAD - tRDS. For tRAC2, use tcyc x (n + 2.5) - 35 instead of tcyc x (n + 2.5) - tRASD1 - tRDS. tRDH is measured from A21-A0, CAS, or RAS, whichever is negated first. Figure 20.26 DRAM Bus Cycle: (Long-Pitch, Normal Mode) Rev. 7.00 Jan 31, 2006 page 507 of 658 REJ09B0272-0700 Section 20 Electrical Characteristics Tp Tr Tc1 Tc2 Tc1 Tc2 CK tAD A21-A0 tAD Row tRASD1 Column Column tRASD2 RAS tCASD2 CAS tCASD3 tRDD tRSD RD(Read) WRH, WRL, WR(Read) AD15-AD0 DPH, DPL (Read) tCASD3 tRAC2*3 DACK0 DACK1 (Read) RD(Write) WRH, WRL, WR(Write) tACC2*2 tCAC2*1 tRDS tRDH*4 tDACD1 tDACD2 tWSD1 tWDD1 tWSD2 tRDH*5 tDACD1 tWSD1 tDACD2 tWSD2 tWDH tWDD1 tWDH tWPDH tWPDD1 tWPDH AD15-AD0 (Write) tWPDD1 DPH, DPL (Write) DACK0 DACK1 (Write) Notes: 1. 2. 3. 4. 5. tDACD3 tDACD3 tDACD3 tDACD3 For tCAC2, use tcyc x (n + 1) - 35 instead of tcyc x (n + 1) - tCASD2 - tRDS. For tACC2, use tcyc x (n + 2) - 44 instead of tcyc x (n + 2) - tAD - tRDS. For tRAC2, use tcyc x (n + 2.5) - 35 instead of tcyc x (n + 2.5) - tRASD2 - tRDS. tRDH is measured from A21-A0 or CAS, whichever is negated first. tRDH is measured from A21-A0, RAS, or CAS whichever is negated first. Figure 20.27 DRAM Bus Cycle: (Long-Pitch, High-Speed Page Mode) Rev. 7.00 Jan 31, 2006 page 508 of 658 REJ09B0272-0700 Section 20 Electrical Characteristics Tp Tr Tc1 Tw Tc2 CK A21-A0 RAS Row Column tRSD tRDD CAS RD(Read) WRH, WRL, WR(Read) tCAC2*1 tACC2*2 tRAC2*3 AD15-AD0 DPH, DPL (Read) DACK0 DACK1 (Read) RD(Write) WRH, WRL, WR(Write) AD15-AD0 (Write) DPH, DPL (Write) DACK0 DACK1 (Write) tWTS tWTH tWTS tWTH WAIT Notes: 1. For tCAC2, use tcyc x (n + 1) - 35 instead of tcyc x (n + 1) - tCASD2 - tRDS. 2. For tACC2, use tcyc x (n + 2) - 44 instead of tcyc x (n + 2) - tAD - tRDS. 3. For tRAC2, use tcyc x (n + 2.5) - 35 instead of tcyc x (n + 2.5) - tRASD1 - tRDS. Figure 20.28 DRAM Bus Cycle: (Long-Pitch, High-Speed Page Mode + Wait State) Rev. 7.00 Jan 31, 2006 page 509 of 658 REJ09B0272-0700 Section 20 Electrical Characteristics TRp TRr TRc CK tRASD1 RAS tRASD2 tCSR tCASD3 tCASD2 CAS WRH, WRL, WR Figure 20.29 CAS-before-RAS Refresh (Short-Pitch) TRp TRr TRc TRc CK tRASD1 RAS tRASD2 tCSR tCASD3 tCASD2 CAS WRH, WRL, WR Figure 20.30 CAS-before-RAS Refresh (Long-Pitch) TRp TRr TRc TRcc CK tRASD1 RAS tCSR tCASD2 CAS Figure 20.31 Self-Refresh Rev. 7.00 Jan 31, 2006 page 510 of 658 REJ09B0272-0700 tRASD2 tCASD3 Section 20 Electrical Characteristics T2 T1 T3 T4 CK tAD A21-A0 HBS, LBS tCSD3 tCSD4 CS6 tAHD1 tAHD2 AH tRDD RD (Read) tMAD AD15-AD0 (Read) tMAH tRSD tRDAC3 Address tRDH Data (input) tDACD1 tDACD2 DACK0 DACK1 (Read) tWSD1 tWSD2 WRH, WRL, WR (Write) tMAD AD15-AD0 (Write) tMAH tWDD1 Data (output) Address tDACD3 DACK0 DACK1 (Write) tWDH tDACD3 tWTH tWTS WAIT Figure 20.32 Address/Data Multiplex I/O Bus Cycle Rev. 7.00 Jan 31, 2006 page 511 of 658 REJ09B0272-0700 Section 20 Electrical Characteristics T1 CK tAD A21-A0 HBS, LBS tCSD2 tCSD1 CSn tWSD1 tWSD4 tDACD1 tDACD2 WRH, WRL, WR (Write) DACK0 DACK1 (Write) Figure 20.33 DMA Single Transfer/One-State Access Write (4) DMAC Timing Table 20.8 DMAC Timing Case A: VCC = 3.0 to 5.5 V, AVCC = 3.0 to 5.5 V, AVCC = VCC 10%, AVref = 3.0 V to AVCC, VSS = AVSS = 0 V, Ta = -20 to +75C* Case B: VCC = 5.0 V 10%, AVCC = 5.0 V 10%, AVCC = VCC 10%, AVref = 4.5 V to AVCC, VSS = AVSS = 0 V, Ta = -20 to +75C* Note: * Regular-specification products; for wide-temperature-range products, Ta = -40 to +85C Case A Case B 12.5 MHz 20 MHz Item Symbol Min Max Min Max Unit Figure DREQ0, DREQ1 setup time tDRQS 80 -- 27 -- ns 20.34 DREQ0, DREQ1 hold time tDRQH 30 -- 30 -- ns DREQ0, DREQ1 Pulse width tDRQW 1.5 -- 1.5 -- tcyc Rev. 7.00 Jan 31, 2006 page 512 of 658 REJ09B0272-0700 20.35 Section 20 Electrical Characteristics CK tDRQS DREQ0, DREQ1 level tDRQS tDRQH DREQ0, DREQ1 edge tDRQS DREQ0, DREQ1 level release Figure 20.34 DREQ0, DREQ0 DREQ1 Input Timing (1) CK DREQ0, DREQ1 edge tDRQW Figure 20.35 DREQ0, DREQ0 DREQ1 Input Timing (2) Rev. 7.00 Jan 31, 2006 page 513 of 658 REJ09B0272-0700 Section 20 Electrical Characteristics (5) 16-bit Integrated Timer Pulse Unit Timing Table 20.9 16-bit Integrated Timer Pulse Unit Timing Case A: VCC = 3.0 to 5.5 V, AVCC = 3.0 to 5.5 V, AVCC = VCC 10%, AVref = 3.0 V to AVCC, VSS = AVSS = 0 V, Ta = -20 to +75C* Case B: VCC = 5.0 V 10%, AVCC = 5.0 V 10%, AVCC = VCC 10%, AVref = 4.5 V to AVCC, VSS = AVSS = 0 V, Ta = -20 to +75C* Note: * Regular-specification products; for wide-temperature-range products, Ta = -40 to +85C Case A Case B 12.5 MHz 20 MHz Item Symbol Min Max Min Max Unit Figure Output compare delay time tTOCD -- 100 -- 100 ns 20.36 Input capture setup time tTICS 50 -- 35 -- ns Timer clock input setup time tTCKS 50 -- 50 -- ns Timer clock pulse width (single edge) tTCKWH/L 1.5 -- 1.5 -- tcyc Timer clock pulse width (both edges) tTCKWL/L 2.5 -- 2.5 -- tcyc CK tTOCD Output compare*1 tTICS Input capture*2 Notes: 1. TIOCA0-TIOCA4, TIOCB0-TIOCB4, TOCXA4, TOCXB4 2. TIOCA0-TIOCA4, TIOCB0-TIOCB4 Figure 20.36 ITU Input/Output Timing Rev. 7.00 Jan 31, 2006 page 514 of 658 REJ09B0272-0700 20.37 Section 20 Electrical Characteristics CK tTCKS TCLKA- TCLKD tTCKS tTCKWL tTCKWH Figure 20.37 ITU Clock Input Timing (6) Programmable Timing Pattern Controller and I/O Port Timing Table 20.10 Programmable Timing Pattern Controller and I/O Port Timing Case A: VCC = 3.0 to 5.5 V, AVCC = 3.0 to 5.5 V, AVCC = VCC 10%, AVref = 3.0 V to AVCC, VSS = AVSS = 0 V, = 12.5 MHz, Ta = -20 to +75C* Case B: VCC = 5.0 V 10%, AVCC = 5.0 V 10%, AVCC = VCC 10%, AVref = 4.5 V to AVCC, VSS = AVSS = 0 V, = 20 MHz, Ta = -20 to +75C* Note: * Regular-specification products; for wide-temperature-range products, Ta = -40 to +85C Cases A and B Item Symbol Min Max Unit Figure Port output delay time tPWD -- 100 ns 20.38 Port input hold time tPRH 50 -- ns Port input setup time tPRS 50 -- ns Rev. 7.00 Jan 31, 2006 page 515 of 658 REJ09B0272-0700 Section 20 Electrical Characteristics T1 T2 T3 CK tPRS tPRH Ports A-C (Read) tPWD Ports A-C (Write) Figure 20.38 Programmable Timing Pattern Controller Output Timing (7) Watchdog Timer Timing Table 20.11 Watchdog Timer Timing Case A: VCC = 3.0 to 5.5 V, AVCC = 3.0 to 5.5 V, AVCC = VCC 10%, AVref = 3.0 V to AVCC, VSS = AVSS = 0 V, = 12.5 MHz, Ta = -20 to +75C* Case B: VCC = 5.0 V 10%, AVCC = 5.0 V 10%, AVCC = VCC 10%, AVref = 4.5 V to AVCC, VSS = AVSS = 0 V, = 20 MHz, Ta = -20 to +75C* Note: * Regular-specification products; for wide-temperature-range products, Ta = -40 to +85C Cases A and B Item Symbol Min Max Unit Figure WDTOVF delay time tWOVD -- 100 ns 20.39 CK tWOVD tWOVD WDTOVF Figure 20.39 Watchdog Timer Output Timing Rev. 7.00 Jan 31, 2006 page 516 of 658 REJ09B0272-0700 Section 20 Electrical Characteristics (8) Serial Communication Interface Timing Table 20.12 Serial Communication Interface Timing Case A: VCC = 3.0 to 5.5 V, AVCC = 3.0 to 5.5 V, AVCC = VCC 10%, AVref = 3.0 V to AVCC, VSS = AVSS = 0 V, = 12.5 MHz, Ta = -20 to +75C* Case B: VCC = 5.0 V 10%, AVCC = 5.0 V 10%, AVCC = VCC 10%, AVref = 4.5 V to AVCC, VSS = AVSS = 0 V, f = 20 MHz, Ta = -20 to +75C* Note: * Regular-specification products; for wide-temperature-range products, Ta = -40 to +85C Cases A and B Item Symbol Min Max Unit Figure Input clock cycle tscyc 4 -- tcyc 20.40 Input clock cycle (synchronous mode) tscyc 6 -- tcyc Input clock pulse width tsckw 0.4 0.6 tscyc Input clock rise time tsckr -- 1.5 tcyc Input clock fall time tsckf -- 1.5 tcyc Transmit data delay time (synchronous mode) tTXD -- 100 ns Receive data setup time (synchronous mode) tRXS 100 -- ns Receive data hold time (synchronous mode) tRXH 100 -- ns tSCKW tSCKr tSCKf 20.41 SCK0, SCK1 tscyc Figure 20.40 Input Clock Timing Rev. 7.00 Jan 31, 2006 page 517 of 658 REJ09B0272-0700 Section 20 Electrical Characteristics tscyc SCK0, SCK1 tTXD TxD0, TxD1 (transmit data) tRXS tRXH RxD0, RxD1 (receive data) Figure 20.41 SCI I/O Timing (Synchronous Mode) (9) A/D Converter Timing Table 20.13 A/D Converter Timing Case A: VCC = 3.0 to 5.5 V, AVCC = 3.0 to 5.5 V, AVCC = VCC 10%, AVref = 3.0 V to AVCC, VSS = AVSS = 0 V, = 12.5 MHz, Ta = -20 to +75C* Case B: VCC = 5.0 V 10%, AVCC = 5.0 V 10%, AVCC = VCC 10%, AVref = 4.5 V to AVCC, VSS = AVSS = 0 V, = 20 MHz, Ta = -20 to +75C* Note: * Regular-specification products; for wide-temperature-range products, Ta = -40 to +85C Cases A and B Item Symbol Min typ Max Unit Figure External trigger input pulse width tTRGW 2.0 -- -- tcyc 20.42 External trigger input start delay time tTRGS 50 -- -- ns A/D conversion start delay time tD 10 -- 17 tcyc 6 -- 9 tcyc tSPL -- 64 -- tcyc -- 32 -- tcyc tCONV 259 -- 266 tcyc 131 -- 134 tcyc CKS = 0 CKS = 1 Input sampling time CKS = 0 CKS = 1 A/D conversion time CKS = 0 CKS = 1 Rev. 7.00 Jan 31, 2006 page 518 of 658 REJ09B0272-0700 20.43 Section 20 Electrical Characteristics 1 state CK ADTRG input tTRGW tTRGS tTRGW ADST Figure 20.42 External Trigger Input Timing tCONV tD 3 states tSPL Max. 14 states CK Address Analog input sampling signal ADF Figure 20.43 Analog Conversion Timing Rev. 7.00 Jan 31, 2006 page 519 of 658 REJ09B0272-0700 Section 20 Electrical Characteristics (10) AC Characteristics Test Conditions IOL Microcomputer output pin Device under test output V Vref CL IOH CL is set as follows for each pin. 30pF: CK, CASH, CASL, CS0-CS7, BREQ, BACK, AH, IRQOUT, RAS, DACK0, DACK1 50pF: A21-A0, AD15-AD0, DPH, DPL, RD, WRH, WRL, HBS, LBS, WR 70pF: All port outputs and supporting module output pins other than the above. IOL and IOH values are as shown in section 20.1.2, DC Characteristics, and table 20.3, Permitted Output Current Values. Figure 20.44 Output Load Circuit Rev. 7.00 Jan 31, 2006 page 520 of 658 REJ09B0272-0700 Section 20 Electrical Characteristics 20.1.4 A/D Converter Characteristics Table 20.14 A/D Converter Characteristics (1) Conditions: VCC = 5.0 V 10%, AVCC = 5.0 V 10%, AVCC = VCC 10%, AVref = 4.5 V to AVCC, VSS = AVSS = 0 V, Ta = -20 to +75C* Note: * Regular-specification products; for wide-temperature-range products, Ta = -40 to +85C 12.5 MHz 20 MHz Item Min Typ Max Min Typ Max Unit Resolution 10 10 10 10 10 10 bit Conversion time -- -- 11.2 -- -- 6.7 S Analog input capacitance -- -- 20 -- -- 20 pF Permissible signal-source impedance -- -- 3 -- -- 3 k Nonlinearity error -- -- 3 -- -- 3 LSB Offset error -- -- 3 -- -- 3 LSB Full-scale error -- -- 3 -- -- 3 LSB Quantization error -- -- 0.5 -- -- 0.5 LSB Absolute accuracy -- -- 4 -- -- 4 LSB Table 20.14 A/D Converter Characteristics (2) Conditions: VCC = 3.0 to 5.5 V, AVCC = 3.0 to 5.5 V, AVCC = VCC 10%, AVref = 3.0 V to AVCC, VSS = AVSS = 0 V, Ta = -20 to +75C* Note: * Regular-specification products; for wide-temperature-range products, Ta = -40 to +85C 12.5 MHz Item Min Typ Max Unit Resolution 10 10 10 bit Conversion time -- -- 11.2 S Analog input capacitance -- -- 20 pF Permissible signal-source impedance -- -- 3 k Nonlinearity error -- -- 4.0 LSB Offset error -- -- 4.0 LSB Full-scale error -- -- 4.0 LSB Quantization error -- -- 0.5 LSB Absolute accuracy -- -- 6.0 LSB Rev. 7.00 Jan 31, 2006 page 521 of 658 REJ09B0272-0700 Section 20 Electrical Characteristics 20.2 SH7034B 3.3 V 12.5 MHz Version and 20 MHz Version*1 Electrical Characteristics 20.2.1 Absolute Maximum Ratings Table 20.15 shows the absolute maximum ratings. Table 20.15 Absolute Maximum Ratings Item Symbol Rating Unit Power supply voltage VCC -0.3 to +4.6 V Input voltage (except port C) Vin -0.3 to VCC + 0.3 V Input voltage (port C) Vin -0.3 to AVCC + 0.3 V Analog power supply voltage AVCC -0.3 to +4.6 V Analog reference voltage AVref -0.3 to AVCC + 0.3 V Analog input voltage VAN -0.3 to AVCC + 0.3 V Operating temperature Topr 2 -20 to +75* uC Storage temperature Tstg -55 to +125 uC Caution: Operating the chip in excess of the absolute maximum rating may result in permanent damage. Notes: 1. ROMless products only for 20 MHz version 2. Regular-specification products; for wide-temperature-range products, Topr = -40 to +85C 20.2.2 DC Characteristics Table 20.16 lists DC characteristics. Table 20.18 lists the permissible output current values. Usage Conditions: * Do not release AVCC, AVref and AVSS when the A/D converter is not in use. Connect AVCC and AVref to VCC and AVSS to VSS. * The current consumption value is measured under conditions of VIH min = VCC - 0.5 V and VIL max = 0.5 V with no load on any output pin and the on-chip pull-up MOS off. * Even when the A/D converter is not used or is in standby mode, connect AVCC and AVref to the power voltage(VCC). Rev. 7.00 Jan 31, 2006 page 522 of 658 REJ09B0272-0700 Section 20 Electrical Characteristics Table 20.16 DC Characteristics Conditions: VCC = 3.3 V 0.3V, AVCC = 3.3 V 0.3V, AVCC = VCC 0.3V, AVref = 3.0 V to AVCC, VSS = AVSS = 0 V, = 12.5 to 20 MHz*1, Ta = -20 to +75C*2 Notes: 1. ROMless products only for 20 MHz version 2. Regular-specification products; for wide-temperature-range products, Ta = -40 to +85C Item Symbol Min Input high-level EXTAL voltage VIH Typ Max Unit VCC x 0.9 -- VCC + 0.3 V Port C VCC x 0.7 -- AVCC + 0.3 V Other input pins VCC x 0.7 -- VCC + 0.3 V VCC x 0.2 V Input low-level Other voltage Schmidt trigger input pins VIL -0.3 Schmidt trigger RES , NMI, MD2-MD0, input voltage VT + VCC x 0.9 -- -- V -- Input leakage current - -- PA13-10, PA2, + - PA0, PB7-PB0 VT -VT VCC x 0.07 -- VCC x 0.1 V -- V RES VT |Iin| -- Test Conditions -- -- 1.0 A Vin = 0.5 to VCC - 0.5 V NMI, MD2-MD0 -- -- 1.0 A Vin = 0.5 to VCC - 0.5 V Port C -- -- 1.0 A Vin = 0.5 to AVCC - 0.5 V 3-state leakage Ports A and |ITSI| current B, CS3-CS0, (off state) A21-A0, AD15-AD0 -- -- 1.0 A Vin = 0.5 to VCC - 0.5 V Input pull-up MOS current PA3 -Ip 20 -- 300 A Vin = 0V Output highlevel voltage All output pins VOH VCC - 0.7 -- -- V IOH = -200 A VCC - 1.0 -- -- V IOH = -1 mA Output low level voltage All output pins VOL -- -- 0.4 V IOL = 1.6 mA -- -- 1.2 V IOL = 8 mA Rev. 7.00 Jan 31, 2006 page 523 of 658 REJ09B0272-0700 Section 20 Electrical Characteristics Item Input capacitance Current consumption Symbol Min Typ Max Unit Test Conditions Cin -- -- 30 pF NMI -- -- 30 pF All other input pins -- -- 20 pF Vin = 0 V Input signal f = 1 MHz Ta = 25C -- 25 -- mA f = 12.5 MHz -- 35 60 mA f = 20 MHz -- 20 -- mA f = 12.5 MHz -- 30 40 mA f = 20 MHz -- 0.1 5 A Ta 50C -- -- 10 A 50C < Ta -- 0.5 1 mA -- 0.1 5 A -- 0.5 1 mA -- 0.1 5 A 2.0 -- -- V RES Ordinary operation ICC Sleep Standby Analog power Ordinary supply current operation, Sleep AICC Standby Reference power supply current Ordinary operation, Sleep AIref Standby RAM standby voltage VRAM Usage Notes: 1. If the A/D converter is not used, do not leave the AVCC, Vref, and AVSS pins open. Connect AVCC and AVref to VCC, and connect AVSS to VSS. 2. Current dissipation values are for VIH min = VCC - 0.5 V and VIL max = 0.5 V with all output pins unloaded and the on-chip pull-up transistors in the off state. 3. When the A/D converter is not used, and in standby mode, AVCC and AVref must still be connected to the power supply (VCC). 4. The Characteristic-related performance values, operating margins, noise margins, noise emissions, etc., of this LSI are different from HD6417034A, etc. Caution is therefore required in carrying out system design, when switching from ZTAT version. Rev. 7.00 Jan 31, 2006 page 524 of 658 REJ09B0272-0700 Section 20 Electrical Characteristics Table 20.17 Permitted Output Current Values Conditions: VCC = 3.3 V 0.3V, AVCC = 3.3 V 0.3V, AVCC = VCC 0.3V, AVref = 3.0 V to AVCC, VSS = AVSS = 0 V, Ta = -20 to +75C* Note: * Regular-specification products; for wide-temperature-range products, Ta = -40 to +85C 12.5 MHz 20 MHz Item Symbol Min Typ Max Min Typ Max Unit Output low-level permissible current (per pin) IOL -- -- 10 -- -- 10 mA Output low-level permissible current (total) IOL -- -- 80 -- -- 80 mA Output high-level permissible current (per pin) -IOH -- -- 2.0 -- -- 2.0 mA Output high-level permissible current (total) - IOH -- -- 25 -- -- 25 mA Caution: To ensure reliability of the chip, do not exceed the output current values given in table 20.17. Rev. 7.00 Jan 31, 2006 page 525 of 658 REJ09B0272-0700 Section 20 Electrical Characteristics 20.2.3 AC Characteristics The following AC timing chart represents the AC characteristics, not signal functions. For signal functions, see the explanation in the text. (1) Clock Timing Table 20.18 Clock Timing Conditions: VCC = 3.3 V 0.3V, AVCC = 3.3 V 0.3V, AVCC = VCC 0.3V, AVref = 3.0 V to AVCC, VSS = AVSS = 0 V, Ta = -20 to +75C* Note: * Regular-specification products; for wide-temperature-range products, Ta = -40 to +85C 12.5 MHz 20 MHz Item Symbol Min Max Min Max Unit Figures EXTAL input high level pulse width tEXH 22 -- 15 -- ns 20.45 EXTAL input low level pulse width tEXL 22 -- 15 -- ns EXTAL input rise time tEXr -- 10 -- 5 ns EXTAL input fall time tEXf -- 10 -- 5 ns Clock cycle time tcyc 80 500 50 250 ns 20.45, 20.46 Clock high pulse width tCH 30 -- 20 -- ns 20.46 Clock low pulse width tCL 30 -- 20 -- ns Clock rise time tCr -- 10 -- 5 ns Clock fall time tCf -- 10 -- 5 ns Reset oscillation settling time tOSC1 10 -- 10 -- ms Software standby oscillation settling time tOSC2 10 -- 10 -- ms Rev. 7.00 Jan 31, 2006 page 526 of 658 REJ09B0272-0700 20.47 Section 20 Electrical Characteristics tcyc tEXH 1/2 VCC EXTAL tEXL VIH VIL tEXr tEXf Figure 20.45 EXTAL Input Timing tCYC tCH tCL CK tCf tCr Figure 20.46 System Clock Timing CK VCC tOSC2 tOSC1 RES Figure 20.47 Oscillation Settling Time Rev. 7.00 Jan 31, 2006 page 527 of 658 REJ09B0272-0700 Section 20 Electrical Characteristics (2) Control Signal Timing Table 20.19 Control Signal Timing Conditions: VCC = 3.3 V 0.3V, AVCC = 3.3 V 0.3V, AVCC = VCC 0.3V, AVref = 3.0 V to AVCC, VSS = AVSS = 0 V, Ta = -20 to +75C* Note: * Regular-specification products; for wide-temperature-range products, Ta = -40 to +85C 12.5 MHz 20 MHz Item Symbol Min Max Min Max Unit Figure RES setup time tRESS 320 -- 200 -- ns 20.48 RES pulse width tRESW 20 -- 20 -- tcyc NMI reset setup time tNMIRS 320 -- 200 -- ns NMI reset hold time tNMIRH 320 -- 200 -- ns NMI setup time tNMIS 160 -- 100 -- ns NMI hold time tNMIH 80 -- 50 -- ns IRQ0-IRQ7 setup time (edge detection) tIRQES 160 -- 100 -- ns IRQ0-IRQ7 setup time (level detection) tIRQLS 160 -- 100 -- ns IRQ0-IRQ7 hold time tIRQEH 80 -- 50 -- ns IRQOUT output delay time tIRQOD -- 80 -- 50 ns 20.50 Bus request setup time tBRQS 80 -- 50 -- ns 20.51 Bus acknowledge delay time 1 tBACD1 -- 80 -- 50 ns Bus acknowledge delay time 2 tBACD2 -- 80 -- 50 ns Bus 3-state delay time tBZD -- 80 -- 50 ns Rev. 7.00 Jan 31, 2006 page 528 of 658 REJ09B0272-0700 20.49 Section 20 Electrical Characteristics CK tRESS tRESS RES tNMIRS tRESW tNMIRH NMI Figure 20.48 Reset Input Timing CK tNMIS tNMIH tIRQES tIRQEH NMI IRQ edge tIRQLS IRQ level Figure 20.49 Interrupt Signal Input Timing CK tIRQOD tIRQOD IRQOUT Figure 20.50 Interrupt Signal Output Timing Rev. 7.00 Jan 31, 2006 page 529 of 658 REJ09B0272-0700 Section 20 Electrical Characteristics CK tBRQS BREQ (Input) tBRQS tBACD1 BACK (Output) tBZD RD, WR, RAS, CAS, CSn tBZD A21-A0 Figure 20.51 Bus Release Timing Rev. 7.00 Jan 31, 2006 page 530 of 658 REJ09B0272-0700 tBACD2 Section 20 Electrical Characteristics (3) Bus Timing Tables 20.20 show the bus timing. Table 20.20 Bus Timing (1) Conditions: VCC = 3.3 V 0.3V, AVCC = 3.3 V 0.3V, AVCC = VCC 0.3V, AVref = 3.0 V to AVCC, VSS = AVSS = 0 V, = 20 MHz*1, Ta = -20 to +75C*2 Notes: 1. ROMless products 2. Regular-specification products; for wide-temperature-range products, Ta = -40 to +85C Item Symbol Min Max 1 Unit Figures ns 20.52, 20.53, 20.55- 20.58, 20.63, 20.64 20.52, 20.53, 20.64 Address delay time tAD -- 20* CS delay time 1 tCSD1 -- 25 ns CS delay time 2 tCSD2 -- 25 ns CS delay time 3 tCSD3 -- 25 ns tCSD4 -- 25 ns tcyc x 0.65 - 20 -- ns CS delay time 4 6 2 6 2 Access time 1* 35% duty* tRDAC1 from read strobe 50% duty Access time 2* 35% duty* tRDAC2 from read strobe 50% duty 6 2 tcyc x 0.5 - 20 -- ns tcyc x (n+1.65) - 20* -- ns 3 3 tcyc x (n+1.5)- 20* -- ns tcyc x (n+0.65) - 20* -- ns 3 20.63 20.52 20.53, 20.54 Access time 3* 35% duty* tRDAC3 from read strobe 50% duty tcyc x (n+0.5)- 20* -- ns Read strobe delay time tRSD -- 20 ns 20.52, 20.53, 20.55- 20.59, 20.63 Read data setup time tRDS 15 -- ns 20.52, 20.53, 20.55- 20.58, 20.63 Read data hold time tRDH 0 -- ns Write strobe delay time 1 tWSD1 -- 20 ns 20.53, 20.57, 20.58, 20.63, 20.64 Write strobe delay time 2 tWSD2 -- 20 ns 20.53, 20.57, 20.58, 20.63 Write strobe delay time 3 tWSD3 -- 20 ns 20.55, 20.56 Write strobe delay time 4 tWSD4 -- 20 ns 20.55, 20.56, 20.64 3 20.63 Rev. 7.00 Jan 31, 2006 page 531 of 658 REJ09B0272-0700 Section 20 Electrical Characteristics Item Symbol Min Write data delay time 1 tWDD1 -- Write data delay time 2 tWDD2 Write data hold time tWDH Parity output delay time 1 Max Unit Figures 35 ns -- 20 ns 20.55, 20.56 0 -- ns 20.53, 20.55-20.58 tWPDD1 -- 40 ns 20.53, 20.57, 20.58 Parity output delay time 2 tWPDD2 -- 20 ns 20.55, 20.56 Parity output hold time tWPDH 0 -- ns 20.53, 20.55-20.58 Wait setup time tWTS 10 -- ns 20.54, 20.59, 20.63 Wait hold time tWTH 6 -- ns tACC1 tcyc - 30* -- ns 20.52, 20.55, 20.56 ns 20.53, 20.54, 20.57- 20.59 6 Read data access time 1* 6 4 3 20.53, 20.57, 20.58, 20.63 Read data access time 2* tACC2 tcyc x (n+2) - 30* -- RAS delay time 1 tRASD1 -- 20 ns RAS delay time 2 tRASD2 -- 30 ns 20.55-20.58, 20.60-20.62 CAS delay time 1 tCASD1 -- 20 ns 20.55 7 tCASD2 -- 20 ns 7 tCASD3 -- 20 ns 20.57, 20.58, 20.60-20.62 20.55, 20.56 CAS delay time 2* CAS delay time 3* Column address setup time tASC 0 -- ns Read data access 35% 6 2 time from CAS 1* duty* tcyc x 0.65 -19 -- ns -- ns tCAC1 50% duty tcyc x 0.5 - 19 3 Read data access time from tCAC2 6 CAS 2* tcyc x (n+1) - 25* -- ns 20.57-20.59 Read data access time from tRAC1 6 RAS 1* tcyc x 1.5 - 20 -- ns 20.55, 20.56 Read data access time from tRAC2 6 RAS 2* tcyc x (n+2.5)- 20* -- ns 20.57-20.59 High-speed page mode CAS tCP precharge time tcyc x 0.25 -- ns 20.56 3 Rev. 7.00 Jan 31, 2006 page 532 of 658 REJ09B0272-0700 Section 20 Electrical Characteristics Item Symbol Min Max Unit Figures AH delay time 1 tAHD1 -- 20 ns AH delay time 2 tAHD2 -- 20 ns Multiplexed address delay time tMAD -- 30 ns Multiplexed address hold time tMAH 0 -- ns DACK0, DACK1 delay time 1 tDACD1 -- 23 ns DACK0, DACK1 delay time 2 20.63 20.52, 20.53, 20.55- 20.58, 20.63, 20.64 tDACD2 -- 23 ns 7 DACK0, DACK1 delay time 3* tDACD3 -- 20 ns 20.53, 20.57, 20.58, 20.63 DACK0, DACK1 delay time 4 tDACD4 -- 20 ns 20.55, 20.56 tDACD5 -- 20 ns 35% duty* tRDD -- tcyc x 0.35 + 12 ns 50% duty -- DACK0, DACK1 delay time 5 Read delay time 2 tcyc x 0.5 + 15 ns 20.52, 20.53, 20.55- 20.59, 20.63 Data setup time for CAS tDS 0* -- ns 20.55, 20.57 CAS setup time for RAS tCSR 10 -- ns 20.60-20.62 Row address hold time tRAH 10 -- ns 20.55, 20.57 Write command hold time tWCH 15 -- ns Write command setup time Access time from 6 CAS precharge* 5 2 35% duty* tWCS 0 -- ns 50% duty tWCS 0 -- ns tACP tcyc -20 -- ns 20.55 20.56 Notes: 1. 2. 3. 4. 5. 6. HBS and LBS signals are 25 ns. When frequency is 10 MHz or more. n is the number of wait cycles. Access time from addresses A0 to A21 is tcyc-25 ns. -5ns for parity output of DRAM long-pitch access. It is not necessary to meet the tRDS specification as long as the access time specification is met. 7. In the relationship of tCASD2 and tCASD3 with respect to tDACD3, a Min-Max combination does not occur because of the logic structure. Rev. 7.00 Jan 31, 2006 page 533 of 658 REJ09B0272-0700 Section 20 Electrical Characteristics Table 20.20 Bus Timing (2) Conditions: VCC = 3.3 V 0.3V, AVCC = 3.3 V 0.3V, AVCC = VCC 0.3V, AVref = 3.0 V to AVCC, VSS = AVSS = 0 V, = 12.5 MHz, Ta = -20 to +75C* Note: * Regular-specification products; for wide-temperature-range products, Ta = -40 to +85C Item Symbol Min Max Unit Figures Address delay time tAD -- 40 ns 20.52, 20.53, 20.55- 20.58, 20.63, 20.64 CS delay time 1 tCSD1 -- 40 ns 20.52, 20.53, 20.64 CS delay time 2 tCSD2 -- 40 ns CS delay time 3 tCSD3 -- 40 ns tCSD4 -- 40 ns tcyc x 0.65 - 35-- ns CS delay time 4 4 1 4 1 Access time 1* 35% duty* tRDAC1 from read strobe 50% duty Access time 2* 35% duty* tRDAC2 from read strobe 50% duty 4 1 35% duty* tRDAC3 Access time 3* from read strobe 50% duty tcyc x 0.5 - 35 -- ns tcyc x (n+1.65) -- 2 - 35* ns tcyc x (n+1.5) 2 - 35* -- ns tcyc x (n+0.65) -- 2 - 35* ns tcyc x (n+0.5) 2 - 35* -- ns 20.63 20.52 20.53, 20.54 20.63 Read strobe delay time tRSD -- 40 ns 20.52, 20.53, 20.55- 20.59, 20.63 Read data setup time tRDS 25 -- ns 20.52, 20.53, 20.55- 20.58, 20.63 Read data hold time tRDH 0 -- ns Write strobe delay time 1 tWSD1 -- 40 ns 20.53, 20.57, 20.58, 20.63, 20.64 Write strobe delay time 2 tWSD2 -- 30 ns 20.53, 20.57, 20.58, 20.63 Write strobe delay time 3 tWSD3 -- 40 ns 20.55, 20.56 Write strobe delay time 4 tWSD4 -- 40 ns 20.55, 20.56, 20.64 Rev. 7.00 Jan 31, 2006 page 534 of 658 REJ09B0272-0700 Section 20 Electrical Characteristics Item Symbol Min Max Unit Figures Write data delay time 1 tWDD1 -- 70 ns 20.53, 20.57, 20.58, 20.63 Write data delay time 2 tWDD2 -- 40 ns 20.55, 20.56 Write data hold time tWDH -10 -- ns 20.53, 20.55-20.58, 20.63 Parity output delay time 1 tWPDD1 -- 80 ns 20.53, 20.57, 20.58 Parity output delay time 2 tWPDD2 -- 40 ns 20.55, 20.56 Parity output hold time tWPDH -10 -- ns 20.53, 20.55-20.58 Wait setup time tWTS 40 -- ns 20.54, 20.59, 20.63 Wait hold time tWTH 10 -- ns 4 tACC1 tcyc - 44 -- ns 20.52, 20.55, 20.56 4 Read data access time 2* tACC2 tcyc x (n+2) - -- 2 44* ns 20.53, 20.54, 20.57- 20.59 RAS delay time 1 tRASD1 -- 40 ns RAS delay time 2 tRASD2 -- 40 ns 20.55-20.58, 20.60-20.62 tCASD1 -- 40 ns 20.55 40 ns Read data access time 1* CAS delay time 1 5 CAS delay time 2* tCASD2 -- 5 CAS delay time 3* tCASD3 -- 40 ns 20.57, 20.58, 20.60-20.62 Column address setup time tASC 0 -- ns 20.55, 20.56 Read data access 35% 4 1 time from CAS 1* duty* tCAC1 tcyc x 0.65 - 35 -- ns tcyc x 0.5 - 35 -- ns 50% duty Read data access time from 4 CAS 2* tCAC2 tcyc x (n+1) - -- 2 35* ns 20.57-20.59 Read data access time from 4 RAS 1* tRAC1 tcyc x 1.5 - 35 -- ns 20.55, 20.56 Read data access time from 4 RAS 2* tRAC2 tcyc x (n+2.5) -- 2 - 35* ns 20.57-20.59 High-speed page mode CAS precharge time tCP tcyc x 0.25 ns 20.56 -- Rev. 7.00 Jan 31, 2006 page 535 of 658 REJ09B0272-0700 Section 20 Electrical Characteristics Item Symbol Min Max Unit Figures AH delay time 1 tAHD1 -- 40 ns AH delay time 2 tAHD2 -- 40 ns Multiplexed address delay time tMAD -- 40 ns Multiplexed address hold time tMAH -10 -- ns DACK0, DACK1 delay time 1 tDACD1 -- 40 ns DACK0, DACK1 delay time 2 20.63 20.52, 20.53, 20.55- 20.58, 20.63, 20.64 tDACD2 -- 40 ns 5 DACK0, DACK1 delay time 3* tDACD3 -- 40 ns 20.53, 20.57, 20.58, 20.63 DACK0, DACK1 delay time 4 tDACD4 -- 40 ns 20.55, 20.56 tDACD5 -- 40 ns 35% duty* tRDD -- tcyc x 0.35 + 35 ns 50% duty -- DACK0, DACK1 delay time 5 Read delay time 1 tcyc x 0.5 + 35 ns 20.52, 20.53, 20.55- 20.59, 20.63 Data setup time for CAS tDS 0* -- ns 20.55, 20.57 CAS setup time for RAS tCSR 10 -- ns 20.60-20.62 Row address hold time tRAH 10 -- ns 20.55, 20.57 Write command hold time tWCH 15 -- ns Write command setup time 1 35% duty* tWCS 0 -- ns 50% duty 0 -- ns tcyc -20 -- ns Access time from CAS 4 precharge* Notes: 1. 2. 3. 4. 5. 3 tACP 20.55 20.56 When frequency is 10 MHz or more. n is the number of wait cycles. -5ns for parity output of DRAM long-pitch access. If the access time is satisfied, tRDS need not be satisfied. In the relationship between tCASD2 and tCASD3 for tDACD3, the pair of Min-Max is not exist in the logical structure. Rev. 7.00 Jan 31, 2006 page 536 of 658 REJ09B0272-0700 Section 20 Electrical Characteristics T1 CK tAD A21-A0 HBS, LBS tCSD2 tCSD1 CSn tRDD tRDAC1*1 tRSD RD (Read) tACC1*2 tRDS AD15-AD0 DPH, DPL (Read) tDACD1 tRDH*3 tDACD2 DACK0 DACK1 Notes: 1. For tRDAC1, use tcyc x 0.65 - 20 (for 35% duty) or tcyc x 0.5 - 20 (for 50% duty) instead of tcyc - tRDD - tRDS. 2. For tACC1, use tcyc - 30 instead of tcyc - tAD (or tCSD1) - tRDS. 3. tRDH is measured from A21-A0, CSn, or RD, whichever is negated first. Figure 20.52 Basic Bus Cycle: One-State Access Rev. 7.00 Jan 31, 2006 page 537 of 658 REJ09B0272-0700 Section 20 Electrical Characteristics T1 CK T2 tAD A21-A0 HBS, LBS tCSD2 tCSD1 CSn tRDD tRDAC2*1 tRSD RD (Read) tACC2*2 AD15-AD0 DPH, DPL (Read) DACK0 DACK1 (Read) tDACD1 tWSD1 tRDH*3 tRDS tDACD2 tWSD2 WRH, WRL, WR (Write) tWDH tWDD1 AD15-AD0 (Write) tWPDH tWPDD1 PL (Write) tDACD3 tDACD3 DACK0 DACK1 (Write) Notes: 1. For tRDAC2, use tcyc x (n + 1.65) - 20 (for 35% duty) or tcyc x (n + 1.5) - 20 (for 50% duty) instead of tcyc x (n + 2) - tRDD - tRDS. 2. For tACC2, use tcyc x (n + 2) - 30 instead of tcyc x (n + 2) - tAD (or tCSD1) - tRDS. 3. tRDH is measured from A21-A0, CSn, or RD, whichever is negated first. Figure 20.53 Basic Bus Cycle: Two-State Access Rev. 7.00 Jan 31, 2006 page 538 of 658 REJ09B0272-0700 Section 20 Electrical Characteristics T1 TW T2 CK A21-A0 HBS, LBS CSn tRDAC2*1 RD (Read) tACC2*2 AD15-AD0 DPH, DPL (Read) DACK0 DACK1 (Read) WRH, WRL, WR (Write) AD15-AD0 DPH, DPL (Write) DACK0 DACK1 (Write) tWTS tWTH tWTS tWTH WAIT Notes: 1. For tRDAC2, use tcyc x (n+1.65) - 20 (for 35% duty) or tcyc x (n+1.5) - 20 (for 50% duty) instead of tcyc x (n+2) - tRDD - tRDS. 2. For tACC2, use tcyc x (n+2) - 30 instead of tcyc x (n+2) - tAD (or tCSD1) - tRDS. Figure 20.54 Basic Bus Cycle: Two States + Wait State Rev. 7.00 Jan 31, 2006 page 539 of 658 REJ09B0272-0700 Section 20 Electrical Characteristics Tp Tr Tc CK tAD tAD Row A21-A0 Column tRASD1 tRASD2 tRAH RAS tDS tASC CAS tRDD tRSD tWCH RD(Read) WRH, WRL, WR(Read) tDACD1 DACK0 DACK1 (Read) tCASD1 tDACD2 tCAC1*1 tACC1*2 tRAC1*3 AD15-AD0 DPH, DPL (Read) RD(Write) tRDS tWSD3 WRH, WRL, WR(Write) tWCS tWDD2 AD15-AD0 (Write) tWSD4 tWDH tWPDH tWPDD2 DPH, DPL (Write) tRDH*4 tDACD4 tDACD5 DACK0 DACK1 (Write) Notes: 1. For tCAC1, use tcyc x 0.65 - 19 (for 35% duty) or tcyc x 0.5 - 19 (for 50% duty) instead of tcyc - tAD - tASC - tRDS. 2. For tACC1, use tcyc - 30 instead of tcyc - tAD - tRDS. 3. For tRAC1, use tcyc x 1.5 - 20 instead of tcyc x 1.5 - tRASD1 - tRDS. 4. tRDH is measured from A21-A0, RAS, or CAS, whichever is negated first. Figure 20.55 DRAM Bus Cycle (Short-Pitch, Normal Mode) Rev. 7.00 Jan 31, 2006 page 540 of 658 REJ09B0272-0700 Section 20 Electrical Characteristics Tp Tr Tc Tc Tc Tc CK tAD A21-A0 tAD Row address Column address Column address Column address Column address tRASD2 tRASD1 RAS tASC tCP CAS tRDD tRSD RD(Read) WRH, WRL, WR(Read) tCAC1*1 AD15-AD0 DPH, DPL (Read) DACK0 DACK1 (Read) tRAC1*3 tACC1*2 tACP tRDS tRDH*4 tRDH*5 tDACD1 tDACD2 Notes: 1. For tCAC1, use tcyc x 0.65 - 19 (for 35% duty) or tcyc x 0.5 - 19 (for 50% duty) instead of tcyc - tAD - tASC - tRDS. It is not necessary to meet the tRDS specification as long as the tCAC1 specification is met. 2. For tACC1, use tcyc - 30 instead of tcyc - tAD - tRDS. It is not necessary to meet the tRDS specification as long as the tACC1 specification is met. 3. For tRAC1, use tcyc x 1.5 - 20 instead of tcyc x 1.5 - tRASD1 - tRDS. It is not necessary to meet the tRDS specification as long as the tRAC1 specification is met. 4. tRDH is measured from A21-A0 or CAS, whichever is negated first. 5. tRDH is measured from A21-A0, RAS, or CAS, whichever is negated first. Figure 20.56 (a) DRAM Bus Cycle (Short-Pitch, High-Speed Page Mode: Read) Rev. 7.00 Jan 31, 2006 page 541 of 658 REJ09B0272-0700 Section 20 Electrical Characteristics Tp Tr Silent cycle Tc Tc CK tAD A21-A0 tAD Row address Column address Column address tRASD2 tRASD1 RAS tASC CAS RD (Write) tWSD3 tWSD4 WRH, WRL, WR (Write) tWDD2 tWDH tWPDD2 tWPDH AD15-AD0 DPH, DPL (Write) DPH, DPL (Write) tDACD4 tDACD5 tDACD5 DACK0 DACK1 (Write) Figure 20.56 (b) DRAM Bus Cycle (Short-Pitch, High-Speed Page Mode: Write) Note: For details of the silent cycle, see section 8.5.5, DRAM Burst Mode. Rev. 7.00 Jan 31, 2006 page 542 of 658 REJ09B0272-0700 Section 20 Electrical Characteristics Tp Tr Tc1 Tc2 CK tAD A21-A0 tRASD1 tAD Row tRAH Column tRASD2 RAS tDS tCASD2 CAS tCASD3 tRDD tRSD RD(Read) WRH, WRL, WR(Read) AD15-AD0 DPH, DPL (Read) DACK0 DACK1 (Read) tWCH tRAC2*3 tACC2*2 tCAC2*1 tRDS tRDH*4 tDACD2 tDACD1 RD(Write) WRH, WRL, WR(Write) AD15-AD0 (Write) DPH, DPL (Write) tWSD1 tWSD2 tWDH tWDD1 tWPDH tWPDD1 tDACD3 tDACD3 DACK0 DACK1 (Write) Notes: 1. 2. 3. 4. For tCAC2, use tcyc x (n + 1) - 25 instead of tcyc x (n + 1) - tCASD2 - tRDS. For tACC2, use tcyc x (n + 2) - 30 instead of tcyc x (n + 2) - tAD - tRDS. For tRAC2, use tcyc x (n + 2.5) - 20 instead of tcyc x (n + 2.5) - tRASD1 - tRDS. tRDH is measured from A21-A0, CAS, or RAS, whichever is negated first. Figure 20.57 DRAM Bus Cycle: (Long-Pitch, Normal Mode) Rev. 7.00 Jan 31, 2006 page 543 of 658 REJ09B0272-0700 Section 20 Electrical Characteristics Tp Tr Tc1 Tc2 Tc1 Tc2 CK tAD A21-A0 tAD Row tRASD1 Column Column tRASD2 RAS tCASD2 CAS tCASD3 tRDD tRSD RD(Read) WRH, WRL, WR (Read) AD15-AD0 DPH, DPL (Read) tCASD3 tRAC2*3 DACK0 DACK1 (Read) RD(Write) WRH, WRL, WR(Write) tACC2*2 tCAC2*1 tRDS tRDH*4 tDACD1 tDACD2 tWSD1 tWDD1 tWSD2 tRDH*5 tDACD1 tWSD1 tDACD2 tWSD2 tWDH tWDD1 tWDH tWPDH tWPDD1 tWPDH AD15-AD0 (Write) tWPDD1 DPH, DPL (Write) DACK0 DACK1 (Write) Notes: 1. 2. 3. 4. 5. tDACD3 tDACD3 tDACD3 tDACD3 For tCAC2, use tcyc x (n + 1) - 25 instead of tcyc x (n + 1) - tCASD2 - tRDS. For tACC2, use tcyc x (n + 2) - 30 instead of tcyc x (n + 2) - tAD - tRDS. For tRAC2, use tcyc x (n + 2.5) - 20 instead of tcyc x (n + 2.5) - tRASD2 - tRDS. tRDH is measured from A21-A0 or CAS, whichever is negated first. tRDH is measured from A21-A0, RAS, or CAS whichever is negated first. Figure 20.58 DRAM Bus Cycle: (Long-Pitch, High-Speed Page Mode) Rev. 7.00 Jan 31, 2006 page 544 of 658 REJ09B0272-0700 Section 20 Electrical Characteristics Tp Tr Tc1 Tw Tc2 CK A21-A0 Row Column tRSD RAS CAS tRDD RD(Read) WRH, WRL, WR(Read) tCAC2*1 tACC2*2 tRAC2*3 AD15-AD0 DPH, DPL (Read) DACK0 DACK1 (Read) RD(Write) WRH, WRL, WR(Write) AD15-AD0 (Write) DPH, DPL (Write) DACK0 DACK1 (Write) tWTS tWTH tWTS tWTH WAIT Notes: 1. For tCAC2, use tcyc x (n + 1) - 25 instead of tcyc x (n + 1) - tCASD2 - tRDS. 2. For tACC2, use tcyc x (n + 2) - 30 instead of tcyc x (n + 2) - tAD - tRDS. 3. For tRAC2, use tcyc x (n + 2.5) - 20 instead of tcyc x (n + 2.5) - tRASD1 - tRDS. Figure 20.59 DRAM Bus Cycle: (Long-Pitch, High-Speed Page Mode + Wait State) Rev. 7.00 Jan 31, 2006 page 545 of 658 REJ09B0272-0700 Section 20 Electrical Characteristics TRp TRr TRc CK tRASD1 RAS tRASD2 tCSR tCASD3 tCASD2 CAS WRH, WRL, WR Figure 20.60 CAS-before-RAS Refresh (Short-Pitch) TRp TRr TRc TRc CK tRASD1 RAS tRASD2 tCSR tCASD3 tCASD2 CAS WRH, WRL, WR Figure 20.61 CAS-before-RAS Refresh (Long-Pitch) Rev. 7.00 Jan 31, 2006 page 546 of 658 REJ09B0272-0700 Section 20 Electrical Characteristics TRp TRr TRc TRcc CK tRASD2 tRASD1 RAS tCSR tCASD3 tCASD2 CAS Figure 20.62 Self-Refresh Rev. 7.00 Jan 31, 2006 page 547 of 658 REJ09B0272-0700 Section 20 Electrical Characteristics T2 T1 T3 T4 CK tAD A21-A0 HBS, LBS tCSD3 tCSD4 CS6 tAHD1 tAHD2 AH tRDD RD (Read) tMAD AD15-AD0 (Read) tMAH tRSD tRDAC3 Address tRDH Data (input) tDACD1 tDACD2 DACK0 DACK1 (Read) tWSD1 tWSD2 WRH, WRL, WR (Write) tMAD AD15-AD0 (Write) tMAH tWDD1 Data (output) Address tDACD3 DACK0 DACK1 (Write) tWDH tDACD3 tWTH tWTS WAIT Figure 20.63 Address/Data Multiplex I/O Bus Cycle Rev. 7.00 Jan 31, 2006 page 548 of 658 REJ09B0272-0700 Section 20 Electrical Characteristics T1 CK tAD A21-A0 HBS, LBS tCSD2 tCSD1 CSn tWSD1 tWSD4 tDACD1 tDACD2 WRH, WRL, WR (Write) DACK0 DACK1 (Write) Figure 20.64 DMA Single Transfer/One-State Access Write (4) DMAC Timing Table 20.21 DMAC Timing Conditions: VCC = 3.3 V 0.3V, AVCC = 3.3 V 0.3V, AVCC = VCC 0.3V, AVref = 3.0 V to AVCC, VSS = AVSS = 0 V, Ta = -20 to +75C* Notes: * Regular-specification products; for wide-temperature-range products, Ta = -40 to +85C 12.5 MHz 20 MHz Item Symbol Min Max Min Max Unit Figure DREQ0, DREQ1 setup time tDRQS 80 -- 27 -- ns 20.65 DREQ0, DREQ1 hold time tDRQH 30 -- 30 -- ns DREQ0, DREQ1 Pulse width tDRQW 1.5 -- 1.5 -- tcyc 20.66 Rev. 7.00 Jan 31, 2006 page 549 of 658 REJ09B0272-0700 Section 20 Electrical Characteristics CK tDRQS DREQ0, DREQ1 level tDRQS tDRQH DREQ0, DREQ1 edge tDRQS DREQ0, DREQ1 level release Figure 20.65 DREQ0, DREQ0 DREQ1 Input Timing (1) CK DREQ0, DREQ1 edge tDRQW Figure 20.66 DREQ0, DREQ0 DREQ1 Input Timing (2) Rev. 7.00 Jan 31, 2006 page 550 of 658 REJ09B0272-0700 Section 20 Electrical Characteristics (5) 16-bit Integrated Timer Pulse Unit Timing Table 20.22 16-bit Integrated Timer Pulse Unit Timing Conditions: VCC = 3.3 V 0.3V, AVCC = 3.3 V 0.3V, AVCC = VCC 0.3V, AVref = 3.0 V to AVCC, VSS = AVSS = 0 V, Ta = -20 to +75C* Notes: * Regular-specification products; for wide-temperature-range products, Ta = -40 to +85C 12.5 MHz 20 MHz Item Symbol Min Max Min Max Unit Figure Output compare delay time tTOCD -- 100 -- 100 ns 20.67 Input capture setup time tTICS 50 -- 35 -- ns Timer clock input setup time tTCKS 50 -- 50 -- ns Timer clock pulse width (single edge) tTCKWH/L 1.5 -- 1.5 -- tcyc Timer clock pulse width (both edges) tTCKWL/L 2.5 -- 2.5 -- tcyc 20.68 CK tTOCD Output compare*1 tTICS Input capture*2 Notes: 1. TIOCA0-TIOCA4, TIOCB0-TIOCB4, TOCXA4, TOCXB4 2. TIOCA0-TIOCA4, TIOCB0-TIOCB4 Figure 20.67 ITU Input/Output Timing Rev. 7.00 Jan 31, 2006 page 551 of 658 REJ09B0272-0700 Section 20 Electrical Characteristics CK tTCKS TCLKA- TCLKD tTCKS tTCKWL tTCKWH Figure 20.68 ITU Clock Input Timing (6) Programmable Timing Pattern Controller and I/O Port Timing Table 20.23 Programmable Timing Pattern Controller and I/O Port Timing Conditions: VCC = 3.3 V 0.3V, AVCC = 3.3 V 0.3V, AVCC = VCC 0.3V, AVref = 3.0 V to AVCC, VSS = AVSS = 0 V, = 12.5 to 20 MHz*1, Ta = -20 to +75C*2 Notes: 1. ROMless products only for 20 MHz version 2. Regular-specification products; for wide-temperature-range products, Ta = -40 to +85C Item Symbol Min Max Unit Figure Port output delay time tPWD -- 100 ns 20.69 Port input hold time tPRH 50 -- ns Port input setup time tPRS 50 -- ns T1 T2 T3 CK tPRS Ports A-C (Read) tPRH tPWD Ports A-C (Write) Figure 20.69 Programmable Timing Pattern Controller Output Timing Rev. 7.00 Jan 31, 2006 page 552 of 658 REJ09B0272-0700 Section 20 Electrical Characteristics (7) Watchdog Timer Timing Table 20.24 Watchdog Timer Timing Conditions: VCC = 3.3 V 0.3V, AVCC = 3.3 V 0.3V, AVCC = VCC 0.3V, AVref = 3.0 V to AVCC, VSS = AVSS = 0 V, = 12.5 to 20 MHz*1, Ta = -20 to +75C*2 Notes: 1. ROMless products only for 20 MHz version 2. Regular-specification products; for wide-temperature-range products, Ta = -40 to +85C Item Symbol Min Max Unit Figure WDTOVF delay time tWOVD -- 100 ns 20.70 CK tWOVD tWOVD WDTOVF Figure 20.70 Watchdog Timer Output Timing Rev. 7.00 Jan 31, 2006 page 553 of 658 REJ09B0272-0700 Section 20 Electrical Characteristics (8) Serial Communication Interface Timing Table 20.25 Serial Communication Interface Timing Conditions: VCC = 3.3 V 0.3V, AVCC = 3.3 V 0.3V, AVCC = VCC 0.3V, AVref = 3.0 V to AVCC, VSS = AVSS = 0 V, = 12.5 to 20 MHz*1, Ta = -20 to +75C*2 Notes: 1. ROMless products only for 20 MHz version 2. Regular-specification products; for wide-temperature-range products, Ta = -40 to +85C Item Symbol Min Max Unit Figure Input clock cycle tscyc 4 -- tcyc 20.71 Input clock cycle (synchronous mode) tscyc 6 -- tcyc Input clock pulse width tSCKW 0.4 0.6 tscyc Input clock rise time tSCKr -- 1.5 tcyc Input clock fall time tSCKf -- 1.5 tcyc Transmit data delay time (synchronous mode) tTXD -- 100 ns Receive data setup time (synchronous mode) tRXS 100 -- ns Receive data hold time (synchronous mode) tRXH 100 -- ns tSCKW tSCKr tSCKf SCK0, SCK1 tscyc Figure 20.71 Input Clock Timing Rev. 7.00 Jan 31, 2006 page 554 of 658 REJ09B0272-0700 20.72 Section 20 Electrical Characteristics tscyc SCK0, SCK1 tTXD TxD0, TxD1 (transmit data) tRXS tRXH RxD0, RxD1 (receive data) Figure 20.72 SCI I/O Timing (Synchronous Mode) (9) A/D Converter Timing Table 20.26 A/D Converter Timing Conditions: VCC = 3.3 V 0.3V, AVCC = 3.3 V 0.3V, AVCC = VCC 0.3V, AVref = 3.0 V to AVCC, VSS = AVSS = 0 V, = 12.5 to 20 MHz*1, Ta = -20 to +75C*2 Notes: 1. ROMless products only for 20 MHz version 2. Regular-specification products; for wide-temperature-range products, Ta = -40 to +85C Item Symbol Min typ Max Unit Figure External trigger input pulse width tTRGW 2.0 -- -- tcyc 20.73 External trigger input start delay time tTRGS 50 -- -- ns A/D conversion start delay time tD 10 -- 17 tcyc 6 -- 9 tcyc -- 64 -- tcyc -- 32 -- tcyc 259 -- 266 tcyc 131 -- 134 tcyc CKS = 0 CKS = 1 Input sampling time CKS = 0 tSPL CKS = 1 A/D conversion time CKS = 0 CKS = 1 tCONV 20.74 Rev. 7.00 Jan 31, 2006 page 555 of 658 REJ09B0272-0700 Section 20 Electrical Characteristics 1 state CK ADTRG input tTRGW tTRGS tTRGW ADST Figure 20.73 External Trigger Input Timing tCONV tD 3 states tSPL Max. 14 states CK Address Analog input sampling signal ADF Figure 20.74 Analog Conversion Timing Rev. 7.00 Jan 31, 2006 page 556 of 658 REJ09B0272-0700 Section 20 Electrical Characteristics (10) AC Characteristics Test Conditions IOL Microcomputer output pin Device under test output V Vref CL IOH CL is set as follows for each pin. 30pF: CK, CASH, CASL, CS0-CS7, BREQ, BACK, AH, IRQOUT, RAS, DACK0, DACK1 50pF: A21-A0, AD15-AD0, DPH, DPL, RD, WRH, WRL, HBS, LBS, WR 70pF: All port outputs and supporting module output pins other than the above. IOL and IOH values are as shown in section 20.2.2, DC Characteristics, and table 20.17, Permitted Output Current Values. Figure 20.75 Output Load Circuit Rev. 7.00 Jan 31, 2006 page 557 of 658 REJ09B0272-0700 Section 20 Electrical Characteristics 20.2.4 A/D Converter Characteristics Table 20.27 A/D Converter Characteristics Conditions: VCC = 3.3 V 0.3V, AVCC = 3.3 V 0.3V, AVCC = VCC 0.3V, AVref = 3.0 V to AVCC, VSS = AVSS = 0 V, Ta = -20 to +75C* Notes: * Regular-specification products; for wide-temperature-range products, Ta = -40 to +85C 12.5 MHz 20 MHz Item Min Typ Max Min Typ Max Unit Resolution 10 10 10 10 10 10 bit Conversion time -- -- 11.2 -- -- 6.7 S Analog input capacitance -- -- 20 -- -- 20 pF Permissible signal-source impedance -- -- 1 -- -- 1 k Nonlinearity error* -- -- 4.0 -- -- 4.0 LSB Offset error* -- -- 4.0 -- -- 4.0 LSB Full-scale error* -- -- 4.0 -- -- 4.0 LSB Quantization error* -- -- 0.5 -- -- 0.5 LSB Absolute accuracy -- -- 6.0 -- -- 6.0 LSB Note: * Reference value Rev. 7.00 Jan 31, 2006 page 558 of 658 REJ09B0272-0700 Appendix A On-Chip Supporting Module Registers Appendix A On-Chip Supporting Module Registers A.1 List of Registers The addresses and bit names of the on-chip supporting module registers are listed below. 16- and 32-bit registers are shown as two or four levels of 8 bits each. Rev. 7.00 Jan 31, 2006 page 559 of 658 REJ09B0272-0700 Appendix A On-Chip Supporting Module Registers Table A.1 8-Bit Access Space (8-Bit and 16-Bit Accessible, 32-Bit Access Disabled) Bit Name Address Register 7 6 5 4 3 2 1 0 Module H'5FFFE00- H'5FFFEBF -- -- -- -- -- -- -- -- -- -- H'5FFFEC0 SMR0 C/A CHR PE O/E STOP MP H'5FFFEC1 BRR0 CKS1 CKS0 SCI (channel 0) H'5FFFEC2 SCR0 TIE RIE TE RE MPIE TEIE CKE1 CKE0 H'5FFFEC3 TDR0 H'5FFFEC4 SSR0 H'5FFFEC5 RDR0 H'5FFFEC6 -- TDRE RDRF ORER FER PER TEND MPB MPBT -- -- -- -- -- -- -- -- -- -- -- H'5FFFEC7 -- -- -- -- -- -- H'5FFFEC8 SMR1 C/A CHR PE O/E STOP MP H'5FFFEC9 BRR1 CKS1 CKS0 SCI (channel 1) H'5FFFECA SCR1 TIE RIE TE RE MPIE TEIE CKE1 CKE0 H'5FFFECB TDR1 H'5FFFECC SSR1 H'5FFFECD RDR1 H'5FFFECE- H'5FFFEDF -- H'5FFFEE0 ADDRAH AD9 TDRE RDRF ORER FER PER TEND MPB MPBT -- -- -- -- -- -- -- -- AD8 AD7 AD6 AD5 AD4 AD3 AD2 H'5FFFEE1 ADDRAL AD1 AD0 -- -- -- -- -- -- H'5FFFEE2 ADDRBH AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 H'5FFFEE3 ADDRBL AD1 AD0 -- -- -- -- -- -- H'5FFFEE4 ADDRCH AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 H'5FFFEE5 ADDRCL AD1 AD0 -- -- -- -- -- -- H'5FFFEE6 ADDRDH AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 H'5FFFEE7 ADDRDL AD1 AD0 -- -- -- -- -- -- H'5FFFEE8 ADCSR ADF ADIE ADST SCAN CKS CH2 CH1 CH0 H'5FFFEE9 ADCR TRGE -- -- -- -- -- -- -- H'5FFFEEA- H'5FFFEEF -- -- -- -- -- -- -- -- -- Rev. 7.00 Jan 31, 2006 page 560 of 658 REJ09B0272-0700 A/D Appendix A On-Chip Supporting Module Registers Table A.2 16-bit Access Space (In Principle, 8-Bit, 16-Bit and 32-Bit Accessible) Bit Name Address Register 7 1 H'5FFFF00 TSTR* 1 H'5FFFF01 TSNC* 6 -- -- 5 4 3 2 1 0 -- STR4 STR3 STR2 STR1 STR0 BFB4 BFA4 BFB3 BFA3 ITU SYNC4 SYNC3 SYNC2 SYNC1 SYNC0 (channels 0-4 PWM4 PWM3 PWM2 PWM1 PWM0 shared) -- -- -- H'5FFFF02 TMDR* -- MDF FDIR 1 -- -- CMD1 CMD0 1 H'5FFFF03 TFCR* 1 H'5FFFF04 TCR0* 1 H'5FFFF05 TIOR0* 1 H'5FFFF06 TIER0* 1 H'5FFFF07 TSR0* Module CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0 ITU (chan-- IOB2 IOB1 IOB0 -- IOA2 IOA1 IOA0 nel 0) -- -- -- -- -- OVIE IMIEB IMIEA -- -- -- -- -- -- OVF IMFB IMFA H'5FFFF08 TCNT0 H'5FFFF09 H'5FFFF0A GRA0 H'5FFFF0B H'5FFFF0C GRB0 H'5FFFF0D 1 H'5FFFF0E TCR1* -- CCLR1 1 * H'5FFFF0F TIORL -- IOB2 1 H'5FFFF10 TIERl* -- -- 1 H'5FFFF11 TSR1* -- -- CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0 ITU (chanIOB1 IOB0 -- IOA2 IOA1 IOA0 nel 1) -- -- -- OVIE IMIEB IMIEA -- -- -- OVF IMFB IMFA H'5FFFF12 TCNT1 H'5FFFF13 H'5FFFF14 GRA1 H'5FFFF15 H'SFFFF16 GRB1 H'5FFFF17 1 H'5FFFF18 TCR2* -- CCLR1 1 * H'5FFFF19 TIOR2 -- IOB2 1 H'5FFFF1A TIER2* -- -- 1 H'5FFFF1B TSR2* -- -- CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0 ITU (chanIOB1 IOB0 -- IOA2 IOA1 IOA0 nel 2) -- -- -- OVIE IMIEB IMIEA -- -- -- OVF IMFB IMFA H'5FFFF1C TCNT2 H'5FFFF1D H'5FFFF1E GRA2 H'5FFFF1F H'5FFFF20 GRB2 H'5FFFF21 Rev. 7.00 Jan 31, 2006 page 561 of 658 REJ09B0272-0700 Appendix A On-Chip Supporting Module Registers Bit Name Address Register 7 6 5 1 H'5FFFF22 TCR3* -- CCLR1 CCLR0 1 H'5FFFF23 TIOR3* -- IOB2 IOB1 1 H'5FFFF24 TIER3* -- -- -- 1 H'5FFFF25 TSR3* -- -- -- 4 3 2 1 0 Module CKEG1 CKEG0 TPSC2 TPSC1 TPSC0 ITU (chanIOB0 -- IOA2 IOA1 IOA0 nel 3) -- -- OVIE IMIEB IMIEA -- -- OVF IMFB IMFA -- -- -- OLS4 OLS3 H'5FFFF26 TCNT3 H'5FFFF27 H'5FFFF28 GRA3 H'5FFFF29 H'5FFFF2A GRB3 H'5FFFF2B H'5FFFF2C BRA3 H'5FFFF2D H'5FFFF2E BRB3 H'5FFFF2F 1 H'5FFFF31 TOCR* -- -- -- 1 H'5FFFF32 TCR4* -- CCLR1 CCLR0 1 H'5FFFF33 TIOR4* -- IOB2 IOB1 1 H'5FFFF34 TIER4* -- -- -- 1 H'5FFFF35 TSR4* -- -- -- H'5FFFF36 TCNT4 H'5FFFF37 H'5FFFF38 GRA4 H'5FFFF39 H'5FFFF3A GRB4 H'5FFFF3B H'5FFFF3C BRA4 H'5FFFF3D H'5FFFF3E BRB4 H'5FFFF3F Rev. 7.00 Jan 31, 2006 page 562 of 658 REJ09B0272-0700 ITU (channels 0-4 shared) CKEG1 CKEG0 TPSC2 TPSC1 TPSC0 ITU (chanIOB0 -- IOA2 IOA1 IOA0 nel 4) -- -- OVIE IMIEB IMIEA -- -- OVF IMFB IMFA Appendix A On-Chip Supporting Module Registers Bit Name Address Register 7 6 5 4 3 2 1 0 5 H'5FFFF40 SAR0* Module DMAC channel 0 H'5FFFF41 H'5FFFF42 H'5FFFF43 5 H'5FFFF44 DAR0* H'5FFFF45 H'5FFFF46 H'5FFFF47 2 H'5FFFF48 DMAOR* -- -- -- -- -- -- PR1 PR0 H'5FFFF49 -- -- -- -- -- AE NMIF DME -- -- -- -- -- -- -- -- 5 H'5FFFF4A TCR0* H'5FFFF4B H'5FFFF4C -- H'5FFFF4D -- -- -- -- -- -- -- -- -- H'5FFFF4E CHCR0 DM1 DM0 SM1 SM0 RS3 RS2 RS1 RS0 H'5FFFF4F AM AL DS TM TS IE TE DE 5 H'5FFFF50 SAR1* DMAC channel 1 H'5FFFF51 H'5FFFF52 H'5FFFF53 5 H'5FFFF54 DAR1* H'5FFFF55 H'5FFFF56 H'5FFFF57 H'5FFFF58 -- -- -- -- -- -- -- -- -- H'5FFFF59 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 5 H'5FFFF5A TCR1* H'5FFFF5B H'5FFFF5C -- H'5FFFF5D -- -- -- -- -- -- -- -- -- H'5FFFF5E CHCR1 DM1 DM0 SM1 SM0 RS3 RS2 RS1 RS0 H'5FFFF5F AM AL DS TM TS IE TE DE Rev. 7.00 Jan 31, 2006 page 563 of 658 REJ09B0272-0700 Appendix A On-Chip Supporting Module Registers Bit Name Address Register 7 6 5 4 3 2 1 0 5 H'5FFFF60 SAR2* Module DMAC channel 2 H'5FFFF61 H'5FFFF62 H'5FFFF63 5 H'5FFFF64 DAR2* H'5FFFF65 H'5FFFF66 H'5FFFF67 H'5FFFF68 -- -- -- -- -- -- -- -- -- H'5FFFF69 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 5 H'5FFFF6A TCR2* H'5FFFF6B H'5FFFF6C -- H'5FFFF6D -- -- -- -- -- -- -- -- -- H'5FFFF6E CHCR2 DM1 DM0 SM1 SM0 RS3 RS2 RS1 RS0 H'5FFFF6F AM AL DS TM TS IE TE DE 5 H'5FFFF70 SAR3* DMAC channel 3 H'5FFFF71 H'5FFFF72 H'5FFFF73 5 H'5FFFF74 DAR3* H'5FFFF75 H'5FFFF76 H'5FFFF77 H'5FFFF78 -- -- -- -- -- -- -- -- -- H'5FFFF79 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 5 H'5FFFF7A TCR3* H'5FFFF7B H'5FFFF7C -- H'5FFFF7D -- -- -- -- -- -- -- -- -- H'5FFFF7E CHCR3 DM1 DM0 SM1 SM0 RS3 RS2 RS1 RS0 H5FFFF7F AM AL DS TM TS IE TE DE Rev. 7.00 Jan 31, 2006 page 564 of 658 REJ09B0272-0700 Appendix A On-Chip Supporting Module Registers Bit Name Address Register 7 6 5 4 3 2 1 0 Module -- -- -- -- -- -- -- -- INTC H'5FFFF8E ICR NMIL -- -- -- -- -- -- NMIE H'5FFFF8F IRQ0S IRQ1S IRQ2S IRQ3S IRQ4S IRQ5S IRQ6S IRQ7S H'5FFFF90 BARH BA31 BA30 H'5FFFF91 BA23 BA22 BA21 BA20 BA19 BA18 BA17 BA16 H'5FFFF92 BARL BA15 BA14 BA13 BA12 BA11 BA10 BA9 BA8 H'5FFFF93 BA7 BA6 BA5 BA4 BA3 BA2 BA1 BA0 H'5FFFF80- -- H'5FFFF83 H'5FFFF84 IPRA H'5FFFF85 H'5FFFF86 IPRB H'5FFFF87 H'5FFFF88 IPRC H'5FFFF89 H'5FFFF8A IPRD H'5FFFF8B H'5FFFF8C IPRE H'5FFFF8D BA29 BA28 BA27 BA26 BA25 BA24 H'5FFFF94 BAMRH BAM31 BAM30 BAM29 BAM28 BAM27 BAM26 BAM25 BAM24 H'5FFFF95 BAM23 BAM22 BAM21 BAM20 BAM19 BAM18 BAM17 BAM16 H'5FFFF96 BAMRL BAM15 BAM14 BAM13 BAM12 BAM11 BAM10 BAM9 BAM8 H'5FFFF97 BAM7 BAM6 BAM5 BAM4 BAM3 BAM2 BAM1 BAM0 H'5FFFF98 BBR -- -- -- -- -- -- -- -- H'5FFFF99 CD1 CD0 ID1 ID0 RW1 RW0 SZ1 SZ0 H'5FFFF9A- -- H'5FFFF9F -- -- -- -- -- -- -- -- UBC Rev. 7.00 Jan 31, 2006 page 565 of 658 REJ09B0272-0700 Appendix A On-Chip Supporting Module Registers Bit Name Address Register 7 H'5FFFFA0 BCR 6 DRAME IOE 5 4 WARP RDDTY BAS 3 2 1 0 Module -- -- -- BSC H'5FFFFA1 -- -- -- -- -- -- -- -- H'5FFFFA2 WCR1 RW7 RW6 RW5 RW4 RW3 RW2 RW1 RW0 H'5FFFFA3 -- -- -- -- -- -- WW1 -- H'5FFFFA4 WCR2 DRW7 DRW6 DRW5 DRW4 DRW3 DRW2 DRW1 DRW0 H'5FFFFA5 DWW7 DWW6 DWW5 DWW4 DWW3 DWW2 DWW1 DWW 0 H'5FFFFA6 WCR3 WPU A02LW1 A02LW0 A6LW1 A6LW0 -- -- -- H'5FFFFA7 -- -- -- -- -- -- -- H'5FFFFA8 DCR CW2 RASD TPC BE CDTY MXE MXC1 MXC0 H'5FFFFA9 -- -- -- -- -- -- -- -- H'5FFFFAA PCR PEF PFRC PEO PCHK1 PCHK0 H'5FFFFAB -- -- -- -- -- -- -- -- H'5FFFFAC RCR -- -- -- -- H'5FFFFAD RFSHE RMODE RLW1 -- -- -- -- -- RLW0 -- -- -- -- -- -- -- H'5FFFFAE RTCSR -- -- -- -- H'5FFFFAF CMF CMIE CKS2 CKS1 CKS0 -- H'5FFFFB0 RTCNT -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- OVF WT/lT TME -- -- CKS2 CKS1 CKS0 WDT -- -- H'5FFFFB1 H'5FFFFB2 RTCOR H'5FFFFB3 H'5FFFFB4- -- H'5FFFFB7 3 H'5FFFFB8 TCSR* 3 H'5FFFFB9 TCNT* H'5FFFFBA -- -- -- -- -- -- -- H'5FFFFBB RSTCSR* WOVF RSTE RSTS -- -- -- -- -- H'5FFFFBC SBYCR SBY HIZ -- -- -- -- -- -- Power down state H'5FFFFBD- -- H'5FFFFBF -- -- -- -- -- -- -- -- -- 3 Rev. 7.00 Jan 31, 2006 page 566 of 658 REJ09B0272-0700 Appendix A On-Chip Supporting Module Registers Bit Name 7 6 5 4 3 2 0 Module H'5FFFFC0 PADR Address Register PA15 DR PA14 DR PA13 DR PA12 DR PA11 DR PA10 PA9 DR DR 1 PA8 DR Port A H'5FFFFC1 PA7 DR PA6 DR PA5 DR PA4 DR PA3 DR PA2 DR PA1 DR PA0 DR H'5FFFFC2 PBDR PB15 DR PB14 DR PB13 DR PB12 DR PB11 DR PB10 PB9 DR DR PB8 DR H'5FFFFC3 PB7 DR PB6 DR PB5 DR PB4 DR PB3 DR PB2 DR PB1 DR PB0 DR H'5FFFFC4 PAIOR PA15 IOR PA14 IOR PA13 IOR PA12 IOR PA11 IOR PA10 PA9 IOR IOR PA8 IOR H'5FFFFC5 PA7 IOR PA6 IOR PA5 IOR PA4 IOR PA3 IOR PA2 IOR PA1 IOR PA0 IOR H'5FFFFC6 PBIOR PB15 IOR PB14 IOR PB13 IOR PB12 IOR PB11 IOR PB10 PB9 IOR IOR PB8 IOR H'SFFFFC7 PB7 IOR PB6 IOR PB5 IOR PB4 IOR PB3 IOR PB2 IOR PB0 IOR H'5FFFFC8 PACR1 PA15 MD1 PA15 MD0 PA14 MD1 PA14 MD0 PA13 MD1 PA13 PA12 PA12 MD0 MD1 MD0 H'5FFFFC9 PA11 MD1 PA11 MD0 PA10 MD1 PA10 MD0 PA9 MD1 PA9 MD0 -- PA8 MD H'5FFFFCA PACR2 -- PA7 MD -- PA6 MD -- PA5 MD -- PA4 MD H'5FFFFCB PA3 MD1 PA3 MD0 PA2 MD1 PA2 MD0 PA1 MD1 PA1 MD0 PA0 MD1 PA0 MD0 H'5FFFFCC PBCR1 PB15 MD1 PB15 MD0 PB14 MD1 PB14 MD0 PB13 MD1 PB13 PB12 PB12 MD0 MD1 MD0 H'5FFFFCD PB11 MD1 PB11 MD0 PB10 MD1 PB10 MD0 PB9 MD1 PB9 MD0 PB8 MD1 PB8 MD0 H'5FFFFCE PBCR2 PB7 MD1 PB7 MD0 PB6 MD1 PB6 MD0 PB5 MD1 PB5 MD0 PB4 MD1 PB4 MD0 H'5FFFFCF PB3 MD1 PB3 MD0 PB2 MD1 PB2 MD0 PB1 MD1 PB1 MD0 PB0 MD1 PB0 MD0 H'5FFFFD0 PCDR -- -- -- -- -- -- -- -- H'5FFFFD1 PC7 DR PC6 DR PC5 DR PC4 DR PC3 DR PC2 DR PC1 DR PC0 DR PB1 IOR Port B PFC Port C Rev. 7.00 Jan 31, 2006 page 567 of 658 REJ09B0272-0700 Appendix A On-Chip Supporting Module Registers Bit Name 7 6 5 4 3 2 1 0 Module H'5FFFFD2- -- H'5FFFFED Address Register -- -- -- -- -- -- -- -- PFC H'5FFFFEE CASCR CASH MD1 CASH MD0 CASL MD1 CASL -- MD0 -- -- -- H'5FFFFEF -- -- -- -- -- -- -- -- H'5FFFFF0 TPMR -- -- -- -- G3N OV G2N OV G1N OV G0N OV H'5FFFFF1 TPCR G3C MS1 G3C MS0 G2C MS1 G2C MS0 G1C MS1 G1C MS0 G0C MS1 G0C MS0 H'5FFFFF2 NDERB NDE R15 NDE R14 NDE R13 NDE R12 NDE R11 NDE R10 NDE R9 NDE R8 H'5FFFFF3 NDERA NDE R7 NDE R6 NDE R5 NDE R4 NDE R3 NDE R2 NDE R1 NDE R0 4 NDR15 NDR14 NDR13 NDR12 -- -- -- -- 4 NDR7 NDR6 NDR5 NDR4 -- -- -- -- 4 -- -- -- -- NDR11 NDR1 NDR9 NDR8 0 H'5FFFFF7 NDRA* 4 -- -- -- -- NDR3 NDR2 NDR1 NDR0 H'5FFFFF8- -- -- -- -- -- -- H'5FFFFF4 NDRB* H'5FFFFF5 NDRA* H'5FFFFF6 NDRB* -- -- TPC -- H'5FFFFFF Notes 1. Only 8-bit accessible. 16-bit and 32-bit access disabled. 2. Register shared by all channels. 3. Address for read. For writing, the addresses are H'5FFFFB8 for TCR and TCNT and H'5FFFFBA for RSTCSR. For more information, see section 12, Watchdog Timer (WDT), particularly section 12.2.4, Notes on Register Access. 4. When the output triggers for TPC output group 0 and TPC output group 1 set by TPCR are the same, the NDRA address is H'5FFFFF5; when the output triggers are different, the NDRA address for group 0 is H'5FFFFF7 and the NDRA address for group 1 is H'5FFFFF5. Likewise, when the output triggers for TPC output group 2 and TPC output group 3 set by TPCR are the same, the NDRB address is H'5FFFFF4; when the output triggers are different, the NDRB address for group 2 is H'5FFFFF6 and the NDRB address for group 3 is H'5FFFFF4. 5. 16-bit and 32-bit accessible. 8-bit access disabled. Rev. 7.00 Jan 31, 2006 page 568 of 658 REJ09B0272-0700 Appendix A On-Chip Supporting Module Registers A.2 Register Tables A.2.1 Serial Mode Register (SMR) SCI Start Address: H'5FFFEC0 (channel 0), H'5FFFEC8 (channel 1) Bus Width: 8/16 Bit 7 6 5 4 3 2 1 0 C/A CHR PE O/E STOP MP CKS1 CKS0 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Table A.3 SMR Bit Functions Bit Bit name Value* Description 7 Communication mode (C/A) 0 Asynchronous mode 1 Synchronous mode 0 8-bit data 1 7-bit data 0 Parity bit addition and check disable (Initial value) 1 Parity bit addition and check enable 0 Even parity 1 Odd parity 1 stop bit 6 5 4 Character length (CHR) Parity enable (PE) Parity mode (O/E) 3 Stop bit length (STOP) 0 1 2 stop bits 2 Multiprocessor mode (MP) 0 Multiprocessor function disabled 1 Multiprocessor function selected 0 0 clock 0 1 /4 clock 1 0 /16 clock 1 1 /64 clock 1,0 Clock select 1, 0 (CKS1, CKS0) (Initial value) (Initial value) (Initial value) (Initial value) (Initial value) (Initial value) Note: * When 2 or more bits are treated as a group, the left side is the upper bit and the right the lower bit. Rev. 7.00 Jan 31, 2006 page 569 of 658 REJ09B0272-0700 Appendix A On-Chip Supporting Module Registers A.2.2 Bit Rate Register (BRR) SCI Start Address: H'5FFFEC1 (channel 0), H'5FFFEC9 (channel 1) Bus Width: 8/16 Bit 7 6 5 4 3 2 1 0 Initial value 1 1 1 1 1 1 1 1 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Table A.4 BBR Bit Functions Bit Bit name Description 7-0 (Bit rate setting) Set serial transmission/reception bit rate A.2.3 Serial Control Register (SCR) SCI Start Address: H'5FFFEC2 (channel 0), H'5FFFECA (channel 1) Bus Width: 8/16 Bit 7 6 5 4 3 2 1 0 TIE RIE TE RE MPIE TEIE CKE1 CKE0 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Rev. 7.00 Jan 31, 2006 page 570 of 658 REJ09B0272-0700 Appendix A On-Chip Supporting Module Registers Table A.5 SCR Bit Functions Bit Bit Name Value Description 7 0 Transmit data-empty interrupt request (TXI) disabled (Initial value) Transmit data-empty interrupt request (TXI) enabled Receive-data-full interrupt request (RXI) and receive-error interrupt request (ERI) disabled (Initial value) Receive-data-full interrupt request (RXI) and receive-error interrupt request (ERI) Transmission disabled (Initial value) Transmission enabled Reception disabled (Initial value) Reception enabled Multiprocessor interrupts disabled (normal receive operation) (Initial value) Clear conditions: (1) MPIE bit cleared to zero; (2) When data the MPB = 1 is received Multiprocessor interrupts enabled. Disables receive interrupts (RXI), receive error interrupts (ERI), and setting of RDRF, FER, and ORER flags in SSR until data with a "1" multiprocessor bit is received Transmit interrupt requests (TEI) disabled (Initial value) Transmit interrupt requests (TEI) enabled Asynchronous Internal clock/SCK pin is input pin (input mode signal ignored) or output pin (output level undetermined) (Initial value) Synchronous Internal clock/SCK pin is synchronous mode clock output (Initial value) Asynchronous Internal clock/SCK pin is clock output mode Synchronous Internal clock/SCK pin is serial clock mode output External clock/SCK pin is clock input Asynchronous mode Synchronous External clock/SCK pin is serial clock mode input Asynchronous External clock/SCK pin is clock input mode Synchronous External clock/SCK pin is serial clock mode input 6 Transmit interrupt enable (TIE) Receive interrupt enable (RIE) 1 0 1 5 4 3 Transmit enable (TE) 0 1 Receive enable (RE) 0 1 Multiprocessor inter- 0 rupt enable (MPIE) 1 2 Transmit end interrupt enable (TEIE) 1 Clock enable 1 (CKE1) 0 Clock enable 0 (CKE0) 0 1 0 0 0 1 1 0 1 1 Rev. 7.00 Jan 31, 2006 page 571 of 658 REJ09B0272-0700 Appendix A On-Chip Supporting Module Registers A.2.4 Transmit Data Register (TDR) SCI Start Address: H'5FFFEC3 (channel 0), H'5FFFECB (channel 1) Bus Width: 8/16 Bit 7 6 5 4 3 2 1 0 Initial value 1 1 1 1 1 1 1 1 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Table A.6 TDR Bit Functions Bit Bit name Description 7-0 (Transmit data storage) Store data for serial transmission A.2.5 Serial Status Register (SSR) SCI Start Address: H'5FFFEC4 (channel 0), H'5FFFECC (channel 1) Bus Width: 8/16 Bit 7 6 5 4 3 2 1 0 TDRE RDRF ORER FER PER TEND MPB MPBT Initial value 1 0 0 0 0 1 0 0 Read/Write R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R R R/W Note: * Only 0 can be written, to clear the flags. Rev. 7.00 Jan 31, 2006 page 572 of 658 REJ09B0272-0700 Appendix A On-Chip Supporting Module Registers Table A.7 SSR Bit Functions Bit Bit name Value Description 7 Transmit data 0 register empty (TDRE) 1 Indicates that valid transmit data has been written to TDR Clear Conditions: (1) 0 written in TDRE after reading TDRE = 1; (2) Data written to TDR by DMAC Indicates that there is no valid transmit data in TDR (Initial value) Set Conditions: (1) Reset or standby mode; (2) TE bit of SCR is 0; (3) Data transferred to TSR from TDR and data writing to TDR enabled 6 Receive data register full (RDRF) 0 Indicates that there is no valid receive data stored in RDR (Initial value) Clear Conditions: (1) Reset or standby mode; (2) 0 written in RDRF after reading RDRF = 1; (3) Data read in RDR by DMAC 1 Indicates that valid receive data is stored in RDR Set Conditions: Serial reception ends normally and receive data is transferred to RDR from RSR 5 Overrun error (ORER) 0 Indicates that reception is in progress or has ended normally (Initial value) Clear Conditions: (1) Reset or standby mode; (2) 0 written in ORER after reading ORER = 1 1 Indicates that an overrun error occurred in reception Set Conditions: The next serial reception ends while RDRF = 1 4 Framing error (FER) 0 Indicates that reception is in progress or has ended normally (Initial value) Clear Conditions: (1) Reset or standby mode; (2) 0 written in FER after reading FER = 1 1 Indicates that a framing error occurred in reception Set Conditions: When the stop bit at the end of the receive data when the SCI finishes receiving has been checked to see if it is 1 and the stop bit is 0 3 Parity error (PER) 0 Indicates that reception is in progress or has ended normally (Initial value) Clear Conditions: (1) Reset or standby mode; (2) 0 written in PER after reading PER = 1 1 Indicates that a parity error occurred in reception Set Conditions: When the number of 1's in the receive data and parity bit together during reception is not consistent with the even/odd parity setting specified in the O/E bit of the serial mode register (SMR) Rev. 7.00 Jan 31, 2006 page 573 of 658 REJ09B0272-0700 Appendix A On-Chip Supporting Module Registers Bit Bit name Value Description 2 Transmit end (TEND) 0 Indicates that transmission is in progress Clear Conditions: (1) 0 written in TDRE after reading TDRE = 1; (2) Data written to TDR by DMAC 1 Indicates that transmission has ended (Initial value) Set Conditions: (1) Reset or standby mode; (2) TE bit in SCR is 0; (3) TDRE = 1 when the final bit of a 1-byte serial transmit character is transmitted 1 Multiprocessor 0 bit (MPB) Indicates that data with multiprocessor bit = 0 has been received (Initial value) 1 0 A.2.6 Indicates that data with multiprocessor bit = 1 has been received Multiprocessor 0 bit transfer 1 (MPBT) 0 transmitted as the multiprocessor bit (Initial value) 1 transmitted as the multiprocessor bit Receive Data Register (RDR) SCI Start Address: H'5FFFEC5 (channel 0), H'5FFFECD (channel 1) Bus Width: 8/16 Bit 7 6 5 4 3 2 1 0 Initial value 0 0 0 0 0 0 0 0 Read/Write R R R R R R R R Bit Bit name Description 7-0 (Receive serial data storage) Store the serial data received Rev. 7.00 Jan 31, 2006 page 574 of 658 REJ09B0272-0700 Appendix A On-Chip Supporting Module Registers A.2.7 A/D Data Register AH-DL (ADDRAH-ADDRL) A/D Start Address: H'5FFFEE0, H'5FFFEE1, H'5FFFEE2, H'5FFFEE3, H'5FFFEE4, H'5FFFEE5, H'5FFFEE6, H'5FFFEE7 Bus Width: 8/16 Bit 15 14 13 12 11 10 9 8 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 Initial value 0 0 0 0 0 0 0 0 Read/Write R R R R R R R R Bit 7 6 5 4 3 2 1 0 AD1 AD0 -- -- -- -- -- -- Initial value 0 0 0 0 0 0 0 0 Read/Write R R R R R R R R Table A.8 ADDRAH-ADDRL Bit Functions Bit Bit name Description 15-8 A/D data 9-2 Stores upper 8 bits of A/D conversion result 7,6 A/D data 1, 0 Stores upper 2 bits of A/D conversion result A.2.8 A/D Control/Status Register (ADCSR) A/D Start Address: H'5FFFEF8 Bus Width: 8/16 Bit 7 6 5 4 3 2 1 0 ADF ADIE ADST SCAN CKS CH2 CH1 CH0 Initial value 0 0 0 0 0 1 0 0 Read/Write R/(W)* R/W R/W R/W R/W R/W R/W R/W Note: * Only 0 can be written, to clear the flag. Rev. 7.00 Jan 31, 2006 page 575 of 658 REJ09B0272-0700 Appendix A On-Chip Supporting Module Registers Table A.9 ADCSR Bit Functions Bit Bit name Value Description 7 A/D end flag (ADF) 0 Clear conditions: (1) 0 written in ADF after reading ADF = 1; (2) DMAC started by ADI interrupt and A/D converter register is accessed (Initial value) 1 Set Conditions: (1) Single mode: A/D conversion ends; (2) Scan mode: A/D conversion of all channels set has ended 0 Interrupt requested by A/D conversion (ADI) disabled (Initial value) 1 Interrupt requested by A/D conversion (ADI) enabled 0 Disable A/D conversion 1 (1) Single mode: Start A/D conversion and when conversion ends, automatically cleared to zero; (2) Scan mode: Start A/D conversion and sequentially continue converting the selected channels until cleared to 0 by software, reset, or standby mode 0 Single mode 1 Scan mode 0 Conversion time = 236 cycles (max) 1 Conversion time = 134 cycles (max) CH2 CH1 CH0 Single mode Scan mode 0 0 0 AN0 (Initial value) AN0 (Initial value) 1 AN1 AN0, AN1 1 0 AN2 AN0-AN2 1 AN3 AN0-AN3 0 AN4 AN4 1 AN5 AN4, AN5 0 AN6 AN4-AN6 1 AN7 AN4-AN7 6 5 A/D interrupt enable (ADF) A/D start (ADST) 4 Scan mode (SCAN) 3 Clock select (CKS) 2-0 Channel select 2-0 1 0 1 Rev. 7.00 Jan 31, 2006 page 576 of 658 REJ09B0272-0700 (Initial value) (Initial value) (Initial value) Appendix A On-Chip Supporting Module Registers A.2.9 A/D Control Register (ADCR) A/D Start Address: H'5FFFEE9 Bus Width: 8/16 Bit 7 6 5 4 3 2 1 0 TRGE -- -- -- -- -- -- -- Initial value 0 1 1 1 1 1 1 1 Read/Write R/W -- -- -- -- -- -- -- Table A.10 ADCR Bit Functions Bit Bit name Value 7 Trigger enable bit (TRGE) 0 1 A.2.10 Description Start of A/D conversion by external trigger disabled (Initial value) Start of A/D conversion by rising edge of external conversion trigger input pin (ADTRG) enabled Timer Start Register (TSTR) ITU Start Address: H'5FFFF00 Bus Width: 8 Bit 7 6 5 4 3 2 1 0 -- -- -- STR4 STR3 STR2 STR1 STR0 Initial value 1 1 1 0 0 0 0 0 Read/Write -- -- -- R/W R/W R/W R/W R/W Rev. 7.00 Jan 31, 2006 page 577 of 658 REJ09B0272-0700 Appendix A On-Chip Supporting Module Registers Table A.11 TSTR Bit Functions Bit Bit name Value Description 4 Counter start 4 (STR4) 0 Count operation of TCNT4 stops 1 TCNT4 counts 0 Count operation of TCNT 3 stops 1 TCNT3 counts 0 Count operation of TCNT 2 stops 1 TCNT2 counts 0 Count operation of TCNT 1 stops 1 TCNT1 counts 3 Counter start 3 (STR3) 2 Counter start 2 (STR2) 1 0 Counter start 1 (STR1) Counter start 0 (STR0) A.2.11 (Initial value) 0 Count operation of TCNT 0 stops 1 TCNT0 counts (Initial value) (Initial value) (Initial value) (Initial value) Timer Synchronization Register (TSNC) ITU Start Address: H'5FFFF01 Bus Width: 8 Bit 7 6 5 4 3 2 1 0 -- -- -- SYNC4 SYNC3 SYNC2 SYNC1 SYNC0 Initial value * 1 1 0 0 0 0 0 Read/Write -- -- -- R/W R/W R/W R/W R/W Note: * Undetermined Rev. 7.00 Jan 31, 2006 page 578 of 658 REJ09B0272-0700 Appendix A On-Chip Supporting Module Registers Table A.12 TSNC Bit Functions Bit Bit name Value Description 4 Timer sync 4 (SYNC4) 0 Independent operation of channel 4 timer counter (TCNT4) (Initial value) (Preset/clear of TCNT4 is unrelated to other channels) 3 Timer sync 3 (SYNC3) 1 Channel 4 operation is synchronous. TCNT4 sync preset/sync clear enabled. 0 Independent operation of channel 3 timer counter (TCNT3) (Initial value) (Preset/clear of TCNT3 is unrelated to other channels) 2 Timer sync 2 (SYNC2) 1 Channel 3 operation is synchronous. TCNT3 sync preset/sync clear enabled. 0 Independent operation of channel 2 timer counter (TCNT2) (Initial value) (Preset/clear of TCNT2 is unrelated to other channels) 1 Timer sync 1 (SYNC1) 1 Channel 2 operation is synchronous. TCNT2 sync preset/sync clear enabled. 0 Independent operation of channel 1 timer counter (TCNT1) (Initial value) (Preset/clear of TCNT1 is unrelated to other channels) 0 Timer sync 0 (SYNC0) 1 Channel 1 operation is synchronous. TCNT1 sync preset/sync clear enabled. 0 Independent operation of channel 0 timer counter (TCNT0) (Initial value) (Preset/clear of TCNT0 is unrelated to other channels) 1 Channel 0 operation is synchronous. TCNT0 sync preset/sync clear enabled. Rev. 7.00 Jan 31, 2006 page 579 of 658 REJ09B0272-0700 Appendix A On-Chip Supporting Module Registers A.2.12 Timer Mode Register (TMDR) ITU Start Address: H'5FFFF02 Bus Width: 8 Bit 7 6 5 4 3 2 1 0 -- MDF FDIR PWM4 PWM3 PWM2 PWM1 PWM0 Initial value * 0 0 0 0 0 0 0 Read/Write -- R/W R/W R/W R/W R/W R/W R/W Note: * Undetermined Table A.13 TMDR Bit Functions Bit Bit name Value Description 6 Phase counting mode (MDF) 0 Channel 2 operates normally 1 Channel 2 in phase count mode 0 OVF of TSR2 set to 1 when TCNT2 overflows or underflows (Initial value) 1 OVF in TSR2 set to 1 when TCNT2 overflows 0 Channel 4 operates normally 1 Channel 4 in PWM mode 0 Channel 3 operates normally 1 Channel 3 in PWM mode 0 Channel 2 operates normally 1 Channel 2 in PWM mode 0 Channel 1 operates normally 1 Channel 1 in PWM mode 0 Channel 0 operates normally 1 Channel 0 in PWM mode 5 Flag direction (FDIR) 4 PWM mode 4 (PWM4) 3 PWM mode 3 (PWM3) 2 PWM mode 2 (PWM2) 1 PWM mode 1 (PWM1) 0 PWM mode 0 (PWM0) Rev. 7.00 Jan 31, 2006 page 580 of 658 REJ09B0272-0700 (Initial value) (Initial value) (Initial value) (Initial value) (Initial value) (Initial value) Appendix A On-Chip Supporting Module Registers A.2.13 Timer Function Control Register (TFCR) ITU Start Address: H'5FFFF03 Bus Width: 8 Bit 7 6 5 4 3 2 1 0 -- -- CMD1 CMD0 BFB4 BFA4 BFB3 BFA3 Initial value * 1 0 0 0 0 0 0 Read/Write -- -- R/W R/W R/W R/W R/W R/W Note: * Undetermined Table A.14 TFCR Bit Functions Bit Bit name Value Description 5,4 Combination modes 1, 0 (CMD1, CMD0) 0 0 Channel 3 and 4 operate normally 0 1 Channel 3 and 4 operate normally 1 0 Channels 3 and 4 are combined to operate in complementary PWM mode 1 1 Channels 3 and 4 are combined to operate in reset-synchronized PWM mode 0 GRB4 operates normally 1 Buffer operation of GRB4 and BRB4 3 2 1 0 Buffer mode B4 (BFB4) Buffer mode A4 (BFA4) Buffer mode B3 (BFB3) Buffer mode A3 (BFA3) 0 GRA4 operates normally 1 Buffer operation of GRA4 and BRA4 0 GRB3 operates normally 1 Buffer operation of GRB3 and BRB3 0 GRA3 operates normally 1 Buffer operation of GRA3 and BRA3 (Initial value) (Initial value) (Initial value) (Initial value) (Initial value) Rev. 7.00 Jan 31, 2006 page 581 of 658 REJ09B0272-0700 Appendix A On-Chip Supporting Module Registers A.2.14 Timer Control Registers 0-4 (TCR0-TCR4) ITU Start Address: H'5FFFF04 (channel 0), H'5FFFF0E (channel 1), H'5FFFF18 (channel 2), H'5FFFF22 (channel 3), H'5FFFF32 (channel 4) Bus Width: 8 Bit 7 6 5 4 3 2 1 0 -- CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0 Initial value * 0 0 0 0 0 0 0 Read/Write -- R/W R/W R/W R/W R/W R/W R/W Note: * Undetermined Table A.15 TCR0-TCR4 Bit Functions Bit Bit name Value Description 6,5 Counter clear 1, 0 (CCLR1, CCLR0) 0 0 TCNT clear disabled 0 1 TCNT cleared upon GRA compare match/input capture 1 0 TCNT cleared upon GRB compare match/input capture 1 1 Synchronized clear. TCNT cleared in synchronization with counter clear of other timers operating in sync 0 0 Count on rising edge 0 1 Count on falling edge 1 * Count on both rising and falling edges 0 0 0 Internal clock: Count on 0 0 1 Internal clock: Count on /2 0 1 0 Internal clock: Count on /4 0 1 1 Internal clock: Count on /8 1 0 0 External clock A: Count on TCLKA pin input 1 0 1 External clock B: Count on TCLKB pin input 1 1 0 External clock C: Count on TCLKC pin input 1 1 1 External clock D: Count on TCLKD pin input 4,3 2-0 Clock edge 1, 0 (CKEG1, CKEG0) Timer prescaler 2-0 (TPSC2-TPSC0) Note: * 0 or 1 Rev. 7.00 Jan 31, 2006 page 582 of 658 REJ09B0272-0700 (Initial value) (Initial value) (Initial value) Appendix A On-Chip Supporting Module Registers A.2.15 Timer I/O Control Registers 0-4 (TIOR0-TIOR4) ITU Start Address: H'5FFFF05 (channel 0), H'5FFFF0F (channel 1), H'5FFFF19 (channel 2), H'5FFFF23 (channel 3), H'5FFFF33 (channel 4) Bus Width: 8 Bit 7 6 5 4 3 2 1 0 -- IOB2 IOB1 IOB0 -- IOA2 IOA1 IOA0 Initial value * 0 0 0 1 0 0 0 Read/Write -- R/W R/W R/W -- R/W R/W R/W Note: * Undetermined Table A.16 TIO0-TIO4 Bit Functions Bit Bit name 6-4 I/O control B2-0 (IOB2-IOB0) 2-0 I/O control A2-0 (IOA2-IOA0) Value Description 0 0 0 GRB is output compare register 0 0 1 0 output on GRB compare match 0 1 0 1 output on GRB compare match 0 1 1 Toggle output on GRB compare match (1 output on channel 2 only) 1 0 0 1 0 1 1 1 * 0 0 0 0 0 1 0 output on GRA compare match 0 1 0 1 output on GRA compare match 0 1 1 Toggle output on GRA compare match (1 output on channel 2 only) 1 0 0 1 0 1 1 1 * GRB is input capture register Pin output due to compare match disabled (Initial value) Input capture to GRB on rising edge Input capture to GRB on falling edge Input capture on both rising and falling edges GRA is output compare register GRA is input capture register Pin output due to compare match disabled (Initial value) Input capture to GRA on rising edge Input capture to GRA on falling edge Input capture on both rising and falling edges Note: * 0 or 1 Rev. 7.00 Jan 31, 2006 page 583 of 658 REJ09B0272-0700 Appendix A On-Chip Supporting Module Registers A.2.16 Timer Interrupt Enable Registers 0-4 (TIER0-TIER4) ITU Start Address: H'5FFFF06 (channel 0), H'5FFFF10 (channel 1), H'5FFFF1A (channel 2), H'5FFFF24 (channel 3), H'5FFFF34 (channel 4), Bus Width: 8 Bit 7 6 5 4 3 2 1 0 -- -- -- -- -- OVIE IMIEB IMIEA Initial value * 1 1 1 1 0 0 0 Read/Write -- -- -- -- -- R/W R/W R/W Note: * Undetermined Table A.17 TIER0-TIER4 Bit Functions Bit Bit name Value Description 2 Overflow interrupt enable (OVIE) 0 Interrupt request by OVF (OVI) disabled (Initial value) 1 Interrupt request by OVF (OVI) enabled 0 Interrupt request by IMFB (IMIB) disabled (Initial value) 1 Interrupt request by IMFB (IMIB) enabled 0 Interrupt request by IMFA (IMIA) disabled (Initial value) 1 Interrupt request by IMFA (IMIA) enabled 1 0 Input capture/compare match interrupt enable B (IMIEB) Input capture/compare match interrupt enable A (IMIEA) Rev. 7.00 Jan 31, 2006 page 584 of 658 REJ09B0272-0700 Appendix A On-Chip Supporting Module Registers A.2.17 Timer Status Registers 0-4 (TSR0-TSR4) ITU Start Address: H'5FFFF07 (channel 0), H'5FFFF11 (channel 1), H'5FFFF1B (channel 2), H'5FFFF25 (channel 3), H'5FFFF35 (channel 4), Bus Width: 8 Bit Initial value Read/Write 7 6 5 4 3 2 1 0 -- -- -- -- -- OVF IMFB IMFA 1 1 1 1 0 1 * -- -- -- -- -- 0 2 R/(W)* 0 2 R/(W)* 2 R/(W)* Notes: 1. Undetermined 2. Only 0 can be written, to clear the flag. Table A.18 TSR0-TSR4 Bit Functions Bit Bit name Value Description 2 Overflow flag (OVF) 0 Clear conditions: 0 is written in OVF after reading OVF = 1 (Initial value) 1 Set conditions: TCNT value overflows (H'FFFF H'0000) or underflows (H'FFFF H'0000) 0 Clear conditions: 0 is written in IMFB after reading IMFB = 1 (Initial value) 1 Set conditions: (1) When GRB is functioning as the output compare register, and TCNT = GRB; (2) When GRB is functioning as the input capture register, and the TCNT value is transferred to GRB by the input capture signal 0 Clear conditions: 0 is written in IMFA after reading IMFA = 1 (Initial value) 1 Set conditions: (1) When GRA is functioning as the output compare register, and TCNT = GRA; (2) When GRA is functioning as the input capture register, and the TCNT value is transferred to GRA by the input capture signal 1 0 Input capture/compare match flag B (IMFB) Input capture/compare match flag A (IMFA) Rev. 7.00 Jan 31, 2006 page 585 of 658 REJ09B0272-0700 Appendix A On-Chip Supporting Module Registers A.2.18 Timer Counter 0-4 (TCNT0-TCNT4) ITU Start Address: H'5FFFF08 (channel 0), H'5FFFF12 (channel 1), H'5FFFF1C (channel 2), H'5FFFF26 (channel 3), H'5FFFF36 (channel 4) Bus Width: 8/16/32 Bit 15 14 13 12 11 10 9 8 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Bit 7 6 5 4 3 2 1 0 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Table A.19 TCNT0-TCNT4 Bit Functions Bit Bit name Description 15-0 (Count value) Count input clocks Rev. 7.00 Jan 31, 2006 page 586 of 658 REJ09B0272-0700 Appendix A On-Chip Supporting Module Registers A.2.19 General Registers A0-4 (GRA0-GRA4) ITU Start Address: H'5FFFF0A (channel 0), H'5FFFF14 (channel 1), H'5FFFF1E (channel 2), H'5FFFF28 (channel 3), H'5FFFF38 (channel 4) Bus Width: 8/16/32 Bit 15 14 13 12 11 10 9 8 Initial value 1 1 1 1 1 1 1 1 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Bit 7 6 5 4 3 2 1 0 Initial value 1 1 1 1 1 1 1 1 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Table A.20 GRA0-GRA4 Bit Functions Bit Bit name Description 15-0 Registers used for both output compare and input capture Output compare register: Set with compare match output Input capture register: Stores the TCNT value when the input capture signal is generated Rev. 7.00 Jan 31, 2006 page 587 of 658 REJ09B0272-0700 Appendix A On-Chip Supporting Module Registers A.2.20 General Registers B0-4 (GRB0-GRB4) ITU Start Address: H'5FFFF0C (channel 0), H'5FFFF16 (channel 1), H'5FFFF20 (channel 2), H'5FFFF2A (channel 3), H'5FFFF3A (channel 4) Bus Width: 8/16/32 Bit 15 14 13 12 11 10 9 8 Initial value 1 1 1 1 1 1 1 1 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Bit 7 6 5 4 3 2 1 0 Initial value 1 1 1 1 1 1 1 1 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Table A.21 GRB0-GRB4 Bit Functions Bit Bit name Description 15-0 Registers used for both output compare and input capture Output compare register: Set with compare match output Input capture register: Stores the TCNT value when the input capture signal is generated Rev. 7.00 Jan 31, 2006 page 588 of 658 REJ09B0272-0700 Appendix A On-Chip Supporting Module Registers A.2.21 Buffer Registers A3, 4 (BRA3, BRA4) ITU Start Address: H'5FFFF2C (channel 3), H'5FFFF3C (channel 4) Bus Width: 8/16/32 Bit 15 14 13 12 11 10 9 8 Initial value 1 1 1 1 1 1 1 1 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 Bit Initial value 1 1 1 1 1 1 1 1 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Table A.22 BRA3, BRA4 Bit Functions Bit Bit name Description 15-0 Buffer registers used for output compare/input capture Output compare register: Transfers to GRA the value stored up to compare match generation Input capture register: Stores the value stored in GRA up to input capture signal generation Rev. 7.00 Jan 31, 2006 page 589 of 658 REJ09B0272-0700 Appendix A On-Chip Supporting Module Registers A.2.22 Buffer Registers B3, 4 (BRB3, BRB4) ITU Start Address: H'5FFFF2E (channel 3), H'5FFFF3E (channel 4) Bus Width: 8/16/32 Bit 15 14 13 12 11 10 9 8 Initial value 1 1 1 1 1 1 1 1 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 Bit Initial value 1 1 1 1 1 1 1 1 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Table A.23 BRB3, BRB4 Bit Functions Bit Bit name Description 15-0 Buffer registers used for output compare/input capture Output compare register: Transfers to GRB the value stored up to compare match generation Input capture register: Stores the value stored in GRB up to input capture signal generation Rev. 7.00 Jan 31, 2006 page 590 of 658 REJ09B0272-0700 Appendix A On-Chip Supporting Module Registers A.2.23 Timer Output Control Register (TOCR) ITU Start Address: H'5FFFF31 Bus Width: 8 Bit 7 6 5 4 3 2 1 0 -- -- -- -- -- -- OLS4 OLS3 Initial value * 1 1 1 1 1 1 1 Read/Write -- -- -- -- -- -- R/W R/W Note: * Undetermined Table A.24 TOCR Bit Functions Bit Bit name Value Description 1 Output level select 4 (OLS4) 0 Reverse output of TIOCA3, TIOCA4, TIOCB4 1 Direct output of TIOCA3, TIOCA4, TIOCB4 (Initial value) 0 Reverse output of TIOCB3, TOCXA4, TOCXB4 1 Direct output of TIOCB3, TOCXA4, TOCXB4 (Initial value) 0 Output level select 3 (OLS3) Rev. 7.00 Jan 31, 2006 page 591 of 658 REJ09B0272-0700 Appendix A On-Chip Supporting Module Registers A.2.24 DMA Source Address Registers 0-3 (SAR0-SAR3) DMAC Start Address: H'5FFFF40 (channel 0), H'5FFFF50 (channel 1), H'5FFFF60 (channel 2), H'5FFFF70 (channel 3) Bus Width: 16/32 Bit 31 30 29 28 27 26 25 24 Initial value * * * * * * * * Read/Write R/W R/W R/W R/W R/W R/W R/W R/W 23 22 21 20 19 18 17 16 Initial value * * * * * * * * Read/Write R/W R/W R/W R/W R/W R/W R/W R/W 15 14 13 12 11 10 9 8 Initial value * * * * * * * * Read/Write R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 Bit Bit Bit Initial value * * * * * * * * Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Note: * Undetermined Table A.25 SAR0-SAR3 Bit Functions Bit Bit name Description 31-0 (Specifies transfer source address) Specifies the address of the DMA transfer source Rev. 7.00 Jan 31, 2006 page 592 of 658 REJ09B0272-0700 Appendix A On-Chip Supporting Module Registers A.2.25 DMA Destination Address Registers 0-3 (DAR0-DAR3) DMAC Start Address: H'5FFFF44 (channel 0), H'5FFFF54 (channel 1), H'5FFFF64 (channel 2), H'5FFFF74 (channel 3) Bus Width: 16/32 Bit 31 30 29 28 27 26 25 24 Initial value * * * * * * * * Read/Write R/W R/W R/W R/W R/W R/W R/W R/W 23 22 21 20 19 18 17 16 Initial value * * * * * * * * Read/Write R/W R/W R/W R/W R/W R/W R/W R/W 15 14 13 12 11 10 9 8 Initial value * * * * * * * * Read/Write R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 Bit Bit Bit Initial value * * * * * * * * Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Note: * Undetermined Table A.26 DAR0-DAR3 Bit Functions Bit Bit name Description 31-0 (Specifies transfer destination address) Specifies the address of the DMA transfer destination Rev. 7.00 Jan 31, 2006 page 593 of 658 REJ09B0272-0700 Appendix A On-Chip Supporting Module Registers A.2.26 DMA Transfer Count Registers 0-3 (TCR0-TCR3) DMAC Start Address: H'5FFFF4A (channel 0), H'5FFFF5A (channel 1), H'5FFFF6A (channel 2), H'5FFFF7A (channel 3) Bus Width: 16/32 Bit 15 14 13 12 11 10 9 8 Initial value * * * * * * * * Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Bit 7 6 5 4 3 2 1 0 Initial value * * * * * * * * Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Note: * Undetermined Table A.27 TCR0-TCR3 Bit Functions Bit Bit name Description 15-0 (Specifies number of DMA transfers) Specifies the number of DMA transfers (bytes or words). During DMA transfer, indicates the number of transfers remaining. Rev. 7.00 Jan 31, 2006 page 594 of 658 REJ09B0272-0700 Appendix A On-Chip Supporting Module Registers A.2.27 DMA Channel Control Registers 0-3 (CHCR0-CHCR3) DMAC Start Address: H'5FFFF4E (channel 0), H'5FFFF5E (channel 1), H'5FFFF6E (channel 2), H'5FFFF7E (channel 3) Bus Width: 8/16/32 Bit 15 14 13 12 11 10 9 8 DM1 DM0 SM1 SM0 RS3 RS2 RS1 RS0 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 AM AL DS TM TS IE TE DE Initial value 0 0 0 0 0 0 0 0 Read/Write 2 R/W * 2 R/W * 2 R/W * R/W 1 R/(W)* R/W Bit R/W R/W Notes: 1. Only 0 can be written, to clear the flag. 2. Writing is valid only for CHCR0 and CHCR1. Rev. 7.00 Jan 31, 2006 page 595 of 658 REJ09B0272-0700 Appendix A On-Chip Supporting Module Registers Table A.28 CHCR0-CHCR3 Bit Functions Bit Bit name 15,14 Destination address mode bits 1, 0 (DM1, DM0) Value Description 0 0 Destination address is fixed 0 1 Destination address incremented (+1 for byte transfer; +2 for word transfer) 1 0 Destination address decremented (-1 for byte transfer; -2 for word transfer) 1 1 Reserved (cannot be set) 13,12 Source address mode 0 0 bits 1, 0 (SM1, SM0) 0 1 11-8 Resource select bits 3-0 (RS3-RS0) Source address is fixed (Initial value) (Initial value) Source address incremented (+1 for byte transfer; +2 for word transfer) 1 0 Source address decremented (-1 for byte transfer; -2 for word transfer) 1 1 Reserved (cannot be set) 1 0 0 0 0 DREQ (external request* ) (Initial value) (Dual address mode) 0 0 0 1 Reserved (cannot be set) 1 2 1 3 0 0 1 0 DREQ (external request* ) (Single address mode* ) 0 0 1 1 DREQ (external request* ) (Single address mode* ) 0 1 0 0 RXIO (transfer request by receive-data-full interrupt of 4 on-chip SCI0)* 0 1 0 1 TXIO (transfer request by transmit-data-empty 4 interrupt of on-chip SCI0)* 0 1 1 0 RXI1 (transfer request by receive-data-full interrupt of 4 on-chip SCI1)* 0 1 1 1 TXI1 (transfer request by transmit-data-empty 4 interrupt of on-chip SCI1)* 1 0 0 0 IMIA0 (input capture A/compare match A interrupt 4 request of on-chip ITU0)* 1 0 0 1 IMIA1 (input capture A/compare match A interrupt 4 request of on-chip ITU1)* 1 0 1 0 IMIA2 (input capture A/compare match A interrupt 4 request of on-chip ITU2)* Rev. 7.00 Jan 31, 2006 page 596 of 658 REJ09B0272-0700 Appendix A On-Chip Supporting Module Registers Bit Bit name Value Description 11-8 Resource select bits 1 0 1 1 IMIA3 (input capture A/compare match A interrupt 4 3-0 (RS3-RS0) (cont) request of on-chip ITU3)* 1 1 0 0 Auto request (transfer request automatically generated 4 within DMAC)* 1 1 0 1 ADI (A/D conversion end interrupt request of on-chip A/D converter) 1 1 1 0 Reserved (cannot be set) 1 1 1 1 Reserved (cannot be set) 7 Acknowledge mode 1 bit (AM)* 0 DACK output in read cycle 1 DACK output in write cycle 6 Acknowledge level 1 bit (AL)* 0 DACK is active-high signal 1 DACK is active-low signal 5 DREQ select bit 1 (DS)* 0 DREQ detected at low 1 DREQ detected on falling edge Transfer bus mode bit (TM) 0 Cycle-steal mode 1 Burst mode 4 3 2 1 0 Transfer size bit (TS) Interrupt enable bit (IE) Transfer end flag bit (TE) DMA enable bit (DE) (Initial value) (Initial value) (Initial value) (Initial value) 0 Byte (8 bits) 1 Word (16 bits) (Initial value) 0 Interrupt request disabled 1 Interrupt request enabled 0 DMA transferring or DMA transfer halted (Initial value) 1 DMA transfer ends normally 0 DMA transfer disabled 1 DMA transfer enabled (Initial value) Clear Conditions: TE bit read and then 0 written in TE (Initial value) Notes: 1. Only valid in channels 0 and 1. 2. Transfer to external device from memory mapped external device or external memory with DACK. 3. Transfer from external device to memory mapped external device or external memory with DACK. 4. Dual address mode. Rev. 7.00 Jan 31, 2006 page 597 of 658 REJ09B0272-0700 Appendix A On-Chip Supporting Module Registers A.2.28 DMA Operation Registers (DMAOR) DMAC Start Address: H'5FFFF48 Bus Width: 8/16/32 Bit 15 14 13 12 11 10 9 8 -- -- -- -- -- -- PR1 PR0 Initial value 0 0 0 0 0 0 0 0 Read/Write -- -- -- -- -- -- R/W R/W Bit 7 6 5 4 3 2 1 0 -- -- -- -- -- AE NMIF DME Initial value 0 0 0 0 0 0 0 0 Read/Write -- -- -- -- -- R/(W)* R/(W)* R/W Note: * Only 0 can be written, to clear the flag. Table A.29 DMAOR Bit Functions Bit Bit name 9,8 Priority mode bits 1, 0 0 (PR1,PR0) 0 Priority order is fixed 0 1 Priority order is fixed (Channel 1 > channel 3 > channel 2 > channel 0) 1 0 Round-robin priority order (Immediately after reset: Channel 0 > channel 3 > channel 2 > channel 1) 1 1 External-pin-alternating mode priority order (Immediately after reset: Channel 3 > channel 2 > channel 1 > channel 0) 2 1 Address error flag bit (AE) NMI flag bit (NMIF) Value Description (Initial value) (Channel 0 > channel 3 > channel 2 > channel 1) 0 No errors caused by DMAC 1 Address error caused by DMAC 0 No NMI interrupt 1 NMI interrupt generated 0 DMA transfer disabled for all channels 1 DMA transfer enabled for all channels (Initial value) Clear Condition: Write 0 in AE after reading AE (Initial value) Clear Condition: Write 0 in NMIF after reading NMIF 0 DMA master enable bit (DME) Rev. 7.00 Jan 31, 2006 page 598 of 658 REJ09B0272-0700 (Initial value) Appendix A On-Chip Supporting Module Registers A.2.29 Interrupt Priority Setting Register A (IPRA) INTC Start Address: H'5FFFF84 Bus Width: 8/16/32 Bit 15 14 13 12 11 10 9 8 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Bit 7 6 5 4 3 2 1 0 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Table A.30 IPRA Bit Functions Bit Bit name Description 15-12 (Set IRQ0 priority level) Sets the IRQ0 priority level value 11-8 (Set IRQ1 priority level) Sets the IRQ1 priority level value 7-4 (Set IRQ2 priority level) Sets the IRQ2 priority level value 3-0 (Set IRQ3 priority level) Sets the IRQ3 priority level value Rev. 7.00 Jan 31, 2006 page 599 of 658 REJ09B0272-0700 Appendix A On-Chip Supporting Module Registers A.2.30 Interrupt Priority Setting Register B (IPRB) INTC Start Address: H'5FFFF86 Bus Width: 8/16/32 Bit 15 14 13 12 11 10 9 8 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 Bit Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Table A.31 IPRB Bit Functions Bit Bit name Description 15-12 (Set IRQ4 priority level) Sets the IRQ4 priority level value 11-8 (Set IRQ5 priority level) Sets the IRQ5 priority level value 7-4 (Set IRQ6 priority level) Sets the IRQ6 priority level value 3-0 (Set IRQ7 priority level) Sets the IRQ7 priority level value Rev. 7.00 Jan 31, 2006 page 600 of 658 REJ09B0272-0700 Appendix A On-Chip Supporting Module Registers A.2.31 Interrupt Priority Setting Register C (IPRC) INTC Start Address: H'5FFFF88 Bus Width: 8/16/32 Bit 15 14 13 12 11 10 9 8 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 Bit Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Table A.32 IPRC Bit Functions Bit Bit name Description 15-12 (Set DMAC0 and DMAC1 priority levels) Sets the DMAC0 and DMAC1 priority level values 11-8 (Set DMAC2 and DMAC3 priority levels) Sets the DMAC2 and DMAC3 priority level values 7-4 (Set ITU0 priority level) Sets the ITU0 priority level value 3-0 (Set ITU1 priority level) Sets the ITU1 priority level value Rev. 7.00 Jan 31, 2006 page 601 of 658 REJ09B0272-0700 Appendix A On-Chip Supporting Module Registers A.2.32 Interrupt Priority Setting Register D (IPRD) INTC Start Address: H'5FFFF8A Bus Width: 8/16/32 Bit 15 14 13 12 11 10 9 8 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 Bit Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Table A.33 IPRD Bit Functions Bit Bit name Description 15-12 (Set ITU2 priority level) Sets the ITU2 priority level value 11-8 (Set ITU3 priority level) Sets the ITU3 priority level value 7-4 (Set ITU4 priority level) Sets the ITU4 priority level value 3-0 (Set SCI0 priority level) Sets the SCI0 priority level value Rev. 7.00 Jan 31, 2006 page 602 of 658 REJ09B0272-0700 Appendix A On-Chip Supporting Module Registers A.2.33 Interrupt Priority Setting Register E (IPRE) INTC Start Address: H'5FFFF8C Bus Width: 8/16/32 Bit 15 14 13 12 11 10 9 8 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 -- -- -- -- Bit Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W -- -- -- -- Table A.34 IPRE Bit Functions Bit Bit name Description 15-12 (Set SCI1 priority level) 1 11-8 (Set PRT* and A/D priority levels) 7-4 (Set WDT and REF* priority levels) 2 Sets the SC1 priority level value 1 Sets the PRT* and A/D priority level values 2 Sets the WDT and REF* priority level value Notes 1. PRT: Parity control section within the bus state controller. See section 8, Bus State Controller (BSC), for more information. 2. REF: DRAM refresh control section within the bus state controller. See section 8, Bus State Controller (BSC), for more information. Rev. 7.00 Jan 31, 2006 page 603 of 658 REJ09B0272-0700 Appendix A On-Chip Supporting Module Registers A.2.34 Interrupt Control Register (ICR) INTC Start Address: H'5FFFF8E Bus Width: 8/16/32 Bit 15 14 13 12 11 10 9 8 NMIL -- -- -- -- -- -- NMIE Initial value * 0 0 0 0 0 0 0 Read/Write R -- -- -- -- -- -- R/W Bit 7 6 5 4 3 2 1 0 IRQ0S IRQ1S IRQ2S IRQ3S IRQ4S IRQ5S IRQ6S IRQ7S Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Note: * NMI pin input high: 1 NMI pin input low: 0 Table A.35 ICR Bit Functions Bit Bit Name Value Description 15 NMI input level (NMIL) 0 Low input to NMI pin 1 High input to NMI pin 0 Interrupt request sensed at falling edge of NMI input (Initial value) 1 Interrupt request sensed at rising edge of NMI input 0 Interrupt request sensed at IRQ input low level (Initial value) 1 Interrupt request sensed at IRQ input falling edge 8 7-0 NMI edge select (NMIE) IRQ0-7 sense select (IRQ0-IRQ7) Rev. 7.00 Jan 31, 2006 page 604 of 658 REJ09B0272-0700 Appendix A On-Chip Supporting Module Registers A.2.35 Break Address Register H (BARH) UBC Start Address: H'5FFFF90 Bus Width: 8/16/32 Bit 15 14 13 12 11 10 9 8 BA31 BA30 BA29 BA28 BA27 BA26 BA25 BA24 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 BA23 BA22 BA21 BA20 BA19 BA18 BA17 BA16 Bit Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Table A.36 BARH Bit Functions Bit Bit name Description 15-0 Set break address bits 31-16 (BA31-BA16) Specifies the upper end (bits 31-16) of the address which is the break condition Rev. 7.00 Jan 31, 2006 page 605 of 658 REJ09B0272-0700 Appendix A On-Chip Supporting Module Registers A.2.36 Break Address Register L (BARL) UBC Start Address: H'5FFFF92 Bus Width: 8/16/32 Bit 15 14 13 12 11 10 9 8 BA15 BA14 BA13 BA12 BA11 BA10 BA9 BA8 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 BA7 BA6 BA5 BA4 BA3 BA2 BA1 BA0 Bit Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Table A.37 BARL Bit Functions Bit Bit name Description 15-0 Set break address bits 15-0 (BA15-BA0) Specifies the lower end (bits 15-0) of the address which is the break condition Rev. 7.00 Jan 31, 2006 page 606 of 658 REJ09B0272-0700 Appendix A On-Chip Supporting Module Registers A.2.37 Break Address Mask Register H (BAMRH) UBC Start Address: H'5FFFF94 Bus Width: 8/16/32 Bit 15 14 13 12 11 10 9 8 BAM31 BAM30 BAM29 BAM28 BAM27 BAM26 BAM25 BAM24 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 BAM23 BAM22 BAM21 BAM20 BAM19 BAM18 BAM17 BAM16 Bit Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Table A.38 BAMRH Bit Functions Bit Bit name Description 15-0 Break address masks 31-16 (BAM31-BAM16) Specifies the bits to be masked in the break address specified in BARH Rev. 7.00 Jan 31, 2006 page 607 of 658 REJ09B0272-0700 Appendix A On-Chip Supporting Module Registers A.2.38 Break Address Mask Register L (BAMRL) UBC Start Address: H'5FFFF96 Bus Width: 8/16/32 Bit 15 14 13 12 11 10 9 8 BAM15 BAM14 BAM13 BAM12 BAM11 BAM10 BAM9 BAM8 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 BAM7 BAM6 BAM5 BAM4 BAM3 BAM2 BAM1 BAM0 Bit Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Table A.39 BAMRL Bit Functions Bit Bit name Description 15-0 Break address masks 15-0 (BAM15-BAM0) Specifies the bits to be masked in the break address specified in BARL Rev. 7.00 Jan 31, 2006 page 608 of 658 REJ09B0272-0700 Appendix A On-Chip Supporting Module Registers A.2.39 Break Bus Cycle Register (BBR) UBC Start Address: H'5FFFF98 Bus Width: 8/16/32 Bit 15 14 13 12 11 10 9 8 -- -- -- -- -- -- -- -- Initial value 0 0 0 0 0 0 0 0 Read/Write -- -- -- -- -- -- -- -- Bit 7 6 5 4 3 2 1 0 CD1 CD0 ID1 ID0 RW1 RW0 SZ1 SZ0 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Table A.40 BBR Bit Functions Bit Bit name 7,6 CPU cycle/DMA cycle 0 select (CD1, CD0) 0 5,4 3,2 1,0 Instruction fetch/data access select (ID1, ID0) Read/write select (RW1, RW0) Operand size select (SZ1, SZ0) Value Description 0 User break interrupt not generated 1 CPU cycle is break condition (Initial value) 1 0 DMA cycle is break condition 1 1 CPU cycle and DMA cycle are both break conditions 0 0 User break interrupt not generated 0 1 Instruction fetch cycle is break condition (Initial value) 1 0 Data access cycle is break condition 1 1 Instruction fetch cycle and data access cycle are both break conditions 0 0 User break interrupt not generated 0 1 Read cycle is break condition 1 0 Write cycle is break condition 1 1 Read cycle and write cycle are both break conditions 0 0 Operand size not included in the break conditions (Initial value) 0 1 Byte access is break condition 1 0 Word access is break condition 1 1 Longword access is break condition (Initial value) Rev. 7.00 Jan 31, 2006 page 609 of 658 REJ09B0272-0700 Appendix A On-Chip Supporting Module Registers A.2.40 Bus Control Register (BCR) BSC Start Address: H'5FFFFA0 Bus Width: 8/16/32 Bit Initial value: Read/Write Bit Initial value: Read/Write 15 14 13 12 11 10 9 8 DRAME IOE WARP RDDTY BAS -- -- -- 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W -- -- -- 7 6 5 4 3 2 1 0 -- -- -- -- -- -- -- -- 0 0 0 0 0 0 0 0 -- -- -- -- -- -- -- -- Table A.41 BCR Bit Functions Bit Bit Name Value Description 15 DRAM enable (DRAME) 0 Area 1 is external memory space (Initial value) 1 Area 1 is DRAM space Area 6 is external memory space (Initial value) 14 Multiplex I/O enable (IOE) 0 1 Area 6 is address/data multiplex I/O space 13 Warp mode (WARP) 0 Normal mode: External access and internal access not performed simultaneously (Initial value) 1 Warp mode: External access and internal access performed simultaneously 0 RD signal high width duty ratio is 50% (Initial value) 1 RD signal high width duty ratio is 35% 0 WRH, WRL, and A0 signals valid (Initial value) 1 WR, HBS, and LBS and signals valid 12 11 RD duty (RDDTY) Byte access select (BAS) Rev. 7.00 Jan 31, 2006 page 610 of 658 REJ09B0272-0700 Appendix A On-Chip Supporting Module Registers A.2.41 Wait State Control Register 1 (WCR1) BSC Start Address: H'5FFFFA2 Bus Width: 8/16/32 Bit Initial value: Read/Write Bit Initial value: Read/Write 15 14 13 12 11 10 9 8 RW7 RW6 RW5 RW4 RW3 RW2 RW1 RW0 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 -- -- -- -- -- -- WW1 -- 1 1 1 1 1 1 1 1 -- -- -- -- -- -- R/W * -- Note: * Only write 0 in the WW1 bit when area 1 is DRAM space. When it is external memory space, do not write 0. Table A.42 WCR Bit Functions Number of read cycles Bit Bit Name WAIT Pin Signal Value Input External Space External Memory Space 15-8 Read wait 0 state control (RW7-RW0) * Not sampled during read * cycle 1 Sampled * during read cycle * (Initial value) Areas 1, 3-5, 7: fixed at 1 cycle Areas 0, 2, 6: 1 cycle + long wait state Areas 1, 3-5, 7: wait state is 2 cycles plus WAIT Areas 0, 2, 6: 1 cycle + long wait state, or wait state from WAIT DRAM Space Column address cycle: Fixed at 1 cycle (short-pitch) Internal Space MultiOn-Chip plex On-Chip ROM, I/O Modules RAM Wait Fixed at Fixed at 1 state 3 cycles cycle is 4 cycles plus WAIT Column address cycle: Wait state is 2 cycles plus WAIT (longpitch)* Rev. 7.00 Jan 31, 2006 page 611 of 658 REJ09B0272-0700 Appendix A On-Chip Supporting Module Registers Description Bit Bit Name 1 Write wait state control (WW1) DRAM Space Value (BCRDRAME = 1) Area 1 External Memory Space (BCRDRAME = 1) 0 Column address cycle: 1 cycle (short-pitch) Setting prohibited 1 Column address cycle: Wait state Wait state is 2 cycles + WAIT is 2 cycles + WAIT (long-pitch) (Initial value) Note: * During a CBR refresh, the WAIT signal is ignored and the wait state inserted using the RLW1 and RLW0 bits. A.2.42 Wait State Control Register 2 (WCR2) BSC Start Address: H'5FFFFA4 Bus Width: 8/16/32 Bit 15 14 13 12 11 10 9 8 DRW7 DRW6 DRW5 DRW4 DRW3 DRW2 DRW1 DRW0 Initial value 1 1 1 1 1 1 1 1 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 DWW7 DWW6 DWW5 DWW4 DWW3 DWW2 DWW1 DWW0 Initial value 1 1 1 1 1 1 1 1 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Bit Rev. 7.00 Jan 31, 2006 page 612 of 658 REJ09B0272-0700 Appendix A On-Chip Supporting Module Registers Table A.43 WCR2 Bit Functions Description Number of Single Mode DMA External Space Cycle States Bit Bit Name 15-8 Single mode DMA memory read wait state control (DRW7- DRW0) WAIT Pin Value Signal Input External Memory Space 0 Not sampled * during single mode DMA * memory read cycle 1 * Sampled during single mode DMA memory read cycle * (Initial value) 7-0 Single mode DMA memory write wait state control (DWW7- DWW0) 0 Not sampled * during single mode DMA * memory write cycle 1 * Sampled during single mode DMA memory write cycle * (Initial value) DRAM Space Areas 1, 3-5, 7: Column fixed at 1 cycle address cycle: Areas 0, 2, 6: Fixed at 1 1 cycle + long cycle (shortpitch) wait state Areas 1, 3-5, 7: Column wait state is 2 address cycle: cycles plus Wait state is 2 WAIT cycles plus Areas 0, 2, 6: WAIT (long1 cycle + long pitch) wait state, or wait state from WAIT Areas 1, 3-5, 7: Column fixed at 1 cycle address cycle: Areas 0, 2, 6: Fixed at 1 1 cycle + long cycle (shortpitch) wait state Multiplex I/O Wait state is 4 cycles plus WAIT Wait state is 4 cycles plus WAIT Areas 1, 3-5, 7: Column wait state is 2 address cycle: cycles plus Wait state is 2 WAIT cycles plus Areas 0, 2, 6: WAIT (long1 cycle + long pitch) wait state, or wait state from WAIT Rev. 7.00 Jan 31, 2006 page 613 of 658 REJ09B0272-0700 Appendix A On-Chip Supporting Module Registers A.2.43 Wait State Control Register 3 (WCR3) BSC Start Address: H'5FFFFA6 Bus Width: 8/16/32 Bit 15 WPU 14 13 12 A02LW1 A02LW0 A6LW1 11 10 9 8 A6LW0 -- -- -- Initial value 1 1 1 1 1 0 0 0 Read/Write R/W R/W R/W R/W R/W -- -- -- 7 6 5 4 3 2 1 0 -- -- -- -- -- -- -- -- Bit Initial value 0 0 0 0 0 0 0 0 Read/Write -- -- -- -- -- -- -- -- Table A.44 WCR3 Bit Functions Bit Bit Name Value Description 15 Wait pin pull-up control (WPU) 0 WAIT pin not pulled up 1 WAIT pin pulled up 14,13 Areas 0 and 2 long wait insert 1, 0 (A02LW1, A02LW0) 12,11 Area 6 long wait insert 1, 0 (A6LW1, A6LW0) 0 0 1-cycle long wait state inserted 0 1 2-cycle long wait state inserted 1 0 3-cycle long wait state inserted 1 1 4-cycle long wait state inserted 0 0 1-cycle long wait state inserted 0 1 2-cycle long wait state inserted 1 0 3-cycle long wait state inserted 1 1 4-cycle long wait state inserted Rev. 7.00 Jan 31, 2006 page 614 of 658 REJ09B0272-0700 (Initial value) (Initial value) (Initial value) Appendix A On-Chip Supporting Module Registers A.2.44 DRAM Area Control Register (DCR) BSC Start Address: H'5FFFFA8 Bus Width: 8/16/32 Bit 15 14 13 12 11 10 9 8 CW2 RASD TPC BE CDTY MXE MXC1 MXC0 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 -- -- -- -- -- -- -- -- Bit Initial value 0 0 0 0 0 0 0 0 Read/Write -- -- -- -- -- -- -- -- Rev. 7.00 Jan 31, 2006 page 615 of 658 REJ09B0272-0700 Appendix A On-Chip Supporting Module Registers Table A.45 DCR Bit Functions Bit Bit Name Value Description 15 2-CAS system/2-WE system (CW2) 0 2-CAS system: CASH, CASL, and WRL signals are valid (Initial value) 1 2-WE system: CASL, WRH, and WRL signals are valid 0 RAS up mode: Returns RAS signal to high and waits for next DRAM access (Initial value) 1 RAS down mode: Leaves RAS signal low and waits for next DRAM access 0 1-cycle pre-charge cycle inserted 1 2-cycle pre-charge cycle inserted 14 13 12 11 10 9,8 RAS down (RASD) Number of RAS pre-charge cycles (TPC) Burst operation enable (BE) 0 CAS duty (CDTY) Multiplex enable (MXE) Normal mode: Full access (Initial value) (Initial value) 1 High-speed page mode: Burst operation 0 CAS signal high width duty ratio is 50% (Initial value) 1 CAS signal high width duty ratio is 35% 0 Row address and column address not multiplexed (Initial value) 1 Row address and column address multiplexed Multiplex shift count 1,0 (MXC1, MXC0) Row address shift (MXE = 1) Row address for comparison during burst (MXE = 0 or 1) 0 0 8 bits (Initial value) A27-A8 0 1 9 bits A27-A9 1 0 10 bits A27-A10 1 1 Reserved Reserved Rev. 7.00 Jan 31, 2006 page 616 of 658 REJ09B0272-0700 (Initial value) Appendix A On-Chip Supporting Module Registers A.2.45 Parity Control Register (PCR) BSC Start Address: H'5FFFFAA Bus Width: 8/16/32 Bit 15 14 13 12 11 10 9 8 PEF PFRC PEO PCHK1 PCHK0 -- -- -- Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W -- -- -- 7 6 5 4 3 2 1 0 -- -- -- -- -- -- -- -- Bit Initial value 0 0 0 0 0 0 0 0 Read/Write -- -- -- -- -- -- -- -- Table A.46 PCR Bit Functions Bit Bit Name Value Description 15 Parity error flag (PEF) 0 No parity error (Initial value) Clear Condition: PEF read, then 0 written in PEF 14 13 Parity forced output (PFRC) Parity polarity (PEO) 12,11 Parity check enable 1, 0 (PCHK1, PCHK0) 1 Parity error occurred 0 No forced parity output 1 Forced high-level output 0 Even parity 1 Odd parity (Initial value) (Initial value) 0 0 Parity not checked or generated (Initial value) 0 1 Parity checked and generated in DRAM space 1 0 Parity checked and generated in DRAM space and area 2 1 1 Reserved Rev. 7.00 Jan 31, 2006 page 617 of 658 REJ09B0272-0700 Appendix A On-Chip Supporting Module Registers A.2.46 Refresh Control Register (RCR) BSC Start Address: H'5FFFFAC Bus Width: 8/16/32 (read), 16 (write) Bit 15 14 13 12 11 10 9 8 -- -- -- -- -- -- -- -- Initial value 0 0 0 0 0 0 0 0 Read/Write -- -- -- -- -- -- -- -- Bit 7 6 5 4 3 2 1 0 RLW1 RLW0 -- -- -- -- RFSHE RMODE Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W -- -- -- -- Table A.47 RCR Bit Functions Bit Bit Name Value Description 7 Refresh control (RFSHE) 0 No refresh control (Initial value) (RTCNT can be used as an interval timer) 6 5,4 Refresh mode (RMODE) Wait state insertion CBR refresh 1,0 (RLW1, RLW0) 1 Refresh control 0 CAS-before-RAS refresh performed 1 Self-refresh performed 0 0 1-cycle wait state inserted 0 1 2-cycle wait state inserted 1 0 3-cycle wait state inserted 1 1 4-cycle wait state inserted Rev. 7.00 Jan 31, 2006 page 618 of 658 REJ09B0272-0700 (Initial value) (Initial value) Appendix A On-Chip Supporting Module Registers A.2.47 Refresh Timer Control/Status Register (RTCSR) BSC Start Address: H'5FFFFAE Bus Width: 8/16/32 (read), 16 (write) Bit 15 14 13 12 11 10 9 8 -- -- -- -- -- -- -- -- Initial value 0 0 0 0 0 0 0 0 Read/Write -- -- -- -- -- -- -- -- Bit 7 6 5 4 3 2 1 0 CMF CMIE CKS2 CKS1 CKS0 -- -- -- Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W -- -- -- Table A.48 RSTCR Bit Functions Bit Bit Name Value Description 7 Compare match flag (CMF) 0 RTCNT and RTCOR values do not match(Initial value) Clear Condition: CMF read, then 0 written in CMF 6 5-3 1 RTCNT and RTCOR values match Compare match interrupt enable (CMIE) 0 Compare match interrupt (CMI) disabled (Initial value) 1 Compare match interrupt (CMI) enabled Clock select 2-0 (CKS2- CKS0) 0 0 0 Clock input disabled 0 0 1 /2 0 1 0 /8 0 1 1 /32 1 0 0 /128 1 0 1 /512 1 1 0 /2048 1 1 1 /4096 (Initial value) Rev. 7.00 Jan 31, 2006 page 619 of 658 REJ09B0272-0700 Appendix A On-Chip Supporting Module Registers A.2.48 Refresh Timer Counter (RTCNT) BSC Start Address: H'5FFFFB0 Bus Width: 8/16/32 (read), 16 (write) Bit 15 14 13 12 11 10 9 8 -- -- -- -- -- -- -- -- Initial value 0 0 0 0 0 0 0 0 Read/Write -- -- -- -- -- -- -- -- Bit 7 6 5 4 3 2 1 0 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Table A.49 RTCNT Bit Functions Bit Bit Name Description 7-0 (Count value) Input clock count value Rev. 7.00 Jan 31, 2006 page 620 of 658 REJ09B0272-0700 Appendix A On-Chip Supporting Module Registers A.2.49 Refresh Timer Constant Register (RTCOR) BSC Start Address: H'5FFFFB2 Bus Width: 8/16/32 (read), 16 (write) Bit 15 14 13 12 11 10 9 8 -- -- -- -- -- -- -- -- Initial value 0 0 0 0 0 0 0 0 Read/Write -- -- -- -- -- -- -- -- Bit 7 6 5 4 3 2 1 0 Initial value 1 1 1 1 1 1 1 1 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Table A.50 RTCOR Bit Functions Bit Bit Name Description 7-0 (Compare match cycle) Set with compare match cycle A.2.50 Timer Control/Status Register (TCSR) WDT Start Address: H'5FFFFB8 Bus Width: 8 (read), 16 (write) Bit 7 6 5 4 3 2 1 0 OVF WT/IT TME -- -- CKS2 CKS1 CKS0 Initial value 0 0 0 1 1 0 0 0 Read/Write R/(W)* R/W R/W -- -- R/W R/W R/W Note: * Only 0 can be written, to clear the flag. Rev. 7.00 Jan 31, 2006 page 621 of 658 REJ09B0272-0700 Appendix A On-Chip Supporting Module Registers Table A.51 TCSR Bit Functions Bit Bit Name Value Description 7 Overflow flag (OVF) 0 No TCNT overflow in interval timer mode (Initial value) 1 TCNT overflow generated in interval timer mode 0 Interval timer mode: When TCNT overflows, interval timer interrupt (ITI) request sent to CPU (Initial value) 1 Watchdog timer mode: When TCNT overflows, WDTOVF signal is output externally* 0 Timer disable: TCNT initialized at H'00 and countup halted (Initial value) 1 Timer enable: TCNT starts counting up. When TCNT overflows, a WDTOVF signal or interrupt is generated Clear Condition: OVF read, then 0 written in OVF 6 5 2-0 Timer mode select (WT/IT) Timer enable (TME) Clock select 2-0 (CKS2-CKS0) Clock Overflow cycle (=20 MHz) 0 0 0 /2 (Initial value) 25.6 s 0 0 1 /64 819.2 s 0 1 0 /128 1.6 ms 0 1 1 /256 3.3 ms 0 0 0 /512 6.6 ms 0 0 1 /1024 13.1 ms 0 1 0 /4096 52.4 ms 0 1 1 /8192 104.9 ms Note: * When the RSTE bit in RSTCSR is 1, an internal reset signal is also generated simultaneously with the WDTOVF signal when TCNT overflows in watchdog timer mode. Rev. 7.00 Jan 31, 2006 page 622 of 658 REJ09B0272-0700 Appendix A On-Chip Supporting Module Registers A.2.51 Timer Counter (TCNT) WDT Start Address: H'5FFFFB9 (read), H'5FFFFB8 (write) Bus Width: 8 (read), 16 (write) Bit 7 6 5 4 3 2 1 0 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Table A.52 TCNT Bit Functions Bit Bit Name Description 7-0 Count value Input clock count value A.2.52 Reset Control/Status Register (RSTCSR) WDT Start Address: H'5FFFFBB (read), H'5FFFFBA (write) Bus Width: 8 (read), 16 (write) Bit 7 6 5 4 3 2 1 0 WOVF RSTE RSTS -- -- -- -- -- Initial value 0 0 0 1 1 1 1 1 Read/Write R/(W)* R/W R/W -- -- -- -- -- Note: * Only 0 can be written, to clear the flag. Rev. 7.00 Jan 31, 2006 page 623 of 658 REJ09B0272-0700 Appendix A On-Chip Supporting Module Registers Table A.53 RSTCSR Bit Functions Bit Bit Name Value Description 7 Watchdog timer overflow flag (WOVF) 0 No TCNT overflow in watchdog timer mode (Initial value) Clear Condition: WOVF read, then 0 written in WOVF 1 6 Reset enable (RSTE) TCNT overflow generated in watchdog timer mode No internal reset when TCNT overflows* (Initial value) 0 1 5 Reset select (RSTS) Internal reset when TCNT overflows 0 Power-on reset 1 Manual reset (Initial value) Note: * The microprocessor is not reset internally, but TCNT and TCSR within the WDT are reset. A.2.53 Standby Control Register (SBYCR) Power-Down State Start Address: H'5FFFFBC Bus Width: 8/16/32 Bit 7 6 5 4 3 2 1 0 SBY HIZ -- -- -- -- -- -- Initial value 0 0 0 1 1 1 1 1 Read/Write R/W R/W -- -- -- -- -- -- Table A.54 SBYCR Bit Functions Bit Bit Name Value Description 7 Standby (SBY) 0 Shift to sleep mode on execution of SLEEP instruction (Initial value) 1 Shift to standby mode on execution of SLEEP instruction 0 Pin states held in standby mode 1 Pins change to high impedance in standby mode 6 Port high impedance (HIZ) Rev. 7.00 Jan 31, 2006 page 624 of 658 REJ09B0272-0700 (Initial value) Appendix A On-Chip Supporting Module Registers A.2.54 Port A Data Register (PADR) Port A Start Address: H'5FFFFC0 Bus Width: 8/16/32 Bit 15 14 13 12 11 10 9 PA15DR PA14DR PA13DR PA12DR PA11DR PA10DR PA9DR 8 PA8DR Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Bit 7 6 5 4 3 2 1 0 PA7DR PA6DR PA5DR PA4DR PA3DR PA2DR PA1DR PA0DR Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Table A.55 PADR Bit Functions PAIOR Pin Function Read Write 0 General input Pin status Can write to PADR, but this does not affect pin status All other Pin status Can write to PADR, but this does not affect pin status General input PADR value Value written is output from pin All other PADR value Can write to PADR, but this does not affect pin status 1 Rev. 7.00 Jan 31, 2006 page 625 of 658 REJ09B0272-0700 Appendix A On-Chip Supporting Module Registers A.2.55 Port B Data Register (PBDR) Port B Start Address: H'5FFFFC2 Bus Width: 8/16/32 Bit 15 14 13 12 11 10 9 PB15DR PB14DR PB13DR PB12DR PB11DR PB10DR PB9DR 8 PB8DR Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 PB7DR PB6DR PB5DR PB4DR PB3DR PB2DR PB1DR PB0DR Bit Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Table A.56 Bit Functions PBIOR Pin Function Read Write 0 General input Pin status Can write to PBDR, but this does not affect pin status TPn Pin status Cannot write All other Pin status Can write to PBDR, but this does not affect pin status General input PBDR value Value written is output from pin TPn PBDR value Cannot write All other PBDR value Can write to PBDR, but this does not affect pin status 1 Rev. 7.00 Jan 31, 2006 page 626 of 658 REJ09B0272-0700 Appendix A On-Chip Supporting Module Registers A.2.56 Port C Data Register (PCDR) Port C Start Address: H'5FFFFD0 Bus Width: 8/16/32 Bit 15 14 13 12 11 10 9 8 -- -- -- -- -- -- -- -- Initial value -- -- -- -- -- -- -- -- Read/Write R R R R R R R R Bit 7 6 5 4 3 2 1 0 PC7DR PC6DR PC5DR PC4DR PC3DR PC2DR PC1DR PC0DR Initial value -- -- -- -- -- -- -- -- Read/Write R R R R R R R R Table A.57 PCDR Bit Functions Pin I/O Pin Function Read Write Input General input Pin status Ignored (no affect on pin status) ANn 1 Ignored (no affect on pin status) Rev. 7.00 Jan 31, 2006 page 627 of 658 REJ09B0272-0700 Appendix A On-Chip Supporting Module Registers A.2.57 Port A I/O Register (PAIOR) PFC Start Address: H'5FFFFC4 Bus Width: 8/16/32 Bit 15 14 13 12 11 10 9 8 PA15 IOR PA14 IOR PA13 IOR PA12 IOR PA11 IOR PA10 IOR PA9 IOR PA8 IOR Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 PA7 IOR PA6 IOR PA5 IOR PA4 IOR PA3 IOR PA2 IOR PA1 IOR PA0 IOR Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Bit Table A.58 PAIOR Bit Functions Bit Bit Name Value 15-0 Port A I/O (PA15IOR- PA0IOR) 0 Input 1 Output Rev. 7.00 Jan 31, 2006 page 628 of 658 REJ09B0272-0700 Description (Initial value) Appendix A On-Chip Supporting Module Registers A.2.58 Port B I/O Register (PBIOR) PFC Start Address: H'5FFFFC6 Bus Width: 8/16/32 Bit 15 14 13 12 11 10 9 8 PB15 IOR PB14 IOR PB13 IOR PB12 IOR PB11 IOR PB10 IOR PB9 IOR PB8 IOR Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 PB7 IOR PB6 IOR PB5 IOR PB4 IOR PB3 IOR PB2 IOR PB1 IOR PB0 IOR Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Bit Table A.59 PBIOR Bit Functions Bit Bit Name Value Description 15-0 Port B I/O (PB15IOR- PB0IOR) 0 Input 1 Output (Initial value) Rev. 7.00 Jan 31, 2006 page 629 of 658 REJ09B0272-0700 Appendix A On-Chip Supporting Module Registers A.2.59 Port A Control Register 1 (PACR1) PFC Start Address: H'5FFFFC8 Bus Width: 8/16/32 Bit 15 14 13 12 11 10 9 8 PA15 MD1 PA15 MD0 PA14 MD1 PA14 MD0 PA13 MD1 PA13 MD0 PA12 MD1 PA12 MD0 Initial value 0 0 1 1 0 0 1 1 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 PA11 MD1 PA11 MD0 PA10 MD1 PA10 MD0 PA9 MD1 PA9 MD0 -- PA8 MD Initial value 0 0 0 0 0 0 1 0 Read/Write R/W R/W R/W R/W R/W R/W -- R/W Bit Rev. 7.00 Jan 31, 2006 page 630 of 658 REJ09B0272-0700 Appendix A On-Chip Supporting Module Registers Table A.60 PACR1 Bit Functions Bit Bit Name 15,14 PA15 mode bits 1,0 (PA15MD1, PA15MD0) 13,12 PA14 mode bits 1,0 (PA14MD1, PA14MD0) 11,10 PA13 mode bits 1,0 (PA13MD1, PA13MD0) 9,8 7,6 5,4 3,2 0 PA12 mode bits 1,0 (PA12MD1, PA12MD0) PA11 mode bits 1,0 (PA11MD1, PA11MD0) PA10 mode bits 1,0 (PA10MD1, PA10MD0) PA9 mode bits 1,0 (PA9MD1, PA9MD0) PA8 mode bit (PA8MD) Value Description 0 0 General-purpose input/output (PA15) 0 1 Interrupt request input (IRQ3) 1 0 Reserved 1 1 DMA transfer request input (DREQ1) 0 0 General-purpose input/output (PA14) 0 1 Interrupt request input (IRQ2) 1 0 Reserved 1 1 DMA transfer request acknowledge output (DACK1) (Initial value) 0 0 General-purpose input/output (PA13) 0 1 Interrupt request input (IRQ1) 1 0 ITU timer clock input (TCLKB) 1 1 DMA transfer request input (DREQ0) 0 0 General-purpose input/output (PA12) 0 1 Interrupt request input (IRQ0) 1 0 ITU timer clock input (TCKLA) 1 1 DMA transfer request acknowledge output (DACK0) (Initial value) 0 0 General-purpose input/output (PA11) 0 1 High data bus parity input/output (DPH) 1 0 ITU input capture input/output compare output (TIOCB1) 1 1 Reserved (Initial value) (Initial value) (Initial value) 0 0 General-purpose input/output (PA10) 0 1 Low data bus parity input/output (DPL) 1 0 ITU input capture input/output compare output (TIOCA1) 1 1 Reserved 0 0 General-purpose input/output (PA9) 0 1 Address hold output (AH) 1 0 A/D conversion trigger input (ADTRG) 1 1 Interrupt request output (IRQOUT) 0 General-purpose input/output (PA8) 1 Bus request input (BREQ) (Initial value) (Initial value) (Initial value) Rev. 7.00 Jan 31, 2006 page 631 of 658 REJ09B0272-0700 Appendix A On-Chip Supporting Module Registers A.2.60 Port A Control Register 2 (PACR2) PFC Start Address: H'5FFFFCA Bus Width: 8/16/32 Bit 15 14 13 12 11 10 9 8 -- PA7MD -- PA6MD -- PA5MD -- PA4MD Initial value 1 1 1 1 1 1 1 1 Read/Write -- R/W -- R/W -- R/W -- R/W 7 6 5 4 3 2 1 0 Bit PA3MD1 PA3MD0 PA2MD1 PA2MD0 PA1MD1 PA1MD0 PA0MD1 PA0MD0 Initial value 1 0 0 1 0 1 0 1 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Rev. 7.00 Jan 31, 2006 page 632 of 658 REJ09B0272-0700 Appendix A On-Chip Supporting Module Registers Table A.61 PACR2 Bit Functions Bit Bit Name Value Description 14 PA7 mode bit (PA7MD) 0 General-purpose input/output (PA7) 1 Bus request acknowledge output (BACK) 0 General-purpose input/output (PA6) 1 Read output (RD) 0 General-purpose input/output (PA5) 1 High write output (WRH) or low byte strobe output (LBS) (Initial value) General-purpose input/output (PA4) 12 PA6 mode bit (PA6MD) 10 PA5 mode bit (PA5MD) (Initial value) (Initial value) 8 PA4 mode bit (PA4MD) 0 7,6 PA3 mode bits 1,0 (PA3MD1, PA3MD0) 0 0 General-purpose input/output (PA3) 0 1 Chip select output (CS7) 1 0 Wait state input (WAIT) 1 1 Reserved 0 0 General-purpose input/output (PA2) 0 1 Chip select output (CS6) 1 0 ITU input capture input/output compare output (TIOCB0) 1 1 Reserved 0 0 General-purpose input/output (PA1) 0 1 Chip select output (CS5) 1 0 Row address strobe output (RAS) 1 1 Reserved 0 0 General-purpose input/output (PA0) 1 5,4 3,2 1,0 PA2 mode bits 1,0 (PA2MD1, PA2MD0) PA1 mode bits 1,0 (PA1MD1, PA1MD0) PA0 mode bits 1,0 (PA0MD1, PA0MD0) Low write output (WRL) or write output (WR)(Initial value) (Initial value) (Initial value) (Initial value) 0 1 Chip select output (CS4) 1 0 ITU input capture input/output compare output (TIOCA0) (Initial value) 1 1 Reserved Rev. 7.00 Jan 31, 2006 page 633 of 658 REJ09B0272-0700 Appendix A On-Chip Supporting Module Registers A.2.61 Port B Control Register 1 (PBCR1) PFC Start Address: H'5FFFFCC Bus Width: 8/16/32 Bit 15 14 13 12 11 10 9 8 PB15 MD1 PB15 MD0 PB14 MD1 PB14 MD0 PB13 MD1 PB13 MD0 PB12 MD1 PB12 MD0 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 PB11 MD1 PB11 MD0 PB10 MD1 PB10 MD0 PB9 MD1 PB9 MD0 PB8 MD1 PB8 MD0 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Bit Rev. 7.00 Jan 31, 2006 page 634 of 658 REJ09B0272-0700 Appendix A On-Chip Supporting Module Registers Table A.62 PBCR1 Bit Functions Bit Bit Name 15,14 PB15 mode bits 1,0 (PB15MD1, PB15MD0) 13,12 PB14 mode bits 1,0 (PB14MD1, PB14MD0) 11,10 PB13 mode bits 1,0 (PB13MD1, PB13MD0) 9,8 7,6 5,4 3,2 1,0 PB12 mode bits 1,0 (PB12MD1, PB12MD0) PB11 mode bits 1,0 (PB11MD1, PB11MD0) PB10 mode bits 1,0 (PB10MD1, PB10MD0) PB9 mode bits 1,0 (PB9MD1, PB9MD0) PB8 mode bits 1,0 (PB8MD1, PB8MD0) Value Description 0 0 General-purpose input/output (PB15) 0 1 Interrupt request input (IRQ7) 1 0 Reserved 1 1 Timing pattern output (TP15) 0 0 General-purpose input/output (PB14) 0 1 Interrupt request input (IRQ6) 1 0 Reserved 1 1 Timing pattern output (TP14) 0 0 General-purpose input/output (PB13) 0 1 Interrupt request input (IRQ5) 1 0 Serial clock input/output (SCK1) 1 1 Timing pattern output (TP13) 0 0 General-purpose input/output (PB12) 0 1 Interrupt request input (IRQ4) 1 0 Serial clock input/output (SCK0) 1 1 Timing pattern output (TP12) 0 0 General-purpose input/output (PB11) 0 1 Reserved 1 0 Transmit data input (TxD1) 1 1 Timing pattern output (TP11) 0 0 General-purpose input/output (PB10) 0 1 Reserved 1 0 Receive data input (RxD1) 1 1 Timing pattern output (TP10) 0 0 General-purpose input/output (PB9) 0 1 Reserved 1 0 Transmit data input (TxD0) 1 1 Timing pattern output (TP9) 0 0 General-purpose input/output (PB8) 0 1 Reserved 1 0 Receive data input (RxD0) 1 1 Timing pattern output (TP8) (Initial value) (Initial value) (Initial value) (Initial value) (Initial value) (Initial value) (Initial value) (Initial value) Rev. 7.00 Jan 31, 2006 page 635 of 658 REJ09B0272-0700 Appendix A On-Chip Supporting Module Registers A.2.62 Port B Control Register 2 (PBCR2) PFC Start Address: H'5FFFFCE Bus Width: 8/16/32 Bit 15 14 13 12 11 10 9 8 PB7MD1 PB7MD0 PB6MD1 PB6MD0 PB5MD1 PB5MD0 PB4MD1 PB4MD0 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 Bit PB3MD1 PB3MD0 PB2MD1 PB2MD0 PB1MD1 PB1MD0 PB0MD1 PB0MD0 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Rev. 7.00 Jan 31, 2006 page 636 of 658 REJ09B0272-0700 Appendix A On-Chip Supporting Module Registers Table A.63 PBCR2 Bit Functions Bit Bit Name 15,14 PB7 mode bits 1,0 (PB7MD1, PB7MD0) 13,12 PB6 mode bits 1,0 (PB6MD1, PB6MD0) 11,10 PB5 mode bits 1,0 (PB5MD1, PB5MD0) 9,8 7,6 5,4 3,2 1,0 PB4 mode bits 1,0 (PB4MD1, PB4MD0) PB3 mode bits 1,0 (PB3MD1, PB3MD0) PB2 mode bits 1,0 (PB2MD1, PB2MD0) PB1 mode bits 1,0 (PB1MD1, PB1MD0) PB0 mode bits 1,0 (PB0MD1, PB0MD0) Value Description 0 0 General-purpose input/output (PB7) 0 1 ITU timer clock input (TCLKD) 1 0 ITU output compare output (TOCXB4) (Initial value) 1 1 Timing pattern output (TP7) 0 0 General-purpose input/output (PB6) 0 1 ITU timer clock input (TCLKC) 1 0 ITU output compare output (TOCXA4) 1 1 Timing pattern output (TP6) 0 0 General-purpose input/output (PB5) 0 1 Reserved 1 0 ITU input capture input/output compare output (TIOCB4) 1 1 Timing pattern output (TP5) 0 0 General-purpose input/output (PB4) 0 1 Reserved 1 0 ITU input capture input/output compare output (TIOCA4) 1 1 Timing pattern output (TP4) 0 0 General-purpose input/output (PB3) 0 1 Reserved 1 0 ITU input capture input/output compare output (TIOCB3) (Initial value) (Initial value) (Initial value) (Initial value) 1 1 Timing pattern output (TP3) 0 0 General-purpose input/output (PB2) 0 1 Reserved 1 0 ITU input capture input/output compare output (TIOCA3) 1 1 Timing pattern output (TP2) 0 0 General-purpose input/output (PB1) 0 1 Reserved 1 0 ITU input capture input/output compare output (TIOCB2) 1 1 Timing pattern output (TP1) 0 0 General-purpose input/output (PB0) 0 1 Reserved 1 0 ITU input capture input/output compare output (TIOCA2) 1 1 Timing pattern output (TP0) (Initial value) (Initial value) (Initial value) Rev. 7.00 Jan 31, 2006 page 637 of 658 REJ09B0272-0700 Appendix A On-Chip Supporting Module Registers A.2.63 Column Address Strobe Pin Control Register (CASCR) PFC Start Address: H'5FFFFEE Bus Width: 8/16/32 Bit 15 14 13 12 11 10 9 8 CASH MD1 CASH MD0 CASL MD1 CASL MD0 -- -- -- -- Initial value 0 1 0 1 1 1 1 1 Read/Write R/W R/W R/W R/W -- -- -- -- 7 6 5 4 3 2 1 0 -- -- -- -- -- -- -- -- Initial value 1 1 1 1 1 1 1 1 Read/Write -- -- -- -- -- -- -- -- Bit Table A.64 CASCR Bit Functions Bit Bit Name 15,14 CASH mode bits 1,0 (CASHMD1, CASHMD0) 13,12 CASL mode bits 1,0 (CASLMD1, CASLMD0) Value Description 0 0 Reserved 0 1 Chip select output (CS1) 1 0 Column address strobe output (CASH) 1 1 Reserved 0 0 Reserved 0 1 Chip select output (CS3) 1 0 Column address strobe output (CASL) 1 1 Reserved Rev. 7.00 Jan 31, 2006 page 638 of 658 REJ09B0272-0700 (Initial value) (Initial value) Appendix A On-Chip Supporting Module Registers A.2.64 TPC Output Mode Register (TPMR) TPC Start Address: H'5FFFFF0 Bus Width: 8/16 Bit 7 6 5 4 3 2 1 0 -- -- -- -- Initial value 1 1 1 1 0 0 0 0 Read/Write -- -- -- -- R/W R/W R/W R/W G3NOV G2NOV G1NOV G0NOV Table A.65 TPMR Bit Functions Bit Bit Name Value Description 3 Group 3 nonoverlap (G3NOV) 0 TPC output group 3 operates normally (the output value is updated at every compare match A of the selected ITU) (Initial value) 1 TPC output group 3 operates in non-overlap mode (1 output and 0 output can be performed independently upon compare matches A and B of the selected ITU) 0 TPC output group 2 operates normally (the output value is updated at every compare match A of the selected ITU) (Initial value) 1 TPC output group 2 operates in non-overlap mode (1 output and 0 output can be performed independently upon compare matches A and B of the selected ITU) 0 TPC output group 1 operates normally (the output value is updated at every compare match A of the selected ITU) (Initial value) 1 TPC output group 1 operates in non-overlap mode (1 output and 0 output can be performed independently upon compare matches A and B of the selected ITU) 0 TPC output group 0 operates normally (the output value is updated at every compare match A of the selected ITU) (Initial value) 1 TPC output group 0 operates in non-overlap mode (1 output and 0 output can be performed independently upon compare matches A and B of the selected ITU) 2 1 0 Group 2 nonoverlap (G2NOV) Group 1 nonoverlap (G1NOV) Group 0 nonoverlap (G0NOV) Rev. 7.00 Jan 31, 2006 page 639 of 658 REJ09B0272-0700 Appendix A On-Chip Supporting Module Registers A.2.65 TPC Output Control Register (TPCR) TPC Start Address: H'5FFFFF1 Bus Width: 8/16 Bit 7 6 5 4 3 2 1 0 G3CMS1 G3CMS0 G2CMS1 G2CMS0 G1CMS1 G1CMS0 G0CMS1 G0CMS0 Initial value 1 1 1 1 1 1 1 1 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Rev. 7.00 Jan 31, 2006 page 640 of 658 REJ09B0272-0700 Appendix A On-Chip Supporting Module Registers Table A.66 TPCR Bit Functions Bit Bit Name Value Description 7,6 Group 3 compare match sel- 0 ect 1, 0 (G3CMS1, G3CMS0) 0 The output trigger of TPC output group 3 (pins TP15- TP12) is the ITU channel 0 compare match 0 1 The output trigger of TPC output group 3 (pins TP15- TP12) is the ITU channel 1 compare match 1 0 The output trigger of TPC output group 3 (pins TP15- TP12) is the ITU channel 2 compare match 1 1 The output trigger of TPC output group 3 (pins TP15- TP12) is the ITU channel 3 compare match* 5,4 Group 2 compare match sel- 0 ect 1, 0 (G2CMS1, G2CMS0) 0 The output trigger of TPC output group 2 (pins TP11- TP8) is the ITU channel 0 compare match 0 1 The output trigger of TPC output group 2 (pins TP11- TP8) is the ITU channel 1 compare match 1 0 The output trigger of TPC output group 2 (pins TP11- TP8) is the ITU channel 2 compare match 1 1 The output trigger of TPC output group 2 (pins TP11- TP8) is the ITU channel 3 compare match* 3,2 Group 1 compare match sel- 0 ect 1, 0 (G1CMS1, G1CMS0) 0 The output trigger of TPC output group 1 (pins TP7- TP4) is the ITU channel 0 compare match 0 1 The output trigger of TPC output group 1 (pins TP7- TP4) is the ITU channel 1 compare match 1 0 The output trigger of TPC output group 1 (pins TP7- TP4) is the ITU channel 2 compare match 1 1 The output trigger of TPC output group 1 (pins TP7- TP4) is the ITU channel 3 compare match* 1,0 Group 0 compare match sel- 0 ect 1, 0 (G0CMS1, G0CMS0) 0 The output trigger of TPC output group 0 (pins TP3- TP0) is the ITU channel 0 compare match 0 1 The output trigger of TPC output group 0 (pins TP3- TP0) is the ITU channel 1 compare match 1 0 The output trigger of TPC output group 0 (pins TP3- TP0) is the ITU channel 2 compare match 1 1 The output trigger of TPC output group 0 (pins TP3- TP0) is the ITU channel 3 compare match* Note: * Initial value Rev. 7.00 Jan 31, 2006 page 641 of 658 REJ09B0272-0700 Appendix A On-Chip Supporting Module Registers A.2.66 Next Data Enable Register A (NDERA) TPC Start Address: H'5FFFFF3 Bus Width: 8/16 Bit 7 6 5 4 3 2 1 0 NDER7 NDER6 NDER5 NDER4 NDER3 NDER2 NDER1 NDER0 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Table A.67 NDERA Bit Functions Bit Bit Name Value Description 7-0 Next data enable 7-0 (NDER7-NDER0) 0 Disable TPC output TP7-TP0 disabled (Initial value) (Transfer from NDR7-NDR0 to PB7-PB0 disabled) 1 TPC output TP7-TP0 enabled (Transfer from NDR7-NDR0 to PB7-PB0 enabled) A.2.67 Next Data Enable Register B (NDERB) TPC Start Address: H'5FFFFF2 Bus Width: 8/16 Bit 7 6 5 4 3 2 1 0 NDER15 NDER14 NDER13 NDER12 NDER11 NDER10 NDER9 NDER8 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Table A.68 NDERB Bit Functions Bit Bit Name Value Description 7-0 Next data enable 7-0 (NDER15-NDER8) 0 TPC output TP15-TP8 disabled (Initial value) (Transfer from NDR15-NDR8 to PB15-PB8 disabled) 1 TPC output TP15-TP8 enabled (Transfer from NDR15-NDR8 to PB15-PB8 enabled) Rev. 7.00 Jan 31, 2006 page 642 of 658 REJ09B0272-0700 Appendix A On-Chip Supporting Module Registers A.2.68 Next Data Register A (NDRA) TPC (When the Output Triggers of TPC Output Groups 0 and 1 are the Same) Start Address: H'5FFFFF5 Bus Width: 8/16 Bit 7 6 5 4 3 2 1 0 NDR7 NDR6 NDR5 NDR4 NDR3 NDR2 NDR1 NDR0 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Table A.69 NDRA Bit Functions Bit Bit Name Description 7-4 Next data 7-4 (NDR7- NDR4) Stores the next output data for TPC output group 1 3-0 Next data 3-0 (NDR3- NDR0) Stores the next output data for TPC output group 0 A.2.69 Next Data Register A (NDRA) TPC (When the Output Triggers of TPC Output Groups 0 and 1 are the Same) Start Address: H'5FFFFF7 Bus Width: 8/16 Bit 7 6 5 4 3 2 1 0 -- -- -- -- -- -- -- -- Initial value 1 1 1 1 1 1 1 1 Read/Write -- -- -- -- -- -- -- -- Table A.70 NDRA Bit Functions Bit Bit Name Description 7-0 Reserved bits Writing is invalid; always read as 1 Rev. 7.00 Jan 31, 2006 page 643 of 658 REJ09B0272-0700 Appendix A On-Chip Supporting Module Registers A.2.70 Next Data Register A (NDRA) TPC (When the Output Triggers of TPC Output Groups 0 and 1 are Different) Start Address: H'5FFFFF5 Bus Width: 8/16 Bit 7 6 5 4 3 2 1 0 NDR7 NDR6 NDR5 NDR4 -- -- -- -- Initial value 0 0 0 0 1 1 1 1 Read/Write R/W R/W R/W R/W -- -- -- -- Table A.71 NDRA Bit Functions Bit Bit Name Description 7-4 Next data 7-4 (NDR7- NDR4) Stores the next output data for TPC output group 1 A.2.71 Next Data Register A (NDRA) TPC (When the Output Triggers of TPC Output Groups 0 and 1 are Different) Start Address: H'5FFFFF7 Bus Width: 8/16 Bit 7 6 5 4 3 2 1 0 -- -- -- -- NDR3 NDR2 NDR1 NDR0 Initial value 1 1 1 1 0 0 0 0 Read/Write -- -- -- -- R/W R/W R/W R/W Table A.72 NDRA Bit Functions Bit Bit Name Description 3-0 Next data 3-0 (NDR3- NDR0) Stores the next output data for TPC output group 0 Rev. 7.00 Jan 31, 2006 page 644 of 658 REJ09B0272-0700 Appendix A On-Chip Supporting Module Registers A.2.72 Next Data Register B (NDRB) TPC (When the Output Triggers of TPC Output Groups 2 and 3 are the Same) Start Address: H'5FFFFF4 Bus Width: 8/16 Bit 7 6 5 4 3 2 1 0 NDR15 NDR14 NDR13 NDR12 NDR11 NDR10 NDR9 NDR8 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Table A.73 NDRB Bit Functions Bit Bit Name Description 7-4 Next data 15-12 (NDR15- NDR12) Stores the next output data for TPC output group 3 3-0 Next data 11-8 (NDR11- NDR8) Stores the next output data for TPC output group 2 A.2.73 Next Data Register B (NDRB) TPC (When the Output Triggers of TPC Output Groups 2 and 3 are the Same) Start Address: H'5FFFFF6 Bus Width: 8/16 Module: TPC Bit 7 6 5 4 3 2 1 0 -- -- -- -- -- -- -- -- Initial value 1 1 1 1 1 1 1 1 Read/Write -- -- -- -- -- -- -- -- Table A.74 NDRB Bit Functions Bit Bit Name Description 7-0 Reserved bits Writing is invalid; always read as 1 Rev. 7.00 Jan 31, 2006 page 645 of 658 REJ09B0272-0700 Appendix A On-Chip Supporting Module Registers A.2.74 Next Data Register B (NDRB) TPC (When the Output Triggers of TPC Output Groups 2 and 3 are Different) Start Address: H'5FFFFF4 Bus Width: 8/16 Bit 7 6 5 4 3 2 1 0 NDR15 NDR14 NDR13 NDR12 -- -- -- -- Initial value 0 0 0 0 1 1 1 1 Read/Write R/W R/W R/W R/W -- -- -- -- Table A.75 NDRB Bit Functions Bit Bit Name Description 7-4 Next data 15-12 (NDR15- NDR12) Stores the next output data for TPC output group 3 A.2.75 Next Data Register B (NDRB) TPC (When the Output Triggers of TPC Output Groups 2 and 3 are Different) Start Address: H'5FFFFF6 Bus Width: 8/16 Bit 7 6 5 4 3 2 1 0 -- -- -- -- NDR11 NDR10 NDR9 NDR8 Initial value 1 1 1 1 0 0 0 0 Read/Write -- -- -- -- R/W R/W R/W R/W Table A.76 NDRB Bit Functions Bit Bit Name Description 3-0 Next data 11-8 (NDR11- NDR8) Stores the next output data for TPC output group 2 Rev. 7.00 Jan 31, 2006 page 646 of 658 REJ09B0272-0700 Appendix A On-Chip Supporting Module Registers A.3 Register Status in Reset and Power-Down States Table A.77 Register Status in Reset and Power-Down States Reset State Power-Down State Category Abbreviation Power On Manual Standby Sleep CPU R0-R15 Initialized Initialized Held Held Initialized Initialized Held Held Initialized Initialized Held Held Initialized Held Held Held Initialized Initialized Initialized Held SR GBR VBR MACH,MACL PR PC Interrupt controller (INTC) IPRA-IPRE ICR User break controller (UBC) BARH,BARL BAMRH,BAMRL BBR Bus state controller (BSC) BCR WCR1-WCR3 DCR RCR RTSCR RTCNT RTCOR PCR Direct memory access controller (DMAC) SAR0-SAR3 DAR0-DAR3 TCR0-TCR3 CHCR0- CHCR3 DMAOR Rev. 7.00 Jan 31, 2006 page 647 of 658 REJ09B0272-0700 Appendix A On-Chip Supporting Module Registers Reset State Category Abbreviation 16-bit integrated timer pulse TSTR unit (ITU) TSNC Power-Down State Power On Manual Standby Sleep Initialized Initialized Initialized Held Initialized Initialized Held Held Initialized Initialized Held Held TMDA, TMDB TCNT0-TCNT4 GRA0-GRA4, GRB0-GRB4 BRA3, BRA4. BRB3, BRB4 TCR0-TCR4 TIOR0-TIOR4 TIER0-TIER4 TSR0-TSR4 Programmable timing pattern controller (TPC) TPMR TPCR NDERA,NDERB NDRA, NDRB Watchdog timer (WDT) TCNT *1 TCSR 2 RSTCR* Serial communication interface (SCI) SMR Initialized Initialized Initialized Initialized BRR SCR TDR TSR Held SSR Initialized RDR RSR Rev. 7.00 Jan 31, 2006 page 648 of 658 REJ09B0272-0700 Held Held Appendix A On-Chip Supporting Module Registers Reset State Power-Down State Category Abbreviation Power On Manual Standby Sleep A/D converter ADDRA- ADDRD Initialized Initialized Initialized Held Initialized Held Held Held Initialized Held Held Held ADCSR ADCR Pin function controller (PFC) PAIOR,PBIOR PACR1,PACR2, PBCR1,PBCR2 CASCR Parallel I/O ports (I/O) Power-down-state related PADR,PBDR 3 3 3 PCDR * * * *3 SBYCR Initialized Initialized Held Held Notes: 1. Bits 7-5 (OVF, WT/IT, TME) are initialized, bits 2-0 (CKS2-CKS0) are held. 2. Not initialized in the case of a reset by the WDT. 3. Bits 15-8 are always undetermined, bits 7-0 always reflect the state of the corresponding pin. Rev. 7.00 Jan 31, 2006 page 649 of 658 REJ09B0272-0700 Appendix B Pin States Appendix B Pin States Table B.1 Pin State In Resets, Power-Down State, and Bus-Released State Pin State Reset Power-Down Category Pin Power-On Manual Bus Standby Sleep Released Clock CK O O H* O O System control RES I I I I I Interrupt 1 1 WDTOVF H H H* O O BREQ -- I Z I I BACK Z O Z O L NMI I I I I I IRQ7-IRQ0 -- I Z I I 1 IRQOUT -- O O* H O Address bus A21-A0 H O Z H Z Data bus AD15-AD0 Z Z Z Z Z DPH,DPL -- Z Z Z WAIT I I* Z I* I* CS7 -- O Z H Z CS6-CS0 Z O Z H Z RD H O Z H Z WRH (LBS),WRL (WR) H O Z H Z RAS -- O O* O Z CASH,CASL -- O O O Z AH -- O Z H Z Bus control Direct memory access DREQ0,DREQ1 controller (DMAC) DACK0,DACK1 16-bit integrated timer TIOCA0-TIOCA4 pulse unit (ITU) TIOCB0-TIOCB4 Timing pattern controller (TPC) 2 1 -- I Z Z O K* -- I K* -- I Z 2 2 I I 1 O O 1 I/O I/O 1 I/O I/O 1 K* TOCXA4, TOCXB4 -- I K* O O TCLKA-TCLKD I Z I I I 1 K* O O TP15-TP0 Rev. 7.00 Jan 31, 2006 page 650 of 658 REJ09B0272-0700 -- -- Appendix B Pin States Pin State Reset Power-Down Category Pin Power-On Manual Bus Standby Sleep Released Serial communication interface (SCI) TxD0-TxD1 -- Z K* O O RxD0,RxD1 -- I Z I I SCK0,SCK1 -- I Z I/O I/O AN7-AN0 Z Z Z I I ADTRG -- I Z A/D converter I/O ports 1 I I 1 I/O I/O 1 PA14, PA12, PA7-PA0 -- I/O K* PA15, PA13, PA11-PA8, PB15-PB0 Z I/O K* I/O I/O PC7-PC0 Z I Z I I --: One of the multiplexed pin functions is allocated, but the pin functions in the reset state are different. I: Input O: Output H: High L: Low Z: High impedance K: Input pins are high-impedance, output pins hold their state. Notes: 1. When the port high impedance bit (HIZ) in the standby control register (SBYCR) is set to 1, the output pins become high-impedance. 2. When the pin pull-up control bit (WPU) in the wait state control register (WCR3) is set to 1, the WAIT pin is pulled up, but if set to 0, it is not pulled up. Rev. 7.00 Jan 31, 2006 page 651 of 658 REJ09B0272-0700 Appendix B Pin States The following table shows the states of bus control pins and external bus pins in accesses of various address spaces. Table B.2 Pin States in Address Space Accesses On-Chip Peripheral Modules 16-Bit Space Pin Name On-Chip ROM Space On-Chip 8-Bit Space Upper RAM Space Byte Lower Byte Word CS7-CS0 High High High High High High RAS High High High High High High CASH High High High High High High CASL High High High High High High AH Low Low Low Low Low Low High High High High High High RD R W -- High High High High High R High High High High High High W -- High High High High High R High High High High High High W -- High High High High High A0/HBS A0 A0 A0 A0 A0 A0 A21-A1 Address Address Address Address Address Address AD15-AD8 High-Z High-Z High-Z High-Z High-Z High-Z AD7-AD0 High-Z High-Z High-Z High-Z High-Z High-Z DPH High-Z High-Z High-Z High-Z High-Z High-Z DPL High-Z High-Z High-Z High-Z High-Z High-Z WRH/LBS WRL/WR R: Read W: Write Rev. 7.00 Jan 31, 2006 page 652 of 658 REJ09B0272-0700 Appendix B Pin States Address/Data Multiplex I/O Space 16-Bit Space WRH, WRL, A0 System WR, HBS, LBS System 8-Bit Space Upper Byte Lower Byte Word Upper Byte Lower Byte Word CS7, CS5- CS0 High High High High High High High CS6 Low Low Low Low Low Low Low RAS High High High High High High High CASH High High High High High High High CASL High High High High High High High AH AH AH AH AH AH AH AH R Low Low Low Low Low Low Low W High High High High High High High R --* High High High High Low Low W --* Low High Low High Low Low R High High High High High High High W Low High Low Low Low Low Low A0/HBS A0 Low High Low Low High Low A21-A1 Address Address Address Address Address Address Address AD15-AD8 High-Z Address/ data Address Address/ data Address/ data Address Address/ data AD7-AD0 Address/ Address data Address/ data Address/ data Address Address/ data Address/ data Pin Name RD WRH/LBS WRL/WR R: Read W: Write AH: When addresses are output from AD15-AD0, an address hold signal is output. Note: * Cannot be used; available only for 16-bit space access. Rev. 7.00 Jan 31, 2006 page 653 of 658 REJ09B0272-0700 Appendix B Pin States DRAM Space 16-Bit Space 2-CAS System 2-WE System 8-Bit Space Upper Byte Lower Byte Word Upper Byte Lower Byte Word CS7-CS2, CS0 High High High High High High High CS1 Low -- -- -- Low Low Low RAS RAS RAS RAS RAS RAS RAS RAS CASH High CASH High CASH High High High CASL CAS High CASL CASL CASL CASL CASL AH Low Low Low Low Low Low Low R Low Low Low Low Low Low Low W High High High High High High High R High High High High High High High W High High High High Low High Low R High High High High High High High W Low Low Low Low High Low Low A0 A0 A0 A0 A0 A0 A0 A0 A21-A1 Address Address Address Address Address Address Address AD15-AD8 High-Z Data High-Z Data Data High-Z Data AD7-AD0 Data High-Z Data Data High-Z Data Data DPH High-Z Parity High-Z Parity Parity High-Z Parity DPL Parity High-Z Parity Parity High-Z Parity Parity Pin Name RD WRH WRL R: Read W: Write --: The CS1 pin is used as the CASH signal output pin. RAS: When a row address is output from A21-A0, an address strobe signal is output. CAS: When a column address is output from A21-A0, an address strobe signal is output. CASH: When a column address is output from A21-A0 during an upper byte access, an address strobe signal is output. CASL: When a column address is output from A21-A0 during a lower byte access, an address strobe signal is output. Parity: When a DRAM space parity check is selected with the parity check enable bits (PCHK1,PCHK0) in the parity control register (PCR), this pin is used as the parity pin. Rev. 7.00 Jan 31, 2006 page 654 of 658 REJ09B0272-0700 Appendix B Pin States External Memory Space 16-Bit Space WRH, WRL, A0 System WR, HBS, LBS System Pin Name 8-Bit Space Upper Byte Lower Byte Word Upper Byte Lower Byte Word CS7-CS0 Valid Valid Valid Valid Valid Valid Valid RAS High High High High High High High CASH High High High High High High High CASL High High High High High High High AH Low Low Low Low Low Low Low RD WRH/LBS WRL/WR R Low Low Low Low Low Low Low W High High High High High High High R --* High High High High Low Low W --* Low High Low High Low Low R High High High High High High High Low High Low Low Low Low Low A0/HBS W A0 A0 A0 A0 Low High Low A21-A1 Address Address Address Address Address Address Address AD15-AD8 High-Z Data High-Z Data Data High-Z Data AD7-AD0 Data High-Z Data Data High-Z Data Data DPH High-Z Parity High-Z Parity Parity High-Z Parity DPL Parity High-Z Parity Parity High-Z Parity Parity R: Read W: Write Valid: Chip select signal for the area accessed is low; other chip select signals are high. Parity: When an area 2 parity check is selected with the parity check enable bits (PCHK1, PCHK0) in the parity control register (PCR), this pin is used as the parity pin. Note: * Cannot be used; available only for 16-bit space access. Rev. 7.00 Jan 31, 2006 page 655 of 658 REJ09B0272-0700 Appendix C Package Dimensions Appendix C Package Dimensions Figure C.1 and figure C.2 show the package dimensions of the SH microcomputer. JEITA Package Code P-QFP112-20x20-0.65 RENESAS Code PRQP0112JA-A Previous Code FP-112/FP-112V MASS[Typ.] 2.4g HD *1 D 84 NOTE) 1. DIMENSIONS"*1"AND"*2" DO NOT INCLUDE MOLD FLASH 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET. 57 85 56 bp c c1 HE *2 E b1 Reference Symbol ZE Terminal cross section 29 112 28 F c A ZD A2 1 A1 L L1 Detail F e *3 y bp x M Figure C.1 Package Dimensions (PRQP0112JA-A) Rev. 7.00 Jan 31, 2006 page 656 of 658 REJ09B0272-0700 D E A2 HD HE A AA bp b1 c c1 e x y ZD ZE L L1 Dimension in Millimeters Min Nom Max 20 20 2.70 22.9 23.2 23.5 22.9 23.2 23.5 3.05 0.00 0.10 0.25 0.24 0.32 0.40 0.30 0.12 0.17 0.22 0.15 0 8 0.65 0.13 0.10 1.23 1.23 0.5 0.8 1.1 1.6 Appendix C Package Dimensions JEITA Package Code P-TQFP120-14x14-0.40 RENESAS Code PTQP0120LA-A Previous Code TFP-120/TFP-120V MASS[Typ.] 0.5g HD *1 D 90 61 91 NOTE) 1. DIMENSIONS"*1"AND"*2" DO NOT INCLUDE MOLD FLASH 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET. 60 bp c c1 HE *2 E b1 Reference Symbol ZE Terminal cross section ZD c 30 A 1 A2 31 120 Index mark F A1 L L1 Detail F e *3 y bp x M D E A2 HD HE A A1 bp b1 c c1 e x y ZD ZE L L1 Dimension in Millimeters Min Nom Max 14 14 1.00 15.8 16.0 16.2 15.8 16.0 16.2 1.20 0.00 0.10 0.20 0.12 0.17 0.22 0.15 0.12 0.17 0.22 0.15 0 8 0.4 0.07 0.10 1.20 1.20 0.4 0.5 0.6 1.0 Figure C.2 Package Dimensions (PTQP0120LA-A) Rev. 7.00 Jan 31, 2006 page 657 of 658 REJ09B0272-0700 Appendix C Package Dimensions Rev. 7.00 Jan 31, 2006 page 658 of 658 REJ09B0272-0700 Renesas 32-Bit RISC Microcomputer Hardware Manual SH7032, SH7034 Publication Date: 1st Edition, September 1994 Rev.7.00, January 31, 2006 Published by: Sales Strategic Planning Div. Renesas Technology Corp. Edited by: Customer Support Department Global Strategic Communication Div. Renesas Solutions Corp. (c) 2006. Renesas Technology Corp., All rights reserved. Printed in Japan. Sales Strategic Planning Div. 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Bhd Unit 906, Block B, Menara Amcorp, Amcorp Trade Centre, No.18, Jalan Persiaran Barat, 46050 Petaling Jaya, Selangor Darul Ehsan, Malaysia Tel: <603> 7955-9390, Fax: <603> 7955-9510 Colophon 5.0 SH7032, SH7034 Hardware Manual 1753, Shimonumabe, Nakahara-ku, Kawasaki-shi, Kanagawa 211-8668 Japan REJ09B0272-0700