5962D9960602QUX - Aeroflex Incorporated

FEATURES

100ns (5 volt supply) maximum address access time

Asynchronous operation for compatibility with industry-

standard 512K x 8 SRAMs

TTL compatible inputs and output levels, three-state

bidirectional data bus

Typical radiation performance

- Total dose: 30krad(Si)

- 30krad(Si) to 300krad(Si), depending on orbit, using

Aeroflex UTMC patented shielded package

- SEL Immune >80 MeV-cm2/mg

- LETTH(0.25) = 5MeV-cm2/mg

- Saturated Cross Section (cm2) per bit, ~1.0E-7

- 1.5E-8 errors/bit-day, Adams 90% geosynchrono us

heavy ion

Packaging options:

- 32-lead ceramic flatpack (weight 2.5-2.6 grams)

Standard Microcircuit Drawing 5962-99606

- QML T and Q compliant

INTRODUCTION

The QCOTSTM UT7Q512 Quantified Commercial Off-the-

Shelf product is a high-performance CMOS static RAM

organized as 524,288 words by 8 bits. Easy memory expansion

is provided by an active LOW Chip Enable (E), an active LOW

Output Enable (G), and three-state drivers. This device has a

power-down feature that reduces power consumption by more

than 90% when deselected.

Writing to the device is accomplished by taking the Chip Enable

One (E) input LOW and the Write Enable (W) input LOW . Data

on the eight I/O pins (DQ0 through DQ7) is then written into the

location specified on the address pins (A0 through A18). Reading

from the device is accomplished by taking Chip Enable One (E)

and Output Enable (G) LOW while forci ng Write Enable (W)

HIGH. Under these conditions, the contents of the memory

location specified by the address pins will appear on the eight I/

O pins.

The eight input/output pins (DQ0 through DQ7) are placed in a

high impedance state when the device is deselected (E, HIGH),

the outputs are disabled (G HIGH), or during a write operation

(E LOW and W LOW).

Standard Products

QCOTSTM UT7Q512 512K x 8 SRAM

Data Sheet

August 19, 2004

Figure 1. UT7Q512 SRAM Block Diagram

Memory Array

1024 Rows

512x8 Columns

Pre-Charge Circuit

Clk. Gen.

Row Select

I/O Circuit

Column Select

Data

Control

CLK

Gen.

A10

A11

A12

A13

A14

A15

A16

A17

A18

- DQ

PIN NAMES DEVICE OPERATION

The UT7Q512 has three control inputs called Enable 1 (E), Write

Enable (W), and Output Enable (G); 19 address inputs, A(18:0);

and eight bidirectional data lines, DQ(7:0). The E Device Enable

controls device selection, active, and standby modes. Asserting

E enables the device, causes IDD to rise to its active value, and

decodes the 19 address inputs to select one of 524,288 words in

the memory. W controls read and write operations. During a read

cycle, G must be asserted to enable the outputs.

Table 1. Device Operation Truth Table

Notes:

1. “X” is defined as a “don’t care” condition.

2. Device active; outputs disabled.

READ CYCLE

A combination of W greater than VIH (min), G and E less than

VIL (max) defines a read cycle. Read access time is measured

from the latter of Device Enable, Output Enable, or valid address

to valid data output.

SRAM read Cycle 1, the Address Access in figure 3a, is initiated

by a change in address inputs while the chip is enabled with G

asserted and W deasserted. Valid data appears on data outputs

DQ(7:0) after the specified tAVQV is satisfied. Outputs remain

active throughout the entire cycle. As long as Device Enable and

Output Enable are active, the address inputs may change at a

rate equal to the minimum read cycle time (tAVAV).

SRAM read Cycle 2, the Chip Enable-Controlled Access in

figure 3b, is initiated by E going active while G remains asserted,

W remains deasserted, and the addresses remain stable for the

entire cycle. After the specified tETQV is satisfied, the eight-bit

word addressed by A(18:0) is accessed and appears at the data

outputs DQ(7:0).

SRAM read Cycle 3, the Output Enable-Controlled Access in

figure 3c, is initiated by G going active while E is asserted, W

is deasserted, and the addresses are stable. Read access time is

tGLQV unless tAVQV or tETQV have not been satisfied.

A(18:0) Address

DQ(7:0) Data Inp ut/Output

EChip Enable

WWrite Enable

GOutput Enable

VDD Power

VSS Ground

136

235

334

433

532

631

730

829

928

10 27

11 26

12 25

13 24

14 23

15 22

16 21

17 20

18 19

Figure 2a. UT7Q512 100ns SRAM Shielded

Package Pinout (36)

A15

A17

A13

A11

VSS

VDD

A10

DQ7

DQ6

DQ5

DQ4

A18

A16

A14

A12

VDD

VSS

DQ0

DQ1

DQ2

DQ3

132

231

330

429

528

627

726

825

924

10 23

11 22

12 21

13 20

14 19

15 18

16 17

Figure 2b. UT7Q512 100ns SRAM

Package Pinout (32)

VDD

A15

A17

A13

A11

A10

DQ7

DQ6

DQ5

DQ4

DQ3

A18

A16

A14

A12

DQ0

DQ1

DQ2

VSS

G W E I/O Mode Mode

X1X 1 3-state Standby

X 0 0 Data in Write

1103-state Read2

010Data out Read

WRITE CYCLE

A combination of W less than VIL(max) and E less than

VIL(max) defines a write cycle. The state of G is a “don’t care”

for a write cycle. The outputs are placed in the high-impedance

state when either G is greater than VIH(min), or when W is less

than VIL(max).

Write Cycle 1, the Write Enable-Controlled Access in figure 4a,

is defined by a write terminat ed by W going high, with E still

active. The write pulse width is defined by tWLWH when the write

is initiated by W, and by tETWH when the write is initiated by E.

Unless the outputs have been previously placed in the high-

impedance state by G, the user must wait tWLQZ before applying

data to the nine bidirectional pins DQ (7: 0) to avoid bus

contention.

W rite Cycle 2, the Chip Enable-Controlled Access in figure 4b,

is defined by a write terminated by the latter of E going inactive.

The write pulse width is defined by tWLEF when the write is

initiated by W, and by tETEF when the write is initiated by the E

going active. For the W initiated write, unless the outputs have

been previously placed in the high-impedance state

by G, the user must wait tWLQZ before applying data to the eight

bidirectional pins DQ(7:0) to avoid bus contention.

TYPICAL RADIATION HARDNESS

Table 2. Typical Radiation Hardness

Design Specifications1

Notes:

1. The SRAM will not latchup during radiation exposure under recommended

operating conditions.

2. 90% worst case particle environment, Geosynchronous orbit, 100 mils of

Aluminum.

Total Dose 30 krad(Si) nominal

Heavy Ion

Error Rate21.5E-7 Errors/Bit-Day

ABSOLUTE MAXIMUM RATINGS1

(Referenced to VSS)

Notes:

1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, and functional operatio n of the device

at these or any other conditions beyond limits indicated in the operational sections of this specification is not recommended. Exposure to absolute maximum rating

conditions for extended periods may affect device reliability and performance.

2. Maximum junction temperature may be increased to +175°C during burn-in and steady-static life.

3. Test per MIL-STD-883, Me thod 1012.

RECOMMENDED OPERATING CONDITIONS

SYMBOL PARAMETER LIMITS

VDD DC supply voltage -0.5 to 7.0V

VI/O Voltage on any pin -0.5 to 7.0V

TSTG Storage temperature -65 to +150°C

PDMaximum power dissipation 1.0W

TJMaximum junctio n temperature2+150°C

ΘJC Thermal resistance, junction-to-case310°C/W

IIDC input current ±10 mA

SYMBOL PARAMETER LIMITS

VDD Positive supply voltage 4.5 to 5.5V

TCCase temperature range -55 to +125°C

VIN DC input voltage 0V to VDD

DC ELECTRICAL CHARACTERISTICS (Pre/Post-Radiation)*

(VDD = 5.0V±10%) (-55°C to +125°C)

Notes:

* Post-radiation pe rfo rm ance guaranteed at 25°C per MIL-STD- 883 Method 1019.

1. Measured only for initial qualification and after process or design changes that could affect input/output capacitance.

2. Supplied as a design limit but not guaranteed or tested.

3. Not more than one output may be shorted at a time for maximum duration of one second.

SYMBOL PARAMETER CONDITION MIN MAX UNIT

VIH High-level input voltage 2.2 V

VIL Low-level input vo ltage .8 V

VOL Low-level output voltage IOL = 2.1mA,VDD =4.5V 0.4 V

VOH High-level output voltag e IOH = -1mA,VDD =4.5V 2.4 V

CIN1Input capacitance ƒ = 1MHz @ 0V 10 pF

CIO1Bidirectional I/O capacitance ƒ = 1MHz @ 0V 10 pF

IIN Input leakage current VSS < VIN < VDD , VDD = VDD (max) -2 2µA

IOZ Three-state output leakage current 0V < VO < VDD

VDD = VDD (max)

G = VDD (max)

-2 2µA

IOS2, 3 Short-circuit output current 0V <VO <VDD -80 80 mA

IDD(OP) Supply current operating

@ 1MHz Inputs: VIL = VSS + 0.8V,

VIH = 2.2V

IOUT = 0mA

VDD = VDD (max)

50 mA

IDD1(OP) Supply current operating

@10MHz Inputs: VIL = VSS + 0.8V,

VIH = 2.2V

IOUT = 0mA

VDD = VDD (max)

100 mA

IDD2(SB) Nominal standby supply current

@0MHz Inputs: VIL = VSS

IOUT = 0mA

E = VDD - 0.5

VDD = VDD (max)

VIH = VDD - 0.5V

µA

-55°C and

25°C

+125°C

AC CHARACTERISTICS READ CYCLE (Pre/Post-Radiation)*

(VDD = 5.0V±10%) (-55°C to +125°C)

Notes: * Post-radiation performance guaranteed at 25°C per MIL-STD-883 Method 1019.

1. Functional test.

2. Three-state is defined as a 500mV change from steady-state output voltage (see Figure 3).

3. The ET (enable true) notation refers to the falling edge of E. SEU immunity does not affect the read parameters.

4. The EF (enable false) notation refers to the ris ing edge of E. SEU immunity does not affect the read parameters.

SYMBOL PARAMETER MIN MAX UNIT

tAVAV1Read cycle time 100 ns

tAVQV Read access time 100 ns

tAXQX2Output hold time 10 ns

tGLQX2G-controlled Output Enable time 5 ns

tGLQV G-controlled Output Enable time (Read Cycle 3) 50 ns

tGHQZ2G-controlled output th ree-state time 30 ns

tETQX2,3 E-controlled Output Enab le time 10 ns

tETQV3E-controlled access time 100 ns

tEFQZ1,2,4 E-controlled output three-state time 30 ns

{

{}

}

VLOAD + 500mV

VLOAD - 500mV

VLOAD

VH - 500mV

VL + 500mV

Active to High Z LevelsHigh Z to Active Levels

Figure 3. 5-Volt SRAM Loading

Assumptions:

1. E and G < VIL (max) and W > VIH (min)

A(18:0)

DQ(7:0)

Figure 4a. SRAM Read Cycle 1: Address Access

tAVAV

tAVQV

tAXQX

Previous Valid Data Valid Data

Assumptions:

1. G < VIL (max) and W > VIH (min)

A(18:0)

Figure 4b. SRAM Read Cycle 2: Chip Enable - Controlled Access

DATA VALID

tEFQZ

tETQV

tETQX

DQ(7:0)

Figure 4c. SRAM Read Cycle 3: Output Enable - Controlled Access

(18:0)

Q(7:0)

tGHQZ

ssumptions:

. E< VIL (max) and W > VIH (min)

tGLQV

tGLQX

tAVQV

DATA VALID

AC CHARACTERISTICS WRITE CYCLE (Pre/Post-Radiation)*

(VDD = 5.0V±10%) (-55°C to +125°C)

Notes:

* Post-radiation pe rfo rm ance guaranteed at 25°C per MIL-STD- 883 Method 1019

1. Functional test performed with outputs disabled (G high).

2. Three-state is defined as 500mV change from steady-state output voltage (see Figure 3).

SYMBOL PARAMETER MIN MAX UNIT

tAVAV1Write cycle time 100 ns

tETWH Device Enable to end of write 80 ns

tAVET Address setup time for write (E - controlled) 0 ns

tAVWL Address setup time for write (W - controlled) 0 ns

tWLWH Write pulse width 60 ns

tWHAX Address hold time for write (W - controlled) 0 ns

tEFAX Address hold time for Device Enable (E - controlled) 0 ns

tWLQZ2W - controlled three-state time 30 ns

tWHQX2W - controlled Output Enable time 5 ns

tETEF Device Enable pulse width (E - controlled) 80 ns

tDVWH Data setup time 40 ns

tWHDX Data hold time 0 ns

tWLEF Device Enable controlled write pulse width 80 ns

tDVEF Data setup time 40 ns

tEFDX Data hold time 0 ns

tAVWH Address valid to end of wri t e 80 ns

tWHWL1Write disable time 5 ns

Assumptions:

1. G < VIL (max). If G > VIH (min) then Q(7:0) will be

in three-state for the entire cycle.

2. G high for tAVAV cycle.

tAVWL

Figure 5a. SRAM Write Cycle 1: Write Enable - Controlled Access

A(18:0)

Q(7:0)

tAVAV2

D(7:0) APPLIED DATA

tDVWH tWHDX

tETWH

tWLWH tWHAX

tWHQX

tWLQZ

tAVWH

tWHWL

tEFDX

Assumptions & Notes:

1. G < VIL (max). If G > VIH (min) then Q(7:0) will be in three-state for the entire cycle.

2. Either E scenario above can occur.

3. G high for tAVAV cycle.

A(18:0)

Figure 5b. SRAM Write Cycle 2: Chip Enable - Controlled Access

D(7:0) APPLIED DATA

Q(7:0) tWLQZ

tETEF

tWLEF

tDVEF

tAVAV3

tAVET

tETEF

tEFAX

Notes:

1. 50pF including scope probe and test socket capacitance.

2. Measurement of data output occurs at the low to high or high to low transition mid-point

(i.e., CMOS input = VDD/2).

90%

Figure 6. AC Test Loads and Input Waveforms

Input Pulses

10%

< 5ns < 5ns

VLOAD = 1.75V

300 ohms

50pF

CMOS

0.5V

VDD-0.05V 90%

10%

DATA RETENTION CHARACTERISTICS (Pre/Post-I rradiation)

(TC = 25°C, 1 Sec Data Retention Test)

Notes:

1. E = VSS, all other inputs = VDR or VSS.

2. Not guaranteed or tested.

DATA RETENTION CHARACTERISTICS (Pre/Post-I rradiation)

(TC = 25°C, 10 Second Data Retention Test)

Notes:

1. Performed at VDD (min) and VDD (max).

2. E = VSS, all other inputs = VDR or VSS.

3. Not guaranteed or tested.

VDD

DATA RETENTION MODE

50% VDR > 4.5V

Figure 7. Low VDD Data Retention Waveform (100ns)

tEFR

50%

SYMBOL PARAMETER MINIMUM MAXIMUM UNIT

VDR VDD for data retention 4.5 -- V

IDDR 1 Data retention current -- .4 mA

tEFR1,2 Chip deselect to data retention time 0 ns

tR1,2 Operation recovery time tAVAV ns

SYMBOL PARAMETER MINIMUM MAXIMUM UNIT

VDD1VDD for data retention 4.5 5.5 V

tEFR2, 3 Chip select to data retention time 0 ns

tR2, 3 Operation recovery time tAVAV ns

PACKAGING

Figure 8. 32-pin Ceramic FLATPACK package

1. All exposed metalized areas are gold plated over electroplated nickel per MIL-PRF-38535.

2. The lid is electrically connected to VSS.

3. Lead finishes are in accordance to MIL-PRF-38535.

4. Lead position and coplanarity are not measured.

5. ID mark is vendor option.

6. With solder increase maximum by 0.003".

7. Weight 2.5-2.6 grams.

ORDERING INFORMATION

512K x 8 SRAM:

- = 100ns access time, 5V operation

Package Type:

(U) = 32-lead ceramic flatpack package (bottom brazed)

Screening:

(P) = Prototype flow

Lead Finish:

(A) = Hot solder dipped

(X) = Factory option (gold or solder)

Notes:

1. Lead finish (A,C, or X) must be specified.

2. If an “X” is specified when ordering, then the part marking will match the lead finish and will be either “A” (solder) or “C” (gold).

3. Prototype flow per UTMC Manufactur ing Flows Document. Tested at 25°C only. Lead finish is GOLD ONLY. Radiation neither

tested nor guaranteed.

4. Military Temperature Range flow per UTMC Manufacturing Flows Document. Devices are tested at -55°C, room temp, and +125°C.

Radiation neither tested nor guaranteed.

5. Extended Industrial Temperature Range flow per UTMC Manufacturing Flows Document. Devices are tested at -40°C to +125°C.

Radiation neither tested nor guaranteed. Gold Lead Finish Only.

UT7Q512 - * * * *

Aeroflex UTMC Core Part Number

Screening:

(P) = Prototype flow

(W) = Extended Industrial Temperature Range Flow (-40oC to +125oC)

512K x 8 SRAM: SMD

5962 - 99606 ** *

Federal Stock Class Designator: No Options

Total Dose

(D) = 1E4 (10krad(Si))

(P) = 3E4 (30krad(Si)), Contact Factory

Drawing Number: 99606

Device Type

01 = 100ns access time, 5.0 volt operation, Mil-Temp

02 = 100ns access time, 5.0 volt operation, Extended Industrial Temp (-40oC to +125oC)

Class Designator:

(T) = QML Class T

(Q) = QML Class Q

Case Outline:

(U) = 32-lead ceramic flatpack package (bottom-brazed)

Lead Finish:

(A) = Hot solder dipped

(X) = Factory Option (gold or solder)

Notes:

1.Lead finish (A,C, or X) must be specifi ed.

2.If an “X” is specified when ordering, part marking will match the lead finish and will be either “A” (solder) or “C” (gold).

3.Total dose radiation must be specified when ordering.

NOTES

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reserves the right to make changes to any products and

services herein at any time without notice. Consult Aeroflex

or an authorized sales representative to verify that the

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