54F373,74F373
54F373 Octal Transparent Latch with TRI-STATE(RM) Outputs
Literature Number: SNOS189A
TL/F/9523
54F/74F373 Octal Transparent Latch with TRI-STATE Outputs
May 1995
54F/74F373
Octal Transparent Latch with TRI-STATEÉOutputs
General Description
The ’F373 consists of eight latches with TRI-STATE outputs
for bus organized system applications. The flip-flops appear
transparent to the data when Latch Enable (LE) is HIGH.
When LE is LOW, the data that meets the setup times is
latched. Data appears on the bus when the Output Enable
(OE) is LOW. When OE is HIGH the bus output is in the high
impedance state.
Features
YEight latches in a single package
YTRI-STATE outputs for bus interfacing
YGuaranteed 4000V minimum ESD protection
Commercial Military Package Package Description
Number
74F373PC N20A 20-Lead (0.300×Wide) Molded Dual-In-Line
54F373DM (QB) J20A 20-Lead Ceramic Dual-In-Line
74F373SC (Note 1) M20B 20-Lead (0.300×Wide) Molded Small Outline, JEDEC
74F373SJ (Note 1) M20D 20-Lead (0.300×Wide) Molded Small Outline, EIAJ
74F373MSA (Note 1) MSA20 20-Lead Molded Shrink Small Outline, EIAJ Type II
54F373FM (QB) W20A 20-Lead Cerpack
54F373LM (QB) E20A 20-Lead Ceramic Leadless Chip Carrier, Type C
Note 1: Devices also available in 13×reel. Use suffix eSCX, SJX, and MSAX.
Logic Symbols Connection Diagrams
IEEE/IEC
TL/F/95234
TL/F/95231
Pin Assignment
for DIP, SOIC, SSOP and Flatpak
TL/F/95232
Pin Assignment
for LCC
TL/F/95233
TRI-STATEÉis a registered trademark of National Semiconductor Corporation.
C1995 National Semiconductor Corporation RRD-B30M75/Printed in U. S. A.
Obsolete
Unit Loading/Fan Out
54F/74F
Pin Names Description U.L. Input IIH/IIL
HIGH/LOW Output IOH/IOL
D0–D7Data Inputs 1.0/1.0 20 mA/b0.6 mA
LE Latch Enable Input (Active HIGH) 1.0/1.0 20 mA/b0.6 mA
OE Output Enable Input (Active LOW) 1.0/1.0 20 mA/b0.6 mA
O0–O7TRI-STATE Latch Outputs 150/40 (33.3) b3 mA/24 mA (20 mA)
Functional Description
The ’F373 contains eight D-type latches with TRI-STATE
output buffers. When the Latch Enable (LE) input is HIGH,
data on the Dninputs enters the latches. In this condition
the latches are transparent, i.e., a latch output will change
state each time its D input changes. When LE is LOW, the
latches store the information that was present on the D in-
puts a setup time preceding the HIGH-to-LOW transition of
LE. The TRI-STATE buffers are controlled by the Output
Enable (OE) input. When OE is LOW, the buffers are in the
bi-state mode. When OE is HIGH the buffers are in the high
impedance mode but this does not interfere with entering
new data into the latches.
Truth Table
Inputs Output
LE OE DnOn
HLH H
HLL L
LLXO
n
(no change)
XHX Z
H
e
HIGH Voltage Level
LeLOW Voltage Level
XeImmaterial
ZeHigh Impedance State
Logic Diagram
TL/F/95235
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
2
Obsolete
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Storage Temperature b65§Ctoa
150§C
Ambient Temperature under Bias b55§Ctoa
125§C
Junction Temperature under Bias b55§Ctoa
175§C
Plastic b55§Ctoa
150§C
VCC Pin Potential to
Ground Pin b0.5V to a7.0V
Input Voltage (Note 2) b0.5V to a7.0V
Input Current (Note 2) b30 mA to a5.0 mA
Note 1: Absolute maximum ratings are values beyond which the device may
be damaged or have its useful life impaired. Functional operation under
these conditions is not implied.
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
Voltage Applied to Output
in HIGH State (with VCC e0V)
Standard Output b0.5V to VCC
TRI-STATE Output b0.5V to a5.5V
Current Applied to Output
in LOW State (Max) twice the rated IOL (mA)
ESD Last Passing Voltage (Min) 4000V
Recommended Operating
Conditions
Free Air Ambient Temperature
Military b55§Ctoa
125§C
Commercial 0§Ctoa
70§C
Supply Voltage
Military a4.5V to a5.5V
Commercial a4.5V to a5.5V
DC Electrical Characteristics
Symbol Parameter 54F/74F Units VCC Conditions
Min Typ Max
VIH Input HIGH Voltage 2.0 V Recognized as a HIGH Signal
VIL Input LOW Voltage 0.8 V Recognized as a LOW Signal
VCD Input Clamp Diode Voltage b1.2 V Min IIN eb
18 mA
VOH Output HIGH 54F 10% VCC 2.5 IOH eb
1mA
Voltage 54F 10% VCC 2.4 IOH eb
3mA
74F 10% VCC 2.5 V Min IOH eb
1mA
74F 10% VCC 2.4 IOH eb
3mA
74F 5% VCC 2.7 IOH eb
1mA
74F 5% VCC 2.7 IOH eb
3mA
V
OL Output LOW 54F 10% VCC 0.5 V Min IOL e20 mA
Voltage 74F 10% VCC 0.5 IOL e24 mA
IIH Input HIGH Current 54F 20.0
mA Max VIN e2.7V
74F 5.0
IBVI Input HIGH Current 54F 100
mA Max VIN e7.0V
Breakdown Test 74F 7.0
ICEX Output HIGH 54F 250
mA Max VOUT eVCC
Leakage Current 74F 50
VID Input Leakage 74F 4.75 V 0.0 IID e1.9 mA
Test All Other Pins Grounded
IOD Output Leakage 74F 3.75 mA 0.0 VIOD e150 mV
Circuit Current All Other Pins Grounded
IIL Input LOW Current b0.6 mA Max VIN e0.5V
IOZH Output Leakage Current 50 mA Max VOUT e2.7V
IOZL Output Leakage Current b50 mA Max VOUT e0.5V
IOS Output Short-Circuit Current b60 b150 mA Max VOUT e0V
IZZ Bus Drainage Test 500 mA 0.0V VOUT e5.25V
ICCZ Power Supply Current 38 55 mA Max VOeHIGH Z
3
Obsolete
AC Electrical Characteristics
74F 54F 74F
TAea
25§CTA,V
CC eMil TA,V
CC eCom
Symbol Parameter VCC ea
5.0V CLe50 pF CLe50 pF Units
CLe50 pF
Min Typ Max Min Max Min Max
tPLH Propagation Delay 3.0 5.3 7.0 3.0 8.5 3.0 8.0 ns
tPHL Dnto On2.0 3.7 5.0 2.0 7.0 2.0 6.0
tPLH Propagation Delay 5.0 9.0 11.5 5.0 15.0 5.0 13.0 ns
tPHL LE to On3.0 5.2 7.0 3.0 8.5 3.0 8.0
tPZH Output Enable Time 2.0 5.0 11.0 2.0 13.5 2.0 12.0 ns
tPZL 2.0 5.6 7.5 2.0 10.0 2.0 8.5
tPHZ Output Disable Time 1.5 4.5 6.5 1.5 10.0 1.5 7.5 ns
tPLZ 1.5 3.8 5.0 1.5 7.0 1.5 6.0
AC Operating Requirements
74F 54F 74F
Symbol Parameter TAea
25§CTA,V
CC eMil TA,V
CC eCom Units
VCC ea
5.0V
Min Max Min Max Min Max
ts(H) Setup Time, HIGH or LOW 2.0 2.0 2.0
ts(L) Dnto LE 2.0 2.0 2.0 ns
th(H) Hold Time, HIGH or LOW 3.0 3.0 3.0
th(L) Dnto LE 3.0 4.0 3.0
tw(H) LE Pulse Width, HIGH 6.0 6.0 6.0 ns
Ordering Information
The device number is used to form part of a simplified purchasing code where the package type and temperature range are
defined as follows:
74F 373 S C X
Temperature Range Family Special Variations
74FeCommercial QB eMilitary grade device with
54FeMilitary environmental and burn-in
processing
Device Type XeDevices shipped in 13×reel
Package Code Temperature Range
PePlastic DIP CeCommercial (0§Ctoa
70§C)
DeCeramic DIP MeMilitary (b55§Ctoa
125§C)
FeFlatpak NOTE:
LeLeadless Chip Carrier (LCC) Not required for MSA package code
SeSmall Outline SOIC JEDEC
SJ eSmall Outline SOIC EIAJ
MSA eShrink Small Outline (EIAJ SSOP)
4
Obsolete
Physical Dimensions inches (millimeters)
20-Lead Ceramic Leadless Chip Carrier (L)
NS Package Number E20A
20-Lead Ceramic Dual-In-Line Package (D)
NS Package Number J20A
5
Obsolete
Physical Dimensions inches (millimeters) (Continued)
20-Lead (0.300×Wide) Molded Small Outline Package, JEDEC (S)
NS Package Number M20B
20-Lead (0.300×Wide) Small Outline Package, EIAJ (SJ)
NS Package Number M20D
6
Obsolete
Physical Dimensions inches (millimeters) (Continued)
20-Lead Molded Shrink Small Outline Package, EIAJ, Type II (MSA)
NS Package Number MSA20
20-Lead (0.300×Wide) Molded Dual-In-Line Package (P)
NS Package Number N20A
7
Obsolete
54F/74F373 Octal Transparent Latch with TRI-STATE Outputs
Physical Dimensions inches (millimeters) (Continued)
20-Lead Ceramic Flatpak (F)
NS Package Number W20A
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Obsolete
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