AQJ119VJ - PANASONIC - Datasheet.Directory

25AA080C/D, 25LC080C/D

Device Selection Table

Features

• Max. Clock 10 MHz

• Low-Power CMOS Technology:

- Max. write current: 5 mA at 5.5V

- Read current: 5 mA at 5.5V, 10 MHz

- Standby current: 5 μA at 5.5V

• 1024 x 8-bit Organization

• 16 Byte Page (‘C’ version devices)

• 32 Byte Page (‘D’ version devices)

• Self-Timed Erase and Write Cycles (5 ms max.)

• Block Write Protection:

- Protect none, 1/4, 1/2 or all of array

• Built-In Write Protection:

- Power-on/off data protection circuitry

- Write enable latch

- Write-protect pin

• Seque nti al Read

• High Reliability:

- Endurance: > 1M erase/write cycles

- Data retention: > 200 years

- ESD protection: > 4000V

• Pb-Free and RoHS Compliant

• Temperature Ranges Supported:

Description

The Microchip Technology Inc. 25AA080C/D,

25LC080C/D (25XX080C/D*) are 8 Kbit Serial

Electrically Erasable PROMs. The memory is accessed

via a simple Serial Peripheral Interface (SPI)

compatible serial bus. The bus signals required are a

clock input (SCK) plus separate data in (SI) and data

out (SO) lines. Access to the device is controlled

through a Chip Select (CS) input.

Communication to the device can be paused via the

hold pin (HOLD). While the device is paused, transi-

tions on its inputs will be ignored, with the exception of

Chip Select, allowing the host to service higher priority

interrupts.

The 25XX080C/D is available in standard packages

including 8-lead PDIP and SOIC, and advanced

packaging including 8-lead MSOP, TSSOP, and 2x3

TDFN. All packages are Pb-free and RoHS compliant.

Package Types (not to scale)

Part Number VCC Range Page Size Temp. Ranges Packages

25LC080C 2.5-5.5V 16 Byte I, E P, SN, ST, MS, MN

25AA080C 1.8-5.5V 16 Byte I P, SN, ST, MS, MN

25LC080D 2.5-5.5V 32 Byte I, E P, SN, ST, MS, MN

25AA080D 1.8-5.5V 32 Byte I P, SN, ST, MS, MN

- Industrial (I): -40°Cto +85°C

- Automotive (E): -40°C to +125°C

HOLD

SCK

PDIP/SOIC

(P, SN)

TSSOP/MSOP

HOLD

SCK

(ST, MS)

TDFN

VSS

HOLD

SCK

1VCC

(MN)

8K SPI Bus Serial EEPROM

*25XX080C/D is used in this document as a generic part

number for the 25AA080C/D, 25LC080C/D.

25XX080C/D

1.0 ELECTRICAL CHARAC TERISTICS

Absolute Maximum Ratings (†)

VCC.............................................................................................................................................................................6.5V

All inputs and outputs w.r.t. VSS ......................................................................................................... -0.6V to VCC +1.0V

Storage temperature .................................................................................................................................-65°C to 150°C

Ambient temperature under bias...............................................................................................................-40°C to 125°C

ESD protection on all pins..........................................................................................................................................4 kV

TABLE 1-1: DC CHARACTERISTICS

† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the

device . This i s a stres s ratin g only and functio nal operati on of the devic e at thos e or any other co nditio ns abov e thos e

indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for an

extended period of time may affect device reliability.

DC CHARACTERISTICS Industrial (I): TA = -40°C to +85°C VCC = 1.8V to 5.5V

Automotive (E): TA = -40°C to +125°C VCC = 2.5V to 5.5V

Param.

No. Sym. Characteristic Min. Max. Units Test Conditions

D001 VIH1High-level input

voltage 0.7 VCC VCC+1 V —

D002 VIL1Low-level input

voltage -0.3 0.3 VCC VVCC ≥ 2.7V

D003 VIL2-0.3 0.2 VCC VVCC < 2.7V

D004 VOL1Low-level output

voltage —0.4VIOL = 2.1 mA

D005 VOL2—0.2VIOL = 1.0 mA, VCC < 2.5V

D006 VOH High-level output

voltage VCC-0.5 — V IOH = -400 μA

D007 ILI Input leakage current ±1 μACS = VCC, VIN = VSS OR VCC

D008 ILO Output lea kage

current ±1 μACS = VCC, VOUT = VSS OR VCC

D009 CINT Intern al Cap acit ance

(all inputs and

outputs)

—7pFTA = 25°C, CLK = 1.0 MHz,

VCC = 5.0V (Note)

D010 ICC Read

Operati ng Curren t

—

—5

2.5

VCC = 5.5V; FCLK = 10.0 MHz;

SO = Open

VCC = 2.5V; FCLK = 5.0 MHz;

SO = Open

D011 ICC Wri te —

—5

3mA

mA VCC = 5.5V

VCC = 2.5V

D012 Iccs Standby Current —

—5

μA

CS = VCC = 5.5V, Inputs tied to VCC or

VSS, TA = +125°C

CS = VCC = 5.5V, Inputs tied to VCC or

VSS, TA = +85°C

Note: This parameter is periodically sampled and not 100% tested.

25XX080C/D

TABLE 1-2: AC CHARACTERISTICS

AC CHARACTERISTICS Industrial (I): TA = -40°C to +85°C VCC = 1.8V to 5.5V

Automotive (E): TA = -40°C to +125°C VCC = 2.5V to 5.5V

Param.

No. Sym. Characteristic Min. Max. Units Test Conditions

CLK Clock Freq uen cy —

—

MHz

4.5V ≤ VCC ≤ 5.5V

2.5V ≤ VCC < 4.5V

1.8V ≤ VCC < 2.5V

CSS CS Setup Time 50

100

150

—

4.5V ≤ VCC ≤ 5.5V

2.5V ≤ VCC < 4.5V

1.8V ≤ VCC < 2.5V

CSH CS Hold Time 100

200

250

—

4.5V ≤ VCC ≤ 5.5V

2.5V ≤ VCC < 4.5V

1.8V ≤ VCC < 2.5V

CSD CS Disable Time 50 — ns —

5 Tsu Data Setup Time 10

—

4.5V ≤ VCC ≤ 5.5V

2.5V ≤ VCC < 4.5V

1.8V ≤ VCC < 2.5V

HD Data Hold Time 20

—

4.5V ≤ VCC ≤ 5.5V

2.5V ≤ VCC < 4.5V

1.8V ≤ VCC < 2.5V

RCLK Rise Time — 2 µs (Note 1)

FCLK Fall Time — 2 µs (Note 1)

HI Clock High Time 50

100

150

—

4.5V ≤ VCC ≤ 5.5V

2.5V ≤ VCC < 4.5V

1.8V ≤ VCC < 2.5V

10 TLO Clock Low Time 50

100

150

—

4.5V ≤ VCC ≤ 5.5V

2.5V ≤ VCC < 4.5V

1.8V ≤ VCC < 2.5V

11 TCLD Clock Delay Time 50 — ns —

12 TCLE Cloc k Enab le Time 50 — ns —

13 TVOutput Valid from Clock

Low —

—

100

160

4.5V ≤ VCC ≤ 5.5V

2.5V ≤ VCC < 4.5V

1.8V ≤ VCC < 2.5V

14 THO Output Hold Time 0 — ns (Note 1)

15 TDIS Output Disable Time —

—

160

4.5V ≤ VCC ≤ 5.5V (Note 1)

2.5V ≤ VCC < 4.5V (Note 1)

1.8V ≤ VCC < 2.5V (Note 1)

16 THS HOLD Setup Time 20

—

4.5V ≤ VCC ≤ 5.5V

2.5V ≤ VCC < 4.5V

1.8V ≤ VCC < 2.5V

Note 1: This parameter is periodically sampled and not 100% tested.

2: TWC begins on the rising edge of CS after a valid write sequence and ends when the internal write cycle

is complete .

3: This parameter is not tested but ensured by characterization. For endurance estimates in a specific

application, please consult the Total Endurance™ Model which can be obtained from our web site:

www.microchip.com.

25XX080C/D

TABLE 1-3: AC TEST CONDITIONS

17 THH HOLD Hold Time 20

—

4.5V ≤ VCC ≤ 5.5V

2.5V ≤ VCC < 4.5V

1.8V ≤ VCC < 2.5V

18 THZ HOLD Low to Output

High-Z 30

160

—

4.5V ≤ VCC ≤ 5.5V (Note 1)

2.5V ≤ VCC < 4.5V (Note 1)

1.8V ≤ VCC < 2.5V (Note 1)

19 THV HOLD High to Output

Valid 30

160

—

4.5V ≤ VCC ≤ 5.5V

2.5V ≤ VCC < 4.5V

1.8V ≤ VCC < 2.5V

20 TWC Internal Write Cycle Time — 5 ms (Note 2)

21 — Endurance 1M — E/W

Cycles (Note 3)

TABLE 1-2: AC CHARACTERISTICS (CONTINUED)

AC CHARACTERISTICS Industrial (I): TA = -40°C to +85°C VCC = 1.8V to 5.5V

Automotive (E): TA = -40°C to +125°C VCC = 2.5V to 5.5V

Param.

No. Sym. Characteristic Min. Max. Units Test Conditions

Note 1: This parameter is periodically sampled and not 100% tested.

2: TWC begins on the rising edge of CS after a valid write sequence and ends when the internal write cycle

is complete .

3: This parameter is not tested but ensured by characterization. For endurance estimates in a specific

application, please consult the Total Endurance™ Model which can be obtained from our web site:

www.microchip.com.

AC Waveform:

VLO = 0.2V —

VHI = VCC - 0.2V (Note 1)

VHI = 4.0V (Note 2)

CL = 50 pF —

Timing Measurement Refere nce Lev el

Input 0.5 VCC

Output 0.5 VCC

Note 1: For VCC ≤ 4.0V

2: For VCC > 4.0V

25XX080C/D

FIGURE 1-1: HOLD TIMING

FIGURE 1-2: SERIAL INPUT TIMING

FIGURE 1-3: SERIAL OUTPUT TIMING

SCK

HOLD

16 16 17

Don’t Care 5

High-Impedance

n + 2 n + 1 n n - 1

n + 2 n + 1 n nn - 1

SCK

711

LSB in

MSB in

High-Impedance

Mode 1,1

Mode 0,0

SCK

MSB out ISB out

Don’t Care

Mode 1,1

Mode 0,0

25XX080C/D

2.0 FUNCTIONAL DESCRIPTION

2.1 Principles of Operation

The 25XX080C/D are 1024 byte Serial EEPROMs

designed to interface directly with the Serial

Peripheral Interface (SPI) Port of many of today’s

popular microcontroller families, including

Microchip’s PIC® microcontrollers. It may also inter-

face with microcontrollers that do not have a built-in

Sync hrono us Se rial Port b y usin g discr ete

I/O lines programmed properly with the software.

The 25XX08 0C /D contai ns an 8 - bit in stru cti on registe r.

The d evic e is acce sse d via the SI pin, w ith data bei ng

clocked in on the ris ing edg e of SCK. Th e C S pin mus t

be low and the HOLD pin must be high for the entire

operation.

Table 2-1 contains a list of the possible instruction

bytes and format for device operation. All instructions,

addresses, and data are transferred MSB first, LSB

last.

Data (SI) is sampled on the first rising edge of SCK

after CS go es low. If the cloc k li ne is sha red wit h ot her

periphera l dev ices on the SPI bus , the user can asser t

the HOLD input and place the 25XX080C/D in ‘HOLD’

mode. After releasing the HOLD pin, operation will

resume from the point when the HOLD was asserted.

2.2 Read Sequence

The device is selected by pulling CS low. The 8-bit

READ instruction is transmitted to the 25XX080C/D fol-

lowe d by the 16-bit address, with th e six MS Bs of the

address being “don’t care” bits. After the correct READ

instruc tio n a nd address ar e s en t, t he dat a store d i n th e

memory at the selected address is shifted out on the

SO pin. The data stored in the memory at the next

address can be read sequentially by continuing to pro-

vide cl ock puls es. The inter nal Addr ess Pointe r is auto-

matically incremented to the next higher address after

each byte of data is shifted out. When the highest

address is reached (03FFh), the address counter rolls

over to address 0000h allowing the read cycle to be

continu ed indefi nitely. The read op eration is terminate d

by raisin g the CS pin (Figure 2-1).

2.3 Write Sequence

Prior to any attempt to write data to the 25XX080C/D,

the write enable latch must be set by issuing the WREN

instruction (Figure 2-4). This is done by setting CS low

and then clocking out the proper instruction into the

25XX080C/D. After all eight bits of the instruction are

transmitted, the CS must be brought high to set the

write enable latch. If the write operation is initiated

immediately after the WREN instruction without CS

being brought high, the data will not be written to the

array bec ause the wr ite enable l atch will not h ave been

properly set.

Once the write enable latch is set, the user may

proceed by setting the CS low, issuing a WRITE

ins tru ct io n, f o llowed b y t he 1 6 -b i t ad d ress, wi th th e s ix

MSBs of the address being “don’t care” bits, and then

the data to be written. Up to 16 bytes (25XX080C) or 32

bytes (25XX080D) of data can be sent to the device

before a w rite cycle is neces sary. The only restric tion is

that all of the bytes must reside in the same page.

For the data to be actually written to the array, the CS

must be brought high a fter the Leas t Significant bit (D0)

of the nth data byte has been clocked in. If CS is

brought high at any other time, the write operation will

not be completed. Refer to Figure 2-2 and Figure 2-3

for more detailed illustrations on the byte write

sequence and the page write sequence, respectively.

While the write is in progress, the ST ATUS register may

be read to check the status of the WPEN, WIP, WEL,

BP1 and BP0 bits (Figure 2-6). A read attempt of a

memory array location will not be possible during a

write cycle. When the write cycle is completed, the

write enab le latc h is res et.

Note: Page write opera tions are l imited to wri ting

bytes within a single physical page,

regardless of the number of bytes

actually being written. Physical page

boundaries start at addresses that are

integer multiples of the page buffer size (or

‘pag e size’) an d, end at addresses tha t are

integer multiples of page size – 1. If a

Page Write command attempts to write

across a physical page boundary, the

result is that the data wraps around to the

beginning of the current page (overwriting

data previously stored there), instead of

being w ritte n to the next p a ge as mi ght be

expected. It is therefore necessary for the

application software to prevent page write

operations that would attempt to cross a

page boundary.

25XX080C/D

Block Diagram

FIGURE 2-1: READ SEQUENCE

SCK

HOLD

STATUS

I/O Control Memory

Control

Logic

Dec

HV Generator

EEPROM

Array

Page Latches

Y Decoder

Sense Amp.

R/W Control

Logic

VCC

VSS

TABLE 2-1: INSTRUCTION SET

Instruction Name Instruction Format Description

READ 0000 0011 Read data from memory array beginning at selected address

WRITE 0000 0010 Write data to memory array beginning at selected address

WRDI 0000 0100 Reset the write enable latch (disable write operations)

WREN 0000 0110 Set the write enable latch (enable write operations)

RDSR 0000 0101 Read STATUS Register

WRSR 0000 0001 Write STATUS Register

SCK

0 234567891011 21222324252627282930311

0100000115 14 13 12 210

76543210

Instruction 16-bit Address

Data Out

High-Impedance

25XX080C/D

FIGURE 2-2: BYTE WRITE SEQUENCE

FIGURE 2-3: PAGE WRITE SEQUENCE

91011 2122232425262728293031

0000000115 14 13 12 21076543210

Instruction 16-bit Address Data Byte

High-Impedance

SCK 0 23456718 Twc

9 1011 2122232425262728293031

0000000115 14 13 12 21076543210

Instructi on 16-bit Addre ss Data Byte 1

SCK 0 23456718

41 42 43 46 47

76543210

Data Byte n (16/32 max)

SCK 32 34 35 36 37 38 3933 40

76543210

Data Byte 3

76543210

Data Byte 2

44 45

25XX080C/D

2.4 Wr ite Enable (WREN) and Write

Disable (WRDI)

The 25XX080C/D contains a write enable latch. See

Table 2-4 for the Write-Protect Functionality Matrix.

This latch must be set before any write operation will be

completed internally. The WREN instruction will set the

latch, and the WRDI will reset the latch.

The following is a list of conditions under which the

write enab le latc h wi ll be reset:

• Power-up

•WRDI instruction successfully executed

•WRSR instruction successfully executed

•WRITE instruction successfully executed

FIGURE 2-4: WRITE ENABLE SEQUENCE (WREN)

FIGURE 2-5: WRITE DISABLE SEQUENCE (WRDI)

SCK

0 2345671

High-Impedance

010000 01

SCK

0 2345671

High-Impedance

010000 01

25XX080C/D

2.5 Read Status Register (RDSR)

Instruction

The Read Status Register (RDSR) instruction provides

access to the STATUS register. The STATUS register

may be rea d at any time, ev en during a write cy cle. The

STATUS register is formatted as follows:

TABLE 2-2: STATUS REGISTER

The Write-In-Process (WIP) bit indicates whether the

25XX080C/D is busy with a write operation. When set

to a ‘1’, a w rite is in prog ress, when set to a ‘0’, no write

is in progress. This bit is read-only.

The Write Enable Lat ch (WEL) bit indicat es the st atus

of the write enable latch and is read only. When set to

a ‘1’, the la tch allow s writes to the array or the STATUS

the array or the STATUS register. The state of this bit

can always be updated via the WREN or WRDI com-

mands r egardle ss of the state o f write pr otecti on on the

STATUS register. These commands are shown in

Figure 2-4 and Figure 2-5.

The Block Protection (BP0 and BP1) bits indicate

which blocks are currently write-protected. These bits

are set by the user issuing the WRSR instruction, which

is in Figure 2-7. These bits are nonvolatile and are

shown in Table 2-3.

See Figure 2-6 for the RDSR timing sequence.

FIGURE 2-6: READ STATUS REGISTER TIMING SEQUENCE (RDSR)

7 654 3 2 1 0

W/R –––W/RW/R R R

WPEN X X X BP1 BP0 WEL WIP

W/R = writable/readable. R = read-only.

9101112131415

11000000

7654 210

Instruction

Data from STATUS Register

High-Impedance

SCK

0 23456718

25XX080C/D

2.6 Wr it e Status Regist er (WRSR)

Instruction

The Write S t atus Re gister (WRSR) inst ruction allows the

user to write to the nonvolatile bits in the STATUS reg-

ister as shown in Table 2-2. The user is able to select

one of four levels of protection for the array by writing

to the appropriate bits in the STATUS register. The

array is divided up into four segment s. The user has the

ability to write-protect none, one, two or all four of the

segments of the array. The partitioning is controlled as

shown in Table 2-3.

The Write-Protect Enable (WPEN) bit is also a

nonvolatile bit that is available as an enable bit for the WP

pin. The Write-Protect (WP) pin and the Write-Protect

Enable (WPEN) bit in the STATUS register control the

progra mmabl e hardw are writ e-prot ect fea ture. Hard ware

writ e protecti on is enable d when WP pin is low and the

WPEN bit is high. Hardware write protection is disabled

when either the WP pin is high or the WPEN bit is low.

When the chip is hardw are write-p rotected, onl y writes to

nonvolatile bits in the ST ATUS register are disabled. See

Table 2-4 for a ma tri x of functi on al ity o n the W PEN b it .

See Figure 2-7 for the WRSR timing sequence.

TABLE 2-3: ARRAY PROTECTION

FIGURE 2-7: WRITE STATUS REGISTER TIMING SEQUENCE (WRSR)

BP1 BP0 Array Addresses

Write-Protected

00 none

01 upper 1/4

(0300h-03FFh)

10 upper 1/2

(0200h-03FFh)

11 all

(0000h-03FFh)

9101112131415

01000000

7654 210

Instruction Data to STATUS Register

High-Impedance

SCK

0 23456718

25XX080C/D

2.7 Data Protection

The following protection has been implemented to

prevent inadvertent writes to the array :

• The write enable latch is reset on power-up

• A write enable instruction must be issued to set

the write enable latch

• After a byte write, page write or STATUS r egister

write, the write enable latch is reset

•CS

must be set high after the proper number of

clock cycles to start an internal write cycle

• Access to the array during an internal write cycle

is ignored and programming is continued

2.8 Power-On State

The 25XX080C/D powers on in the following state:

• The device is in low-power Standby mode

(CS=1)

• The write enable latch is reset

• SO is in high-impedance state

• A high-to-low-level transition on CS is required to

enter activ e st ate

TABLE 2-4: WRITE-PROTECT FUNCTIONALITY MATRIX

WEL

(SR bit 1) WPEN

(SR bit 7) WP

(pin 3) Protected Blocks Unprotected Blocks STATUS Register

0xx

Protected Protected Protected

10x

Protected Writable Writable

110 (low) Protected Writable Protected

111 (high) Protected Writable Writable

x = don’t care

25XX080C/D

3.0 PIN DESCRIPTIONS

The descriptions of the pins are listed in Table 3-1.

TABLE 3-1: PIN FUNCTION TABLE

3.1 Chip Select (CS)

A low level on this pin selects the device. A high level

deselects the device and forces it into Standby mode.

However, a programming cycle which is already

initiated or in p r ogre ss w il l be co mpl ete d, regardle ss of

the CS input signal. If CS is brought high during a

progra m cycle, t he device wil l go into Standb y mode as

soon as the programming cycle is complete. When the

device is deselected, SO goes to the high-impedance

state, allowing multiple parts to share the same SPI

bus. A low-to-high transition on CS after a valid write

sequence initiates an internal write cycle. After power-

up, a low lev el on CS is required p r ior to any se qu enc e

being initiated.

3.2 Serial Output (SO)

The SO pin is used to transfer data out of the

25XX080C/D. During a read cycle, data is shifted out

on this pin after the falling edge of the serial clock.

3.3 Write-Protect (WP)

This pin is used in conjunction with the WPEN bit in the

STATUS register to prohibit writes to the nonvolatile

bits in the STATUS register. When WP is low and

WPEN is high, wr iting to the nonvolat ile bits in the STA-

TUS register is disabled. All other operations function

normally. When WP is high, all functions, including

writes to the nonvolatile bits in the STATUS register

operate no rmally. If the WPEN bit is set, WP low during

a STATUS register write sequence will disable writing

to the STATUS register. If an internal write cycle has

already begun, WP go ing low w ill h ave no ef fect on the

write.

The WP pin function is blocked when the WPEN bit in

the STATUS register is low. This allows the user to

install the 25XX080C/D in a system with WP pin

grounded and still be able to write to the STATUS reg-

ister. The WP pin functions will be enabled when the

WPEN bit is set high.

3.4 Seria l In p u t (SI)

The SI pin is used to transfer data into the device. It

receives instructions, addresses and data. Data is

latched on the rising edge of the serial clock.

3.5 Serial Clock (SCK)

The SCK is used to synchronize the communication

between a master and the 25XX080C/D. Instructions,

address es or data presen t on the SI pin are la tc hed on

the risin g edge of t he c lo ck in put, w hil e d at a on th e SO

pin is updated after the falling edge of the clock input.

3.6 Hold (HOLD)

The HOLD pin is used to suspend transmission to the

25XX0 80C/D wh ile in t he middl e of a se rial seq uence

withou t having to retransmit the entire se quence ag ain.

It must be he ld high any t ime t his fun cti on is not bei ng

used. Once the device is selected and a serial

sequence is underway, the HOLD pin may be pulled

low to pause further serial communication without

resetting the serial sequence. The HOLD pin must be

brought low while SCK is low, otherwise the HOLD

function will not be invoked until the next SCK high-to-

low transition. The 25XX080C/D must remain selected

during this sequence. The SI, SCK and SO pins are in

a high-impedance state during the time the device is

paus ed and tran sitions on these p ins will be ignored. To

resume serial communication, HOLD must be brought

high while the SCK pin is low, otherwise serial

communication will not resume. Lowering the HOLD

line at any time will tri-state the SO line.

Name Pin Number Function

CS 1 Chip Sele ct Input

SO 2 Serial Data Output

WP 3 Write-Protect Pin

VSS 4 Ground

SI 5 Serial Data Input

SCK 6 Serial Clock Input

HOLD 7 H old Input

VCC 8 Supply Voltage

25XX080C/D

4.0 PACKAGING INFORMATION

4.1 Package Marking Information

8-Lead MSOP (150 mil) Example:

XXXXXXT

YWWNNN 5L8DI

9281L7

T/XXXNNN

XXXXXXXX

YYWW

8-Lead PDIP

8-Lead SOIC

XXXXYYWW

XXXXXXXT

NNN

XXXX

TYWW

8-Lead TSSOP

NNN

I/P 1L7

25LC080D

0928

Example:

SN 0928

25LC08DI

1L7

5L8D

I628

Example:

8-Lead 2x3 TDFN Example:

XXX

YWW

C44

928

25XX080C/D

Part Number

1st Line Marking Codes

TSSOP MSOP TDFN

I Temp. E Temp.

25AA080C 5A8C 5A8CT C31 —

25AA080D 5A8D 5A8DT C41 —

25LC080C 5L8C 5L8CT C34 C35

25LC080D 5L8D 5L8DT C44 C45

Note: T = Temperature grade (I, E)

Legend: XX...X Customer-specific information

Y Year code (last digit of calendar year)

YY Year code (last 2 digits of calendar year)

WW We ek code (week of January 1 is week ‘01’)

NNN Alphanumeric traceability code

Pb-free JEDEC designator for Matte Tin (Sn)

*This package is Pb-free. The Pb-free JEDEC designator ( )

can be found on the outer packaging for this package.

Note: In the even t the full M icroc hip p art numb er cann ot be mark ed on one line, it w ill

be carried over to the next line, thus limiting the number of available

characters for customer-specific information.

25XX080C/D

8-Lead Plastic Micro Small Outline Package (MS or UA) [MSOP]

Notes:

1. Pin 1 visual index feature may vary, but must be located within the hatched area.

2. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15 mm per side.

3. Dimensioning and tolerancing per ASME Y14.5M.

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

REF: Reference Dimension, usually without tolerance, for information purposes only.

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

Units MILLIMETERS

Dimension Limits MIN NOM MAX

Number of Pins N 8

Pitch e 0.65 BSC

Overall Height A – – 1.10

Molded Package Thickness A2 0.75 0.85 0.95

Standoff A1 0.00 – 0.15

Overall Width E 4.90 BSC

Molded Package Width E1 3.00 BSC

Overall Length D 3.00 BSC

Foot Length L 0.40 0.60 0.80

Footprint L1 0.95 REF

Foot Angle φ0° – 8°

Lead Thickness c 0.08 – 0.23

Lead Width b 0.22 – 0.40

NOTE 1

L1 L

Microchip Technology Drawing C04-111B

25XX080C/D

8-Lead Plastic Dual In-Line (P or PA) – 300 mil Body [PDIP]

Notes:

1. Pin 1 visual index feature may vary, but must be located with the hatched area.

2. § Significant Characteristic.

3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" per side.

4. Dimensioning and tolerancing per ASME Y14.5M.

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

Units INCHES

Dimension Limits MIN NOM MAX

Number of Pins N 8

Pitch e .100 BSC

Top to Seating Plane A – – .210

Molded Package Thickness A2 .115 .130 .195

Base to Seating Plane A1 .015 – –

Shoulder to Shoulder Width E .290 .310 .325

Molded Package Width E1 .240 .250 .280

Overall Length D .348 .365 .400

Tip to Seating Plane L .115 .130 .150

Lead Thickness c .008 .010 .015

Upper Lead Width b1 .040 .060 .070

Lower Lead Width b .014 .018 .022

Overall Row Spacing § eB – – .430

NOTE 1

Microchip Technology Drawing C04-018B

25XX080C/D

8-Lead Plastic Small Outline (SN or OA) – Narrow, 3.90 mm Body [SOIC]

Notes:

1. Pin 1 visual index feature may vary, but must be located within the hatched area.

2. § Significant Characteristic.

3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15 mm per side.

4. Dimensioning and tolerancing per ASME Y14.5M.

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

REF: Reference Dimension, usually without tolerance, for information purposes only.

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

Units MILLIMETERS

Dimension Limits MIN NOM MAX

Number of Pins N 8

Pitch e 1.27 BSC

Overall Height A – – 1.75

Molded Package Thickness A2 1.25 – –

Standoff §A1 0.10 – 0.25

Overall Width E 6.00 BSC

Molded Package Width E1 3.90 BSC

Overall Length D 4.90 BSC

Chamfer (optional) h 0.25 – 0.50

Foot Length L 0.40 – 1.27

Footprint L1 1.04 REF

Foot Angle φ0° – 8°

Lead Thickness c 0.17 – 0.25

Lead Width b 0.31 – 0.51

Mold Draft Angle Top α5° – 15°

Mold Draft Angle Bottom β5° – 15°

NOTE 1

12 3

Microchip Technology Drawing C04-057B

25XX080C/D

8-Lead Plastic Thin Shrink Small Outline (ST) – 4.4 mm Body [TSSOP]

Notes:

1. Pin 1 visual index feature may vary, but must be located within the hatched area.

2. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15 mm per side.

3. Dimensioning and tolerancing per ASME Y14.5M.

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

REF: Reference Dimension, usually without tolerance, for information purposes only.

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

Units MILLIMETERS

Dimension Limits MIN NOM MAX

Number of Pins N 8

Pitch e 0.65 BSC

Overall Height A – – 1.20

Molded Package Thickness A2 0.80 1.00 1.05

Standoff A1 0.05 – 0.15

Overall Width E 6.40 BSC

Molded Package Width E1 4.30 4.40 4.50

Molded Package Length D 2.90 3.00 3.10

Foot Length L 0.45 0.60 0.75

Footprint L1 1.00 REF

Foot Angle φ0° – 8°

Lead Thickness c 0.09 – 0.20

Lead Width b 0.19 – 0.30

NOTE 1

L1 L

Microchip Technology Drawing C04-086B

25XX080C/D

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25XX080C/D

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25XX080C/D

APPENDIX A: REVISION HISTORY

Revision A (4/2009)

Original release of this document.

25XX080C/D

THE MICROCHIP WEB SITE

Microc hip pro vides onl ine s upport v ia our W WW site at

www.microchi p.c om . Thi s web si te i s us ed as a m ean s

to make files and information easily available to

customers. Accessible by using your favorite Internet

browser, the web site contains the following

information:

•Product Support – Data sheets and errata,

application notes and sample programs, design

resources, user’s guides and hardware support

documents, latest software releases and archived

software

•General Technical Support – Frequently Asked

Questions (FAQ), technical support requests,

online dis cu ss io n gr oups, Microchip con sultant

program member listing

•Business of Microchip – Product selector and

ordering guides, latest Microchip press releases,

listing of seminars and events, listings of

Microchip sales offices, distributors and factory

representatives

CUSTOMER CHANGE NOTIFICATION

SERVICE

Microchip’s customer notification service helps keep

customers current on Microchip products. Subscribers

will receive e-mail notification whenever there are

changes, updates, revisions or errata related to a

specif ied produ ct family or develo pment tool of interes t.

To register, access the Microchip web site at

www.microchip.com, click on Customer Change

Notification and follow the registration instructions.

CUSTOMER SUPP ORT

Users of Microchip products can receive assistance

through several channels:

• Distributor or Representative

• Local Sales Office

• Field Application Engineer (FAE)

• Technical Support

• Development Systems Information Line

Customers should contact their distributor,

representative or field application engineer (FAE) for

support. Local sales offices are also available to help

customers. A listing of sales offices and locations is

included in the back of this document.

Technical s upport is a vailable through the web si te

at: http://support.microchip.com

25XX080C/D

READER RESP ONSE

It is ou r intentio n to provide you w it h th e b es t do cument ation po ss ib le to ensure suc c es sfu l u se of y ou r M ic roc hip prod-

uct. If you wi sh to prov ide you r comment s on org aniza tion, clar ity, subj ect matte r , and ways i n which o ur docum entatio n

can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150.

Please list the following information, and use this outline to provide us with your comments about this document.

To: Technical Publications Manager

RE: Reader Response Total Pages Sent ________

From: Name

Company

Address

City / State / ZIP / Country

Telephone: (_______) _________ - _________

Application (optional):

Would you like a reply? Y N

Device: Literature Number:

Questions:

FAX: (______) _________ - _________

DS22151A25XX080C/D

1. What are the best featu res of this document ?

2. How does this document meet your hardware and software development needs?

3. Do you find the organization of this document easy to follow? If not, why?

4. What additions to the document do you think would enhance the structure and subject?

5. What deletions from the document could be made without affecting the overall usefulness?

6. Is there any incorrect or misleading information (what and where)?

7. How would you improve this document?

25XX080C/D

PRODUCT IDENTIFICATION SYSTEM

To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.

PART NO. X/XX

PackageTape & Reel

Device

Device: 25AA080C

25AA080D

25LC080C

25LC080D

8 Kbit, 1.8V, 16 Byte Page SPI Serial EEPROM

8 Kbit, 1.8V, 32 Byte Page SPI Serial EEPROM

8 Kbit, 2.5V, 16 Byte Page SPI Serial EEPROM

8 Kbit, 2.5V, 32 Byte Page SPI Serial EEPROM

Tape & Reel: Blank =

Standard packaging

Tape & Reel

Temperature

Range: I=

-40°C to+85°C

-40°C to+125°C

Package: MS =

SN =

ST =

MNY(1) =

Plastic MSOP (Micro Small Outline), 8-lead

Plastic DIP (300 mil body), 8-lead

Plastic SOIC (3.90 mm body), 8-lead

TSSOP, 8-lead

8-lead 2x3 mm TDFN

Examples:

a) 25AA080C-I/MS = 8 Kbit, 16-byte page, 1.8V

Serial EEPROM, Industrial temp., MSOP

package

b) 25AA080CT-I/SN = 8 Kbit, 16-byte page, 1.8V

Serial EEPROM, Industrial temp., T ape & Reel,

SOIC package

c) 25LC080DT-I/SN = 8 Kbit, 32-byte page, 2.5V

Serial EEPROM, Industrial temp., Tape & Reel,

SOIC package

d) 25LC080DT-I/ST = 8 Kbit, 32-byte page, 2.5V

Serial EEPROM, Industrial temp., Tape & Reel,

TSSOP package

–

Note 1: “Y ” indicates a Nickel Palladium Gold (NiPdAu) finish.

Temp Range

25XX080C/D

NOTES:

Information contained in this publication regarding device

applications and the like is provided only for your con ve nience

and may be superseded by u pdates. It is y our respo ns ibility to

ensure that your application meets with your specifications.

MICROCHIP MAKES NO REPRESENTATIONS OR

WARRANTIES OF ANY KIND WHETHER EXPRESS OR

IMPLIED, WRITTEN OR ORAL, STATUTORY OR

OTHERWISE, RELATED TO THE INFORMATION,

INCLUDING BUT NOT LIMITED TO ITS CONDITION,

QUALITY, PERFORMANCE, MERCHANTABILITY OR

FITNESS FOR PURPOSE. Microchip disclaims all liability

arising from this information and its use. Use of Microchip

devices in life support and/or safety applications is entirely at

the buyer’s risk, and the buyer agrees to defend, indemnify and

hold harmless Microchip from any and all damages, claims,

suits, or expenses resulting from such use. No licenses are

conveyed, implicitly or otherwise, under any Microchip

intellectual property rights.

Trademarks

The Microchip name and logo, the Microchip logo, Accuron,

dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro,

PICSTA RT, rfPI C, SmartS hunt and UNI/O are registered

trademarks of Microchip Tec hnology Incorporat ed in the

U.S.A. and other countries.

FilterLab, Hampshire, Linear Active Thermistor, MXDEV,

MXLAB, SEEVAL, SmartSensor and The Embedded Control

Solutions Company are registered trademarks of Microchip

Technology Incorporated in the U.S.A.

Analog-for-the-Digital Age, Application Maestro, CodeGuard,

dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,

ECONOMONITOR, FanSense, In-Circuit Serial

Prog ra m ming, IC S P, ICE PI C , M i n di , MiWi, MPASM , MPLAB

Certified logo, MPLIB, MPLINK, mTouch, nanoW att XLP,

PICkit, PICDEM, P ICDEM.net, PICtail , PIC32 logo, PowerCal,

PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB, Select

Mode, Total Endurance, TSHARC, WiperLock and ZENA are

trademarks of Microchip Tec hnology Incorporat ed in the

U.S.A. and other countries.

SQTP is a service mark of Microchip T echnology Incorporated

in the U.S.A.

All other trademarks mentioned herein are property of their

respective companies.

Printed on recycled paper.

Note the following details of the code protection feature on Microchip devices:

• Microchip products meet the specification contained in their particular Microchip Data Sheet.

• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in t he

intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our

knowledge, require using the Microchip products in a manner outside the operating specifications contai ned in Microchip’s Data

Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not

mean that we are guaranteeing the product as “unbreakable.”

Code protection is c onstantly evolving. We a t Microc hip are co m mitted to continuously improving the code prot ect ion featur es of our

products. Attempts to break Microchip’ s code protection feature may be a violation of the Digital Millennium Copyright Act. If such act s

allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Microchip received ISO/TS-16949:2002 certification for its worldwide

headquarters, design and wafer fabrication facilities in Chandler and

Tempe, Arizona; Gresham, Oregon and design centers in California

and India. The Company’s quality system processes and procedures

are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code ho pping

devices, Serial EEPROMs, microperiph erals, nonvolatile memory and

analog products. In addition, Microchip’s quality system for the design

and manufacture of development systems is ISO 9001:2000 certified.

AMERICAS

Corporate Office

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WORLDWIDE SALES AND SERVICE

03/26/09